a4091: clear FIFOs on CTEST8.CLF strobe#157
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A write to CTEST8 with the CLF bit (0x04) drains both the DMA FIFO (all four lanes) and the SCSI FIFO. The strobe is self-clearing, so the bit never latches in the register file. Mirrors the 53C710 behavior ported into Amiberry (qemuvga/lsi53c710.cpp). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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A write to the 53C710 CTEST8 register with the CLF bit (0x04) drains
both FIFOs: the DMA FIFO (all four lanes) and the SCSI FIFO. The bit is
a self-clearing strobe, so it never latches in the register file (the
read path already masks it off; this makes the stored value agree).
This matches the datasheet semantics and the equivalent behavior in the
53C710 model I ported into Amiberry's
qemuvga/lsi53c710.cpp. Note theAmiberry side only zeroes its SCSI FIFO count because its DMA FIFO uses
a separate byte-count model; here both FIFOs are explicit, so both are
cleared.
Adds
ctest8_clf_drains_both_fifos: fills every DMA lane and the SCSIFIFO, strobes CLF, then verifies CTEST1 reads all-lanes-empty, the
SSTAT2 count is zero, and the CLF bit reads back clear. All 17 a4091
tests pass.
🤖 Generated with Claude Code