General description

This repository contains a framework for low-level microarchitecture evaluation of hardware faults and their impact on software applications. Furthermore, the framework allows the exploration and evaluation of software-based solutions to improve resilience and fault-tolerance.

Quick start with the evaluation environment:

The framework is managed through commands using the makefile in the main folder of the framework.

Steps to compute and evaluate a targeted application:

• 1. Compile a source code program (in case of hardened program already in sbst.hex, this step can be skipped, just place the sbst.hex file in the sbst folder)

Use:

Make compile_sbst INPUT=programs/conv_INT/main

• 2. Compile the RTL code of the processor (the function is able to compile both RTL and gate level at the same time)

Use:

Make Questa/compile

• 3. Simulation of a program in the RTL processor (a file end_memory.txt is created with the final memory content)

Use:

Make Questa/lsim/rtl/shell_polimi_polito

• 4. Simulation of a program in the gate-level processor (a file end_memory.txt is created with the final memory content) (required to generate the VCD file to be used during the zoix analysis)

Use:

Make Questa/lsim/gate/shell_polimi_polito

• 5. Fault simulation on gate-level processor (only works with gate level processor)

Use:

Make zoix/compile    (compile the framework and all required files)
Make zoix/fgen/saf   (generate the fault list in “zoix/” folder (.sff file))
Make zoix/lsim     (used to verify the input patterns on the gate version)
Make zoix/fsim FAULT_LIST= (path to file file in “zoix/” folder (.sff file))

Experimental results

Table I. Preliminary fault vulnerability results for several benchmarks.

Application		Execution RTL (ns)	Evaluated faults	Faults propagated	Faults masked	FPR%
MxM_INT		5,351,610	17,930	10,705	7,220	59.7
Conv_INT		6,334,320	17,930	10,921	7,004	60.9
Reduction_INT		92,500	17,930	10,346	7,579	57.7
Vector Add INT (Active Debugger)		1,105,410	17,930	11,595	6,330	64.49
Vector Add		64,920	17,930	5,314	12,616	29.65
Vector_add_alt1		133,010	17,930	10,028	7,902	55.93
Vector_add_alt2		133,010	17,930	10,028	7,902	55.93
Vector_add_alt2 (Active Debugger)		948,780	17,930	11,587	6,343	64.64
Vector_add_alt3		152,250	17,930	10,176	7,754	56.77
Vector_Add_INT_DWC		197,260	17,930	10,741	7,189	59.91
Transpose_INT(_alt1)		50,380	17,930	4,679	13,251	26.11
Transpose_INT_alt2		32,450	17,930	4,506	13,424	25.15
Transpose_INT_alt3		62,680	17,930	4,760	13,170	26.55
Transpose_INT_DWC (Active Debugger)		4,633,870	17,930	9,937	7,993	55.44
Transpose_INT_DWC		122,240	17,930	6,061	11,869	33.82

Employed hardware benchmark:

OpenHW Group CORE-V CV32E40P RISC-V IP

CV32E40P is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements the RV32IM[F|Zfinx]C instruction set architecture, and the PULP custom extensions for achieving higher code density, performance, and energy efficiency [1], [2]. It started its life as a fork of the OR10N CPU core that is based on the OpenRISC ISA. Then, under the name of RI5CY, it became a RISC-V core (2016), and it has been maintained by the PULP platform team until February 2020, when it has been contributed to OpenHW Group.

Documentation

The CV32E40P user manual can be found in the docs folder and it is captured in reStructuredText, rendered to html using Sphinx. These documents are viewable using readthedocs and can be viewed here.

Verification

The verification environment for the CV32E40P is not in this Repository. There is a small, simple testbench here which is useful for experimentation only and should not be used to validate any changes to the RTL prior to pushing to the master branch of this repo.

The verification environment for this core as well as other cores in the OpenHW Group CORE-V family is at the core-v-verif repository on GitHub.

The Makefiles supported in the core-v-verif project automatically clone the appropriate version of the cv32e40p RTL sources.

Changelog

A changelog is generated automatically in the documentation from the individual pull requests. In order to enable automatic changelog generation within the CV32E40P documentation, the committer is required to label each pull request that touches any file in 'rtl' (or any of its subdirectories) with Component:RTL and label each pull request that touches any file in 'docs' (or any of its subdirectories) with Component:Doc. Pull requests that are not labeled or labeled with ignore-for-release are ignored for the changelog generation.

Only the person who actually performs the merge can add these labels (you need committer rights). The changelog flow only works if at most 1 label is applied and therefore pull requests that touches both RTL and documentation files in the same pull request are not allowed.

Constraints

Example synthesis constraints for the CV32E40P are provided.

For more details on how this is implemented, have a look at this page.

To get started, please check out the "Good First Issue" list.

The RTL code has been formatted with "Verible" v0.0-1149-g7eae750. Run ./util/format-verible to format all the files.