DFSDM by oganigl · Pull Request #614 · Hyperloop-UPV/ST-LIB

oganigl · 2026-03-26T19:17:33Z

DFSDM module finished and tested. Only missing try in the hyperNucleo

…es of the DMA without removing double entries with the dfsdm.

…st in my test has worked fine.

* Fixed copy pointers leading with possible missalignment * fix(tcp): handle fragmented order streams and queue backpressure * fix(server): own and recycle ServerSocket instances safely * fix(udp): harden DatagramSocket lifecycle and pbuf parsing * fix(lwip): align ICMP checksum settings with hw offload * fix(net): harden socket teardown and unify TCP order parsing * Applied formatter * perf(net): benchmark-driven TCP TX fast path * feat(error): decouple transport from legacy update * Modified warning to decouple from protections * Better timestamp in error and warning * Protection manager more robust * Always enqueuing msgs even when there are no sockets * sorry, I forgot one file * SNTP set * minor fix on protections * Being able to compile without ehternet * formatter

* Prescaler was not initialized in init * formatting: Remove spaces * formatting * hardened a lot the encoder, being sure that instances are properly set * minor fix, not setting properly the encoder start * added tests for the encoder * reverted nullptr checks, and made builder private * applied formatter * Make constructors private in Encoder, PWM, DualPWM * applied formatter * fixed merge mess --------- Co-authored-by: Víctor López <120128034+victor-Lopez25@users.noreply.github.com> Co-authored-by: Jorge Sáez <jorgeesg82@gmail.com>

* Scheduler now "reserves" a timer from timerdomain * Also remove possibility of getting scheduler timer from bits32_timers * stupid change to get precommit to work (?) * fix formatting (?) * more format fix * fix segfault in tests (?) * fix formatting * move Scheduler_global_timer in scheduler_test.cpp

* Fixed issues with MSVC on windows * Move implementation into cpp * Return to inlining clz and ctz * fix formatting (hopefully) * more formatting fixes * fix formatting final please

* Fix: rcc_enable_timer for scheduler timer * formatting nº1

* No more fixed_vector(idk why I did that) * First version implementing std::tupple * No more copy constructor bullshit * Equal operator fixed, now it compiles * Compiling version, tests to be done * Okay now we check for duplicates * Some formating changes * Clanker made me do this so the start and exit functions stop when the condition is true * Made nesting consteval * Fix short circuit no use on return warning * Added state machine tests * Formating errors fixed * Ok now format errors are fixed * More tests need to be addes * Compile testing added, as well as reduced task array to only allow 16 task * Formating errores fixed * Delete tests for the tests * Now you cant use state machine without start * Fixed logic for nested machine start * Formating error fix * clanker commit Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Now we use a concept for a correct tuple in state machine helper function * Formating fix --------- Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

* Max ARR * fix encoder test * actually fix tests now * fix formatting

* chore(release): add semver foundation and tooling * ci(release): require changesets on pull requests * ci(release): automate release preparation and publishing * chore(release): add bootstrap changeset for release infra * fix(release): address Copilot review feedback

jorgesg82 · 2026-03-27T20:21:25Z

@claude review

github-actions · 2026-03-29T18:31:13Z

ST-LIB Release Plan

Current version: 5.0.0
Pending changesets: 3
Highest requested bump: minor
Next version if merged now: 5.1.0

Pending changes

minor Refactor the ADC stack around DMA-backed acquisition using new MPU (.changesets/adc-dma-minor.md)
minor Added module dfsdm tested (.changesets/dfsdm-module-minor.md)
none Introduce semver tooling and release automation infrastructure (.changesets/revive-releases-bootstrap.md)

… apple computer ejem

Copilot

Pull request overview

This PR adds a new DFSDM (Digital Filter for Sigma-Delta Modulators) service/domain and wires it into the ST-LIB board build/init pipeline (including DMA integration and IRQ handlers), plus supporting updates to timer trigger configuration and mocks.

Changes:

Introduces DFSDM_CHANNEL_DOMAIN and DFSDM_CLK_DOMAIN, plus DFSDM IRQ handlers and build-time DMA contributions.
Extends DMA + mocked HAL definitions to support DFSDM filter DMA requests and richer TIM TRGO/TRGO2 options.
Minor build/tooling updates (Linux STM32CubeCLT path globbing, small formatting cleanup, changeset entry).

Reviewed changes

Copilot reviewed 13 out of 13 changed files in this pull request and generated 11 comments.

Show a summary per file

File	Description
toolchains/stm32.cmake	Makes Linux STM32CubeCLT discovery more case-insensitive via glob patterns.
Src/HALAL/Services/DFSDM/DFSDM.cpp	Adds DFSDM filter IRQ handlers that forward to DFSDM domain IRQ dispatcher.
Inc/HALAL/Services/DFSDM/DFSDM.hpp	New DFSDM domains: config/build logic, DMA contribution helpers, runtime instances, and IRQ dispatch.
Inc/ST-LIB_LOW/ST-LIB_LOW.hpp	Exposes DFSDM header through the low-level umbrella include.
Inc/ST-LIB.hpp	Registers DFSDM domains in `DomainsCtx`, adds DFSDM config building, DMA merging, and init wiring.
Inc/MockedDrivers/stm32h7xx_hal_mock.h	Adds DFSDM DMA request IDs and expands TIM TRGO/TRGO2 constants for simulation.
Inc/HALAL/Services/ADC/ADC.hpp	Constructor formatting change only.
Inc/HALAL/Models/TimerDomain/TimerDomain.hpp	Adds TRGO/TRGO2 selection to timer entries/configs and applies master sync configuration.
Inc/HALAL/Models/Pin.hpp	Updates pin metadata bitfields for several pins used by DFSDM/timers.
Inc/HALAL/Models/DMA/DMA2.hpp	Adds DFSDM DMA peripherals and request mapping; tweaks alignment handling for DFSDM.
Inc/HALAL/HALAL.hpp	Includes DFSDM service header in HALAL umbrella.
CMakeLists.txt	Adds DFSDM.cpp to the HALAL source list.
.changesets/dfsdm-module-minor.md	Declares a minor release changeset for DFSDM addition.

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Copilot · 2026-03-30T16:36:49Z

Inc/HALAL/Services/DFSDM/DFSDM.hpp

+        if (isr & (channels_enabled << DFSDM_FLTICR_CLRSCDF_Pos)) {
+            uint32_t ch = __builtin_ctz(isr & DFSDM_FLTISR_SCDF_Msk) >> DFSDM_FLTISR_SCDF_Pos;
+            if (channel_instances[ch] != nullptr &&
+                channel_instances[ch]->short_circuit_cb != nullptr)
+                channel_instances[ch]->short_circuit_cb();


Short-circuit IRQ decoding uses __builtin_ctz(masked) >> DFSDM_FLTISR_SCDF_Pos, but ctz returns a bit index, so shifting will not yield the channel number (it should be adjusted by subtracting the field position, or by shifting the masked value down first). As written, callbacks may fire for the wrong channel.

Copilot · 2026-03-30T16:36:50Z

Inc/HALAL/Services/DFSDM/DFSDM.hpp

+        if (isr & (channels_enabled << DFSDM_FLTISR_CKABF_Pos)) {
+            uint32_t ch = __builtin_ctz(isr & DFSDM_FLTISR_CKABF_Msk) >> DFSDM_FLTISR_CKABF_Pos;
+            if (channel_instances[ch] != nullptr &&
+                channel_instances[ch]->clock_absence_cb != nullptr)
+                channel_instances[ch]->clock_absence_cb();


Clock-absence IRQ decoding has the same issue as short-circuit: __builtin_ctz(masked) >> DFSDM_FLTISR_CKABF_Pos does not compute the channel index correctly from a positioned bitfield. This can dispatch clock_absence_cb on the wrong channel; shift the bitfield down or subtract the position from the ctz result.

Copilot · 2026-03-30T16:36:50Z

Inc/HALAL/Models/TimerDomain/TimerDomain.hpp

+                    .trgo1 = requests[i].trgo1,
+                    .trgo2 = requests[i].trgo2


In TimerDomain::build(), the AnyGeneralPurpose allocation loop sets trgo1/trgo2 from requests[i] even though it picks the request via remaining_requests[i] (const Entry& e = requests[remaining_requests[i]]). This can assign triggers from the wrong timer request; use e.trgo1/e.trgo2 instead.

Suggested change

.trgo1 = requests[i].trgo1,

.trgo2 = requests[i].trgo2

.trgo1 = e.trgo1,

.trgo2 = e.trgo2

Copilot · 2026-03-30T16:36:50Z

Inc/HALAL/Services/DFSDM/DFSDM.hpp

+        }
+        // check that dma buffer size is 1 if there is more than one channel per filter and add the
+        // buffer_pos_ini to every channel
+        std::array<std::array<uint8_t, 8>, 4> channels_filter = {};


channels_filter stores cfgs[i].buffer_size into a uint8_t matrix. Since buffer_size is size_t, values >255 will truncate, which can break the active_channels and > 1 validation logic. Use a wider element type (e.g., std::size_t/uint16_t) for channels_filter.

Suggested change

std::array<std::array<uint8_t, 8>, 4> channels_filter = {};

std::array<std::array<std::size_t, 8>, 4> channels_filter = {};

Copilot · 2026-03-30T16:36:50Z

Inc/HALAL/Services/DFSDM/DFSDM.hpp

+        if (isr & DFSDM_FLTISR_JEOCF_Msk) {
+            // Save it in the address provide by the user
+            int32_t data = filter->FLTJDATAR;
+            uint8_t channel = (data & DFSDM_FLTJDATAR_JDATACH_Msk);


In the JEOCF IRQ path, channel is extracted as (data & DFSDM_FLTJDATAR_JDATACH_Msk) but never shifted by DFSDM_FLTJDATAR_JDATACH_Pos. This will index channel_instances with the raw masked bits rather than the channel number. Extract the field the same way as the regular path (mask then shift).

Suggested change

uint8_t channel = (data & DFSDM_FLTJDATAR_JDATACH_Msk);

uint8_t channel = (data & DFSDM_FLTJDATAR_JDATACH_Msk) >> DFSDM_FLTJDATAR_JDATACH_Pos;

Copilot · 2026-03-30T16:36:51Z

Inc/HALAL/Services/DFSDM/DFSDM.hpp

+    __attribute__((section(".mpu_ram_d1_nc.buffer"))) alignas(32
+    ) static inline int32_t DFSDM_Buffer_Pool[MAX_BUFFER_SIZE_TOTAL];


DFSDM_Buffer_Pool reserves MAX_BUFFER_SIZE_TOTAL int32s in the D1 non-cached section but is never referenced anywhere in this header. On embedded targets this is a permanent RAM cost; remove it or wire it into the actual buffering strategy.

Suggested change

__attribute__((section(".mpu_ram_d1_nc.buffer"))) alignas(32

) static inline int32_t DFSDM_Buffer_Pool[MAX_BUFFER_SIZE_TOTAL];

Copilot · 2026-03-30T16:36:51Z

Inc/HALAL/Services/DFSDM/DFSDM.hpp

+    static void handle_irq(uint8_t filter_index) {
+
+        DFSDM_Filter_TypeDef* filter = filter_hw[filter_index];
+
+        uint32_t isr = filter->FLTISR;
+


The DFSDM module introduces substantial new logic (compile-time config building, DMA contributions, and IRQ dispatch in handle_irq) but there are no corresponding unit tests under Tests/ (the repo already uses googletest for ADC/DMA/SPI). Adding at least a simulation test covering config validation and IRQ channel decoding would help prevent regressions.

Copilot · 2026-03-30T16:36:51Z

Inc/HALAL/Models/TimerDomain/TimerDomain.hpp

+                        .trgo1 = requests[i].trgo1,
+                        .trgo2 = requests[i].trgo2


In TimerDomain::build(), when allocating Any32bit requests you compute const Entry& e = requests[remaining_requests[i]] but the config copies trgo1/trgo2 from requests[i] instead of e. This will misconfigure triggers whenever remaining_requests[i] != i; use the selected entry (e.trgo1/e.trgo2).

Suggested change

.trgo1 = requests[i].trgo1,

.trgo2 = requests[i].trgo2

.trgo1 = e.trgo1,

.trgo2 = e.trgo2

Copilot · 2026-03-30T16:36:52Z

Inc/HALAL/Services/DFSDM/DFSDM.hpp

+            }
+            cfg.buffer_pos_ini = buffer_pos[cfg.filter];
+            buffer_pos[cfg.filter] += cfg.buffer_size;


buffer_pos_ini is set to 0 for regular conversions, but then it is immediately overwritten unconditionally with buffer_pos[cfg.filter]. This defeats the intent of giving regular conversions the whole buffer starting at 0. Make the second assignment conditional (e.g., else) or otherwise preserve the regular-mode behavior.

Suggested change

}

cfg.buffer_pos_ini = buffer_pos[cfg.filter];

buffer_pos[cfg.filter] += cfg.buffer_size;

// Keep buffer_pos in sync, even though multiple regular channels per filter

// are not allowed by earlier validation.

buffer_pos[cfg.filter] += cfg.buffer_size;

} else {

cfg.buffer_pos_ini = buffer_pos[cfg.filter];

buffer_pos[cfg.filter] += cfg.buffer_size;

}

Copilot · 2026-03-30T16:36:52Z

Inc/HALAL/Services/DFSDM/DFSDM.hpp

+            filter->FLTICR |= DFSDM_FLTICR_CLRROVRF_Msk;
+        }
+        if (isr & DFSDM_FLTISR_JOVRF_Msk) {
+            Instance* inst = channel_instances[filter->FLTJDATAR & DFSDM_FLTJDATAR_JDATACH_Msk];


In the JOVRF handler, filter->FLTJDATAR & DFSDM_FLTJDATAR_JDATACH_Msk is used directly as an index into channel_instances[] without shifting. Like the JEOCF path, this should be mask+shift to obtain the channel number before indexing.

Suggested change

Instance* inst = channel_instances[filter->FLTJDATAR & DFSDM_FLTJDATAR_JDATACH_Msk];

uint32_t jdata = filter->FLTJDATAR;

uint8_t channel = (jdata & DFSDM_FLTJDATAR_JDATACH_Msk) >> DFSDM_FLTJDATAR_JDATACH_Pos;

Instance* inst = channel_instances[channel];

oganigl and others added 30 commits January 28, 2026 18:09

add all enums needed, I hope

90ca98e

CLK finished, half way from finishing DFSDM.HPP

8732116

First total draft of dfsdm finished

3445aa2

Merge branch 'development' into feat/DFSDM

4f13110

fix some errors from the merge, mia culpa

fd1b967

eliminate right bit shift in execution time

894d60e

added some changes to compile clk

e8216f7

change a bit of AF in PB0 for dfsdm_clk_out

5cc4af8

clock works for every possible pin

27f2b93

added a config, you're welcome Boris

71661b1

compiles let's see if it works

7b07dcd

add buffer and callbacks in compile time

342c9a9

some more changes in the dfsdm

6c67c0c

fix some minor errors

12d51ca

add again max_instances

691b396

Add dma safety, not implemented yet

0cb2cbe

Masinstances updated to max_instances

412e133

now the callbacks works

22ab26d

some more more changes

0e0235b

the trigger works gg

fbfc0d6

okay this might work

574abd8

okay dma works, something to look is how to allow to use the 16 entri…

63cb9e8

…es of the DMA without removing double entries with the dfsdm.

dma tested, don't ask how, don't ask why but it works fine. Or at lea…

457a791

…st in my test has worked fine.

Fixed issues with MSVC on windows in tests (#583)

47efb88

* Fixed issues with MSVC on windows * Move implementation into cpp * Return to inlining clz and ctz * fix formatting (hopefully) * more formatting fixes * fix formatting final please

Fix: rcc_enable_timer for scheduler timer (#586)

9cfa240

* Fix: rcc_enable_timer for scheduler timer * formatting nº1

fix(MDMA): Fix, MDMA AHBS is 32-bit only (#588)

b5846fd

victor-Lopez25 and others added 10 commits March 22, 2026 22:32

Fix Scheduler race conditions (#591)

cc4e9bc

Max out ARR for encoder (#587)

24738ff

* Max ARR * fix encoder test * actually fix tests now * fix formatting

Hotfix/sched register b4 start (#593)

5cbb065

Change the frequency if this can be called frequency of the leds (#580)

21bc1b8

merge development to main

c088c60

compiles, but not tested

683b056

OKay tested this works fine with dma and without.

12a4c0f

readme version

0e3d73b

indentation done

8683e31

oganigl linked an issue Mar 26, 2026 that may be closed by this pull request

DFSDM Domain #608

Open

oganigl added 2 commits March 26, 2026 20:40

change start() to static functions

9df3168

add more safety

18705ce

jorgesg82 changed the title ~~Development~~ DFSDM Mar 27, 2026

jorgesg82 assigned oganigl Mar 27, 2026

oganigl and others added 2 commits March 29, 2026 20:26

Merge branch 'development' into feat/DFSDM

2ed7947

change changeset

80be128

oganigl added 5 commits March 29, 2026 20:39

Remove duplicity

c06bd0f

add indentation for 14 time

7af2239

add defines for the simulator

969f5d9

modify stm32.cmake so everyone can use it and not only people with an…

7fc4709

… apple computer ejem

done again changes do to indentation

50cff63

jorgesg82 requested a review from Copilot March 30, 2026 16:28

Copilot started reviewing on behalf of jorgesg82 March 30, 2026 16:30 View session

Copilot AI reviewed Mar 30, 2026

View reviewed changes

	std::array<std::array<uint8_t, 8>, 4> channels_filter = {};
	std::array<std::array<std::size_t, 8>, 4> channels_filter = {};

	uint8_t channel = (data & DFSDM_FLTJDATAR_JDATACH_Msk);
	uint8_t channel = (data & DFSDM_FLTJDATAR_JDATACH_Msk) >> DFSDM_FLTJDATAR_JDATACH_Pos;

		__attribute__((section(".mpu_ram_d1_nc.buffer"))) alignas(32
		) static inline int32_t DFSDM_Buffer_Pool[MAX_BUFFER_SIZE_TOTAL];

-            Instance* inst = channel_instances[filter->FLTJDATAR & DFSDM_FLTJDATAR_JDATACH_Msk];
+            uint32_t jdata = filter->FLTJDATAR;
+            uint8_t channel = (jdata & DFSDM_FLTJDATAR_JDATACH_Msk) >> DFSDM_FLTJDATAR_JDATACH_Pos;
+            Instance* inst = channel_instances[channel];

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oganigl commented Mar 26, 2026

Uh oh!

jorgesg82 commented Mar 27, 2026

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github-actions bot commented Mar 29, 2026

ST-LIB Release Plan

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