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Monitor cache events with samply and use isolation#404

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GuillaumeLagrange merged 5 commits into
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cod-2844-re-enable-runner-isolation-for-samply-profiler
Jun 15, 2026
Merged

Monitor cache events with samply and use isolation#404
GuillaumeLagrange merged 5 commits into
mainfrom
cod-2844-re-enable-runner-isolation-for-samply-profiler

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@greptile-apps

greptile-apps Bot commented Jun 12, 2026

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Greptile Summary

This PR extends the samply wall-time profiler to capture hardware cache/instruction events alongside CPU-cycle sampling, and re-enables systemd-run isolation for samply (previously it had opted out). It also adds a developer convenience script for patching samply and related crates to local checkouts.

  • Cache event PMU encoding (perf_event.rs): adds to_samply_spec() which resolves each PerfEvent to a <name>:<type>:<config> string for samply's SAMPLY_PERF_EVENTS; arch-specific raw configs are provided for Intel x86_64 (Skylake+ perfmon events) and ARMv8 aarch64, with a safe None fallback for unrecognised CPUs and vendors.
  • Samply profiler (samply/mod.rs): removes the requires_isolation → false override so samply now runs inside the same systemd-run isolation scope as perf; wires SAMPLY_PERF_EVENTS from the new API on Linux only.
  • Dev tooling (scripts/samply-dev.sh): new on/off script that appends sentinel-delimited [patch] blocks to Cargo.toml for iterating on samply, framehop, and linux-perf-event-reader locally without touching the committed lockfile.

Confidence Score: 5/5

Safe to merge; the changes are well-scoped and samply degrades gracefully when requested PMU events are unavailable.

The cache event logic is architecturally sound — x86 Intel and aarch64 paths are distinct and have correct fallbacks, and the samply comment confirms graceful degradation. Re-enabling isolation for samply is a deliberate, single-line change. The only findings are minor style concerns (a println! in a diagnostic test and an abbreviated git SHA).

No files require special attention.

Important Files Changed

Filename Overview
crates/runner-shared/src/perf_event.rs Adds to_samply_spec() and arch-specific raw_cache_config() for x86_64 (Intel-only) and aarch64; logic is sound but a diagnostic test uses println! in violation of the no-println! rule.
src/executor/wall_time/profiler/samply/mod.rs Removes the requires_isolation → false override (samply now inherits the default true) and wires SAMPLY_PERF_EVENTS from PerfEvent::to_samply_spec() on Linux; straightforward and safe.
Cargo.toml Bumps samply to a new partial-SHA rev and adds linux-perf-event-reader = "0.10.2" to workspace deps; abbreviated SHA is a minor style inconsistency vs the prior full SHA.
scripts/samply-dev.sh New developer utility that toggles local patch overrides for samply/framehop/linux-perf-event-reader via sentinel-delimited blocks; sentinel regex is correct for POSIX sed BRE.
crates/runner-shared/Cargo.toml Adds linux-perf-event-reader from the workspace dep to runner-shared; no issues.
Cargo.lock Lockfile updated to reflect the new CodSpeedHQ forks of linux-perf-data and linux-perf-event-reader, and the samply-codspeed rev bump; no issues.

Flowchart

%%{init: {'theme': 'neutral'}}%%
flowchart TD
    A[PerfEvent variant] --> B{perf_event_attr}
    B -->|CpuCycles| C["PERF_TYPE_HARDWARE\nPERF_COUNT_HW_CPU_CYCLES"]
    B -->|Instructions| D["PERF_TYPE_HARDWARE\nPERF_COUNT_HW_CPU_INSTRUCTIONS"]
    B -->|L1DCache / L2DCache / CacheMisses| E{raw_cache_config}
    E -->|x86_64 + GenuineIntel| F["PERF_TYPE_RAW\nIntel perfmon code\n(Skylake MEM_*_RETIRED)"]
    E -->|aarch64| G["PERF_TYPE_RAW\nArm architected PMU\n(L1D_CACHE / L1D_CACHE_REFILL / L2D_CACHE_REFILL)"]
    E -->|other arch / non-Intel| H["None → event skipped"]
    C --> I["format: name:type:config_hex"]
    D --> I
    F --> I
    G --> I
    I --> J["SAMPLY_PERF_EVENTS env var\n(comma-separated)"]
    J --> K["samply record\n(degrades gracefully if PMU unavailable)"]
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Reviews (4): Last reviewed commit: "feat: use extra events when using samply..." | Re-trigger Greptile

@codspeed-hq

codspeed-hq Bot commented Jun 12, 2026

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Merging this PR will not alter performance

⚠️ Unknown Walltime execution environment detected

Using the Walltime instrument on standard Hosted Runners will lead to inconsistent data.

For the most accurate results, we recommend using CodSpeed Macro Runners: bare-metal machines fine-tuned for performance measurement consistency.

✅ 7 untouched benchmarks


Comparing cod-2844-re-enable-runner-isolation-for-samply-profiler (9e21a9c) with main (32229fd)

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@GuillaumeLagrange GuillaumeLagrange force-pushed the cod-2844-re-enable-runner-isolation-for-samply-profiler branch from 22d1089 to 8b78457 Compare June 15, 2026 09:29
@GuillaumeLagrange GuillaumeLagrange changed the title feat: use isolation for with samply Monitor cache events with samply and use isolation Jun 15, 2026
@GuillaumeLagrange GuillaumeLagrange changed the base branch from cod-2810-check-samply-possibilitieslimitations-regarding-additional to main June 15, 2026 09:31
@GuillaumeLagrange GuillaumeLagrange force-pushed the cod-2844-re-enable-runner-isolation-for-samply-profiler branch from 8b78457 to f3d930e Compare June 15, 2026 09:58
Comment thread scripts/samply-dev.sh Outdated
@GuillaumeLagrange GuillaumeLagrange force-pushed the cod-2844-re-enable-runner-isolation-for-samply-profiler branch from f3d930e to 9e21a9c Compare June 15, 2026 10:08
@GuillaumeLagrange

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@not-matthias addressing your comments on #400:

  1. Switched to using linux-perf-event-reader to retrieve common perf event attribute types (HARDWARE, RAW, etc)
  2. Documented the source of truth used for the attribute types where relevant, as there are no catalog of perf events available as of today, maybe we'll make one in this repo at some point when we expand the CPU architecture we support

@GuillaumeLagrange GuillaumeLagrange merged commit 9e21a9c into main Jun 15, 2026
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@GuillaumeLagrange GuillaumeLagrange deleted the cod-2844-re-enable-runner-isolation-for-samply-profiler branch June 15, 2026 10:17
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