dt-bindings/arm64: apple: add Neural Engine hardware description - #584
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dt-bindings/arm64: apple: add Neural Engine hardware description#584ctr49 wants to merge 5 commits into
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Document the Apple Neural Engine accelerator found in Apple SoCs. ANE uses three DART IOMMU instances and either one or five power domains, depending on the SoC generation. Assisted-by: ChatGPT:GPT-5.6-Sol Signed-off-by: Christian Tramnitz <christian@tramnitz.com>
Describe the T8103 Neural Engine and its three DART IOMMU instances, along with the power domains required by the accelerator. The register, interrupt and power-domain data are based on Eileen Yoon's earlier T8103 ANE work. Represent the DARTs as normal IOMMU providers instead of exposing their register windows through the ANE node. Link: eiln@6027c18 Assisted-by: ChatGPT:GPT-5.6-Sol Signed-off-by: Christian Tramnitz <christian@tramnitz.com>
Describe the primary T600x Neural Engine and its three DART IOMMU instances on each die. The register, interrupt and power-domain data are derived from Apple DeviceTree data. Do not enable the second ANE power-domain path, which is already marked as disabled on shipping hardware in the existing PMGR description. Assisted-by: ChatGPT:GPT-5.6-Sol Signed-off-by: Christian Tramnitz <christian@tramnitz.com>
Describe the T8112 Neural Engine and its three DART IOMMU instances. The register, interrupt and power-domain data are derived from Apple DeviceTree data. Assisted-by: ChatGPT:GPT-5.6-Sol Signed-off-by: Christian Tramnitz <christian@tramnitz.com>
Describe the T602x Neural Engine and its three DART IOMMU instances. The register, interrupt and power-domain data are derived from Apple DeviceTree data and validated on hardware. Assisted-by: ChatGPT:GPT-5.6-Sol Signed-off-by: Christian Tramnitz <christian@tramnitz.com>
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What is the purpose of this series if a driver is not included? |
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Summary
Add a DeviceTree binding and hardware descriptions for the Apple Neural
Engine (ANE) on T8103, T600x, T8112 and T602x SoCs.
The ANE is described as an NPU device connected to three Apple DART IOMMU
instances. The DARTs are modeled as normal IOMMU providers and referenced
through the ANE
iommusproperty, rather than exposing DART resourcesthrough the accelerator node.
This series contains only hardware description and does not depend on a
particular ANE driver implementation.
SoC support
For T600x, only the primary ANE is described. The existing PMGR description
already marks the second ANE power-domain path as disabled on shipping
hardware, so this series intentionally leaves it disabled.
The historical
apple,always-onworkaround used by earlier out-of-tree ANEwork is also intentionally not carried over.
Data provenance
The T8103 description is based on Eileen Yoon's earlier ANE work, referenced
from the corresponding commit.
T600x, T8112 and T602x register, interrupt and power-domain data are derived
from Apple DeviceTree data.
The T6020/H14G configuration has additionally been runtime-tested on M2 Max
hardware. T600x has not been runtime-tested as part of this series.
Testing
The following checks were run against the series:
dt_binding_checkanddtbs_checkcomplete successfully.checkpatch.pl --strictreports no errors or relevant checks.