Custom Image Downsampling Processor

Verilog custom processor that low-pass filters and downsamples (factor 2) an image, verified against a Python reference using Sum of Squared Differences (SSD).

Built as part of EN3030 — Circuits and Systems Design at the University of Moratuwa.

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The pipeline

   input image                                       output image
   (PNG / JPG)                                      (downsampled
       │                                              by factor 2)
       ▼                                                   ▲
 ┌─────────────┐    ┌─────────────┐    ┌──────────────┐    │
 │ Img         │    │ Verilog     │    │ Img          │    │
 │ generator   │──▶ │ processor   │──▶ │ conversion   │────┘
 │ (Python)    │    │ low-pass +  │    │ (Python)     │
 │             │    │ decimate ×2 │    │              │
 └─────────────┘    └─────────────┘    └──────────────┘
                                              │
                                              ▼
                                       ┌──────────────┐
                                       │ SSD error    │
                                       │ vs Python    │
                                       │ reference    │
                                       └──────────────┘

Each stage is a small, focused script — the Verilog RTL is the centrepiece; the Python tooling exists only to feed and drain it, and to verify correctness.

How it's built

• Filtering — a low-pass kernel runs before decimation to prevent aliasing
• Arithmetic — fixed-point in hardware (small float-vs-fixed differences against the Python reference are expected and measured by SSD)
• Verification — Python computes the canonical downsampled image with the same kernel; SSD between Python and hardware outputs quantifies correctness (lower = better; zero = pixel-identical)

Project structure

custom-image-downsampling-processor/
├─ Img generator/        # Generate input test images / pixel vectors (Python)
├─ Processor/            # Vivado project + Verilog RTL (SRC/)
├─ Img conversion/       # Convert simulation output back to an image (Python)
├─ Error calculation/    # Compute SSD between hardware and Python reference
├─ Compiler/             # Assembly / hex helpers
├─ LICENSE
└─ README.md

Run the flow

1. Generate input image vectors

cd "Img generator"
python Img_gen.py

Produces output.txt with pixel data suitable as testbench input.

2. Simulate the processor

Vivado (preferred — project files included):

1. Open Processor/Processor.xpr
2. Run Simulation → Run Behavioral Simulation
3. Export the result to a .txt file

Icarus Verilog (lightweight alternative):

iverilog -o build/downsampler.vvp Processor/SRC/*.v
vvp build/downsampler.vvp > build/sim_output.txt

3. Reconstruct the output image

cd "Img conversion"
python Conversion.py

Converts the simulation dump (imgdata.txt) into a viewable image (img.jpg).

4. Compute SSD error

cd "Error calculation"
python "SSD error.py"

Outputs SSD = <value>. Lower is better; zero means the hardware matches the Python reference exactly.

Prerequisites

• Verilog — Vivado (recommended) or Icarus Verilog
• Python 3.8+ — numpy, Pillow, matplotlib (pip install numpy pillow matplotlib)

License

MIT — see anjanamb.github.io for more projects.