From 06a2103266fc38657deaad9017cf21b37d9bcb72 Mon Sep 17 00:00:00 2001 From: Mattia Moffa Date: Wed, 15 Jul 2026 20:23:55 +0200 Subject: [PATCH] Regenerate armasm after wolfssl/scripts#625 --- wolfcrypt/src/port/arm/thumb2-aes-asm_c.c | 1858 +- wolfcrypt/src/port/arm/thumb2-chacha-asm_c.c | 363 +- wolfcrypt/src/port/arm/thumb2-curve25519_c.c | 2631 +- wolfcrypt/src/port/arm/thumb2-mlkem-asm_c.c | 478 +- .../src/port/arm/thumb2-poly1305-asm_c.c | 319 +- wolfcrypt/src/port/arm/thumb2-sha256-asm_c.c | 1054 +- wolfcrypt/src/port/arm/thumb2-sha3-asm_c.c | 349 +- wolfcrypt/src/port/arm/thumb2-sha512-asm_c.c | 1237 +- wolfcrypt/src/sp_cortexm.c | 33523 +++++++++------- 9 files changed, 23728 insertions(+), 18084 deletions(-) diff --git a/wolfcrypt/src/port/arm/thumb2-aes-asm_c.c b/wolfcrypt/src/port/arm/thumb2-aes-asm_c.c index b77be89e737..b011e4e07f7 100644 --- a/wolfcrypt/src/port/arm/thumb2-aes-asm_c.c +++ b/wolfcrypt/src/port/arm/thumb2-aes-asm_c.c @@ -50,6 +50,14 @@ #ifndef NO_AES #include +/* Blocks must be inlined when registers are not assigned to + * variables as the block functions take values in registers + * that are not parameter registers. */ +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG +#undef WOLFSSL_ARMASM_AES_BLOCK_INLINE +#define WOLFSSL_ARMASM_AES_BLOCK_INLINE +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + #ifdef HAVE_AES_DECRYPT XALIGNED(8) static const word32 L_AES_Thumb2_td_data[] = { 0x5051f4a7, 0x537e4165, 0xc31a17a4, 0x963a275e, @@ -216,25 +224,31 @@ WC_OMIT_FRAME_POINTER void AES_invert_key(unsigned char* ks, word32 rounds) register word32* L_AES_Thumb2_td_c __asm__ ("r3") = (word32*)L_AES_Thumb2_td; #else - register word32* L_AES_Thumb2_te_c = (word32*)L_AES_Thumb2_te; - register word32* L_AES_Thumb2_td_c = (word32*)L_AES_Thumb2_td; + void* L_asm_args[4] = {(void*)(size_t)ks, (void*)(size_t)rounds, + (void*)(size_t)L_AES_Thumb2_te, (void*)(size_t)L_AES_Thumb2_td + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "MOV r12, %[L_AES_Thumb2_te]\n\t" - "MOV lr, %[L_AES_Thumb2_td]\n\t" - "ADD r10, %[ks], %[rounds], LSL #4\n\t" - "MOV r11, %[rounds]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "MOV r12, r2\n\t" + "MOV lr, r3\n\t" + "ADD r10, r0, r1, LSL #4\n\t" + "MOV r11, r1\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_AES_invert_key_loop:\n\t" #else "L_AES_invert_key_loop_%=:\n\t" #endif - "LDM %[ks], {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" "LDM r10, {r6, r7, r8, r9}\n\t" "STM r10, {r2, r3, r4, r5}\n\t" - "STM %[ks]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r6, r7, r8, r9}\n\t" "SUBS r11, r11, #2\n\t" "SUB r10, r10, #16\n\t" #if defined(__GNUC__) @@ -244,16 +258,16 @@ WC_OMIT_FRAME_POINTER void AES_invert_key(unsigned char* ks, word32 rounds) #else "BNE.N L_AES_invert_key_loop_%=\n\t" #endif - "SUB %[ks], %[ks], %[rounds], LSL #3\n\t" - "ADD %[ks], %[ks], #16\n\t" - "SUB r11, %[rounds], #1\n\t" + "SUB r0, r0, r1, LSL #3\n\t" + "ADD r0, r0, #16\n\t" + "SUB r11, r1, #1\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_AES_invert_key_mix_loop:\n\t" #else "L_AES_invert_key_mix_loop_%=:\n\t" #endif - "LDM %[ks], {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" "UBFX r6, r2, #0, #8\n\t" "UBFX r7, r2, #8, #8\n\t" "UBFX r8, r2, #16, #8\n\t" @@ -269,7 +283,7 @@ WC_OMIT_FRAME_POINTER void AES_invert_key(unsigned char* ks, word32 rounds) "EOR r8, r8, r6, ROR #16\n\t" "EOR r8, r8, r7, ROR #8\n\t" "EOR r8, r8, r9, ROR #24\n\t" - "STR r8, [%[ks]], #4\n\t" + "STR r8, [r0], #4\n\t" "UBFX r6, r3, #0, #8\n\t" "UBFX r7, r3, #8, #8\n\t" "UBFX r8, r3, #16, #8\n\t" @@ -285,7 +299,7 @@ WC_OMIT_FRAME_POINTER void AES_invert_key(unsigned char* ks, word32 rounds) "EOR r8, r8, r6, ROR #16\n\t" "EOR r8, r8, r7, ROR #8\n\t" "EOR r8, r8, r9, ROR #24\n\t" - "STR r8, [%[ks]], #4\n\t" + "STR r8, [r0], #4\n\t" "UBFX r6, r4, #0, #8\n\t" "UBFX r7, r4, #8, #8\n\t" "UBFX r8, r4, #16, #8\n\t" @@ -301,7 +315,7 @@ WC_OMIT_FRAME_POINTER void AES_invert_key(unsigned char* ks, word32 rounds) "EOR r8, r8, r6, ROR #16\n\t" "EOR r8, r8, r7, ROR #8\n\t" "EOR r8, r8, r9, ROR #24\n\t" - "STR r8, [%[ks]], #4\n\t" + "STR r8, [r0], #4\n\t" "UBFX r6, r5, #0, #8\n\t" "UBFX r7, r5, #8, #8\n\t" "UBFX r8, r5, #16, #8\n\t" @@ -317,7 +331,7 @@ WC_OMIT_FRAME_POINTER void AES_invert_key(unsigned char* ks, word32 rounds) "EOR r8, r8, r6, ROR #16\n\t" "EOR r8, r8, r7, ROR #8\n\t" "EOR r8, r8, r9, ROR #24\n\t" - "STR r8, [%[ks]], #4\n\t" + "STR r8, [r0], #4\n\t" "SUBS r11, r11, #1\n\t" #if defined(__GNUC__) "BNE L_AES_invert_key_mix_loop_%=\n\t" @@ -326,20 +340,28 @@ WC_OMIT_FRAME_POINTER void AES_invert_key(unsigned char* ks, word32 rounds) #else "BNE.W L_AES_invert_key_mix_loop_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [ks] "+r" (ks), [rounds] "+r" (rounds), [L_AES_Thumb2_te] "+r" (L_AES_Thumb2_te_c), [L_AES_Thumb2_td] "+r" (L_AES_Thumb2_td_c) : + : "memory", "cc", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", + "r10", "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [ks] "r" (ks), [rounds] "r" (rounds), - [L_AES_Thumb2_te] "r" (L_AES_Thumb2_te_c), - [L_AES_Thumb2_td] "r" (L_AES_Thumb2_td_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", - "r10", "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + ks = (unsigned char*)(size_t)L_asm_args[0]; + rounds = (word32)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* HAVE_AES_DECRYPT */ @@ -369,14 +391,21 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, register word32* L_AES_Thumb2_rcon_c __asm__ ("r4") = (word32*)&L_AES_Thumb2_rcon; #else - register word32* L_AES_Thumb2_te_c = (word32*)L_AES_Thumb2_te; - register word32* L_AES_Thumb2_rcon_c = (word32*)&L_AES_Thumb2_rcon; + void* L_asm_args[5] = {(void*)(size_t)key, (void*)(size_t)len, + (void*)(size_t)ks, (void*)(size_t)L_AES_Thumb2_te, + (void*)(size_t)&L_AES_Thumb2_rcon + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "MOV r10, %[L_AES_Thumb2_te]\n\t" - "MOV lr, %[L_AES_Thumb2_rcon]\n\t" - "CMP %[len], #0x80\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "MOV r10, r3\n\t" + "MOV lr, r4\n\t" + "CMP r1, #0x80\n\t" #if defined(__GNUC__) "BEQ L_AES_set_encrypt_key_start_128_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -384,7 +413,7 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, #else "BEQ.W L_AES_set_encrypt_key_start_128_%=\n\t" #endif - "CMP %[len], #0xc0\n\t" + "CMP r1, #0xc0\n\t" #if defined(__GNUC__) "BEQ L_AES_set_encrypt_key_start_192_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -392,25 +421,25 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, #else "BEQ.W L_AES_set_encrypt_key_start_192_%=\n\t" #endif - "LDR r4, [%[key]]\n\t" - "LDR r5, [%[key], #4]\n\t" - "LDR r6, [%[key], #8]\n\t" - "LDR r7, [%[key], #12]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STM %[ks]!, {r4, r5, r6, r7}\n\t" - "LDR r4, [%[key], #16]\n\t" - "LDR r5, [%[key], #20]\n\t" - "LDR r6, [%[key], #24]\n\t" - "LDR r7, [%[key], #28]\n\t" + "STM r2!, {r4, r5, r6, r7}\n\t" + "LDR r4, [r0, #16]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STM %[ks], {r4, r5, r6, r7}\n\t" - "SUB %[ks], %[ks], #16\n\t" + "STM r2, {r4, r5, r6, r7}\n\t" + "SUB r2, r2, #16\n\t" "MOV r12, #6\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -429,16 +458,16 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, "EOR r3, r7, r4, LSL #8\n\t" "EOR r3, r3, r5, LSL #16\n\t" "EOR r3, r3, r6, LSL #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "EOR r4, r4, r3\n\t" "LDM lr!, {r3}\n\t" "EOR r4, r4, r3\n\t" "EOR r5, r5, r4\n\t" "EOR r6, r6, r5\n\t" "EOR r7, r7, r6\n\t" - "ADD %[ks], %[ks], #16\n\t" - "STM %[ks], {r4, r5, r6, r7}\n\t" - "SUB %[ks], %[ks], #16\n\t" + "ADD r2, r2, #16\n\t" + "STM r2, {r4, r5, r6, r7}\n\t" + "SUB r2, r2, #16\n\t" "UBFX r4, r7, #8, #8\n\t" "UBFX r5, r7, #16, #8\n\t" "LSR r6, r7, #24\n\t" @@ -450,14 +479,14 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, "EOR r3, r3, r4, LSL #8\n\t" "EOR r3, r3, r5, LSL #16\n\t" "EOR r3, r3, r6, LSL #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "EOR r4, r4, r3\n\t" "EOR r5, r5, r4\n\t" "EOR r6, r6, r5\n\t" "EOR r7, r7, r6\n\t" - "ADD %[ks], %[ks], #16\n\t" - "STM %[ks], {r4, r5, r6, r7}\n\t" - "SUB %[ks], %[ks], #16\n\t" + "ADD r2, r2, #16\n\t" + "STM r2, {r4, r5, r6, r7}\n\t" + "SUB r2, r2, #16\n\t" "SUBS r12, r12, #1\n\t" #if defined(__GNUC__) "BNE L_AES_set_encrypt_key_loop_256_%=\n\t" @@ -477,16 +506,16 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, "EOR r3, r7, r4, LSL #8\n\t" "EOR r3, r3, r5, LSL #16\n\t" "EOR r3, r3, r6, LSL #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "EOR r4, r4, r3\n\t" "LDM lr!, {r3}\n\t" "EOR r4, r4, r3\n\t" "EOR r5, r5, r4\n\t" "EOR r6, r6, r5\n\t" "EOR r7, r7, r6\n\t" - "ADD %[ks], %[ks], #16\n\t" - "STM %[ks], {r4, r5, r6, r7}\n\t" - "SUB %[ks], %[ks], #16\n\t" + "ADD r2, r2, #16\n\t" + "STM r2, {r4, r5, r6, r7}\n\t" + "SUB r2, r2, #16\n\t" #if defined(__GNUC__) "B L_AES_set_encrypt_key_end_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -500,20 +529,20 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, #else "L_AES_set_encrypt_key_start_192_%=:\n\t" #endif - "LDR r4, [%[key]]\n\t" - "LDR r5, [%[key], #4]\n\t" - "LDR r6, [%[key], #8]\n\t" - "LDR r7, [%[key], #12]\n\t" - "LDR r8, [%[key], #16]\n\t" - "LDR r9, [%[key], #20]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r8, [r0, #16]\n\t" + "LDR r9, [r0, #20]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" "REV r8, r8\n\t" "REV r9, r9\n\t" - "STM %[ks], {r4, r5, r6, r7}\n\t" - "STRD r8, r9, [%[ks], #16]\n\t" + "STM r2, {r4, r5, r6, r7}\n\t" + "STRD r8, r9, [r2, #16]\n\t" "MOV r7, r9\n\t" "MOV r12, #7\n\t" "\n" @@ -533,7 +562,7 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, "EOR r3, r9, r4, LSL #8\n\t" "EOR r3, r3, r5, LSL #16\n\t" "EOR r3, r3, r6, LSL #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r2!, {r4, r5, r6, r7, r8, r9}\n\t" "EOR r4, r4, r3\n\t" "LDM lr!, {r3}\n\t" "EOR r4, r4, r3\n\t" @@ -542,7 +571,7 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, "EOR r7, r7, r6\n\t" "EOR r8, r8, r7\n\t" "EOR r9, r9, r8\n\t" - "STM %[ks], {r4, r5, r6, r7, r8, r9}\n\t" + "STM r2, {r4, r5, r6, r7, r8, r9}\n\t" "SUBS r12, r12, #1\n\t" #if defined(__GNUC__) "BNE L_AES_set_encrypt_key_loop_192_%=\n\t" @@ -562,14 +591,14 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, "EOR r3, r9, r4, LSL #8\n\t" "EOR r3, r3, r5, LSL #16\n\t" "EOR r3, r3, r6, LSL #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r2!, {r4, r5, r6, r7, r8, r9}\n\t" "EOR r4, r4, r3\n\t" "LDM lr!, {r3}\n\t" "EOR r4, r4, r3\n\t" "EOR r5, r5, r4\n\t" "EOR r6, r6, r5\n\t" "EOR r7, r7, r6\n\t" - "STM %[ks], {r4, r5, r6, r7}\n\t" + "STM r2, {r4, r5, r6, r7}\n\t" #if defined(__GNUC__) "B L_AES_set_encrypt_key_end_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -583,15 +612,15 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, #else "L_AES_set_encrypt_key_start_128_%=:\n\t" #endif - "LDR r4, [%[key]]\n\t" - "LDR r5, [%[key], #4]\n\t" - "LDR r6, [%[key], #8]\n\t" - "LDR r7, [%[key], #12]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STM %[ks], {r4, r5, r6, r7}\n\t" + "STM r2, {r4, r5, r6, r7}\n\t" "MOV r12, #10\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -610,14 +639,14 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, "EOR r3, r7, r4, LSL #8\n\t" "EOR r3, r3, r5, LSL #16\n\t" "EOR r3, r3, r6, LSL #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "EOR r4, r4, r3\n\t" "LDM lr!, {r3}\n\t" "EOR r4, r4, r3\n\t" "EOR r5, r5, r4\n\t" "EOR r6, r6, r5\n\t" "EOR r7, r7, r6\n\t" - "STM %[ks], {r4, r5, r6, r7}\n\t" + "STM r2, {r4, r5, r6, r7}\n\t" "SUBS r12, r12, #1\n\t" #if defined(__GNUC__) "BNE L_AES_set_encrypt_key_loop_128_%=\n\t" @@ -632,19 +661,28 @@ WC_OMIT_FRAME_POINTER void AES_set_encrypt_key(const unsigned char* key, #else "L_AES_set_encrypt_key_end_%=:\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [key] "+r" (key), [len] "+r" (len), [ks] "+r" (ks), [L_AES_Thumb2_te] "+r" (L_AES_Thumb2_te_c), [L_AES_Thumb2_rcon] "+r" (L_AES_Thumb2_rcon_c) : + : "memory", "cc", "r12", "lr", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [key] "r" (key), [len] "r" (len), [ks] "r" (ks), - [L_AES_Thumb2_te] "r" (L_AES_Thumb2_te_c), - [L_AES_Thumb2_rcon] "r" (L_AES_Thumb2_rcon_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r12", "lr", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + key = (const unsigned char*)(size_t)L_asm_args[0]; + len = (word32)(size_t)L_asm_args[1]; + ks = (unsigned char*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_ARMASM_AES_BLOCK_INLINE @@ -676,10 +714,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "LSR r11, r4, #24\n\t" "UBFX lr, r6, #8, #8\n\t" "UBFX r2, r7, #0, #8\n\t" - "LDR r8, [%[te], r8, LSL #2]\n\t" - "LDR r11, [%[te], r11, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r8, [r0, r8, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "UBFX r9, r6, #16, #8\n\t" "EOR r8, r8, r11, ROR #24\n\t" "LSR r11, r5, #24\n\t" @@ -687,10 +725,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "UBFX lr, r7, #8, #8\n\t" "EOR r8, r8, r2, ROR #16\n\t" "UBFX r2, r4, #0, #8\n\t" - "LDR r9, [%[te], r9, LSL #2]\n\t" - "LDR r11, [%[te], r11, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r9, [r0, r9, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "UBFX r10, r7, #16, #8\n\t" "EOR r9, r9, r11, ROR #24\n\t" "LSR r11, r6, #24\n\t" @@ -698,10 +736,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "UBFX lr, r4, #8, #8\n\t" "EOR r9, r9, r2, ROR #16\n\t" "UBFX r2, r5, #0, #8\n\t" - "LDR r10, [%[te], r10, LSL #2]\n\t" - "LDR r11, [%[te], r11, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r10, [r0, r10, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "UBFX r6, r6, #0, #8\n\t" "EOR r10, r10, r11, ROR #24\n\t" "UBFX r11, r4, #16, #8\n\t" @@ -709,12 +747,12 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "LSR lr, r7, #24\n\t" "EOR r10, r10, r2, ROR #16\n\t" "UBFX r2, r5, #8, #8\n\t" - "LDR r6, [%[te], r6, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r11, [%[te], r11, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r6, [r0, r6, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -726,10 +764,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "LSR r7, r8, #24\n\t" "UBFX lr, r10, #8, #8\n\t" "UBFX r2, r11, #0, #8\n\t" - "LDR r4, [%[te], r4, LSL #2]\n\t" - "LDR r7, [%[te], r7, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r4, [r0, r4, LSL #2]\n\t" + "LDR r7, [r0, r7, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "UBFX r5, r10, #16, #8\n\t" "EOR r4, r4, r7, ROR #24\n\t" "LSR r7, r9, #24\n\t" @@ -737,10 +775,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "UBFX lr, r11, #8, #8\n\t" "EOR r4, r4, r2, ROR #16\n\t" "UBFX r2, r8, #0, #8\n\t" - "LDR r5, [%[te], r5, LSL #2]\n\t" - "LDR r7, [%[te], r7, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r5, [r0, r5, LSL #2]\n\t" + "LDR r7, [r0, r7, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "UBFX r6, r11, #16, #8\n\t" "EOR r5, r5, r7, ROR #24\n\t" "LSR r7, r10, #24\n\t" @@ -748,10 +786,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "UBFX lr, r8, #8, #8\n\t" "EOR r5, r5, r2, ROR #16\n\t" "UBFX r2, r9, #0, #8\n\t" - "LDR r6, [%[te], r6, LSL #2]\n\t" - "LDR r7, [%[te], r7, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r6, [r0, r6, LSL #2]\n\t" + "LDR r7, [r0, r7, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "UBFX r10, r10, #0, #8\n\t" "EOR r6, r6, r7, ROR #24\n\t" "UBFX r7, r8, #16, #8\n\t" @@ -759,12 +797,12 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "LSR lr, r11, #24\n\t" "EOR r6, r6, r2, ROR #16\n\t" "UBFX r2, r9, #8, #8\n\t" - "LDR r10, [%[te], r10, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r7, [%[te], r7, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r10, [r0, r10, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r7, [r0, r7, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -772,7 +810,7 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "SUBS %[nr], %[nr], #1\n\t" + "SUBS r1, r1, #1\n\t" #if defined(__GNUC__) "BNE L_AES_encrypt_block_nr_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -784,10 +822,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "LSR r11, r4, #24\n\t" "UBFX lr, r6, #8, #8\n\t" "UBFX r2, r7, #0, #8\n\t" - "LDR r8, [%[te], r8, LSL #2]\n\t" - "LDR r11, [%[te], r11, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r8, [r0, r8, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "UBFX r9, r6, #16, #8\n\t" "EOR r8, r8, r11, ROR #24\n\t" "LSR r11, r5, #24\n\t" @@ -795,10 +833,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "UBFX lr, r7, #8, #8\n\t" "EOR r8, r8, r2, ROR #16\n\t" "UBFX r2, r4, #0, #8\n\t" - "LDR r9, [%[te], r9, LSL #2]\n\t" - "LDR r11, [%[te], r11, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r9, [r0, r9, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "UBFX r10, r7, #16, #8\n\t" "EOR r9, r9, r11, ROR #24\n\t" "LSR r11, r6, #24\n\t" @@ -806,10 +844,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "UBFX lr, r4, #8, #8\n\t" "EOR r9, r9, r2, ROR #16\n\t" "UBFX r2, r5, #0, #8\n\t" - "LDR r10, [%[te], r10, LSL #2]\n\t" - "LDR r11, [%[te], r11, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r10, [r0, r10, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "UBFX r6, r6, #0, #8\n\t" "EOR r10, r10, r11, ROR #24\n\t" "UBFX r11, r4, #16, #8\n\t" @@ -817,12 +855,12 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "LSR lr, r7, #24\n\t" "EOR r10, r10, r2, ROR #16\n\t" "UBFX r2, r5, #8, #8\n\t" - "LDR r6, [%[te], r6, LSL #2]\n\t" - "LDR lr, [%[te], lr, LSL #2]\n\t" - "LDR r11, [%[te], r11, LSL #2]\n\t" - "LDR r2, [%[te], r2, LSL #2]\n\t" + "LDR r6, [r0, r6, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -834,10 +872,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "UBFX r7, r10, #8, #8\n\t" "UBFX lr, r9, #16, #8\n\t" "LSR r2, r8, #24\n\t" - "LDRB r4, [%[te], r4, LSL #2]\n\t" - "LDRB r7, [%[te], r7, LSL #2]\n\t" - "LDRB lr, [%[te], lr, LSL #2]\n\t" - "LDRB r2, [%[te], r2, LSL #2]\n\t" + "LDRB r4, [r0, r4, LSL #2]\n\t" + "LDRB r7, [r0, r7, LSL #2]\n\t" + "LDRB lr, [r0, lr, LSL #2]\n\t" + "LDRB r2, [r0, r2, LSL #2]\n\t" "UBFX r5, r8, #0, #8\n\t" "EOR r4, r4, r7, LSL #8\n\t" "UBFX r7, r11, #8, #8\n\t" @@ -845,10 +883,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "UBFX lr, r10, #16, #8\n\t" "EOR r4, r4, r2, LSL #24\n\t" "LSR r2, r9, #24\n\t" - "LDRB r5, [%[te], r5, LSL #2]\n\t" - "LDRB r7, [%[te], r7, LSL #2]\n\t" - "LDRB lr, [%[te], lr, LSL #2]\n\t" - "LDRB r2, [%[te], r2, LSL #2]\n\t" + "LDRB r5, [r0, r5, LSL #2]\n\t" + "LDRB r7, [r0, r7, LSL #2]\n\t" + "LDRB lr, [r0, lr, LSL #2]\n\t" + "LDRB r2, [r0, r2, LSL #2]\n\t" "UBFX r6, r9, #0, #8\n\t" "EOR r5, r5, r7, LSL #8\n\t" "UBFX r7, r8, #8, #8\n\t" @@ -856,10 +894,10 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "UBFX lr, r11, #16, #8\n\t" "EOR r5, r5, r2, LSL #24\n\t" "LSR r2, r10, #24\n\t" - "LDRB r6, [%[te], r6, LSL #2]\n\t" - "LDRB r7, [%[te], r7, LSL #2]\n\t" - "LDRB lr, [%[te], lr, LSL #2]\n\t" - "LDRB r2, [%[te], r2, LSL #2]\n\t" + "LDRB r6, [r0, r6, LSL #2]\n\t" + "LDRB r7, [r0, r7, LSL #2]\n\t" + "LDRB lr, [r0, lr, LSL #2]\n\t" + "LDRB r2, [r0, r2, LSL #2]\n\t" "LSR r11, r11, #24\n\t" "EOR r6, r6, r7, LSL #8\n\t" "UBFX r7, r10, #0, #8\n\t" @@ -867,12 +905,12 @@ WC_OMIT_FRAME_POINTER void AES_encrypt_block(const word32* te, int nr, int len, "UBFX lr, r9, #8, #8\n\t" "EOR r6, r6, r2, LSL #24\n\t" "UBFX r2, r8, #16, #8\n\t" - "LDRB r11, [%[te], r11, LSL #2]\n\t" - "LDRB r7, [%[te], r7, LSL #2]\n\t" - "LDRB lr, [%[te], lr, LSL #2]\n\t" - "LDRB r2, [%[te], r2, LSL #2]\n\t" + "LDRB r11, [r0, r11, LSL #2]\n\t" + "LDRB r7, [r0, r7, LSL #2]\n\t" + "LDRB lr, [r0, lr, LSL #2]\n\t" + "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -922,18 +960,22 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, register word32* L_AES_Thumb2_te_ecb_c __asm__ ("r5") = (word32*)L_AES_Thumb2_te_ecb; #else - register word32* L_AES_Thumb2_te_ecb_c = (word32*)L_AES_Thumb2_te_ecb; + void* L_asm_args[6] = {(void*)(size_t)in, (void*)(size_t)out, + (void*)(size_t)len, (void*)(size_t)ks, (void*)(size_t)nr, + (void*)(size_t)L_AES_Thumb2_te_ecb + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "MOV lr, %[in]\n\t" - "MOV r0, %[L_AES_Thumb2_te_ecb]\n\t" -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4, r5}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "MOV lr, r0\n\t" + "MOV r0, r5\n\t" "MOV r12, r4\n\t" -#else - "MOV r12, %[nr]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - "PUSH {%[ks]}\n\t" + "PUSH {r3}\n\t" "CMP r12, #10\n\t" #if defined(__GNUC__) "BEQ L_AES_ECB_encrypt_start_block_128_%=\n\t" @@ -964,8 +1006,8 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "PUSH {r1, %[len], lr}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "PUSH {r1, r2, lr}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -1023,7 +1065,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -1073,7 +1115,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -1131,7 +1173,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -1181,7 +1223,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -1190,19 +1232,19 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" - "SUBS %[len], %[len], #16\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_ECB_encrypt_loop_block_256_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -1237,8 +1279,8 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "PUSH {r1, %[len], lr}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "PUSH {r1, r2, lr}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -1296,7 +1338,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -1346,7 +1388,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -1404,7 +1446,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -1454,7 +1496,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -1463,19 +1505,19 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" - "SUBS %[len], %[len], #16\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_ECB_encrypt_loop_block_192_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -1510,8 +1552,8 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "PUSH {r1, %[len], lr}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "PUSH {r1, r2, lr}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -1569,7 +1611,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -1619,7 +1661,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -1677,7 +1719,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -1727,7 +1769,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -1736,19 +1778,19 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" - "SUBS %[len], %[len], #16\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_ECB_encrypt_loop_block_128_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -1762,18 +1804,30 @@ WC_OMIT_FRAME_POINTER void AES_ECB_encrypt(const unsigned char* in, #else "L_AES_ECB_encrypt_end_%=:\n\t" #endif - "POP {%[ks]}\n\t" + "POP {r3}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4, r5}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [in] "+r" (in), [out] "+r" (out), [len] "+r" (len), [ks] "+r" (ks), [nr] "+r" (nr), [L_AES_Thumb2_te_ecb] "+r" (L_AES_Thumb2_te_ecb_c) : + : "memory", "cc", "r12", "lr", "r6", "r7", "r8", "r9", "r10", "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [in] "r" (in), [out] "r" (out), [len] "r" (len), [ks] "r" (ks), - [nr] "r" (nr), [L_AES_Thumb2_te_ecb] "r" (L_AES_Thumb2_te_ecb_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r12", "lr", "r6", "r7", "r8", "r9", "r10", "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + in = (const unsigned char*)(size_t)L_asm_args[0]; + out = (unsigned char*)(size_t)L_asm_args[1]; + len = (unsigned long)(size_t)L_asm_args[2]; + ks = (const unsigned char*)(size_t)L_asm_args[3]; + nr = (int)(size_t)L_asm_args[4]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* HAVE_AESCCM || HAVE_AESGCM || WOLFSSL_AES_DIRECT || @@ -1804,24 +1858,24 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, register word32* L_AES_Thumb2_te_ecb_c __asm__ ("r6") = (word32*)L_AES_Thumb2_te_ecb; #else - register word32* L_AES_Thumb2_te_ecb_c = (word32*)L_AES_Thumb2_te_ecb; + void* L_asm_args[7] = {(void*)(size_t)in, (void*)(size_t)out, + (void*)(size_t)len, (void*)(size_t)ks, (void*)(size_t)nr, + (void*)(size_t)iv, (void*)(size_t)L_AES_Thumb2_te_ecb + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, r4\n\t" -#else - "MOV r8, %[nr]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG "MOV r9, r5\n\t" -#else - "MOV r9, %[iv]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - "MOV lr, %[in]\n\t" - "MOV r0, %[L_AES_Thumb2_te_ecb]\n\t" + "MOV lr, r0\n\t" + "MOV r0, r6\n\t" "LDM r9, {r4, r5, r6, r7}\n\t" - "PUSH {%[ks], r9}\n\t" + "PUSH {r3, r9}\n\t" "CMP r8, #10\n\t" #if defined(__GNUC__) "BEQ L_AES_CBC_encrypt_start_block_128_%=\n\t" @@ -1852,8 +1906,8 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "PUSH {r1, %[len], lr}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "PUSH {r1, r2, lr}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -1915,7 +1969,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -1965,7 +2019,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -2023,7 +2077,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -2073,7 +2127,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -2082,19 +2136,19 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" - "SUBS %[len], %[len], #16\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_CBC_encrypt_loop_block_256_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2129,8 +2183,8 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "PUSH {r1, %[len], lr}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "PUSH {r1, r2, lr}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -2192,7 +2246,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -2242,7 +2296,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -2300,7 +2354,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -2350,7 +2404,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -2359,19 +2413,19 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" - "SUBS %[len], %[len], #16\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_CBC_encrypt_loop_block_192_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2406,8 +2460,8 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "PUSH {r1, %[len], lr}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "PUSH {r1, r2, lr}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -2469,7 +2523,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -2519,7 +2573,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -2577,7 +2631,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -2627,7 +2681,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -2636,19 +2690,19 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" - "SUBS %[len], %[len], #16\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_CBC_encrypt_loop_block_128_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2662,21 +2716,33 @@ WC_OMIT_FRAME_POINTER void AES_CBC_encrypt(const unsigned char* in, #else "L_AES_CBC_encrypt_end_%=:\n\t" #endif - "POP {%[ks], r9}\n\t" + "POP {r3, r9}\n\t" "STM r9, {r4, r5, r6, r7}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [in] "+r" (in), [out] "+r" (out), [len] "+r" (len), [ks] "+r" (ks), [nr] "+r" (nr), [iv] "+r" (iv), [L_AES_Thumb2_te_ecb] "+r" (L_AES_Thumb2_te_ecb_c) : + : "memory", "cc", "r12", "lr", "r7", "r8", "r9", "r10", "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [in] "r" (in), [out] "r" (out), [len] "r" (len), [ks] "r" (ks), - [nr] "r" (nr), [iv] "r" (iv), - [L_AES_Thumb2_te_ecb] "r" (L_AES_Thumb2_te_ecb_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r12", "lr", "r7", "r8", "r9", "r10", "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + in = (const unsigned char*)(size_t)L_asm_args[0]; + out = (unsigned char*)(size_t)L_asm_args[1]; + len = (unsigned long)(size_t)L_asm_args[2]; + ks = (const unsigned char*)(size_t)L_asm_args[3]; + nr = (int)(size_t)L_asm_args[4]; + iv = (unsigned char*)(size_t)L_asm_args[5]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* HAVE_AES_CBC */ @@ -2707,29 +2773,29 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, register word32* L_AES_Thumb2_te_ctr_c __asm__ ("r6") = (word32*)L_AES_Thumb2_te_ctr; #else - register word32* L_AES_Thumb2_te_ctr_c = (word32*)L_AES_Thumb2_te_ctr; + void* L_asm_args[7] = {(void*)(size_t)in, (void*)(size_t)out, + (void*)(size_t)len, (void*)(size_t)ks, (void*)(size_t)nr, + (void*)(size_t)ctr, (void*)(size_t)L_AES_Thumb2_te_ctr + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r12, r4\n\t" -#else - "MOV r12, %[nr]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG "MOV r8, r5\n\t" -#else - "MOV r8, %[ctr]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - "MOV lr, %[in]\n\t" - "MOV r0, %[L_AES_Thumb2_te_ctr]\n\t" + "MOV lr, r0\n\t" + "MOV r0, r6\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" "STM r8, {r4, r5, r6, r7}\n\t" - "PUSH {%[ks], r8}\n\t" + "PUSH {r3, r8}\n\t" "CMP r12, #10\n\t" #if defined(__GNUC__) "BEQ L_AES_CTR_encrypt_start_block_128_%=\n\t" @@ -2752,14 +2818,14 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, #else "L_AES_CTR_encrypt_loop_block_256_%=:\n\t" #endif - "PUSH {r1, %[len], lr}\n\t" + "PUSH {r1, r2, lr}\n\t" "LDR lr, [sp, #16]\n\t" "ADDS r11, r7, #1\n\t" "ADCS r10, r6, #0\n\t" "ADCS r9, r5, #0\n\t" "ADC r8, r4, #0\n\t" "STM lr, {r8, r9, r10, r11}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -2817,7 +2883,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -2867,7 +2933,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -2925,7 +2991,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -2975,7 +3041,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -2984,8 +3050,8 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -2999,14 +3065,14 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" "LDR r8, [sp, #4]\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" - "SUBS %[len], %[len], #16\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_CTR_encrypt_loop_block_256_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -3033,14 +3099,14 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, #else "L_AES_CTR_encrypt_loop_block_192_%=:\n\t" #endif - "PUSH {r1, %[len], lr}\n\t" + "PUSH {r1, r2, lr}\n\t" "LDR lr, [sp, #16]\n\t" "ADDS r11, r7, #1\n\t" "ADCS r10, r6, #0\n\t" "ADCS r9, r5, #0\n\t" "ADC r8, r4, #0\n\t" "STM lr, {r8, r9, r10, r11}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -3098,7 +3164,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -3148,7 +3214,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -3206,7 +3272,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -3256,7 +3322,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -3265,8 +3331,8 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -3280,14 +3346,14 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" "LDR r8, [sp, #4]\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" - "SUBS %[len], %[len], #16\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_CTR_encrypt_loop_block_192_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -3314,14 +3380,14 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, #else "L_AES_CTR_encrypt_loop_block_128_%=:\n\t" #endif - "PUSH {r1, %[len], lr}\n\t" + "PUSH {r1, r2, lr}\n\t" "LDR lr, [sp, #16]\n\t" "ADDS r11, r7, #1\n\t" "ADCS r10, r6, #0\n\t" "ADCS r9, r5, #0\n\t" "ADC r8, r4, #0\n\t" "STM lr, {r8, r9, r10, r11}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -3379,7 +3445,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -3429,7 +3495,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -3487,7 +3553,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -3537,7 +3603,7 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -3546,8 +3612,8 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -3561,14 +3627,14 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" "LDR r8, [sp, #4]\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" - "SUBS %[len], %[len], #16\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_CTR_encrypt_loop_block_128_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -3582,25 +3648,37 @@ WC_OMIT_FRAME_POINTER void AES_CTR_encrypt(const unsigned char* in, #else "L_AES_CTR_encrypt_end_%=:\n\t" #endif - "POP {%[ks], r8}\n\t" + "POP {r3, r8}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" "STM r8, {r4, r5, r6, r7}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [in] "+r" (in), [out] "+r" (out), [len] "+r" (len), [ks] "+r" (ks), [nr] "+r" (nr), [ctr] "+r" (ctr), [L_AES_Thumb2_te_ctr] "+r" (L_AES_Thumb2_te_ctr_c) : + : "memory", "cc", "r12", "lr", "r7", "r8", "r9", "r10", "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [in] "r" (in), [out] "r" (out), [len] "r" (len), [ks] "r" (ks), - [nr] "r" (nr), [ctr] "r" (ctr), - [L_AES_Thumb2_te_ctr] "r" (L_AES_Thumb2_te_ctr_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r12", "lr", "r7", "r8", "r9", "r10", "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + in = (const unsigned char*)(size_t)L_asm_args[0]; + out = (unsigned char*)(size_t)L_asm_args[1]; + len = (unsigned long)(size_t)L_asm_args[2]; + ks = (const unsigned char*)(size_t)L_asm_args[3]; + nr = (int)(size_t)L_asm_args[4]; + ctr = (unsigned char*)(size_t)L_asm_args[5]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_AES_COUNTER */ @@ -3634,10 +3712,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "LSR r11, r4, #24\n\t" "UBFX r12, r6, #8, #8\n\t" "UBFX lr, r5, #0, #8\n\t" - "LDR r8, [%[td], r8, LSL #2]\n\t" - "LDR r11, [%[td], r11, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r8, [r0, r8, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "UBFX r9, r4, #16, #8\n\t" "EOR r8, r8, r11, ROR #24\n\t" "LSR r11, r5, #24\n\t" @@ -3645,10 +3723,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "UBFX r12, r7, #8, #8\n\t" "EOR r8, r8, lr, ROR #16\n\t" "UBFX lr, r6, #0, #8\n\t" - "LDR r9, [%[td], r9, LSL #2]\n\t" - "LDR r11, [%[td], r11, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r9, [r0, r9, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "UBFX r10, r5, #16, #8\n\t" "EOR r9, r9, r11, ROR #24\n\t" "LSR r11, r6, #24\n\t" @@ -3656,10 +3734,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "UBFX r12, r4, #8, #8\n\t" "EOR r9, r9, lr, ROR #16\n\t" "UBFX lr, r7, #0, #8\n\t" - "LDR r10, [%[td], r10, LSL #2]\n\t" - "LDR r11, [%[td], r11, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r10, [r0, r10, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "UBFX r4, r4, #0, #8\n\t" "EOR r10, r10, r11, ROR #24\n\t" "UBFX r11, r6, #16, #8\n\t" @@ -3667,10 +3745,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "LSR r12, r7, #24\n\t" "EOR r10, r10, lr, ROR #16\n\t" "UBFX lr, r5, #8, #8\n\t" - "LDR r4, [%[td], r4, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR r11, [%[td], r11, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r4, [r0, r4, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" @@ -3684,10 +3762,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "LSR r7, r8, #24\n\t" "UBFX r12, r10, #8, #8\n\t" "UBFX lr, r9, #0, #8\n\t" - "LDR r4, [%[td], r4, LSL #2]\n\t" - "LDR r7, [%[td], r7, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r4, [r0, r4, LSL #2]\n\t" + "LDR r7, [r0, r7, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "UBFX r5, r8, #16, #8\n\t" "EOR r4, r4, r7, ROR #24\n\t" "LSR r7, r9, #24\n\t" @@ -3695,10 +3773,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "UBFX r12, r11, #8, #8\n\t" "EOR r4, r4, lr, ROR #16\n\t" "UBFX lr, r10, #0, #8\n\t" - "LDR r5, [%[td], r5, LSL #2]\n\t" - "LDR r7, [%[td], r7, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r5, [r0, r5, LSL #2]\n\t" + "LDR r7, [r0, r7, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "UBFX r6, r9, #16, #8\n\t" "EOR r5, r5, r7, ROR #24\n\t" "LSR r7, r10, #24\n\t" @@ -3706,10 +3784,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "UBFX r12, r8, #8, #8\n\t" "EOR r5, r5, lr, ROR #16\n\t" "UBFX lr, r11, #0, #8\n\t" - "LDR r6, [%[td], r6, LSL #2]\n\t" - "LDR r7, [%[td], r7, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r6, [r0, r6, LSL #2]\n\t" + "LDR r7, [r0, r7, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "UBFX r8, r8, #0, #8\n\t" "EOR r6, r6, r7, ROR #24\n\t" "UBFX r7, r10, #16, #8\n\t" @@ -3717,10 +3795,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "LSR r12, r11, #24\n\t" "EOR r6, r6, lr, ROR #16\n\t" "UBFX lr, r9, #8, #8\n\t" - "LDR r8, [%[td], r8, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR r7, [%[td], r7, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r8, [r0, r8, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR r7, [r0, r7, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r8, ROR #24\n\t" "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #8\n\t" @@ -3730,7 +3808,7 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "SUBS %[nr], %[nr], #1\n\t" + "SUBS r1, r1, #1\n\t" #if defined(__GNUC__) "BNE L_AES_decrypt_block_nr_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -3742,10 +3820,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "LSR r11, r4, #24\n\t" "UBFX r12, r6, #8, #8\n\t" "UBFX lr, r5, #0, #8\n\t" - "LDR r8, [%[td], r8, LSL #2]\n\t" - "LDR r11, [%[td], r11, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r8, [r0, r8, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "UBFX r9, r4, #16, #8\n\t" "EOR r8, r8, r11, ROR #24\n\t" "LSR r11, r5, #24\n\t" @@ -3753,10 +3831,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "UBFX r12, r7, #8, #8\n\t" "EOR r8, r8, lr, ROR #16\n\t" "UBFX lr, r6, #0, #8\n\t" - "LDR r9, [%[td], r9, LSL #2]\n\t" - "LDR r11, [%[td], r11, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r9, [r0, r9, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "UBFX r10, r5, #16, #8\n\t" "EOR r9, r9, r11, ROR #24\n\t" "LSR r11, r6, #24\n\t" @@ -3764,10 +3842,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "UBFX r12, r4, #8, #8\n\t" "EOR r9, r9, lr, ROR #16\n\t" "UBFX lr, r7, #0, #8\n\t" - "LDR r10, [%[td], r10, LSL #2]\n\t" - "LDR r11, [%[td], r11, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r10, [r0, r10, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "UBFX r4, r4, #0, #8\n\t" "EOR r10, r10, r11, ROR #24\n\t" "UBFX r11, r6, #16, #8\n\t" @@ -3775,10 +3853,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "LSR r12, r7, #24\n\t" "EOR r10, r10, lr, ROR #16\n\t" "UBFX lr, r5, #8, #8\n\t" - "LDR r4, [%[td], r4, LSL #2]\n\t" - "LDR r12, [%[td], r12, LSL #2]\n\t" - "LDR r11, [%[td], r11, LSL #2]\n\t" - "LDR lr, [%[td], lr, LSL #2]\n\t" + "LDR r4, [r0, r4, LSL #2]\n\t" + "LDR r12, [r0, r12, LSL #2]\n\t" + "LDR r11, [r0, r11, LSL #2]\n\t" + "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" @@ -3792,10 +3870,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "UBFX r7, r10, #8, #8\n\t" "UBFX r12, r11, #16, #8\n\t" "LSR lr, r8, #24\n\t" - "LDRB r4, [%[td4], r4]\n\t" - "LDRB r7, [%[td4], r7]\n\t" - "LDRB r12, [%[td4], r12]\n\t" - "LDRB lr, [%[td4], lr]\n\t" + "LDRB r4, [r2, r4]\n\t" + "LDRB r7, [r2, r7]\n\t" + "LDRB r12, [r2, r12]\n\t" + "LDRB lr, [r2, lr]\n\t" "UBFX r5, r10, #0, #8\n\t" "EOR r4, r4, r7, LSL #8\n\t" "UBFX r7, r11, #8, #8\n\t" @@ -3803,10 +3881,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "UBFX r12, r8, #16, #8\n\t" "EOR r4, r4, lr, LSL #24\n\t" "LSR lr, r9, #24\n\t" - "LDRB r7, [%[td4], r7]\n\t" - "LDRB lr, [%[td4], lr]\n\t" - "LDRB r5, [%[td4], r5]\n\t" - "LDRB r12, [%[td4], r12]\n\t" + "LDRB r7, [r2, r7]\n\t" + "LDRB lr, [r2, lr]\n\t" + "LDRB r5, [r2, r5]\n\t" + "LDRB r12, [r2, r12]\n\t" "UBFX r6, r11, #0, #8\n\t" "EOR r5, r5, r7, LSL #8\n\t" "UBFX r7, r8, #8, #8\n\t" @@ -3814,10 +3892,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "UBFX r12, r9, #16, #8\n\t" "EOR r5, r5, lr, LSL #24\n\t" "LSR lr, r10, #24\n\t" - "LDRB r7, [%[td4], r7]\n\t" - "LDRB lr, [%[td4], lr]\n\t" - "LDRB r6, [%[td4], r6]\n\t" - "LDRB r12, [%[td4], r12]\n\t" + "LDRB r7, [r2, r7]\n\t" + "LDRB lr, [r2, lr]\n\t" + "LDRB r6, [r2, r6]\n\t" + "LDRB r12, [r2, r12]\n\t" "LSR r11, r11, #24\n\t" "EOR r6, r6, r7, LSL #8\n\t" "UBFX r7, r8, #0, #8\n\t" @@ -3825,10 +3903,10 @@ WC_OMIT_FRAME_POINTER void AES_decrypt_block(const word32* td, int nr, "UBFX r12, r9, #8, #8\n\t" "EOR r6, r6, lr, LSL #24\n\t" "UBFX lr, r10, #16, #8\n\t" - "LDRB r11, [%[td4], r11]\n\t" - "LDRB r12, [%[td4], r12]\n\t" - "LDRB r7, [%[td4], r7]\n\t" - "LDRB lr, [%[td4], lr]\n\t" + "LDRB r11, [r2, r11]\n\t" + "LDRB r12, [r2, r12]\n\t" + "LDRB r7, [r2, r7]\n\t" + "LDRB lr, [r2, lr]\n\t" "EOR r12, r12, r11, LSL #16\n\t" "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, r12, LSL #8\n\t" @@ -3912,20 +3990,23 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, register word8* L_AES_Thumb2_td4_c __asm__ ("r6") = (word8*)&L_AES_Thumb2_td4; #else - register word32* L_AES_Thumb2_td_ecb_c = (word32*)L_AES_Thumb2_td_ecb; - register word8* L_AES_Thumb2_td4_c = (word8*)&L_AES_Thumb2_td4; + void* L_asm_args[7] = {(void*)(size_t)in, (void*)(size_t)out, + (void*)(size_t)len, (void*)(size_t)ks, (void*)(size_t)nr, + (void*)(size_t)L_AES_Thumb2_td_ecb, (void*)(size_t)&L_AES_Thumb2_td4 + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, r4\n\t" -#else - "MOV r8, %[nr]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - "MOV lr, %[in]\n\t" - "MOV r0, %[L_AES_Thumb2_td_ecb]\n\t" - "MOV r12, %[len]\n\t" - "MOV r2, %[L_AES_Thumb2_td4]\n\t" + "MOV lr, r0\n\t" + "MOV r0, r5\n\t" + "MOV r12, r2\n\t" + "MOV r2, r6\n\t" "CMP r8, #10\n\t" #if defined(__GNUC__) "BEQ L_AES_ECB_decrypt_start_block_128_%=\n\t" @@ -3956,8 +4037,8 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "PUSH {r1, %[ks], r12, lr}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "PUSH {r1, r3, r12, lr}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -4015,7 +4096,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -4065,7 +4146,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r8, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #8\n\t" "EOR r7, r7, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -4123,7 +4204,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -4173,7 +4254,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDRB r7, [r2, r7]\n\t" "LDRB lr, [r2, lr]\n\t" "EOR r12, r12, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, r12, LSL #8\n\t" "EOR r7, r7, lr, LSL #16\n\t" /* XOR in Key Schedule */ @@ -4182,18 +4263,18 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[ks], r12, lr}\n\t" + "POP {r1, r3, r12, lr}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "SUBS r12, r12, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_ECB_decrypt_loop_block_256_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -4228,8 +4309,8 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "PUSH {r1, %[ks], r12, lr}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "PUSH {r1, r3, r12, lr}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -4287,7 +4368,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -4337,7 +4418,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r8, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #8\n\t" "EOR r7, r7, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -4395,7 +4476,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -4445,7 +4526,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDRB r7, [r2, r7]\n\t" "LDRB lr, [r2, lr]\n\t" "EOR r12, r12, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, r12, LSL #8\n\t" "EOR r7, r7, lr, LSL #16\n\t" /* XOR in Key Schedule */ @@ -4454,18 +4535,18 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[ks], r12, lr}\n\t" + "POP {r1, r3, r12, lr}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "SUBS r12, r12, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_ECB_decrypt_loop_block_192_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -4500,8 +4581,8 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "PUSH {r1, %[ks], r12, lr}\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "PUSH {r1, r3, r12, lr}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -4559,7 +4640,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -4609,7 +4690,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r8, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #8\n\t" "EOR r7, r7, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -4667,7 +4748,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -4717,7 +4798,7 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "LDRB r7, [r2, r7]\n\t" "LDRB lr, [r2, lr]\n\t" "EOR r12, r12, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, r12, LSL #8\n\t" "EOR r7, r7, lr, LSL #16\n\t" /* XOR in Key Schedule */ @@ -4726,18 +4807,18 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[ks], r12, lr}\n\t" + "POP {r1, r3, r12, lr}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "SUBS r12, r12, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_ECB_decrypt_loop_block_128_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -4751,19 +4832,30 @@ WC_OMIT_FRAME_POINTER void AES_ECB_decrypt(const unsigned char* in, #else "L_AES_ECB_decrypt_end_%=:\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [in] "+r" (in), [out] "+r" (out), [len] "+r" (len), [ks] "+r" (ks), [nr] "+r" (nr), [L_AES_Thumb2_td_ecb] "+r" (L_AES_Thumb2_td_ecb_c), [L_AES_Thumb2_td4] "+r" (L_AES_Thumb2_td4_c) : + : "memory", "cc", "r12", "lr", "r7", "r8", "r9", "r10", "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [in] "r" (in), [out] "r" (out), [len] "r" (len), [ks] "r" (ks), - [nr] "r" (nr), [L_AES_Thumb2_td_ecb] "r" (L_AES_Thumb2_td_ecb_c), - [L_AES_Thumb2_td4] "r" (L_AES_Thumb2_td4_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r12", "lr", "r7", "r8", "r9", "r10", "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + in = (const unsigned char*)(size_t)L_asm_args[0]; + out = (unsigned char*)(size_t)L_asm_args[1]; + len = (unsigned long)(size_t)L_asm_args[2]; + ks = (const unsigned char*)(size_t)L_asm_args[3]; + nr = (int)(size_t)L_asm_args[4]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || defined(HAVE_AES_ECB) */ @@ -4795,26 +4887,26 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, register word8* L_AES_Thumb2_td4_c __asm__ ("r7") = (word8*)&L_AES_Thumb2_td4; #else - register word32* L_AES_Thumb2_td_ecb_c = (word32*)L_AES_Thumb2_td_ecb; - register word8* L_AES_Thumb2_td4_c = (word8*)&L_AES_Thumb2_td4; + void* L_asm_args[8] = {(void*)(size_t)in, (void*)(size_t)out, + (void*)(size_t)len, (void*)(size_t)ks, (void*)(size_t)nr, + (void*)(size_t)iv, (void*)(size_t)L_AES_Thumb2_td_ecb, + (void*)(size_t)&L_AES_Thumb2_td4 + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "MOV lr, %[in]\n\t" - "MOV r0, %[L_AES_Thumb2_td_ecb]\n\t" - "MOV r12, %[len]\n\t" - "MOV r2, %[L_AES_Thumb2_td4]\n\t" -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "MOV lr, r0\n\t" + "MOV r0, r6\n\t" + "MOV r12, r2\n\t" + "MOV r2, r7\n\t" "MOV r8, r4\n\t" -#else - "MOV r8, %[nr]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG "MOV r4, r5\n\t" -#else - "MOV r4, %[iv]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - "PUSH {%[ks], r4}\n\t" + "PUSH {r3, r4}\n\t" "CMP r8, #10\n\t" #if defined(__GNUC__) "BEQ L_AES_CBC_decrypt_loop_block_128_%=\n\t" @@ -4845,7 +4937,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR lr, [sp, #16]\n\t" "STRD r4, r5, [lr, #16]\n\t" "STRD r6, r7, [lr, #24]\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -4907,7 +4999,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -4957,7 +5049,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r8, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #8\n\t" "EOR r7, r7, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -5015,7 +5107,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -5065,7 +5157,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDRB r7, [r2, r7]\n\t" "LDRB lr, [r2, lr]\n\t" "EOR r12, r12, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, r12, LSL #8\n\t" "EOR r7, r7, lr, LSL #16\n\t" /* XOR in Key Schedule */ @@ -5081,18 +5173,18 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "REV r7, r7\n\t" "LDM lr, {r8, r9, r10, r11}\n\t" "POP {r1, r12, lr}\n\t" - "LDR %[ks], [sp]\n\t" + "LDR r3, [sp]\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "SUBS r12, r12, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BEQ L_AES_CBC_decrypt_end_odd_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -5108,7 +5200,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR lr, [sp, #16]\n\t" "STRD r4, r5, [lr]\n\t" "STRD r6, r7, [lr, #8]\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -5170,7 +5262,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -5220,7 +5312,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r8, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #8\n\t" "EOR r7, r7, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -5278,7 +5370,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -5328,7 +5420,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDRB r7, [r2, r7]\n\t" "LDRB lr, [r2, lr]\n\t" "EOR r12, r12, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, r12, LSL #8\n\t" "EOR r7, r7, lr, LSL #16\n\t" /* XOR in Key Schedule */ @@ -5345,18 +5437,18 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDRD r8, r9, [lr, #16]\n\t" "LDRD r10, r11, [lr, #24]\n\t" "POP {r1, r12, lr}\n\t" - "LDR %[ks], [sp]\n\t" + "LDR r3, [sp]\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "SUBS r12, r12, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_CBC_decrypt_loop_block_256_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -5385,7 +5477,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR lr, [sp, #16]\n\t" "STRD r4, r5, [lr, #16]\n\t" "STRD r6, r7, [lr, #24]\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -5447,7 +5539,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -5497,7 +5589,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r8, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #8\n\t" "EOR r7, r7, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -5555,7 +5647,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -5605,7 +5697,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDRB r7, [r2, r7]\n\t" "LDRB lr, [r2, lr]\n\t" "EOR r12, r12, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, r12, LSL #8\n\t" "EOR r7, r7, lr, LSL #16\n\t" /* XOR in Key Schedule */ @@ -5621,18 +5713,18 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "REV r7, r7\n\t" "LDM lr, {r8, r9, r10, r11}\n\t" "POP {r1, r12, lr}\n\t" - "LDR %[ks], [sp]\n\t" + "LDR r3, [sp]\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "SUBS r12, r12, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BEQ L_AES_CBC_decrypt_end_odd_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -5648,7 +5740,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR lr, [sp, #16]\n\t" "STRD r4, r5, [lr]\n\t" "STRD r6, r7, [lr, #8]\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -5710,7 +5802,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -5760,7 +5852,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r8, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #8\n\t" "EOR r7, r7, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -5818,7 +5910,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -5868,7 +5960,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDRB r7, [r2, r7]\n\t" "LDRB lr, [r2, lr]\n\t" "EOR r12, r12, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, r12, LSL #8\n\t" "EOR r7, r7, lr, LSL #16\n\t" /* XOR in Key Schedule */ @@ -5885,18 +5977,18 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDRD r8, r9, [lr, #16]\n\t" "LDRD r10, r11, [lr, #24]\n\t" "POP {r1, r12, lr}\n\t" - "LDR %[ks], [sp]\n\t" + "LDR r3, [sp]\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "SUBS r12, r12, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_CBC_decrypt_loop_block_192_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -5925,7 +6017,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR lr, [sp, #16]\n\t" "STRD r4, r5, [lr, #16]\n\t" "STRD r6, r7, [lr, #24]\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -5987,7 +6079,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -6037,7 +6129,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r8, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #8\n\t" "EOR r7, r7, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -6095,7 +6187,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -6145,7 +6237,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDRB r7, [r2, r7]\n\t" "LDRB lr, [r2, lr]\n\t" "EOR r12, r12, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, r12, LSL #8\n\t" "EOR r7, r7, lr, LSL #16\n\t" /* XOR in Key Schedule */ @@ -6161,18 +6253,18 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "REV r7, r7\n\t" "LDM lr, {r8, r9, r10, r11}\n\t" "POP {r1, r12, lr}\n\t" - "LDR %[ks], [sp]\n\t" + "LDR r3, [sp]\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "SUBS r12, r12, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BEQ L_AES_CBC_decrypt_end_odd_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -6188,7 +6280,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR lr, [sp, #16]\n\t" "STRD r4, r5, [lr]\n\t" "STRD r6, r7, [lr, #8]\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -6250,7 +6342,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -6300,7 +6392,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r8, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #8\n\t" "EOR r7, r7, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -6358,7 +6450,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR lr, [r0, lr, LSL #2]\n\t" "EOR r12, r12, r4, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #8\n\t" "EOR r11, r11, r12, ROR #24\n\t" /* XOR in Key Schedule */ @@ -6408,7 +6500,7 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDRB r7, [r2, r7]\n\t" "LDRB lr, [r2, lr]\n\t" "EOR r12, r12, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, r12, LSL #8\n\t" "EOR r7, r7, lr, LSL #16\n\t" /* XOR in Key Schedule */ @@ -6425,18 +6517,18 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, "LDRD r8, r9, [lr, #16]\n\t" "LDRD r10, r11, [lr, #24]\n\t" "POP {r1, r12, lr}\n\t" - "LDR %[ks], [sp]\n\t" + "LDR r3, [sp]\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "SUBS r12, r12, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_CBC_decrypt_loop_block_128_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -6468,22 +6560,33 @@ WC_OMIT_FRAME_POINTER void AES_CBC_decrypt(const unsigned char* in, #else "L_AES_CBC_decrypt_end_%=:\n\t" #endif - "POP {%[ks], r4}\n\t" + "POP {r3, r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [in] "+r" (in), [out] "+r" (out), [len] "+r" (len), [ks] "+r" (ks), [nr] "+r" (nr), [iv] "+r" (iv), [L_AES_Thumb2_td_ecb] "+r" (L_AES_Thumb2_td_ecb_c), [L_AES_Thumb2_td4] "+r" (L_AES_Thumb2_td4_c) : + : "memory", "cc", "r12", "lr", "r8", "r9", "r10", "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [in] "r" (in), [out] "r" (out), [len] "r" (len), [ks] "r" (ks), - [nr] "r" (nr), [iv] "r" (iv), - [L_AES_Thumb2_td_ecb] "r" (L_AES_Thumb2_td_ecb_c), - [L_AES_Thumb2_td4] "r" (L_AES_Thumb2_td4_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r12", "lr", "r8", "r9", "r10", "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + in = (const unsigned char*)(size_t)L_asm_args[0]; + out = (unsigned char*)(size_t)L_asm_args[1]; + len = (unsigned long)(size_t)L_asm_args[2]; + ks = (const unsigned char*)(size_t)L_asm_args[3]; + nr = (int)(size_t)L_asm_args[4]; + iv = (unsigned char*)(size_t)L_asm_args[5]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* HAVE_AES_CBC */ @@ -6518,11 +6621,19 @@ WC_OMIT_FRAME_POINTER void GCM_gmult_len(unsigned char* x, register word32* L_GCM_gmult_len_r_c __asm__ ("r4") = (word32*)&L_GCM_gmult_len_r; #else - register word32* L_GCM_gmult_len_r_c = (word32*)&L_GCM_gmult_len_r; + void* L_asm_args[5] = {(void*)(size_t)x, (void*)(size_t)m, + (void*)(size_t)data, (void*)(size_t)len, + (void*)(size_t)&L_GCM_gmult_len_r + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "MOV lr, %[L_GCM_gmult_len_r]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "MOV lr, r4\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_GCM_gmult_len_start_block:\n\t" @@ -6531,512 +6642,512 @@ WC_OMIT_FRAME_POINTER void GCM_gmult_len(unsigned char* x, #endif "PUSH {r3}\n\t" "LDR r12, [r0, #12]\n\t" - "LDR %[len], [r2, #12]\n\t" - "EOR r12, r12, %[len]\n\t" - "UBFX %[len], r12, #24, #4\n\t" - "ADD %[len], %[m], %[len], LSL #4\n\t" - "LDM %[len], {r8, r9, r10, r11}\n\t" + "LDR r3, [r2, #12]\n\t" + "EOR r12, r12, r3\n\t" + "UBFX r3, r12, #24, #4\n\t" + "ADD r3, r1, r3, LSL #4\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #28, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #16, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #20, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #8, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #12, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "AND r4, r12, #15\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #4, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "LDR r12, [r0, #8]\n\t" - "LDR %[len], [r2, #8]\n\t" - "EOR r12, r12, %[len]\n\t" - "UBFX %[len], r12, #24, #4\n\t" - "ADD %[len], %[m], %[len], LSL #4\n\t" - "LDM %[len], {r4, r5, r6, r7}\n\t" + "LDR r3, [r2, #8]\n\t" + "EOR r12, r12, r3\n\t" + "UBFX r3, r12, #24, #4\n\t" + "ADD r3, r1, r3, LSL #4\n\t" + "LDM r3, {r4, r5, r6, r7}\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #28, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #16, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #20, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #8, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #12, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "AND r4, r12, #15\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #4, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "LDR r12, [r0, #4]\n\t" - "LDR %[len], [r2, #4]\n\t" - "EOR r12, r12, %[len]\n\t" - "UBFX %[len], r12, #24, #4\n\t" - "ADD %[len], %[m], %[len], LSL #4\n\t" - "LDM %[len], {r4, r5, r6, r7}\n\t" + "LDR r3, [r2, #4]\n\t" + "EOR r12, r12, r3\n\t" + "UBFX r3, r12, #24, #4\n\t" + "ADD r3, r1, r3, LSL #4\n\t" + "LDM r3, {r4, r5, r6, r7}\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #28, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #16, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #20, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #8, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #12, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "AND r4, r12, #15\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #4, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "LDR r12, [r0]\n\t" - "LDR %[len], [r2]\n\t" - "EOR r12, r12, %[len]\n\t" - "UBFX %[len], r12, #24, #4\n\t" - "ADD %[len], %[m], %[len], LSL #4\n\t" - "LDM %[len], {r4, r5, r6, r7}\n\t" + "LDR r3, [r2]\n\t" + "EOR r12, r12, r3\n\t" + "UBFX r3, r12, #24, #4\n\t" + "ADD r3, r1, r3, LSL #4\n\t" + "LDM r3, {r4, r5, r6, r7}\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #28, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #16, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #20, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #8, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #12, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "AND r4, r12, #15\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "LSR r6, r10, #4\n\t" - "AND %[len], r11, #15\n\t" + "AND r3, r11, #15\n\t" "LSR r11, r11, #4\n\t" "UBFX r4, r12, #4, #4\n\t" "EOR r11, r11, r10, LSL #28\n\t" - "LDR %[len], [lr, r3, LSL #2]\n\t" - "ADD r4, %[m], r4, LSL #4\n\t" + "LDR r3, [lr, r3, LSL #2]\n\t" + "ADD r4, r1, r4, LSL #4\n\t" "EOR r10, r6, r9, LSL #28\n\t" "LSR r9, r9, #4\n\t" "LDM r4, {r4, r5, r6, r7}\n\t" "EOR r9, r9, r8, LSL #28\n\t" - "EOR r8, %[len], r8, LSR #4\n\t" + "EOR r8, r3, r8, LSR #4\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" @@ -7045,10 +7156,10 @@ WC_OMIT_FRAME_POINTER void GCM_gmult_len(unsigned char* x, "REV r9, r9\n\t" "REV r10, r10\n\t" "REV r11, r11\n\t" - "STM %[x], {r8, r9, r10, r11}\n\t" + "STM r0, {r8, r9, r10, r11}\n\t" "POP {r3}\n\t" - "SUBS %[len], %[len], #16\n\t" - "ADD %[data], %[data], #16\n\t" + "SUBS r3, r3, #16\n\t" + "ADD r2, r2, #16\n\t" #if defined(__GNUC__) "BNE L_GCM_gmult_len_start_block_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -7056,18 +7167,29 @@ WC_OMIT_FRAME_POINTER void GCM_gmult_len(unsigned char* x, #else "BNE.W L_GCM_gmult_len_start_block_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [x] "+r" (x), [m] "+r" (m), [data] "+r" (data), [len] "+r" (len), [L_GCM_gmult_len_r] "+r" (L_GCM_gmult_len_r_c) : + : "memory", "cc", "r12", "lr", "r5", "r6", "r7", "r8", "r9", "r10", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [x] "r" (x), [m] "r" (m), [data] "r" (data), [len] "r" (len), - [L_GCM_gmult_len_r] "r" (L_GCM_gmult_len_r_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r12", "lr", "r5", "r6", "r7", "r8", "r9", "r10", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + x = (unsigned char*)(size_t)L_asm_args[0]; + m = (const unsigned char**)(size_t)L_asm_args[1]; + data = (const unsigned char*)(size_t)L_asm_args[2]; + len = (unsigned long)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } static const word32* L_AES_Thumb2_te_gcm = L_AES_Thumb2_te_data; @@ -7096,29 +7218,29 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, register word32* L_AES_Thumb2_te_gcm_c __asm__ ("r6") = (word32*)L_AES_Thumb2_te_gcm; #else - register word32* L_AES_Thumb2_te_gcm_c = (word32*)L_AES_Thumb2_te_gcm; + void* L_asm_args[7] = {(void*)(size_t)in, (void*)(size_t)out, + (void*)(size_t)len, (void*)(size_t)ks, (void*)(size_t)nr, + (void*)(size_t)ctr, (void*)(size_t)L_AES_Thumb2_te_gcm + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r12, r4\n\t" -#else - "MOV r12, %[nr]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG "MOV r8, r5\n\t" -#else - "MOV r8, %[ctr]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - "MOV lr, %[in]\n\t" - "MOV r0, %[L_AES_Thumb2_te_gcm]\n\t" + "MOV lr, r0\n\t" + "MOV r0, r6\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" "STM r8, {r4, r5, r6, r7}\n\t" - "PUSH {%[ks], r8}\n\t" + "PUSH {r3, r8}\n\t" "CMP r12, #10\n\t" #if defined(__GNUC__) "BEQ L_AES_GCM_encrypt_start_block_128_%=\n\t" @@ -7141,10 +7263,10 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, #else "L_AES_GCM_encrypt_loop_block_256_%=:\n\t" #endif - "PUSH {r1, %[len], lr}\n\t" + "PUSH {r1, r2, lr}\n\t" "LDR lr, [sp, #16]\n\t" "ADD r7, r7, #1\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "STR r7, [lr, #12]\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" @@ -7203,7 +7325,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -7253,7 +7375,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -7311,7 +7433,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -7361,7 +7483,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -7370,8 +7492,8 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -7385,14 +7507,14 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" "LDR r8, [sp, #4]\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" - "SUBS %[len], %[len], #16\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_GCM_encrypt_loop_block_256_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -7419,10 +7541,10 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, #else "L_AES_GCM_encrypt_loop_block_192_%=:\n\t" #endif - "PUSH {r1, %[len], lr}\n\t" + "PUSH {r1, r2, lr}\n\t" "LDR lr, [sp, #16]\n\t" "ADD r7, r7, #1\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "STR r7, [lr, #12]\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" @@ -7481,7 +7603,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -7531,7 +7653,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -7589,7 +7711,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -7639,7 +7761,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -7648,8 +7770,8 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -7663,14 +7785,14 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" "LDR r8, [sp, #4]\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" - "SUBS %[len], %[len], #16\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_GCM_encrypt_loop_block_192_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -7697,10 +7819,10 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, #else "L_AES_GCM_encrypt_loop_block_128_%=:\n\t" #endif - "PUSH {r1, %[len], lr}\n\t" + "PUSH {r1, r2, lr}\n\t" "LDR lr, [sp, #16]\n\t" "ADD r7, r7, #1\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "STR r7, [lr, #12]\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" @@ -7759,7 +7881,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -7809,7 +7931,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[ks]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -7867,7 +7989,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[ks]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -7917,7 +8039,7 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[ks], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -7926,8 +8048,8 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[len], lr}\n\t" - "LDR %[ks], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -7941,14 +8063,14 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" "LDR r8, [sp, #4]\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" - "SUBS %[len], %[len], #16\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_GCM_encrypt_loop_block_128_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -7962,25 +8084,37 @@ WC_OMIT_FRAME_POINTER void AES_GCM_encrypt(const unsigned char* in, #else "L_AES_GCM_encrypt_end_%=:\n\t" #endif - "POP {%[ks], r8}\n\t" + "POP {r3, r8}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" "STM r8, {r4, r5, r6, r7}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [in] "+r" (in), [out] "+r" (out), [len] "+r" (len), [ks] "+r" (ks), [nr] "+r" (nr), [ctr] "+r" (ctr), [L_AES_Thumb2_te_gcm] "+r" (L_AES_Thumb2_te_gcm_c) : + : "memory", "cc", "r12", "lr", "r7", "r8", "r9", "r10", "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [in] "r" (in), [out] "r" (out), [len] "r" (len), [ks] "r" (ks), - [nr] "r" (nr), [ctr] "r" (ctr), - [L_AES_Thumb2_te_gcm] "r" (L_AES_Thumb2_te_gcm_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r12", "lr", "r7", "r8", "r9", "r10", "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + in = (const unsigned char*)(size_t)L_asm_args[0]; + out = (unsigned char*)(size_t)L_asm_args[1]; + len = (unsigned long)(size_t)L_asm_args[2]; + ks = (const unsigned char*)(size_t)L_asm_args[3]; + nr = (int)(size_t)L_asm_args[4]; + ctr = (unsigned char*)(size_t)L_asm_args[5]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* HAVE_AESGCM */ @@ -8012,14 +8146,21 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, register word32* L_AES_GCMSIV_polyval_thumb2_r_c __asm__ ("r5") = (word32*)&L_AES_GCMSIV_polyval_thumb2_r; #else - register word32* L_AES_Thumb2_te_gcm_c = (word32*)L_AES_Thumb2_te_gcm; - register word32* L_AES_GCMSIV_polyval_thumb2_r_c = - (word32*)&L_AES_GCMSIV_polyval_thumb2_r; + void* L_asm_args[6] = {(void*)(size_t)s, (void*)(size_t)m, + (void*)(size_t)data, (void*)(size_t)blocks, + (void*)(size_t)L_AES_Thumb2_te_gcm, + (void*)(size_t)&L_AES_GCMSIV_polyval_thumb2_r + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "MOV r8, %[L_AES_GCMSIV_polyval_thumb2_r]\n\t" - "CMP %[blocks], #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4, r5}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "MOV r8, r5\n\t" + "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_AES_GCMSIV_polyval_thumb2_done_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -8033,33 +8174,33 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, #else "L_AES_GCMSIV_polyval_thumb2_loop_%=:\n\t" #endif - "LDR r12, [%[data], #12]\n\t" + "LDR r12, [r2, #12]\n\t" "REV r12, r12\n\t" - "LDR r10, [%[s]]\n\t" + "LDR r10, [r0]\n\t" "EOR r10, r10, r12\n\t" - "STR r10, [%[s]]\n\t" - "LDR r12, [%[data], #8]\n\t" + "STR r10, [r0]\n\t" + "LDR r12, [r2, #8]\n\t" "REV r12, r12\n\t" - "LDR r10, [%[s], #4]\n\t" + "LDR r10, [r0, #4]\n\t" "EOR r10, r10, r12\n\t" - "STR r10, [%[s], #4]\n\t" - "LDR r12, [%[data], #4]\n\t" + "STR r10, [r0, #4]\n\t" + "LDR r12, [r2, #4]\n\t" "REV r12, r12\n\t" - "LDR r10, [%[s], #8]\n\t" + "LDR r10, [r0, #8]\n\t" "EOR r10, r10, r12\n\t" - "STR r10, [%[s], #8]\n\t" - "LDR r12, [%[data]]\n\t" + "STR r10, [r0, #8]\n\t" + "LDR r12, [r2]\n\t" "REV r12, r12\n\t" - "LDR r10, [%[s], #12]\n\t" + "LDR r10, [r0, #12]\n\t" "EOR r10, r10, r12\n\t" - "STR r10, [%[s], #12]\n\t" + "STR r10, [r0, #12]\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" "MOV r6, #0\n\t" "MOV r7, #0\n\t" - "LDR r9, [%[s], #12]\n\t" + "LDR r9, [r0, #12]\n\t" "UBFX r10, r9, #24, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8079,7 +8220,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #28, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8099,7 +8240,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #16, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8119,7 +8260,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #20, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8139,7 +8280,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #8, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8159,7 +8300,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #12, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8179,7 +8320,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #0, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8199,7 +8340,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #4, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8218,9 +8359,9 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LSR r5, r5, #4\n\t" "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" - "LDR r9, [%[s], #8]\n\t" + "LDR r9, [r0, #8]\n\t" "UBFX r10, r9, #24, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8240,7 +8381,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #28, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8260,7 +8401,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #16, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8280,7 +8421,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #20, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8300,7 +8441,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #8, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8320,7 +8461,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #12, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8340,7 +8481,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #0, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8360,7 +8501,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #4, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8379,9 +8520,9 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LSR r5, r5, #4\n\t" "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" - "LDR r9, [%[s], #4]\n\t" + "LDR r9, [r0, #4]\n\t" "UBFX r10, r9, #24, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8401,7 +8542,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #28, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8421,7 +8562,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #16, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8441,7 +8582,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #20, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8461,7 +8602,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #8, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8481,7 +8622,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #12, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8501,7 +8642,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #0, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8521,7 +8662,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #4, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8540,9 +8681,9 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LSR r5, r5, #4\n\t" "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" - "LDR r9, [%[s]]\n\t" + "LDR r9, [r0]\n\t" "UBFX r10, r9, #24, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8562,7 +8703,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #28, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8582,7 +8723,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #16, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8602,7 +8743,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #20, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8622,7 +8763,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #8, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8642,7 +8783,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #12, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8662,7 +8803,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #0, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8682,7 +8823,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "LDR r12, [r8, r10, LSL #2]\n\t" "EOR r5, r5, r12\n\t" "UBFX r10, r9, #4, #4\n\t" - "ADD r11, %[m], r10, LSL #4\n\t" + "ADD r11, r1, r10, LSL #4\n\t" "LDR r12, [r11]\n\t" "EOR r4, r4, r12\n\t" "LDR r12, [r11, #4]\n\t" @@ -8695,12 +8836,12 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, "REV r4, r4\n\t" "REV r7, r7\n\t" "REV r6, r6\n\t" - "STR r5, [%[s]]\n\t" - "STR r4, [%[s], #4]\n\t" - "STR r7, [%[s], #8]\n\t" - "STR r6, [%[s], #12]\n\t" - "SUBS %[blocks], %[blocks], #1\n\t" - "ADD %[data], %[data], #16\n\t" + "STR r5, [r0]\n\t" + "STR r4, [r0, #4]\n\t" + "STR r7, [r0, #8]\n\t" + "STR r6, [r0, #12]\n\t" + "SUBS r3, r3, #1\n\t" + "ADD r2, r2, #16\n\t" #if defined(__GNUC__) "BNE L_AES_GCMSIV_polyval_thumb2_loop_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -8714,20 +8855,30 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_polyval_thumb2(unsigned char* s, #else "L_AES_GCMSIV_polyval_thumb2_done_%=:\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4, r5}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [s] "+r" (s), [m] "+r" (m), [data] "+r" (data), [blocks] "+r" (blocks), [L_AES_Thumb2_te_gcm] "+r" (L_AES_Thumb2_te_gcm_c), [L_AES_GCMSIV_polyval_thumb2_r] "+r" (L_AES_GCMSIV_polyval_thumb2_r_c) : + : "memory", "cc", "r6", "r7", "r8", "r9", "r10", "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [s] "r" (s), [m] "r" (m), [data] "r" (data), [blocks] "r" (blocks), - [L_AES_Thumb2_te_gcm] "r" (L_AES_Thumb2_te_gcm_c), - [L_AES_GCMSIV_polyval_thumb2_r] "r" (L_AES_GCMSIV_polyval_thumb2_r_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r6", "r7", "r8", "r9", "r10", "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + s = (unsigned char*)(size_t)L_asm_args[0]; + m = (const unsigned char*)(size_t)L_asm_args[1]; + data = (const unsigned char*)(size_t)L_asm_args[2]; + blocks = (unsigned int)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } XALIGNED(8) static const word32 L_AES_GCMSIV_ctr_thumb2_te_data[] = { @@ -8820,30 +8971,29 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, register word32* L_AES_GCMSIV_ctr_thumb2_te_c __asm__ ("r6") = (word32*)L_AES_GCMSIV_ctr_thumb2_te; #else - register word32* L_AES_GCMSIV_ctr_thumb2_te_c = - (word32*)L_AES_GCMSIV_ctr_thumb2_te; + void* L_asm_args[7] = {(void*)(size_t)in, (void*)(size_t)out, + (void*)(size_t)length, (void*)(size_t)KS, (void*)(size_t)nr, + (void*)(size_t)ctr, (void*)(size_t)L_AES_GCMSIV_ctr_thumb2_te + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r12, r4\n\t" -#else - "MOV r12, %[nr]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG "MOV r8, r5\n\t" -#else - "MOV r8, %[ctr]\n\t" -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - "MOV lr, %[in]\n\t" - "MOV r0, %[L_AES_GCMSIV_ctr_thumb2_te]\n\t" + "MOV lr, r0\n\t" + "MOV r0, r6\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" "STM r8, {r4, r5, r6, r7}\n\t" - "PUSH {%[KS], r8}\n\t" + "PUSH {r3, r8}\n\t" "CMP r12, #10\n\t" #if defined(__GNUC__) "BEQ L_AES_GCMSIV_ctr_thumb2_start_block_128_%=\n\t" @@ -8866,7 +9016,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, #else "L_AES_GCMSIV_ctr_thumb2_loop_block_256_%=:\n\t" #endif - "PUSH {r1, %[length], lr}\n\t" + "PUSH {r1, r2, lr}\n\t" "LDR lr, [sp, #16]\n\t" "REV r8, r4\n\t" "ADD r8, r8, #1\n\t" @@ -8875,7 +9025,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "MOV r10, r6\n\t" "MOV r11, r7\n\t" "STM lr, {r8, r9, r10, r11}\n\t" - "LDM %[KS]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -8933,7 +9083,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[KS]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -8983,7 +9133,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[KS]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -9041,7 +9191,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[KS]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -9091,7 +9241,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[KS], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -9100,8 +9250,8 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[length], lr}\n\t" - "LDR %[KS], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -9115,14 +9265,14 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" "LDR r8, [sp, #4]\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" - "SUBS %[length], %[length], #16\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_GCMSIV_ctr_thumb2_loop_block_256_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -9149,7 +9299,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, #else "L_AES_GCMSIV_ctr_thumb2_loop_block_192_%=:\n\t" #endif - "PUSH {r1, %[length], lr}\n\t" + "PUSH {r1, r2, lr}\n\t" "LDR lr, [sp, #16]\n\t" "REV r8, r4\n\t" "ADD r8, r8, #1\n\t" @@ -9158,7 +9308,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "MOV r10, r6\n\t" "MOV r11, r7\n\t" "STM lr, {r8, r9, r10, r11}\n\t" - "LDM %[KS]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -9216,7 +9366,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[KS]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -9266,7 +9416,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[KS]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -9324,7 +9474,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[KS]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -9374,7 +9524,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[KS], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -9383,8 +9533,8 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[length], lr}\n\t" - "LDR %[KS], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -9398,14 +9548,14 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" "LDR r8, [sp, #4]\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" - "SUBS %[length], %[length], #16\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_GCMSIV_ctr_thumb2_loop_block_192_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -9432,7 +9582,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, #else "L_AES_GCMSIV_ctr_thumb2_loop_block_128_%=:\n\t" #endif - "PUSH {r1, %[length], lr}\n\t" + "PUSH {r1, r2, lr}\n\t" "LDR lr, [sp, #16]\n\t" "REV r8, r4\n\t" "ADD r8, r8, #1\n\t" @@ -9441,7 +9591,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "MOV r10, r6\n\t" "MOV r11, r7\n\t" "STM lr, {r8, r9, r10, r11}\n\t" - "LDM %[KS]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" /* Round: 0 - XOR in key schedule */ "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" @@ -9499,7 +9649,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[KS]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -9549,7 +9699,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDR r7, [r0, r7, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r10, ROR #24\n\t" - "LDM %[KS]!, {r8, r9, r10, r11}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, ROR #24\n\t" "EOR r7, r7, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -9607,7 +9757,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDR r11, [r0, r11, LSL #2]\n\t" "LDR r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r6, ROR #24\n\t" - "LDM %[KS]!, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r4, r5, r6, r7}\n\t" "EOR r11, r11, lr, ROR #24\n\t" "EOR r11, r11, r2, ROR #8\n\t" /* XOR in Key Schedule */ @@ -9657,7 +9807,7 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "LDRB lr, [r0, lr, LSL #2]\n\t" "LDRB r2, [r0, r2, LSL #2]\n\t" "EOR lr, lr, r11, LSL #16\n\t" - "LDM %[KS], {r8, r9, r10, r11}\n\t" + "LDM r3, {r8, r9, r10, r11}\n\t" "EOR r7, r7, lr, LSL #8\n\t" "EOR r7, r7, r2, LSL #16\n\t" /* XOR in Key Schedule */ @@ -9666,8 +9816,8 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" #endif /* !WOLFSSL_ARMASM_AES_BLOCK_INLINE */ - "POP {r1, %[length], lr}\n\t" - "LDR %[KS], [sp]\n\t" + "POP {r1, r2, lr}\n\t" + "LDR r3, [sp]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -9681,14 +9831,14 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" "LDR r8, [sp, #4]\n\t" - "STR r4, [%[out]]\n\t" - "STR r5, [%[out], #4]\n\t" - "STR r6, [%[out], #8]\n\t" - "STR r7, [%[out], #12]\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" "LDM r8, {r4, r5, r6, r7}\n\t" - "SUBS %[length], %[length], #16\n\t" + "SUBS r2, r2, #16\n\t" "ADD lr, lr, #16\n\t" - "ADD %[out], %[out], #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "BNE L_AES_GCMSIV_ctr_thumb2_loop_block_128_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -9702,25 +9852,37 @@ WC_OMIT_FRAME_POINTER void AES_GCMSIV_ctr_thumb2(const unsigned char* in, #else "L_AES_GCMSIV_ctr_thumb2_end_%=:\n\t" #endif - "POP {%[KS], r8}\n\t" + "POP {r3, r8}\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" "REV r7, r7\n\t" "STM r8, {r4, r5, r6, r7}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4, r5, r6}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [in] "+r" (in), [out] "+r" (out), [length] "+r" (length), [KS] "+r" (KS), [nr] "+r" (nr), [ctr] "+r" (ctr), [L_AES_GCMSIV_ctr_thumb2_te] "+r" (L_AES_GCMSIV_ctr_thumb2_te_c) : + : "memory", "cc", "r12", "lr", "r7", "r8", "r9", "r10", "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [in] "r" (in), [out] "r" (out), [length] "r" (length), [KS] "r" (KS), - [nr] "r" (nr), [ctr] "r" (ctr), - [L_AES_GCMSIV_ctr_thumb2_te] "r" (L_AES_GCMSIV_ctr_thumb2_te_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r12", "lr", "r7", "r8", "r9", "r10", "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + in = (const unsigned char*)(size_t)L_asm_args[0]; + out = (unsigned char*)(size_t)L_asm_args[1]; + length = (unsigned long)(size_t)L_asm_args[2]; + KS = (const unsigned char*)(size_t)L_asm_args[3]; + nr = (int)(size_t)L_asm_args[4]; + ctr = (unsigned char*)(size_t)L_asm_args[5]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_AESGCM_SIV */ diff --git a/wolfcrypt/src/port/arm/thumb2-chacha-asm_c.c b/wolfcrypt/src/port/arm/thumb2-chacha-asm_c.c index 72668873894..43e8704a784 100644 --- a/wolfcrypt/src/port/arm/thumb2-chacha-asm_c.c +++ b/wolfcrypt/src/port/arm/thumb2-chacha-asm_c.c @@ -62,29 +62,49 @@ WC_OMIT_FRAME_POINTER void wc_chacha_setiv(word32* x, const byte* iv, register word32* x __asm__ ("r0") = (word32*)x_p; register const byte* iv __asm__ ("r1") = (const byte*)iv_p; register word32 counter __asm__ ("r2") = (word32)counter_p; +#else + void* L_asm_args[3] = {(void*)(size_t)x, (void*)(size_t)iv, + (void*)(size_t)counter + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "ADD r3, %[x], #52\n\t" - "LDR r4, [%[iv]]\n\t" - "LDR r5, [%[iv], #4]\n\t" - "LDR r6, [%[iv], #8]\n\t" - "STR %[counter], [%[x], #48]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "ADD r3, r0, #52\n\t" + "LDR r4, [r1]\n\t" + "LDR r5, [r1, #4]\n\t" + "LDR r6, [r1, #8]\n\t" + "STR r2, [r0, #48]\n\t" #ifdef BIG_ENDIAN_ORDER "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" #endif /* BIG_ENDIAN_ORDER */ "STM r3, {r4, r5, r6}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [x] "+r" (x), [iv] "+r" (iv), [counter] "+r" (counter) : + : "memory", "cc", "r3", "r4", "r5", "r6" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [x] "r" (x), [iv] "r" (iv), [counter] "r" (counter) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + x = (word32*)(size_t)L_asm_args[0]; + iv = (const byte*)(size_t)L_asm_args[1]; + counter = (word32)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } XALIGNED(8) static const word32 L_chacha_thumb2_constants[] = { @@ -107,29 +127,35 @@ WC_OMIT_FRAME_POINTER void wc_chacha_setkey(word32* x, const byte* key, register word32* L_chacha_thumb2_constants_c __asm__ ("r3") = (word32*)&L_chacha_thumb2_constants; #else - register word32* L_chacha_thumb2_constants_c = - (word32*)&L_chacha_thumb2_constants; + void* L_asm_args[4] = {(void*)(size_t)x, (void*)(size_t)key, + (void*)(size_t)keySz, (void*)(size_t)&L_chacha_thumb2_constants + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "MOV r7, %[L_chacha_thumb2_constants]\n\t" - "SUBS %[keySz], %[keySz], #16\n\t" - "ADD r7, r7, %[keySz]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "MOV r7, r3\n\t" + "SUBS r2, r2, #16\n\t" + "ADD r7, r7, r2\n\t" /* Start state with constants */ "LDM r7, {r3, r4, r5, r6}\n\t" - "STM %[x]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" /* Next is first 16 bytes of key. */ - "LDR r3, [%[key]]\n\t" - "LDR r4, [%[key], #4]\n\t" - "LDR r5, [%[key], #8]\n\t" - "LDR r6, [%[key], #12]\n\t" + "LDR r3, [r1]\n\t" + "LDR r4, [r1, #4]\n\t" + "LDR r5, [r1, #8]\n\t" + "LDR r6, [r1, #12]\n\t" #ifdef BIG_ENDIAN_ORDER "REV r3, r3\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" #endif /* BIG_ENDIAN_ORDER */ - "STM %[x]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" /* Next 16 bytes of key. */ #if defined(__GNUC__) "BEQ L_chacha_thumb2_setkey_same_key_bytes_%=\n\t" @@ -139,29 +165,39 @@ WC_OMIT_FRAME_POINTER void wc_chacha_setkey(word32* x, const byte* key, "BEQ.N L_chacha_thumb2_setkey_same_key_bytes_%=\n\t" #endif /* Update key pointer for next 16 bytes. */ - "ADD %[key], %[key], %[keySz]\n\t" - "LDR r3, [%[key]]\n\t" - "LDR r4, [%[key], #4]\n\t" - "LDR r5, [%[key], #8]\n\t" - "LDR r6, [%[key], #12]\n\t" + "ADD r1, r1, r2\n\t" + "LDR r3, [r1]\n\t" + "LDR r4, [r1, #4]\n\t" + "LDR r5, [r1, #8]\n\t" + "LDR r6, [r1, #12]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_chacha_thumb2_setkey_same_key_bytes:\n\t" #else "L_chacha_thumb2_setkey_same_key_bytes_%=:\n\t" #endif - "STM %[x], {r3, r4, r5, r6}\n\t" + "STM r0, {r3, r4, r5, r6}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [x] "+r" (x), [key] "+r" (key), [keySz] "+r" (keySz), [L_chacha_thumb2_constants] "+r" (L_chacha_thumb2_constants_c) : + : "memory", "cc", "r4", "r5", "r6", "r7" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [x] "r" (x), [key] "r" (key), [keySz] "r" (keySz), - [L_chacha_thumb2_constants] "r" (L_chacha_thumb2_constants_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + x = (word32*)(size_t)L_asm_args[0]; + key = (const byte*)(size_t)L_asm_args[1]; + keySz = (word32)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -177,13 +213,22 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, register byte* c __asm__ ("r1") = (byte*)c_p; register const byte* m __asm__ ("r2") = (const byte*)m_p; register word32 len __asm__ ("r3") = (word32)len_p; +#else + void* L_asm_args[4] = {(void*)(size_t)ctx, (void*)(size_t)c, + (void*)(size_t)m, (void*)(size_t)len + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #52\n\t" - "MOV lr, %[ctx]\n\t" - "STRD %[ctx], %[c], [sp, #32]\n\t" - "STRD %[m], %[len], [sp, #40]\n\t" + "MOV lr, r0\n\t" + "STRD r0, r1, [sp, #32]\n\t" + "STRD r2, r3, [sp, #40]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_chacha_thumb2_crypt_block:\n\t" @@ -209,10 +254,10 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, /* 0, 4, 8, 12 */ /* 1, 5, 9, 13 */ "LDR lr, [sp, #20]\n\t" - "ADD %[ctx], %[ctx], r4\n\t" - "ADD %[c], %[c], r5\n\t" - "EOR r12, r12, %[ctx]\n\t" - "EOR lr, lr, %[c]\n\t" + "ADD r0, r0, r4\n\t" + "ADD r1, r1, r5\n\t" + "EOR r12, r12, r0\n\t" + "EOR lr, lr, r1\n\t" "ROR r12, r12, #16\n\t" "ROR lr, lr, #16\n\t" "ADD r8, r8, r12\n\t" @@ -221,10 +266,10 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "EOR r5, r5, r9\n\t" "ROR r4, r4, #20\n\t" "ROR r5, r5, #20\n\t" - "ADD %[ctx], %[ctx], r4\n\t" - "ADD %[c], %[c], r5\n\t" - "EOR r12, r12, %[ctx]\n\t" - "EOR lr, lr, %[c]\n\t" + "ADD r0, r0, r4\n\t" + "ADD r1, r1, r5\n\t" + "EOR r12, r12, r0\n\t" + "EOR lr, lr, r1\n\t" "ROR r12, r12, #24\n\t" "ROR lr, lr, #24\n\t" "ADD r8, r8, r12\n\t" @@ -239,10 +284,10 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, /* 3, 7, 11, 15 */ "LDR r12, [sp, #24]\n\t" "LDR lr, [sp, #28]\n\t" - "ADD %[m], %[m], r6\n\t" - "ADD %[len], %[len], r7\n\t" - "EOR r12, r12, %[m]\n\t" - "EOR lr, lr, %[len]\n\t" + "ADD r2, r2, r6\n\t" + "ADD r3, r3, r7\n\t" + "EOR r12, r12, r2\n\t" + "EOR lr, lr, r3\n\t" "ROR r12, r12, #16\n\t" "ROR lr, lr, #16\n\t" "ADD r10, r10, r12\n\t" @@ -251,10 +296,10 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "EOR r7, r7, r11\n\t" "ROR r6, r6, #20\n\t" "ROR r7, r7, #20\n\t" - "ADD %[m], %[m], r6\n\t" - "ADD %[len], %[len], r7\n\t" - "EOR r12, r12, %[m]\n\t" - "EOR lr, lr, %[len]\n\t" + "ADD r2, r2, r6\n\t" + "ADD r3, r3, r7\n\t" + "EOR r12, r12, r2\n\t" + "EOR lr, lr, r3\n\t" "ROR r12, r12, #24\n\t" "ROR lr, lr, #24\n\t" "ADD r10, r10, r12\n\t" @@ -265,10 +310,10 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "ROR r7, r7, #25\n\t" /* 3, 4, 9, 14 */ /* 0, 5, 10, 15 */ - "ADD %[len], %[len], r4\n\t" - "ADD %[ctx], %[ctx], r5\n\t" - "EOR r12, r12, %[len]\n\t" - "EOR lr, lr, %[ctx]\n\t" + "ADD r3, r3, r4\n\t" + "ADD r0, r0, r5\n\t" + "EOR r12, r12, r3\n\t" + "EOR lr, lr, r0\n\t" "ROR r12, r12, #16\n\t" "ROR lr, lr, #16\n\t" "ADD r9, r9, r12\n\t" @@ -277,10 +322,10 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "EOR r5, r5, r10\n\t" "ROR r4, r4, #20\n\t" "ROR r5, r5, #20\n\t" - "ADD %[len], %[len], r4\n\t" - "ADD %[ctx], %[ctx], r5\n\t" - "EOR r12, r12, %[len]\n\t" - "EOR lr, lr, %[ctx]\n\t" + "ADD r3, r3, r4\n\t" + "ADD r0, r0, r5\n\t" + "EOR r12, r12, r3\n\t" + "EOR lr, lr, r0\n\t" "ROR r12, r12, #24\n\t" "ROR lr, lr, #24\n\t" "ADD r9, r9, r12\n\t" @@ -295,10 +340,10 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "LDR lr, [sp, #20]\n\t" /* 1, 6, 11, 12 */ /* 2, 7, 8, 13 */ - "ADD %[c], %[c], r6\n\t" - "ADD %[m], %[m], r7\n\t" - "EOR r12, r12, %[c]\n\t" - "EOR lr, lr, %[m]\n\t" + "ADD r1, r1, r6\n\t" + "ADD r2, r2, r7\n\t" + "EOR r12, r12, r1\n\t" + "EOR lr, lr, r2\n\t" "ROR r12, r12, #16\n\t" "ROR lr, lr, #16\n\t" "ADD r11, r11, r12\n\t" @@ -307,10 +352,10 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "EOR r7, r7, r8\n\t" "ROR r6, r6, #20\n\t" "ROR r7, r7, #20\n\t" - "ADD %[c], %[c], r6\n\t" - "ADD %[m], %[m], r7\n\t" - "EOR r12, r12, %[c]\n\t" - "EOR lr, lr, %[m]\n\t" + "ADD r1, r1, r6\n\t" + "ADD r2, r2, r7\n\t" + "EOR r12, r12, r1\n\t" + "EOR lr, lr, r2\n\t" "ROR r12, r12, #24\n\t" "ROR lr, lr, #24\n\t" "ADD r11, r11, r12\n\t" @@ -336,10 +381,10 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "MOV r12, sp\n\t" /* Add in original state */ "LDM lr!, {r8, r9, r10, r11}\n\t" - "ADD %[ctx], %[ctx], r8\n\t" - "ADD %[c], %[c], r9\n\t" - "ADD %[m], %[m], r10\n\t" - "ADD %[len], %[len], r11\n\t" + "ADD r0, r0, r8\n\t" + "ADD r1, r1, r9\n\t" + "ADD r2, r2, r10\n\t" + "ADD r3, r3, r11\n\t" "LDM lr!, {r8, r9, r10, r11}\n\t" "ADD r4, r4, r8\n\t" "ADD r5, r5, r9\n\t" @@ -383,14 +428,14 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "LDR r9, [r12, #4]\n\t" "LDR r10, [r12, #8]\n\t" "LDR r11, [r12, #12]\n\t" - "EOR %[ctx], %[ctx], r8\n\t" - "EOR %[c], %[c], r9\n\t" - "EOR %[m], %[m], r10\n\t" - "EOR %[len], %[len], r11\n\t" - "STR %[ctx], [lr]\n\t" - "STR %[c], [lr, #4]\n\t" - "STR %[m], [lr, #8]\n\t" - "STR %[len], [lr, #12]\n\t" + "EOR r0, r0, r8\n\t" + "EOR r1, r1, r9\n\t" + "EOR r2, r2, r10\n\t" + "EOR r3, r3, r11\n\t" + "STR r0, [lr]\n\t" + "STR r1, [lr, #4]\n\t" + "STR r2, [lr, #8]\n\t" + "STR r3, [lr, #12]\n\t" "LDR r8, [r12, #16]\n\t" "LDR r9, [r12, #20]\n\t" "LDR r10, [r12, #24]\n\t" @@ -435,14 +480,14 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "STR r5, [lr, #52]\n\t" "STR r6, [lr, #56]\n\t" "STR r7, [lr, #60]\n\t" - "LDR %[len], [sp, #44]\n\t" + "LDR r3, [sp, #44]\n\t" "ADD r12, r12, #0x40\n\t" "ADD lr, lr, #0x40\n\t" "STR r12, [sp, #40]\n\t" "STR lr, [sp, #36]\n\t" - "SUBS %[len], %[len], #0x40\n\t" + "SUBS r3, r3, #0x40\n\t" "LDR lr, [sp, #32]\n\t" - "STR %[len], [sp, #44]\n\t" + "STR r3, [sp, #44]\n\t" #if defined(__GNUC__) "BNE L_chacha_thumb2_crypt_block_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -466,12 +511,12 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, /* Store in over field of ChaCha. */ "LDR lr, [sp, #32]\n\t" "ADD r12, lr, #0x44\n\t" - "STM r12!, {%[ctx], %[c], %[m], %[len], r4, r5, r6, r7}\n\t" + "STM r12!, {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" "LDM sp, {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" - "STM r12, {%[ctx], %[c], %[m], %[len], r4, r5, r6, r7}\n\t" - "LDRD %[m], %[len], [sp, #40]\n\t" - "LDR %[c], [sp, #36]\n\t" - "RSB r12, %[len], #0x40\n\t" + "STM r12, {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" + "LDRD r2, r3, [sp, #40]\n\t" + "LDR r1, [sp, #36]\n\t" + "RSB r12, r3, #0x40\n\t" "STR r12, [lr, #64]\n\t" "ADD lr, lr, #0x44\n\t" "\n" @@ -480,7 +525,7 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, #else "L_chacha_thumb2_crypt_16byte_loop_%=:\n\t" #endif - "CMP %[len], #16\n\t" + "CMP r3, #16\n\t" #if defined(__GNUC__) "BLT L_chacha_thumb2_crypt_word_loop_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -490,19 +535,19 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, #endif /* 16 bytes of state XORed into message. */ "LDM lr!, {r4, r5, r6, r7}\n\t" - "LDR r8, [%[m]]\n\t" - "LDR r9, [%[m], #4]\n\t" - "LDR r10, [%[m], #8]\n\t" - "LDR r11, [%[m], #12]\n\t" + "LDR r8, [r2]\n\t" + "LDR r9, [r2, #4]\n\t" + "LDR r10, [r2, #8]\n\t" + "LDR r11, [r2, #12]\n\t" "EOR r8, r8, r4\n\t" "EOR r9, r9, r5\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "SUBS %[len], %[len], #16\n\t" - "STR r8, [%[c]]\n\t" - "STR r9, [%[c], #4]\n\t" - "STR r10, [%[c], #8]\n\t" - "STR r11, [%[c], #12]\n\t" + "SUBS r3, r3, #16\n\t" + "STR r8, [r1]\n\t" + "STR r9, [r1, #4]\n\t" + "STR r10, [r1, #8]\n\t" + "STR r11, [r1, #12]\n\t" #if defined(__GNUC__) "BEQ L_chacha_thumb2_crypt_done_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -510,8 +555,8 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, #else "BEQ.N L_chacha_thumb2_crypt_done_%=\n\t" #endif - "ADD %[m], %[m], #16\n\t" - "ADD %[c], %[c], #16\n\t" + "ADD r2, r2, #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "B L_chacha_thumb2_crypt_16byte_loop_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -525,7 +570,7 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, #else "L_chacha_thumb2_crypt_word_loop_%=:\n\t" #endif - "CMP %[len], #4\n\t" + "CMP r3, #4\n\t" #if defined(__GNUC__) "BLT L_chacha_thumb2_crypt_byte_start_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -535,10 +580,10 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, #endif /* 4 bytes of state XORed into message. */ "LDR r4, [lr]\n\t" - "LDR r8, [%[m]]\n\t" + "LDR r8, [r2]\n\t" "EOR r8, r8, r4\n\t" - "SUBS %[len], %[len], #4\n\t" - "STR r8, [%[c]]\n\t" + "SUBS r3, r3, #4\n\t" + "STR r8, [r1]\n\t" #if defined(__GNUC__) "BEQ L_chacha_thumb2_crypt_done_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -547,8 +592,8 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "BEQ.N L_chacha_thumb2_crypt_done_%=\n\t" #endif "ADD lr, lr, #4\n\t" - "ADD %[m], %[m], #4\n\t" - "ADD %[c], %[c], #4\n\t" + "ADD r2, r2, #4\n\t" + "ADD r1, r1, #4\n\t" #if defined(__GNUC__) "B L_chacha_thumb2_crypt_word_loop_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -569,10 +614,10 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, #else "L_chacha_thumb2_crypt_byte_loop_%=:\n\t" #endif - "LDRB r8, [%[m]]\n\t" + "LDRB r8, [r2]\n\t" "EOR r8, r8, r4\n\t" - "SUBS %[len], %[len], #1\n\t" - "STRB r8, [%[c]]\n\t" + "SUBS r3, r3, #1\n\t" + "STRB r8, [r1]\n\t" #if defined(__GNUC__) "BEQ L_chacha_thumb2_crypt_done_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -581,8 +626,8 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "BEQ.N L_chacha_thumb2_crypt_done_%=\n\t" #endif "LSR r4, r4, #8\n\t" - "ADD %[m], %[m], #1\n\t" - "ADD %[c], %[c], #1\n\t" + "ADD r2, r2, #1\n\t" + "ADD r1, r1, #1\n\t" #if defined(__GNUC__) "B L_chacha_thumb2_crypt_byte_loop_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -597,16 +642,28 @@ WC_OMIT_FRAME_POINTER void wc_chacha_crypt_bytes(ChaCha* ctx, byte* c, "L_chacha_thumb2_crypt_done_%=:\n\t" #endif "ADD sp, sp, #52\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [ctx] "+r" (ctx), [c] "+r" (c), [m] "+r" (m), [len] "+r" (len) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [ctx] "r" (ctx), [c] "r" (c), [m] "r" (m), [len] "r" (len) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + ctx = (ChaCha*)(size_t)L_asm_args[0]; + c = (byte*)(size_t)L_asm_args[1]; + m = (const byte*)(size_t)L_asm_args[2]; + len = (word32)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -622,16 +679,25 @@ WC_OMIT_FRAME_POINTER void wc_chacha_use_over(byte* over, byte* output, register byte* output __asm__ ("r1") = (byte*)output_p; register const byte* input __asm__ ("r2") = (const byte*)input_p; register word32 len __asm__ ("r3") = (word32)len_p; +#else + void* L_asm_args[4] = {(void*)(size_t)over, (void*)(size_t)output, + (void*)(size_t)input, (void*)(size_t)len + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_chacha_thumb2_over_16byte_loop:\n\t" #else "L_chacha_thumb2_over_16byte_loop_%=:\n\t" #endif - "CMP %[len], #16\n\t" + "CMP r3, #16\n\t" #if defined(__GNUC__) "BLT L_chacha_thumb2_over_word_loop_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -640,23 +706,23 @@ WC_OMIT_FRAME_POINTER void wc_chacha_use_over(byte* over, byte* output, "BLT.N L_chacha_thumb2_over_word_loop_%=\n\t" #endif /* 16 bytes of state XORed into message. */ - "LDR r4, [%[over]]\n\t" - "LDR r5, [%[over], #4]\n\t" - "LDR r6, [%[over], #8]\n\t" - "LDR r7, [%[over], #12]\n\t" - "LDR r8, [%[input]]\n\t" - "LDR r9, [%[input], #4]\n\t" - "LDR r10, [%[input], #8]\n\t" - "LDR r11, [%[input], #12]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r8, [r2]\n\t" + "LDR r9, [r2, #4]\n\t" + "LDR r10, [r2, #8]\n\t" + "LDR r11, [r2, #12]\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "SUBS %[len], %[len], #16\n\t" - "STR r4, [%[output]]\n\t" - "STR r5, [%[output], #4]\n\t" - "STR r6, [%[output], #8]\n\t" - "STR r7, [%[output], #12]\n\t" + "SUBS r3, r3, #16\n\t" + "STR r4, [r1]\n\t" + "STR r5, [r1, #4]\n\t" + "STR r6, [r1, #8]\n\t" + "STR r7, [r1, #12]\n\t" #if defined(__GNUC__) "BEQ L_chacha_thumb2_over_done_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -664,9 +730,9 @@ WC_OMIT_FRAME_POINTER void wc_chacha_use_over(byte* over, byte* output, #else "BEQ.N L_chacha_thumb2_over_done_%=\n\t" #endif - "ADD %[over], %[over], #16\n\t" - "ADD %[input], %[input], #16\n\t" - "ADD %[output], %[output], #16\n\t" + "ADD r0, r0, #16\n\t" + "ADD r2, r2, #16\n\t" + "ADD r1, r1, #16\n\t" #if defined(__GNUC__) "B L_chacha_thumb2_over_16byte_loop_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -680,7 +746,7 @@ WC_OMIT_FRAME_POINTER void wc_chacha_use_over(byte* over, byte* output, #else "L_chacha_thumb2_over_word_loop_%=:\n\t" #endif - "CMP %[len], #4\n\t" + "CMP r3, #4\n\t" #if defined(__GNUC__) "BLT L_chacha_thumb2_over_byte_loop_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -689,11 +755,11 @@ WC_OMIT_FRAME_POINTER void wc_chacha_use_over(byte* over, byte* output, "BLT.N L_chacha_thumb2_over_byte_loop_%=\n\t" #endif /* 4 bytes of state XORed into message. */ - "LDR r4, [%[over]]\n\t" - "LDR r8, [%[input]]\n\t" + "LDR r4, [r0]\n\t" + "LDR r8, [r2]\n\t" "EOR r4, r4, r8\n\t" - "SUBS %[len], %[len], #4\n\t" - "STR r4, [%[output]]\n\t" + "SUBS r3, r3, #4\n\t" + "STR r4, [r1]\n\t" #if defined(__GNUC__) "BEQ L_chacha_thumb2_over_done_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -701,9 +767,9 @@ WC_OMIT_FRAME_POINTER void wc_chacha_use_over(byte* over, byte* output, #else "BEQ.N L_chacha_thumb2_over_done_%=\n\t" #endif - "ADD %[over], %[over], #4\n\t" - "ADD %[input], %[input], #4\n\t" - "ADD %[output], %[output], #4\n\t" + "ADD r0, r0, #4\n\t" + "ADD r2, r2, #4\n\t" + "ADD r1, r1, #4\n\t" #if defined(__GNUC__) "B L_chacha_thumb2_over_word_loop_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -718,11 +784,11 @@ WC_OMIT_FRAME_POINTER void wc_chacha_use_over(byte* over, byte* output, "L_chacha_thumb2_over_byte_loop_%=:\n\t" #endif /* 4 bytes of state XORed into message. */ - "LDRB r4, [%[over]]\n\t" - "LDRB r8, [%[input]]\n\t" + "LDRB r4, [r0]\n\t" + "LDRB r8, [r2]\n\t" "EOR r4, r4, r8\n\t" - "SUBS %[len], %[len], #1\n\t" - "STRB r4, [%[output]]\n\t" + "SUBS r3, r3, #1\n\t" + "STRB r4, [r1]\n\t" #if defined(__GNUC__) "BEQ L_chacha_thumb2_over_done_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -730,9 +796,9 @@ WC_OMIT_FRAME_POINTER void wc_chacha_use_over(byte* over, byte* output, #else "BEQ.N L_chacha_thumb2_over_done_%=\n\t" #endif - "ADD %[over], %[over], #1\n\t" - "ADD %[input], %[input], #1\n\t" - "ADD %[output], %[output], #1\n\t" + "ADD r0, r0, #1\n\t" + "ADD r2, r2, #1\n\t" + "ADD r1, r1, #1\n\t" #if defined(__GNUC__) "B L_chacha_thumb2_over_byte_loop_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -746,17 +812,28 @@ WC_OMIT_FRAME_POINTER void wc_chacha_use_over(byte* over, byte* output, #else "L_chacha_thumb2_over_done_%=:\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [over] "+r" (over), [output] "+r" (output), [input] "+r" (input), [len] "+r" (len) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [over] "r" (over), [output] "r" (output), [input] "r" (input), - [len] "r" (len) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + over = (byte*)(size_t)L_asm_args[0]; + output = (byte*)(size_t)L_asm_args[1]; + input = (const byte*)(size_t)L_asm_args[2]; + len = (word32)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* HAVE_CHACHA */ diff --git a/wolfcrypt/src/port/arm/thumb2-curve25519_c.c b/wolfcrypt/src/port/arm/thumb2-curve25519_c.c index aff1997f0c6..fd9e213fcbd 100644 --- a/wolfcrypt/src/port/arm/thumb2-curve25519_c.c +++ b/wolfcrypt/src/port/arm/thumb2-curve25519_c.c @@ -243,20 +243,39 @@ WC_OMIT_FRAME_POINTER void fe_sub(fe r, const fe a, const fe b) register sword32* r __asm__ ("r0") = (sword32*)r_p; register const sword32* a __asm__ ("r1") = (const sword32*)a_p; register const sword32* b __asm__ ("r2") = (const sword32*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "BL fe_sub_op\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (const sword32*)(size_t)L_asm_args[1]; + b = (const sword32*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } void fe_add_op(void); @@ -315,20 +334,39 @@ WC_OMIT_FRAME_POINTER void fe_add(fe r, const fe a, const fe b) register sword32* r __asm__ ("r0") = (sword32*)r_p; register const sword32* a __asm__ ("r1") = (const sword32*)a_p; register const sword32* b __asm__ ("r2") = (const sword32*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "BL fe_add_op\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (const sword32*)(size_t)L_asm_args[1]; + b = (const sword32*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #if defined(HAVE_ED25519) || defined(WOLFSSL_CURVE25519_USE_ED25519) @@ -342,35 +380,53 @@ WC_OMIT_FRAME_POINTER void fe_frombytes(fe out, const unsigned char* in) register sword32* out __asm__ ("r0") = (sword32*)out_p; register const unsigned char* in __asm__ ("r1") = (const unsigned char*)in_p; +#else + void* L_asm_args[2] = {(void*)(size_t)out, (void*)(size_t)in + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r2, [%[in]]\n\t" - "LDR r3, [%[in], #4]\n\t" - "LDR r4, [%[in], #8]\n\t" - "LDR r5, [%[in], #12]\n\t" - "LDR r6, [%[in], #16]\n\t" - "LDR r7, [%[in], #20]\n\t" - "LDR r8, [%[in], #24]\n\t" - "LDR r9, [%[in], #28]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r2, [r1]\n\t" + "LDR r3, [r1, #4]\n\t" + "LDR r4, [r1, #8]\n\t" + "LDR r5, [r1, #12]\n\t" + "LDR r6, [r1, #16]\n\t" + "LDR r7, [r1, #20]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r1, #28]\n\t" "BFC r9, #31, #1\n\t" - "STR r2, [%[out]]\n\t" - "STR r3, [%[out], #4]\n\t" - "STR r4, [%[out], #8]\n\t" - "STR r5, [%[out], #12]\n\t" - "STR r6, [%[out], #16]\n\t" - "STR r7, [%[out], #20]\n\t" - "STR r8, [%[out], #24]\n\t" - "STR r9, [%[out], #28]\n\t" + "STR r2, [r0]\n\t" + "STR r3, [r0, #4]\n\t" + "STR r4, [r0, #8]\n\t" + "STR r5, [r0, #12]\n\t" + "STR r6, [r0, #16]\n\t" + "STR r7, [r0, #20]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #28]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [out] "+r" (out), [in] "+r" (in) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [out] "r" (out), [in] "r" (in) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + out = (sword32*)(size_t)L_asm_args[0]; + in = (const unsigned char*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -382,10 +438,18 @@ WC_OMIT_FRAME_POINTER void fe_tobytes(unsigned char* out, const fe n) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register unsigned char* out __asm__ ("r0") = (unsigned char*)out_p; register const sword32* n __asm__ ("r1") = (const sword32*)n_p; +#else + void* L_asm_args[2] = {(void*)(size_t)out, (void*)(size_t)n + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[n], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "ADDS r12, r2, #19\n\t" "ADCS r12, r3, #0\n\t" "ADCS r12, r4, #0\n\t" @@ -405,23 +469,33 @@ WC_OMIT_FRAME_POINTER void fe_tobytes(unsigned char* out, const fe n) "ADCS r8, r8, #0\n\t" "ADC r9, r9, #0\n\t" "BFC r9, #31, #1\n\t" - "STR r2, [%[out]]\n\t" - "STR r3, [%[out], #4]\n\t" - "STR r4, [%[out], #8]\n\t" - "STR r5, [%[out], #12]\n\t" - "STR r6, [%[out], #16]\n\t" - "STR r7, [%[out], #20]\n\t" - "STR r8, [%[out], #24]\n\t" - "STR r9, [%[out], #28]\n\t" + "STR r2, [r0]\n\t" + "STR r3, [r0, #4]\n\t" + "STR r4, [r0, #8]\n\t" + "STR r5, [r0, #12]\n\t" + "STR r6, [r0, #16]\n\t" + "STR r7, [r0, #20]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #28]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [out] "+r" (out), [n] "+r" (n) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [out] "r" (out), [n] "r" (n) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + out = (unsigned char*)(size_t)L_asm_args[0]; + n = (const sword32*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -432,9 +506,17 @@ WC_OMIT_FRAME_POINTER void fe_1(fe n) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sword32* n __asm__ ("r0") = (sword32*)n_p; +#else + void* L_asm_args[1] = {(void*)(size_t)n + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* Set one */ "MOV r2, #1\n\t" "MOV r3, #0\n\t" @@ -444,16 +526,25 @@ WC_OMIT_FRAME_POINTER void fe_1(fe n) "MOV r7, #0\n\t" "MOV r8, #0\n\t" "MOV r9, #0\n\t" - "STM %[n], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "STM r0, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [n] "+r" (n) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [n] "r" (n) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + n = (sword32*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -464,9 +555,17 @@ WC_OMIT_FRAME_POINTER void fe_0(fe n) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sword32* n __asm__ ("r0") = (sword32*)n_p; +#else + void* L_asm_args[1] = {(void*)(size_t)n + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* Set zero */ "MOV r2, #0\n\t" "MOV r3, #0\n\t" @@ -476,16 +575,25 @@ WC_OMIT_FRAME_POINTER void fe_0(fe n) "MOV r7, #0\n\t" "MOV r8, #0\n\t" "MOV r9, #0\n\t" - "STM %[n], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "STM r0, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [n] "+r" (n) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [n] "r" (n) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + n = (sword32*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -497,27 +605,45 @@ WC_OMIT_FRAME_POINTER void fe_copy(fe r, const fe a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sword32* r __asm__ ("r0") = (sword32*)r_p; register const sword32* a __asm__ ("r1") = (const sword32*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* Copy */ - "LDRD r2, r3, [%[a]]\n\t" - "LDRD r4, r5, [%[a], #8]\n\t" - "STRD r2, r3, [%[r]]\n\t" - "STRD r4, r5, [%[r], #8]\n\t" - "LDRD r2, r3, [%[a], #16]\n\t" - "LDRD r4, r5, [%[a], #24]\n\t" - "STRD r2, r3, [%[r], #16]\n\t" - "STRD r4, r5, [%[r], #24]\n\t" + "LDRD r2, r3, [r1]\n\t" + "LDRD r4, r5, [r1, #8]\n\t" + "STRD r2, r3, [r0]\n\t" + "STRD r4, r5, [r0, #8]\n\t" + "LDRD r2, r3, [r1, #16]\n\t" + "LDRD r4, r5, [r1, #24]\n\t" + "STRD r2, r3, [r0, #16]\n\t" + "STRD r4, r5, [r0, #24]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (const sword32*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -529,33 +655,51 @@ WC_OMIT_FRAME_POINTER void fe_neg(fe r, const fe a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sword32* r __asm__ ("r0") = (sword32*)r_p; register const sword32* a __asm__ ("r1") = (const sword32*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MVN lr, #0\n\t" "MVN r12, #18\n\t" - "LDM %[a]!, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r2, r3, r4, r5}\n\t" "SUBS r2, r12, r2\n\t" "SBCS r3, lr, r3\n\t" "SBCS r4, lr, r4\n\t" "SBCS r5, lr, r5\n\t" - "STM %[r]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" "MVN r12, #0x80000000\n\t" - "LDM %[a]!, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r2, r3, r4, r5}\n\t" "SBCS r2, lr, r2\n\t" "SBCS r3, lr, r3\n\t" "SBCS r4, lr, r4\n\t" "SBC r5, r12, r5\n\t" - "STM %[r]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (const sword32*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -566,10 +710,18 @@ WC_OMIT_FRAME_POINTER int fe_isnonzero(const fe a) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sword32* a __asm__ ("r0") = (const sword32*)a_p; +#else + void* L_asm_args[1] = {(void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "ADDS r1, r2, #19\n\t" "ADCS r1, r3, #0\n\t" "ADCS r1, r4, #0\n\t" @@ -595,17 +747,26 @@ WC_OMIT_FRAME_POINTER int fe_isnonzero(const fe a) "ORR r8, r8, r9\n\t" "ORR r4, r4, r6\n\t" "ORR r2, r2, r8\n\t" - "ORR %[a], r2, r4\n\t" + "ORR r0, r2, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a) : + : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sword32*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -617,31 +778,48 @@ WC_OMIT_FRAME_POINTER int fe_isnegative(const fe a) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sword32* a __asm__ ("r0") = (const sword32*)a_p; +#else + void* L_asm_args[1] = {(void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r2, r3, r4, r5}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0!, {r2, r3, r4, r5}\n\t" "AND r12, r2, #1\n\t" "ADDS r1, r2, #19\n\t" "ADCS r1, r3, #0\n\t" "ADCS r1, r4, #0\n\t" "ADCS r1, r5, #0\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" "ADCS r1, r2, #0\n\t" "ADCS r1, r3, #0\n\t" "ADCS r1, r4, #0\n\t" "ADC r1, r5, #0\n\t" "LSR r1, r1, #31\n\t" - "EOR %[a], r12, r1\n\t" + "EOR r0, r12, r1\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a) : + : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sword32*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -659,12 +837,21 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) register fe* r __asm__ ("r0") = (fe*)r_p; register const fe* base __asm__ ("r1") = (const fe*)base_p; register signed char b __asm__ ("r2") = (signed char)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)base, + (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "SXTB %[b], %[b]\n\t" - "SBFX r3, %[b], #7, #1\n\t" - "EOR r12, %[b], r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "SXTB r2, r2\n\t" + "SBFX r3, r2, #7, #1\n\t" + "EOR r12, r2, r3\n\t" "SUB r12, r12, r3\n\t" "MOV r4, #1\n\t" "MOV r5, #0\n\t" @@ -676,216 +863,216 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "ROR r3, r3, #31\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base]]\n\t" + "LDRD r10, r11, [r1]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #32]\n\t" + "LDRD r10, r11, [r1, #32]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #64]\n\t" + "LDRD r10, r11, [r1, #64]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #30\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base]]\n\t" + "LDRD r10, r11, [r1]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #32]\n\t" + "LDRD r10, r11, [r1, #32]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #64]\n\t" + "LDRD r10, r11, [r1, #64]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #29\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base]]\n\t" + "LDRD r10, r11, [r1]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #32]\n\t" + "LDRD r10, r11, [r1, #32]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #64]\n\t" + "LDRD r10, r11, [r1, #64]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #28\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base]]\n\t" + "LDRD r10, r11, [r1]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #32]\n\t" + "LDRD r10, r11, [r1, #32]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #64]\n\t" + "LDRD r10, r11, [r1, #64]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #27\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base]]\n\t" + "LDRD r10, r11, [r1]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #32]\n\t" + "LDRD r10, r11, [r1, #32]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #64]\n\t" + "LDRD r10, r11, [r1, #64]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #26\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base]]\n\t" + "LDRD r10, r11, [r1]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #32]\n\t" + "LDRD r10, r11, [r1, #32]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #64]\n\t" + "LDRD r10, r11, [r1, #64]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #25\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base]]\n\t" + "LDRD r10, r11, [r1]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #32]\n\t" + "LDRD r10, r11, [r1, #32]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #64]\n\t" + "LDRD r10, r11, [r1, #64]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #24\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base]]\n\t" + "LDRD r10, r11, [r1]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #32]\n\t" + "LDRD r10, r11, [r1, #32]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #64]\n\t" + "LDRD r10, r11, [r1, #64]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "SUB %[base], %[base], #0x2a0\n\t" + "SUB r1, r1, #0x2a0\n\t" "MVN r10, #18\n\t" "MVN r11, #0\n\t" "SUBS r10, r10, r8\n\t" "SBCS r11, r11, r9\n\t" "SBC lr, lr, lr\n\t" - "ASR r12, %[b], #31\n\t" + "ASR r12, r2, #31\n\t" "EOR r3, r4, r6\n\t" "AND r3, r3, r12\n\t" "EOR r4, r4, r3\n\t" @@ -900,11 +1087,11 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "EOR r11, r11, r9\n\t" "AND r11, r11, r12\n\t" "EOR r9, r9, r11\n\t" - "STRD r4, r5, [%[r]]\n\t" - "STRD r6, r7, [%[r], #32]\n\t" - "STRD r8, r9, [%[r], #64]\n\t" - "SBFX r3, %[b], #7, #1\n\t" - "EOR r12, %[b], r3\n\t" + "STRD r4, r5, [r0]\n\t" + "STRD r6, r7, [r0, #32]\n\t" + "STRD r8, r9, [r0, #64]\n\t" + "SBFX r3, r2, #7, #1\n\t" + "EOR r12, r2, r3\n\t" "SUB r12, r12, r3\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -916,217 +1103,217 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "ROR r3, r3, #31\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #8]\n\t" + "LDRD r10, r11, [r1, #8]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #40]\n\t" + "LDRD r10, r11, [r1, #40]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #72]\n\t" + "LDRD r10, r11, [r1, #72]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #30\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #8]\n\t" + "LDRD r10, r11, [r1, #8]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #40]\n\t" + "LDRD r10, r11, [r1, #40]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #72]\n\t" + "LDRD r10, r11, [r1, #72]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #29\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #8]\n\t" + "LDRD r10, r11, [r1, #8]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #40]\n\t" + "LDRD r10, r11, [r1, #40]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #72]\n\t" + "LDRD r10, r11, [r1, #72]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #28\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #8]\n\t" + "LDRD r10, r11, [r1, #8]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #40]\n\t" + "LDRD r10, r11, [r1, #40]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #72]\n\t" + "LDRD r10, r11, [r1, #72]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #27\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #8]\n\t" + "LDRD r10, r11, [r1, #8]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #40]\n\t" + "LDRD r10, r11, [r1, #40]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #72]\n\t" + "LDRD r10, r11, [r1, #72]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #26\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #8]\n\t" + "LDRD r10, r11, [r1, #8]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #40]\n\t" + "LDRD r10, r11, [r1, #40]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #72]\n\t" + "LDRD r10, r11, [r1, #72]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #25\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #8]\n\t" + "LDRD r10, r11, [r1, #8]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #40]\n\t" + "LDRD r10, r11, [r1, #40]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #72]\n\t" + "LDRD r10, r11, [r1, #72]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #24\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #8]\n\t" + "LDRD r10, r11, [r1, #8]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #40]\n\t" + "LDRD r10, r11, [r1, #40]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #72]\n\t" + "LDRD r10, r11, [r1, #72]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "SUB %[base], %[base], #0x2a0\n\t" + "SUB r1, r1, #0x2a0\n\t" "MVN r10, #0\n\t" "MVN r11, #0\n\t" "RSBS lr, lr, #0\n\t" "SBCS r10, r10, r8\n\t" "SBCS r11, r11, r9\n\t" "SBC lr, lr, lr\n\t" - "ASR r12, %[b], #31\n\t" + "ASR r12, r2, #31\n\t" "EOR r3, r4, r6\n\t" "AND r3, r3, r12\n\t" "EOR r4, r4, r3\n\t" @@ -1141,11 +1328,11 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "EOR r11, r11, r9\n\t" "AND r11, r11, r12\n\t" "EOR r9, r9, r11\n\t" - "STRD r4, r5, [%[r], #8]\n\t" - "STRD r6, r7, [%[r], #40]\n\t" - "STRD r8, r9, [%[r], #72]\n\t" - "SBFX r3, %[b], #7, #1\n\t" - "EOR r12, %[b], r3\n\t" + "STRD r4, r5, [r0, #8]\n\t" + "STRD r6, r7, [r0, #40]\n\t" + "STRD r8, r9, [r0, #72]\n\t" + "SBFX r3, r2, #7, #1\n\t" + "EOR r12, r2, r3\n\t" "SUB r12, r12, r3\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -1157,217 +1344,217 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "ROR r3, r3, #31\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #16]\n\t" + "LDRD r10, r11, [r1, #16]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #48]\n\t" + "LDRD r10, r11, [r1, #48]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #80]\n\t" + "LDRD r10, r11, [r1, #80]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #30\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #16]\n\t" + "LDRD r10, r11, [r1, #16]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #48]\n\t" + "LDRD r10, r11, [r1, #48]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #80]\n\t" + "LDRD r10, r11, [r1, #80]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #29\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #16]\n\t" + "LDRD r10, r11, [r1, #16]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #48]\n\t" + "LDRD r10, r11, [r1, #48]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #80]\n\t" + "LDRD r10, r11, [r1, #80]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #28\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #16]\n\t" + "LDRD r10, r11, [r1, #16]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #48]\n\t" + "LDRD r10, r11, [r1, #48]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #80]\n\t" + "LDRD r10, r11, [r1, #80]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #27\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #16]\n\t" + "LDRD r10, r11, [r1, #16]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #48]\n\t" + "LDRD r10, r11, [r1, #48]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #80]\n\t" + "LDRD r10, r11, [r1, #80]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #26\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #16]\n\t" + "LDRD r10, r11, [r1, #16]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #48]\n\t" + "LDRD r10, r11, [r1, #48]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #80]\n\t" + "LDRD r10, r11, [r1, #80]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #25\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #16]\n\t" + "LDRD r10, r11, [r1, #16]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #48]\n\t" + "LDRD r10, r11, [r1, #48]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #80]\n\t" + "LDRD r10, r11, [r1, #80]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #24\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #16]\n\t" + "LDRD r10, r11, [r1, #16]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #48]\n\t" + "LDRD r10, r11, [r1, #48]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #80]\n\t" + "LDRD r10, r11, [r1, #80]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "SUB %[base], %[base], #0x2a0\n\t" + "SUB r1, r1, #0x2a0\n\t" "MVN r10, #0\n\t" "MVN r11, #0\n\t" "RSBS lr, lr, #0\n\t" "SBCS r10, r10, r8\n\t" "SBCS r11, r11, r9\n\t" "SBC lr, lr, lr\n\t" - "ASR r12, %[b], #31\n\t" + "ASR r12, r2, #31\n\t" "EOR r3, r4, r6\n\t" "AND r3, r3, r12\n\t" "EOR r4, r4, r3\n\t" @@ -1382,11 +1569,11 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "EOR r11, r11, r9\n\t" "AND r11, r11, r12\n\t" "EOR r9, r9, r11\n\t" - "STRD r4, r5, [%[r], #16]\n\t" - "STRD r6, r7, [%[r], #48]\n\t" - "STRD r8, r9, [%[r], #80]\n\t" - "SBFX r3, %[b], #7, #1\n\t" - "EOR r12, %[b], r3\n\t" + "STRD r4, r5, [r0, #16]\n\t" + "STRD r6, r7, [r0, #48]\n\t" + "STRD r8, r9, [r0, #80]\n\t" + "SBFX r3, r2, #7, #1\n\t" + "EOR r12, r2, r3\n\t" "SUB r12, r12, r3\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -1398,216 +1585,216 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "ROR r3, r3, #31\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #24]\n\t" + "LDRD r10, r11, [r1, #24]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #56]\n\t" + "LDRD r10, r11, [r1, #56]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #88]\n\t" + "LDRD r10, r11, [r1, #88]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #30\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #24]\n\t" + "LDRD r10, r11, [r1, #24]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #56]\n\t" + "LDRD r10, r11, [r1, #56]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #88]\n\t" + "LDRD r10, r11, [r1, #88]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #29\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #24]\n\t" + "LDRD r10, r11, [r1, #24]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #56]\n\t" + "LDRD r10, r11, [r1, #56]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #88]\n\t" + "LDRD r10, r11, [r1, #88]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #28\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #24]\n\t" + "LDRD r10, r11, [r1, #24]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #56]\n\t" + "LDRD r10, r11, [r1, #56]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #88]\n\t" + "LDRD r10, r11, [r1, #88]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #27\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #24]\n\t" + "LDRD r10, r11, [r1, #24]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #56]\n\t" + "LDRD r10, r11, [r1, #56]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #88]\n\t" + "LDRD r10, r11, [r1, #88]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #26\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #24]\n\t" + "LDRD r10, r11, [r1, #24]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #56]\n\t" + "LDRD r10, r11, [r1, #56]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #88]\n\t" + "LDRD r10, r11, [r1, #88]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #25\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #24]\n\t" + "LDRD r10, r11, [r1, #24]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #56]\n\t" + "LDRD r10, r11, [r1, #56]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #88]\n\t" + "LDRD r10, r11, [r1, #88]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "ADD %[base], %[base], #0x60\n\t" + "ADD r1, r1, #0x60\n\t" "MOV r3, #0x80000000\n\t" "ROR r3, r3, #24\n\t" "ROR r3, r3, r12\n\t" "ASR r3, r3, #31\n\t" - "LDRD r10, r11, [%[base], #24]\n\t" + "LDRD r10, r11, [r1, #24]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r4, r4, r10\n\t" "EOR r5, r5, r11\n\t" - "LDRD r10, r11, [%[base], #56]\n\t" + "LDRD r10, r11, [r1, #56]\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r6, r6, r10\n\t" "EOR r7, r7, r11\n\t" - "LDRD r10, r11, [%[base], #88]\n\t" + "LDRD r10, r11, [r1, #88]\n\t" "EOR r10, r10, r8\n\t" "EOR r11, r11, r9\n\t" "AND r10, r10, r3\n\t" "AND r11, r11, r3\n\t" "EOR r8, r8, r10\n\t" "EOR r9, r9, r11\n\t" - "SUB %[base], %[base], #0x2a0\n\t" + "SUB r1, r1, #0x2a0\n\t" "MVN r10, #0\n\t" "MVN r11, #0x80000000\n\t" "RSBS lr, lr, #0\n\t" "SBCS r10, r10, r8\n\t" "SBC r11, r11, r9\n\t" - "ASR r12, %[b], #31\n\t" + "ASR r12, r2, #31\n\t" "EOR r3, r4, r6\n\t" "AND r3, r3, r12\n\t" "EOR r4, r4, r3\n\t" @@ -1622,19 +1809,30 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "EOR r11, r11, r9\n\t" "AND r11, r11, r12\n\t" "EOR r9, r9, r11\n\t" - "STRD r4, r5, [%[r], #24]\n\t" - "STRD r6, r7, [%[r], #56]\n\t" - "STRD r8, r9, [%[r], #88]\n\t" + "STRD r4, r5, [r0, #24]\n\t" + "STRD r6, r7, [r0, #56]\n\t" + "STRD r8, r9, [r0, #88]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [base] "+r" (base), [b] "+r" (b) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r3", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [base] "r" (base), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r3", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (fe*)(size_t)L_asm_args[0]; + base = (const fe*)(size_t)L_asm_args[1]; + b = (signed char)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -1649,22 +1847,31 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) register fe* r __asm__ ("r0") = (fe*)r_p; register const fe* base __asm__ ("r1") = (const fe*)base_p; register signed char b __asm__ ("r2") = (signed char)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)base, + (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "SXTB %[b], %[b]\n\t" - "SBFX r3, %[b], #7, #1\n\t" - "EOR %[b], %[b], r3\n\t" - "SUB %[b], %[b], r3\n\t" - "CLZ lr, %[b]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "SXTB r2, r2\n\t" + "SBFX r3, r2, #7, #1\n\t" + "EOR r2, r2, r3\n\t" + "SUB r2, r2, r3\n\t" + "CLZ lr, r2\n\t" "LSL lr, lr, #26\n\t" "ASR lr, lr, #31\n\t" "MVN lr, lr\n\t" - "ADD %[b], %[b], lr\n\t" + "ADD r2, r2, lr\n\t" "MOV r12, #0x60\n\t" - "MUL %[b], %[b], r12\n\t" - "ADD %[base], %[base], %[b]\n\t" - "LDM %[base]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "MUL r2, r2, r12\n\t" + "ADD r1, r1, r2\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "AND r4, r4, lr\n\t" "AND r5, r5, lr\n\t" "AND r6, r6, lr\n\t" @@ -1677,10 +1884,10 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "SUB r4, r4, r12\n\t" "MOV r12, #32\n\t" "AND r12, r12, r3\n\t" - "ADD %[r], %[r], r12\n\t" - "STM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "SUB %[r], %[r], r12\n\t" - "LDM %[base]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "ADD r0, r0, r12\n\t" + "STM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "SUB r0, r0, r12\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "AND r4, r4, lr\n\t" "AND r5, r5, lr\n\t" "AND r6, r6, lr\n\t" @@ -1693,11 +1900,11 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "SUB r4, r4, r12\n\t" "MOV r12, #32\n\t" "BIC r12, r12, r3\n\t" - "ADD %[r], %[r], r12\n\t" - "STM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "SUB %[r], %[r], r12\n\t" - "ADD %[r], %[r], #0x40\n\t" - "LDM %[base]!, {r4, r5, r6, r7}\n\t" + "ADD r0, r0, r12\n\t" + "STM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "SUB r0, r0, r12\n\t" + "ADD r0, r0, #0x40\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" "MVN r12, #18\n\t" "SUBS r8, r12, r4\n\t" "SBCS r9, r3, r5\n\t" @@ -1719,8 +1926,8 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "AND r5, r5, lr\n\t" "AND r6, r6, lr\n\t" "AND r7, r7, lr\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[base]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" "MVN r12, #0x80000000\n\t" "SBCS r8, r3, r4\n\t" "SBCS r9, r3, r5\n\t" @@ -1742,18 +1949,29 @@ WC_OMIT_FRAME_POINTER void fe_cmov_table(fe* r, const fe* base, signed char b) "AND r5, r5, lr\n\t" "AND r6, r6, lr\n\t" "AND r7, r7, lr\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "SUB %[base], %[base], %[b]\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "SUB r1, r1, r2\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [base] "+r" (base), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [base] "r" (base), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (fe*)(size_t)L_asm_args[0]; + base = (const fe*)(size_t)L_asm_args[1]; + b = (signed char)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WC_NO_CACHE_RESISTANT */ @@ -2879,20 +3097,39 @@ WC_OMIT_FRAME_POINTER void fe_mul(fe r, const fe a, const fe b) register sword32* r __asm__ ("r0") = (sword32*)r_p; register const sword32* a __asm__ ("r1") = (const sword32*)a_p; register const sword32* b __asm__ ("r2") = (const sword32*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "BL fe_mul_op\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (const sword32*)(size_t)L_asm_args[1]; + b = (const sword32*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifdef WOLFSSL_ARM_ARCH_7M @@ -3771,20 +4008,38 @@ WC_OMIT_FRAME_POINTER void fe_sq(fe r, const fe a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sword32* r __asm__ ("r0") = (sword32*)r_p; register const sword32* a __asm__ ("r1") = (const sword32*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "BL fe_sq_op\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (const sword32*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifdef HAVE_CURVE25519 @@ -3798,11 +4053,19 @@ WC_OMIT_FRAME_POINTER void fe_mul121666(fe r, fe a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sword32* r __asm__ ("r0") = (sword32*)r_p; register sword32* a __asm__ ("r1") = (sword32*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* Multiply by 121666 */ - "LDM %[a], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "LDM r1, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "MOV r10, #0xdb42\n\t" "MOVT r10, #0x1\n\t" "UMULL r2, r12, r2, r10\n\t" @@ -3840,17 +4103,27 @@ WC_OMIT_FRAME_POINTER void fe_mul121666(fe r, fe a) "BFC r9, #31, #1\n\t" "ADCS r8, r8, #0\n\t" "ADC r9, r9, #0\n\t" - "STM %[r], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "STM r0, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r12", + "lr", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r12", - "lr", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (sword32*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -3863,11 +4136,19 @@ WC_OMIT_FRAME_POINTER void fe_mul121666(fe r, fe a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sword32* r __asm__ ("r0") = (sword32*)r_p; register sword32* a __asm__ ("r1") = (sword32*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* Multiply by 121666 */ - "LDM %[a], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "LDM r1, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "MOV lr, #0xdb42\n\t" "MOVT lr, #0x1\n\t" "UMULL r2, r10, r2, lr\n\t" @@ -3892,17 +4173,27 @@ WC_OMIT_FRAME_POINTER void fe_mul121666(fe r, fe a) "BFC r9, #31, #1\n\t" "ADCS r8, r8, #0\n\t" "ADC r9, r9, #0\n\t" - "STM %[r], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "STM r0, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r12", + "lr", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r12", - "lr", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (sword32*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_ARM_ARCH_7M */ @@ -3918,15 +4209,23 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) register byte* r __asm__ ("r0") = (byte*)r_p; register const byte* n __asm__ ("r1") = (const byte*)n_p; register const byte* a __asm__ ("r2") = (const byte*)a_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)n, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0xbc\n\t" - "STR %[r], [sp, #160]\n\t" - "STR %[n], [sp, #164]\n\t" - "STR %[a], [sp, #168]\n\t" - "MOV %[n], #0\n\t" - "STR %[n], [sp, #172]\n\t" + "STR r0, [sp, #160]\n\t" + "STR r1, [sp, #164]\n\t" + "STR r2, [sp, #168]\n\t" + "MOV r1, #0\n\t" + "STR r1, [sp, #172]\n\t" "MOV r4, #1\n\t" "MOV r5, #0\n\t" "MOV r6, #0\n\t" @@ -3935,7 +4234,7 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "MOV r9, #0\n\t" "MOV r10, #0\n\t" "MOV r11, #0\n\t" - "STM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADD r3, sp, #32\n\t" "STM r3, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "MOV r4, #0\n\t" @@ -3945,10 +4244,10 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) /* Copy */ "LDM r2, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "STM r3, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "MOV %[n], #30\n\t" - "STR %[n], [sp, #180]\n\t" - "MOV %[a], #28\n\t" - "STR %[a], [sp, #176]\n\t" + "MOV r1, #30\n\t" + "STR r1, [sp, #180]\n\t" + "MOV r2, #28\n\t" + "STR r2, [sp, #176]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_curve25519_words:\n\t" @@ -3961,26 +4260,26 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) #else "L_curve25519_bits_%=:\n\t" #endif - "LDR %[n], [sp, #164]\n\t" - "LDR %[a], [%[n], r2]\n\t" - "LDR %[n], [sp, #180]\n\t" - "LSR %[a], %[a], %[n]\n\t" - "AND %[a], %[a], #1\n\t" - "STR %[a], [sp, #184]\n\t" - "LDR %[n], [sp, #172]\n\t" - "EOR %[n], %[n], %[a]\n\t" - "STR %[n], [sp, #172]\n\t" - "LDR %[r], [sp, #160]\n\t" + "LDR r1, [sp, #164]\n\t" + "LDR r2, [r1, r2]\n\t" + "LDR r1, [sp, #180]\n\t" + "LSR r2, r2, r1\n\t" + "AND r2, r2, #1\n\t" + "STR r2, [sp, #184]\n\t" + "LDR r1, [sp, #172]\n\t" + "EOR r1, r1, r2\n\t" + "STR r1, [sp, #172]\n\t" + "LDR r0, [sp, #160]\n\t" /* Conditional Swap */ - "RSB %[n], %[n], #0\n\t" + "RSB r1, r1, #0\n\t" "MOV r3, r0\n\t" "ADD r12, sp, #0x40\n\t" "LDM r3, {r4, r5}\n\t" "LDM r12, {r6, r7}\n\t" "EOR r8, r4, r6\n\t" "EOR r9, r5, r7\n\t" - "AND r8, r8, %[n]\n\t" - "AND r9, r9, %[n]\n\t" + "AND r8, r8, r1\n\t" + "AND r9, r9, r1\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r8\n\t" @@ -3991,8 +4290,8 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "LDM r12, {r6, r7}\n\t" "EOR r8, r4, r6\n\t" "EOR r9, r5, r7\n\t" - "AND r8, r8, %[n]\n\t" - "AND r9, r9, %[n]\n\t" + "AND r8, r8, r1\n\t" + "AND r9, r9, r1\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r8\n\t" @@ -4003,8 +4302,8 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "LDM r12, {r6, r7}\n\t" "EOR r8, r4, r6\n\t" "EOR r9, r5, r7\n\t" - "AND r8, r8, %[n]\n\t" - "AND r9, r9, %[n]\n\t" + "AND r8, r8, r1\n\t" + "AND r9, r9, r1\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r8\n\t" @@ -4015,25 +4314,25 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "LDM r12, {r6, r7}\n\t" "EOR r8, r4, r6\n\t" "EOR r9, r5, r7\n\t" - "AND r8, r8, %[n]\n\t" - "AND r9, r9, %[n]\n\t" + "AND r8, r8, r1\n\t" + "AND r9, r9, r1\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "STM r3!, {r4, r5}\n\t" "STM r12!, {r6, r7}\n\t" - "LDR %[n], [sp, #172]\n\t" + "LDR r1, [sp, #172]\n\t" /* Conditional Swap */ - "RSB %[n], %[n], #0\n\t" + "RSB r1, r1, #0\n\t" "MOV r3, sp\n\t" "ADD r12, sp, #32\n\t" "LDM r3, {r4, r5}\n\t" "LDM r12, {r6, r7}\n\t" "EOR r8, r4, r6\n\t" "EOR r9, r5, r7\n\t" - "AND r8, r8, %[n]\n\t" - "AND r9, r9, %[n]\n\t" + "AND r8, r8, r1\n\t" + "AND r9, r9, r1\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r8\n\t" @@ -4044,8 +4343,8 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "LDM r12, {r6, r7}\n\t" "EOR r8, r4, r6\n\t" "EOR r9, r5, r7\n\t" - "AND r8, r8, %[n]\n\t" - "AND r9, r9, %[n]\n\t" + "AND r8, r8, r1\n\t" + "AND r9, r9, r1\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r8\n\t" @@ -4056,8 +4355,8 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "LDM r12, {r6, r7}\n\t" "EOR r8, r4, r6\n\t" "EOR r9, r5, r7\n\t" - "AND r8, r8, %[n]\n\t" - "AND r9, r9, %[n]\n\t" + "AND r8, r8, r1\n\t" + "AND r9, r9, r1\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r8\n\t" @@ -4068,16 +4367,16 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "LDM r12, {r6, r7}\n\t" "EOR r8, r4, r6\n\t" "EOR r9, r5, r7\n\t" - "AND r8, r8, %[n]\n\t" - "AND r9, r9, %[n]\n\t" + "AND r8, r8, r1\n\t" + "AND r9, r9, r1\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r9\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "STM r3!, {r4, r5}\n\t" "STM r12!, {r6, r7}\n\t" - "LDR %[n], [sp, #184]\n\t" - "STR %[n], [sp, #172]\n\t" + "LDR r1, [sp, #184]\n\t" + "STR r1, [sp, #172]\n\t" "MOV r3, sp\n\t" "LDR r2, [sp, #160]\n\t" "ADD r1, sp, #0x80\n\t" @@ -4136,10 +4435,10 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "ADD r1, sp, #0x60\n\t" "MOV r0, sp\n\t" "BL fe_mul_op_full_red\n\t" - "LDR %[a], [sp, #176]\n\t" - "LDR %[n], [sp, #180]\n\t" - "SUBS %[n], %[n], #1\n\t" - "STR %[n], [sp, #180]\n\t" + "LDR r2, [sp, #176]\n\t" + "LDR r1, [sp, #180]\n\t" + "SUBS r1, r1, #1\n\t" + "STR r1, [sp, #180]\n\t" #if defined(__GNUC__) "BGE L_curve25519_bits_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -4147,10 +4446,10 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) #else "BGE.W L_curve25519_bits_%=\n\t" #endif - "MOV %[n], #31\n\t" - "STR %[n], [sp, #180]\n\t" - "SUBS %[a], %[a], #4\n\t" - "STR %[a], [sp, #176]\n\t" + "MOV r1, #31\n\t" + "STR r1, [sp, #180]\n\t" + "SUBS r2, r2, #4\n\t" + "STR r2, [sp, #176]\n\t" #if defined(__GNUC__) "BGE L_curve25519_words_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -4395,19 +4694,19 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "LDR r0, [sp, #160]\n\t" "BL fe_mul_op\n\t" /* Ensure result is less than modulus */ - "LDR %[r], [sp, #160]\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "ADDS %[a], r4, #19\n\t" - "ADCS %[a], r5, #0\n\t" - "ADCS %[a], r6, #0\n\t" - "ADCS %[a], r7, #0\n\t" - "ADCS %[a], r8, #0\n\t" - "ADCS %[a], r9, #0\n\t" - "ADCS %[a], r10, #0\n\t" - "ADC %[a], r11, #0\n\t" - "ASR %[a], %[a], #31\n\t" - "AND %[a], %[a], #19\n\t" - "ADDS r4, r4, %[a]\n\t" + "LDR r0, [sp, #160]\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "ADDS r2, r4, #19\n\t" + "ADCS r2, r5, #0\n\t" + "ADCS r2, r6, #0\n\t" + "ADCS r2, r7, #0\n\t" + "ADCS r2, r8, #0\n\t" + "ADCS r2, r9, #0\n\t" + "ADCS r2, r10, #0\n\t" + "ADC r2, r11, #0\n\t" + "ASR r2, r2, #31\n\t" + "AND r2, r2, #19\n\t" + "ADDS r4, r4, r2\n\t" "ADCS r5, r5, #0\n\t" "ADCS r6, r6, #0\n\t" "ADCS r7, r7, #0\n\t" @@ -4416,19 +4715,30 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "ADCS r10, r10, #0\n\t" "ADC r11, r11, #0\n\t" "BFC r11, #31, #1\n\t" - "STM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "MOV r0, #0\n\t" "ADD sp, sp, #0xbc\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [n] "+r" (n), [a] "+r" (a) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [n] "r" (n), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (byte*)(size_t)L_asm_args[0]; + n = (const byte*)(size_t)L_asm_args[1]; + a = (const byte*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -4444,20 +4754,28 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) register byte* r __asm__ ("r0") = (byte*)r_p; register const byte* n __asm__ ("r1") = (const byte*)n_p; register const byte* a __asm__ ("r2") = (const byte*)a_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)n, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0xc0\n\t" - "STR %[r], [sp, #176]\n\t" - "STR %[n], [sp, #160]\n\t" - "STR %[a], [sp, #172]\n\t" + "STR r0, [sp, #176]\n\t" + "STR r1, [sp, #160]\n\t" + "STR r2, [sp, #172]\n\t" "ADD r5, sp, #0x40\n\t" "ADD r4, sp, #32\n\t" "STR sp, [sp, #184]\n\t" "STR r5, [sp, #180]\n\t" "STR r4, [sp, #188]\n\t" - "MOV %[n], #0\n\t" - "STR %[n], [sp, #164]\n\t" + "MOV r1, #0\n\t" + "STR r1, [sp, #164]\n\t" "MOV r4, #1\n\t" "MOV r5, #0\n\t" "MOV r6, #0\n\t" @@ -4466,7 +4784,7 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "MOV r9, #0\n\t" "MOV r10, #0\n\t" "MOV r11, #0\n\t" - "STM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADD r3, sp, #32\n\t" "STM r3, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "MOV r4, #0\n\t" @@ -4476,31 +4794,31 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) /* Copy */ "LDM r2, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "STM r3, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "MOV %[a], #0xfe\n\t" + "MOV r2, #0xfe\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_curve25519_bits:\n\t" #else "L_curve25519_bits_%=:\n\t" #endif - "STR %[a], [sp, #168]\n\t" - "LDR %[n], [sp, #160]\n\t" - "AND r4, %[a], #31\n\t" - "LSR %[a], %[a], #5\n\t" - "LDR %[a], [%[n], r2, LSL #2]\n\t" + "STR r2, [sp, #168]\n\t" + "LDR r1, [sp, #160]\n\t" + "AND r4, r2, #31\n\t" + "LSR r2, r2, #5\n\t" + "LDR r2, [r1, r2, LSL #2]\n\t" "RSB r4, r4, #31\n\t" - "LSL %[a], %[a], r4\n\t" - "LDR %[n], [sp, #164]\n\t" - "EOR %[n], %[n], %[a]\n\t" - "ASR %[n], %[n], #31\n\t" - "STR %[a], [sp, #164]\n\t" + "LSL r2, r2, r4\n\t" + "LDR r1, [sp, #164]\n\t" + "EOR r1, r1, r2\n\t" + "ASR r1, r1, #31\n\t" + "STR r2, [sp, #164]\n\t" /* Conditional Swap */ "ADD r11, sp, #0xb0\n\t" "LDM r11, {r4, r5, r6, r7}\n\t" "EOR r8, r4, r5\n\t" "EOR r9, r6, r7\n\t" - "AND r8, r8, %[n]\n\t" - "AND r9, r9, %[n]\n\t" + "AND r8, r8, r1\n\t" + "AND r9, r9, r1\n\t" "EOR r4, r4, r8\n\t" "EOR r5, r5, r8\n\t" "EOR r6, r6, r9\n\t" @@ -4565,8 +4883,8 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "ADD r1, sp, #0x80\n\t" "LDR r0, [sp, #184]\n\t" "BL fe_mul_op_full_red\n\t" - "LDR %[a], [sp, #168]\n\t" - "SUBS %[a], %[a], #1\n\t" + "LDR r2, [sp, #168]\n\t" + "SUBS r2, r2, #1\n\t" #if defined(__GNUC__) "BGE L_curve25519_bits_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -4575,7 +4893,7 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "BGE.N L_curve25519_bits_%=\n\t" #endif /* Cycle Count: 166 */ - "LDR %[n], [sp, #184]\n\t" + "LDR r1, [sp, #184]\n\t" /* Copy */ "LDM r1, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "STM sp, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" @@ -4816,19 +5134,19 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "LDR r0, [sp, #176]\n\t" "BL fe_mul_op\n\t" /* Ensure result is less than modulus */ - "LDR %[r], [sp, #176]\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "ADDS %[a], r4, #19\n\t" - "ADCS %[a], r5, #0\n\t" - "ADCS %[a], r6, #0\n\t" - "ADCS %[a], r7, #0\n\t" - "ADCS %[a], r8, #0\n\t" - "ADCS %[a], r9, #0\n\t" - "ADCS %[a], r10, #0\n\t" - "ADC %[a], r11, #0\n\t" - "ASR %[a], %[a], #31\n\t" - "AND %[a], %[a], #19\n\t" - "ADDS r4, r4, %[a]\n\t" + "LDR r0, [sp, #176]\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "ADDS r2, r4, #19\n\t" + "ADCS r2, r5, #0\n\t" + "ADCS r2, r6, #0\n\t" + "ADCS r2, r7, #0\n\t" + "ADCS r2, r8, #0\n\t" + "ADCS r2, r9, #0\n\t" + "ADCS r2, r10, #0\n\t" + "ADC r2, r11, #0\n\t" + "ASR r2, r2, #31\n\t" + "AND r2, r2, #19\n\t" + "ADDS r4, r4, r2\n\t" "ADCS r5, r5, #0\n\t" "ADCS r6, r6, #0\n\t" "ADCS r7, r7, #0\n\t" @@ -4837,19 +5155,30 @@ WC_OMIT_FRAME_POINTER int curve25519(byte* r, const byte* n, const byte* a) "ADCS r10, r10, #0\n\t" "ADC r11, r11, #0\n\t" "BFC r11, #31, #1\n\t" - "STM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "MOV r0, #0\n\t" "ADD sp, sp, #0xc0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [n] "+r" (n), [a] "+r" (a) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [n] "r" (n), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (byte*)(size_t)L_asm_args[0]; + n = (const byte*)(size_t)L_asm_args[1]; + a = (const byte*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -4865,13 +5194,21 @@ WC_OMIT_FRAME_POINTER void fe_invert(fe r, const fe a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sword32* r __asm__ ("r0") = (sword32*)r_p; register const sword32* a __asm__ ("r1") = (const sword32*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x88\n\t" /* Invert */ - "STR %[r], [sp, #128]\n\t" - "STR %[a], [sp, #132]\n\t" + "STR r0, [sp, #128]\n\t" + "STR r1, [sp, #132]\n\t" "LDR r1, [sp, #132]\n\t" "MOV r0, sp\n\t" "BL fe_sq_op\n\t" @@ -5103,19 +5440,29 @@ WC_OMIT_FRAME_POINTER void fe_invert(fe r, const fe a) "ADD r1, sp, #32\n\t" "LDR r0, [sp, #128]\n\t" "BL fe_mul_op\n\t" - "LDR %[a], [sp, #132]\n\t" - "LDR %[r], [sp, #128]\n\t" + "LDR r1, [sp, #132]\n\t" + "LDR r0, [sp, #128]\n\t" "ADD sp, sp, #0x88\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "lr", "r12", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "lr", "r12", "r2", "r3", "r4", "r5", "r6", "r7", "r8", - "r9", "r10", "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (const sword32*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifdef WOLFSSL_ARM_ARCH_7M @@ -5128,9 +5475,17 @@ WC_OMIT_FRAME_POINTER void fe_sq2(fe r, const fe a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sword32* r __asm__ ("r0") = (sword32*)r_p; register const sword32* a __asm__ ("r1") = (const sword32*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x44\n\t" "STR r0, [sp, #64]\n\t" /* Square * 2 */ @@ -5445,15 +5800,25 @@ WC_OMIT_FRAME_POINTER void fe_sq2(fe r, const fe a) "LDR r0, [sp, #64]\n\t" "STM r0, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" "ADD sp, sp, #0x44\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (const sword32*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -5466,9 +5831,17 @@ WC_OMIT_FRAME_POINTER void fe_sq2(fe r, const fe a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sword32* r __asm__ ("r0") = (sword32*)r_p; register const sword32* a __asm__ ("r1") = (const sword32*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #36\n\t" "STRD r0, r1, [sp, #28]\n\t" "LDM r1, {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" @@ -5632,15 +6005,25 @@ WC_OMIT_FRAME_POINTER void fe_sq2(fe r, const fe a) "STM r12, {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" "MOV r0, r12\n\t" "MOV r1, lr\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (const sword32*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_ARM_ARCH_7M */ @@ -5653,13 +6036,21 @@ WC_OMIT_FRAME_POINTER void fe_pow22523(fe r, const fe a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sword32* r __asm__ ("r0") = (sword32*)r_p; register const sword32* a __asm__ ("r1") = (const sword32*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x68\n\t" /* pow22523 */ - "STR %[r], [sp, #96]\n\t" - "STR %[a], [sp, #100]\n\t" + "STR r0, [sp, #96]\n\t" + "STR r1, [sp, #100]\n\t" "LDR r1, [sp, #100]\n\t" "MOV r0, sp\n\t" "BL fe_sq_op\n\t" @@ -5891,19 +6282,29 @@ WC_OMIT_FRAME_POINTER void fe_pow22523(fe r, const fe a) "MOV r1, sp\n\t" "LDR r0, [sp, #96]\n\t" "BL fe_mul_op\n\t" - "LDR %[a], [sp, #100]\n\t" - "LDR %[r], [sp, #96]\n\t" + "LDR r1, [sp, #100]\n\t" + "LDR r0, [sp, #96]\n\t" "ADD sp, sp, #0x68\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "lr", "r12", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "lr", "r12", "r2", "r3", "r4", "r5", "r6", "r7", "r8", - "r9", "r10", "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword32*)(size_t)L_asm_args[0]; + a = (const sword32*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -5915,12 +6316,20 @@ WC_OMIT_FRAME_POINTER void ge_p1p1_to_p2(ge_p2 * r, const ge_p1p1 * p) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register ge_p2 * r __asm__ ("r0") = (ge_p2 *)r_p; register const ge_p1p1 * p __asm__ ("r1") = (const ge_p1p1 *)p_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)p + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #8\n\t" - "STR %[r], [sp]\n\t" - "STR %[p], [sp, #4]\n\t" + "STR r0, [sp]\n\t" + "STR r1, [sp, #4]\n\t" "ADD r2, r1, #0x60\n\t" "BL fe_mul_op\n\t" "LDR r0, [sp]\n\t" @@ -5936,16 +6345,26 @@ WC_OMIT_FRAME_POINTER void ge_p1p1_to_p2(ge_p2 * r, const ge_p1p1 * p) "ADD r0, r0, #0x40\n\t" "BL fe_mul_op\n\t" "ADD sp, sp, #8\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [p] "+r" (p) : + : "memory", "cc", "lr", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + "r10", "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [p] "r" (p) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "lr", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", - "r10", "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (ge_p2 *)(size_t)L_asm_args[0]; + p = (const ge_p1p1 *)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -5957,12 +6376,20 @@ WC_OMIT_FRAME_POINTER void ge_p1p1_to_p3(ge_p3 * r, const ge_p1p1 * p) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register ge_p3 * r __asm__ ("r0") = (ge_p3 *)r_p; register const ge_p1p1 * p __asm__ ("r1") = (const ge_p1p1 *)p_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)p + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #8\n\t" - "STR %[r], [sp]\n\t" - "STR %[p], [sp, #4]\n\t" + "STR r0, [sp]\n\t" + "STR r1, [sp, #4]\n\t" "ADD r2, r1, #0x60\n\t" "BL fe_mul_op\n\t" "LDR r0, [sp]\n\t" @@ -5983,16 +6410,26 @@ WC_OMIT_FRAME_POINTER void ge_p1p1_to_p3(ge_p3 * r, const ge_p1p1 * p) "ADD r0, r0, #0x60\n\t" "BL fe_mul_op\n\t" "ADD sp, sp, #8\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [p] "+r" (p) : + : "memory", "cc", "lr", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + "r10", "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [p] "r" (p) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "lr", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", - "r10", "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (ge_p3 *)(size_t)L_asm_args[0]; + p = (const ge_p1p1 *)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -6004,12 +6441,20 @@ WC_OMIT_FRAME_POINTER void ge_p2_dbl(ge_p1p1 * r, const ge_p2 * p) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register ge_p1p1 * r __asm__ ("r0") = (ge_p1p1 *)r_p; register const ge_p2 * p __asm__ ("r1") = (const ge_p2 *)p_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)p + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #8\n\t" - "STR %[r], [sp]\n\t" - "STR %[p], [sp, #4]\n\t" + "STR r0, [sp]\n\t" + "STR r1, [sp, #4]\n\t" "BL fe_sq_op\n\t" "LDR r0, [sp]\n\t" "LDR r1, [sp, #4]\n\t" @@ -6042,16 +6487,26 @@ WC_OMIT_FRAME_POINTER void ge_p2_dbl(ge_p1p1 * r, const ge_p2 * p) "MOV r1, r0\n\t" "BL fe_sub_op\n\t" "ADD sp, sp, #8\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [p] "+r" (p) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [p] "r" (p) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (ge_p1p1 *)(size_t)L_asm_args[0]; + p = (const ge_p2 *)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -6066,13 +6521,21 @@ WC_OMIT_FRAME_POINTER void ge_madd(ge_p1p1 * r, const ge_p3 * p, register ge_p1p1 * r __asm__ ("r0") = (ge_p1p1 *)r_p; register const ge_p3 * p __asm__ ("r1") = (const ge_p3 *)p_p; register const ge_precomp * q __asm__ ("r2") = (const ge_precomp *)q_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)p, (void*)(size_t)q + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #12\n\t" - "STR %[r], [sp]\n\t" - "STR %[p], [sp, #4]\n\t" - "STR %[q], [sp, #8]\n\t" + "STR r0, [sp]\n\t" + "STR r1, [sp, #4]\n\t" + "STR r2, [sp, #8]\n\t" "MOV r2, r1\n\t" "ADD r1, r1, #32\n\t" "BL fe_add_op\n\t" @@ -6138,16 +6601,27 @@ WC_OMIT_FRAME_POINTER void ge_madd(ge_p1p1 * r, const ge_p3 * p, "ADD r1, r0, #32\n\t" "BL fe_add_sub_op\n\t" "ADD sp, sp, #12\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [p] "+r" (p), [q] "+r" (q) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [p] "r" (p), [q] "r" (q) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (ge_p1p1 *)(size_t)L_asm_args[0]; + p = (const ge_p3 *)(size_t)L_asm_args[1]; + q = (const ge_precomp *)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -6162,13 +6636,21 @@ WC_OMIT_FRAME_POINTER void ge_msub(ge_p1p1 * r, const ge_p3 * p, register ge_p1p1 * r __asm__ ("r0") = (ge_p1p1 *)r_p; register const ge_p3 * p __asm__ ("r1") = (const ge_p3 *)p_p; register const ge_precomp * q __asm__ ("r2") = (const ge_precomp *)q_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)p, (void*)(size_t)q + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #12\n\t" - "STR %[r], [sp]\n\t" - "STR %[p], [sp, #4]\n\t" - "STR %[q], [sp, #8]\n\t" + "STR r0, [sp]\n\t" + "STR r1, [sp, #4]\n\t" + "STR r2, [sp, #8]\n\t" "MOV r2, r1\n\t" "ADD r1, r1, #32\n\t" "BL fe_add_op\n\t" @@ -6235,16 +6717,27 @@ WC_OMIT_FRAME_POINTER void ge_msub(ge_p1p1 * r, const ge_p3 * p, "ADD r0, r0, #32\n\t" "BL fe_add_sub_op\n\t" "ADD sp, sp, #12\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [p] "+r" (p), [q] "+r" (q) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [p] "r" (p), [q] "r" (q) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (ge_p1p1 *)(size_t)L_asm_args[0]; + p = (const ge_p3 *)(size_t)L_asm_args[1]; + q = (const ge_precomp *)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -6259,13 +6752,21 @@ WC_OMIT_FRAME_POINTER void ge_add(ge_p1p1 * r, const ge_p3 * p, register ge_p1p1 * r __asm__ ("r0") = (ge_p1p1 *)r_p; register const ge_p3 * p __asm__ ("r1") = (const ge_p3 *)p_p; register const ge_cached* q __asm__ ("r2") = (const ge_cached*)q_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)p, (void*)(size_t)q + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #44\n\t" - "STR %[r], [sp]\n\t" - "STR %[p], [sp, #4]\n\t" - "STR %[q], [sp, #8]\n\t" + "STR r0, [sp]\n\t" + "STR r1, [sp, #4]\n\t" + "STR r2, [sp, #8]\n\t" "MOV r3, r1\n\t" "ADD r2, r1, #32\n\t" "ADD r1, r0, #32\n\t" @@ -6332,16 +6833,27 @@ WC_OMIT_FRAME_POINTER void ge_add(ge_p1p1 * r, const ge_p3 * p, "ADD r0, r0, #32\n\t" "BL fe_add_sub_op\n\t" "ADD sp, sp, #44\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [p] "+r" (p), [q] "+r" (q) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [p] "r" (p), [q] "r" (q) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (ge_p1p1 *)(size_t)L_asm_args[0]; + p = (const ge_p3 *)(size_t)L_asm_args[1]; + q = (const ge_cached*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -6356,13 +6868,21 @@ WC_OMIT_FRAME_POINTER void ge_sub(ge_p1p1 * r, const ge_p3 * p, register ge_p1p1 * r __asm__ ("r0") = (ge_p1p1 *)r_p; register const ge_p3 * p __asm__ ("r1") = (const ge_p3 *)p_p; register const ge_cached* q __asm__ ("r2") = (const ge_cached*)q_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)p, (void*)(size_t)q + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #44\n\t" - "STR %[r], [sp]\n\t" - "STR %[p], [sp, #4]\n\t" - "STR %[q], [sp, #8]\n\t" + "STR r0, [sp]\n\t" + "STR r1, [sp, #4]\n\t" + "STR r2, [sp, #8]\n\t" "MOV r3, r1\n\t" "ADD r2, r1, #32\n\t" "ADD r1, r0, #32\n\t" @@ -6429,16 +6949,27 @@ WC_OMIT_FRAME_POINTER void ge_sub(ge_p1p1 * r, const ge_p3 * p, "ADD r0, r0, #0x40\n\t" "BL fe_add_sub_op\n\t" "ADD sp, sp, #44\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [p] "+r" (p), [q] "+r" (q) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [p] "r" (p), [q] "r" (q) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (ge_p1p1 *)(size_t)L_asm_args[0]; + p = (const ge_p3 *)(size_t)L_asm_args[1]; + q = (const ge_cached*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* HAVE_ED25519 || WOLFSSL_CURVE25519_USE_ED25519 */ @@ -6452,14 +6983,22 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register byte* s __asm__ ("r0") = (byte*)s_p; +#else + void* L_asm_args[1] = {(void*)(size_t)s + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #56\n\t" - "STR %[s], [sp, #52]\n\t" + "STR r0, [sp, #52]\n\t" /* Load bits 252-511 */ - "ADD %[s], %[s], #28\n\t" - "LDM %[s], {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "ADD r0, r0, #28\n\t" + "LDM r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "LSR lr, r9, #24\n\t" "LSL r9, r9, #4\n\t" "ORR r9, r9, r8, LSR #28\n\t" @@ -6478,7 +7017,7 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "LSL r2, r2, #4\n\t" "ORR r2, r2, r1, LSR #28\n\t" "BFC r9, #28, #4\n\t" - "SUB %[s], %[s], #28\n\t" + "SUB r0, r0, #28\n\t" /* Add order times bits 504..511 */ "MOV r10, #0x2c13\n\t" "MOVT r10, #0xa30a\n\t" @@ -6515,14 +7054,14 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "MOV r1, #0x2c13\n\t" "MOVT r1, #0xa30a\n\t" "MOV lr, #0\n\t" - "LDM %[s]!, {r10, r11}\n\t" + "LDM r0!, {r10, r11}\n\t" "UMLAL r10, lr, r2, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" "UMLAL r11, lr, r3, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" + "LDM r0!, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" @@ -6532,7 +7071,7 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "ADC lr, lr, #0\n\t" "UMLAL r11, lr, r5, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" + "LDM r0!, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" @@ -6542,7 +7081,7 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "ADC lr, lr, #0\n\t" "UMLAL r11, lr, r7, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" + "LDM r0!, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" @@ -6553,7 +7092,7 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "ADC lr, lr, #0\n\t" "UMLAL r11, lr, r9, r1\n\t" "STM r12!, {r10, r11, lr}\n\t" - "SUB %[s], %[s], #16\n\t" + "SUB r0, r0, #16\n\t" "SUB r12, r12, #32\n\t" "MOV r1, #0x9ce5\n\t" "MOVT r1, #0xa7ed\n\t" @@ -6733,7 +7272,7 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "LDM r12, {r10}\n\t" "ADCS r10, r10, #0\n\t" "STM r12!, {r10}\n\t" - "SUB %[s], %[s], #16\n\t" + "SUB r0, r0, #16\n\t" "MOV r12, sp\n\t" /* Load bits 252-376 */ "ADD r12, r12, #28\n\t" @@ -6749,12 +7288,12 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "BFC r5, #29, #3\n\t" "SUB r12, r12, #28\n\t" /* Sub product of top 4 words and order */ - "MOV %[s], sp\n\t" + "MOV r0, sp\n\t" /* * -5cf5d3ed */ "MOV r1, #0x2c13\n\t" "MOVT r1, #0xa30a\n\t" "MOV lr, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "UMLAL r6, lr, r2, r1\n\t" "ADDS r7, r7, lr\n\t" "MOV lr, #0\n\t" @@ -6768,13 +7307,13 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" "UMLAL r9, lr, r5, r1\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -5812631b */ "MOV r1, #0x9ce5\n\t" "MOVT r1, #0xa7ed\n\t" "MOV r10, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "UMLAL r6, r10, r2, r1\n\t" "ADDS r7, r7, r10\n\t" "MOV r10, #0\n\t" @@ -6788,13 +7327,13 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "MOV r10, #0\n\t" "ADC r10, r10, #0\n\t" "UMLAL r9, r10, r5, r1\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -a2f79cd7 */ "MOV r1, #0x6329\n\t" "MOVT r1, #0x5d08\n\t" "MOV r11, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "UMLAL r6, r11, r2, r1\n\t" "ADDS r7, r7, r11\n\t" "MOV r11, #0\n\t" @@ -6808,13 +7347,13 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "MOV r11, #0\n\t" "ADC r11, r11, #0\n\t" "UMLAL r9, r11, r5, r1\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -14def9df */ "MOV r1, #0x621\n\t" "MOVT r1, #0xeb21\n\t" "MOV r12, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "UMLAL r6, r12, r2, r1\n\t" "ADDS r7, r7, r12\n\t" "MOV r12, #0\n\t" @@ -6828,10 +7367,10 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "MOV r12, #0\n\t" "ADC r12, r12, #0\n\t" "UMLAL r9, r12, r5, r1\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* Add overflows at 4 * 32 */ - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "BFC r9, #28, #4\n\t" "ADDS r6, r6, lr\n\t" "ADCS r7, r7, r10\n\t" @@ -6843,8 +7382,8 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "SBCS r8, r8, r4\n\t" "SBCS r9, r9, r5\n\t" "SBC r1, r1, r1\n\t" - "SUB %[s], %[s], #16\n\t" - "LDM %[s], {r2, r3, r4, r5}\n\t" + "SUB r0, r0, #16\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" "MOV r10, #0xd3ed\n\t" "MOVT r10, #0x5cf5\n\t" "MOV r11, #0x631a\n\t" @@ -6868,19 +7407,28 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "ADC r9, r9, r1\n\t" "BFC r9, #28, #4\n\t" /* Store result */ - "LDR %[s], [sp, #52]\n\t" - "STM %[s], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "LDR r0, [sp, #52]\n\t" + "STM r0, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "ADD sp, sp, #56\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [s] "+r" (s) : + : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + "r10", "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [s] "r" (s) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", - "r10", "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + s = (byte*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -6892,14 +7440,22 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register byte* s __asm__ ("r0") = (byte*)s_p; +#else + void* L_asm_args[1] = {(void*)(size_t)s + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #56\n\t" - "STR %[s], [sp, #52]\n\t" + "STR r0, [sp, #52]\n\t" /* Load bits 252-511 */ - "ADD %[s], %[s], #28\n\t" - "LDM %[s], {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "ADD r0, r0, #28\n\t" + "LDM r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "LSR lr, r9, #24\n\t" "LSL r9, r9, #4\n\t" "ORR r9, r9, r8, LSR #28\n\t" @@ -6918,7 +7474,7 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "LSL r2, r2, #4\n\t" "ORR r2, r2, r1, LSR #28\n\t" "BFC r9, #28, #4\n\t" - "SUB %[s], %[s], #28\n\t" + "SUB r0, r0, #28\n\t" /* Add order times bits 504..511 */ "MOV r10, #0x2c13\n\t" "MOVT r10, #0xa30a\n\t" @@ -6946,24 +7502,24 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "MOV r1, #0x2c13\n\t" "MOVT r1, #0xa30a\n\t" "MOV lr, #0\n\t" - "LDM %[s]!, {r10, r11}\n\t" + "LDM r0!, {r10, r11}\n\t" "UMLAL r10, lr, r2, r1\n\t" "UMAAL r11, lr, r3, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" + "LDM r0!, {r10, r11}\n\t" "UMAAL r10, lr, r4, r1\n\t" "UMAAL r11, lr, r5, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" + "LDM r0!, {r10, r11}\n\t" "UMAAL r10, lr, r6, r1\n\t" "UMAAL r11, lr, r7, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" + "LDM r0!, {r10, r11}\n\t" "UMAAL r10, lr, r8, r1\n\t" "BFC r11, #28, #4\n\t" "UMAAL r11, lr, r9, r1\n\t" "STM r12!, {r10, r11, lr}\n\t" - "SUB %[s], %[s], #16\n\t" + "SUB r0, r0, #16\n\t" "SUB r12, r12, #32\n\t" "MOV r1, #0x9ce5\n\t" "MOVT r1, #0xa7ed\n\t" @@ -7080,7 +7636,7 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "LDM r12, {r10}\n\t" "ADCS r10, r10, #0\n\t" "STM r12!, {r10}\n\t" - "SUB %[s], %[s], #16\n\t" + "SUB r0, r0, #16\n\t" "MOV r12, sp\n\t" /* Load bits 252-376 */ "ADD r12, r12, #28\n\t" @@ -7096,53 +7652,53 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "BFC r5, #29, #3\n\t" "SUB r12, r12, #28\n\t" /* Sub product of top 4 words and order */ - "MOV %[s], sp\n\t" + "MOV r0, sp\n\t" /* * -5cf5d3ed */ "MOV r1, #0x2c13\n\t" "MOVT r1, #0xa30a\n\t" "MOV lr, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "UMLAL r6, lr, r2, r1\n\t" "UMAAL r7, lr, r3, r1\n\t" "UMAAL r8, lr, r4, r1\n\t" "UMAAL r9, lr, r5, r1\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -5812631b */ "MOV r1, #0x9ce5\n\t" "MOVT r1, #0xa7ed\n\t" "MOV r10, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "UMLAL r6, r10, r2, r1\n\t" "UMAAL r7, r10, r3, r1\n\t" "UMAAL r8, r10, r4, r1\n\t" "UMAAL r9, r10, r5, r1\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -a2f79cd7 */ "MOV r1, #0x6329\n\t" "MOVT r1, #0x5d08\n\t" "MOV r11, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "UMLAL r6, r11, r2, r1\n\t" "UMAAL r7, r11, r3, r1\n\t" "UMAAL r8, r11, r4, r1\n\t" "UMAAL r9, r11, r5, r1\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -14def9df */ "MOV r1, #0x621\n\t" "MOVT r1, #0xeb21\n\t" "MOV r12, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "UMLAL r6, r12, r2, r1\n\t" "UMAAL r7, r12, r3, r1\n\t" "UMAAL r8, r12, r4, r1\n\t" "UMAAL r9, r12, r5, r1\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* Add overflows at 4 * 32 */ - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "BFC r9, #28, #4\n\t" "ADDS r6, r6, lr\n\t" "ADCS r7, r7, r10\n\t" @@ -7154,8 +7710,8 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "SBCS r8, r8, r4\n\t" "SBCS r9, r9, r5\n\t" "SBC r1, r1, r1\n\t" - "SUB %[s], %[s], #16\n\t" - "LDM %[s], {r2, r3, r4, r5}\n\t" + "SUB r0, r0, #16\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" "MOV r10, #0xd3ed\n\t" "MOVT r10, #0x5cf5\n\t" "MOV r11, #0x631a\n\t" @@ -7179,19 +7735,28 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "ADC r9, r9, r1\n\t" "BFC r9, #28, #4\n\t" /* Store result */ - "LDR %[s], [sp, #52]\n\t" - "STM %[s], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "LDR r0, [sp, #52]\n\t" + "STM r0, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "ADD sp, sp, #56\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [s] "+r" (s) : + : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + "r10", "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [s] "r" (s) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", - "r10", "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + s = (byte*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_ARM_ARCH_7M */ @@ -7210,364 +7775,373 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, register const byte* a __asm__ ("r1") = (const byte*)a_p; register const byte* b __asm__ ("r2") = (const byte*)b_p; register const byte* c __asm__ ("r3") = (const byte*)c_p; +#else + void* L_asm_args[4] = {(void*)(size_t)s, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)c + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x50\n\t" "ADD lr, sp, #0x44\n\t" - "STM lr, {%[s], %[a], %[c]}\n\t" - "MOV %[s], #0\n\t" - "LDR r12, [%[a]]\n\t" + "STM lr, {r0, r1, r3}\n\t" + "MOV r0, #0\n\t" + "LDR r12, [r1]\n\t" /* A[0] * B[0] */ - "LDR lr, [%[b]]\n\t" - "UMULL %[c], r4, r12, lr\n\t" + "LDR lr, [r2]\n\t" + "UMULL r3, r4, r12, lr\n\t" /* A[0] * B[2] */ - "LDR lr, [%[b], #8]\n\t" + "LDR lr, [r2, #8]\n\t" "UMULL r5, r6, r12, lr\n\t" /* A[0] * B[4] */ - "LDR lr, [%[b], #16]\n\t" + "LDR lr, [r2, #16]\n\t" "UMULL r7, r8, r12, lr\n\t" /* A[0] * B[6] */ - "LDR lr, [%[b], #24]\n\t" + "LDR lr, [r2, #24]\n\t" "UMULL r9, r10, r12, lr\n\t" - "STR %[c], [sp]\n\t" + "STR r3, [sp]\n\t" /* A[0] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "MOV r11, %[s]\n\t" + "LDR lr, [r2, #4]\n\t" + "MOV r11, r0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[0] * B[3] */ - "LDR lr, [%[b], #12]\n\t" + "LDR lr, [r2, #12]\n\t" "ADCS r6, r6, #0\n\t" - "ADC r11, %[s], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[0] * B[5] */ - "LDR lr, [%[b], #20]\n\t" + "LDR lr, [r2, #20]\n\t" "ADCS r8, r8, #0\n\t" - "ADC r11, %[s], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[0] * B[7] */ - "LDR lr, [%[b], #28]\n\t" + "LDR lr, [r2, #28]\n\t" "ADCS r10, r10, #0\n\t" - "ADC %[c], %[s], #0\n\t" - "UMLAL r10, %[c], r12, lr\n\t" + "ADC r3, r0, #0\n\t" + "UMLAL r10, r3, r12, lr\n\t" /* A[1] * B[0] */ - "LDR r12, [%[a], #4]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #4]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "STR r4, [sp, #4]\n\t" "ADDS r5, r5, r11\n\t" /* A[1] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[1] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[1] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[1] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[1] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[1] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" - "ADDS %[c], %[c], r11\n\t" + "ADDS r3, r3, r11\n\t" /* A[1] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r4, %[s], #0\n\t" - "UMLAL %[c], r4, r12, lr\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r4, r0, #0\n\t" + "UMLAL r3, r4, r12, lr\n\t" /* A[2] * B[0] */ - "LDR r12, [%[a], #8]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #8]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "STR r5, [sp, #8]\n\t" "ADDS r6, r6, r11\n\t" /* A[2] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[2] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[2] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[2] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[2] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" - "ADDS %[c], %[c], r11\n\t" + "ADDS r3, r3, r11\n\t" /* A[2] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[s], #0\n\t" - "UMLAL %[c], r11, r12, lr\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" + "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[2] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r5, %[s], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r5, r0, #0\n\t" "UMLAL r4, r5, r12, lr\n\t" /* A[3] * B[0] */ - "LDR r12, [%[a], #12]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #12]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "STR r6, [sp, #12]\n\t" "ADDS r7, r7, r11\n\t" /* A[3] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[3] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[3] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[3] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" - "ADDS %[c], %[c], r11\n\t" + "ADDS r3, r3, r11\n\t" /* A[3] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[s], #0\n\t" - "UMLAL %[c], r11, r12, lr\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" + "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[3] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[3] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r6, %[s], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r6, r0, #0\n\t" "UMLAL r5, r6, r12, lr\n\t" /* A[4] * B[0] */ - "LDR r12, [%[a], #16]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #16]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "STR r7, [sp, #16]\n\t" "ADDS r8, r8, r11\n\t" /* A[4] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[4] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[4] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" - "ADDS %[c], %[c], r11\n\t" + "ADDS r3, r3, r11\n\t" /* A[4] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[s], #0\n\t" - "UMLAL %[c], r11, r12, lr\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" + "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[4] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[4] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[4] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r7, %[s], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r7, r0, #0\n\t" "UMLAL r6, r7, r12, lr\n\t" /* A[5] * B[0] */ - "LDR r12, [%[a], #20]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "STR r8, [sp, #20]\n\t" "ADDS r9, r9, r11\n\t" /* A[5] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[5] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" - "ADDS %[c], %[c], r11\n\t" + "ADDS r3, r3, r11\n\t" /* A[5] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[s], #0\n\t" - "UMLAL %[c], r11, r12, lr\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" + "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[5] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[5] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[5] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[5] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r8, %[s], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r8, r0, #0\n\t" "UMLAL r7, r8, r12, lr\n\t" /* A[6] * B[0] */ - "LDR r12, [%[a], #24]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "STR r9, [sp, #24]\n\t" "ADDS r10, r10, r11\n\t" /* A[6] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" - "ADDS %[c], %[c], r11\n\t" + "ADDS r3, r3, r11\n\t" /* A[6] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[s], #0\n\t" - "UMLAL %[c], r11, r12, lr\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" + "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[6] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[6] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[6] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[6] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[6] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r9, %[s], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r9, r0, #0\n\t" "UMLAL r8, r9, r12, lr\n\t" /* A[7] * B[0] */ - "LDR r12, [%[a], #28]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "STR r10, [sp, #28]\n\t" - "ADDS %[c], %[c], r11\n\t" + "ADDS r3, r3, r11\n\t" /* A[7] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[s], #0\n\t" - "UMLAL %[c], r11, r12, lr\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" + "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[7] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[7] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[7] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[7] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[7] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[s], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[7] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r10, %[s], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r10, r0, #0\n\t" "UMLAL r9, r10, r12, lr\n\t" "ADD lr, sp, #32\n\t" - "STM lr, {%[c], r4, r5, r6, r7, r8, r9, r10}\n\t" - "MOV %[s], sp\n\t" + "STM lr, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" + "MOV r0, sp\n\t" /* Add c to a * b */ "LDR lr, [sp, #76]\n\t" - "LDM %[s], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "LDM lr!, {r1, r10, r11, r12}\n\t" - "ADDS %[b], %[b], %[a]\n\t" - "ADCS %[c], %[c], r10\n\t" + "ADDS r2, r2, r1\n\t" + "ADCS r3, r3, r10\n\t" "ADCS r4, r4, r11\n\t" "ADCS r5, r5, r12\n\t" "LDM lr!, {r1, r10, r11, r12}\n\t" - "ADCS r6, r6, %[a]\n\t" + "ADCS r6, r6, r1\n\t" "ADCS r7, r7, r10\n\t" "ADCS r8, r8, r11\n\t" "ADCS r9, r9, r12\n\t" - "MOV %[a], r9\n\t" - "STM %[s]!, {%[b], %[c], r4, r5, r6, r7, r8, r9}\n\t" - "LDM %[s], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" - "ADCS %[b], %[b], #0\n\t" - "ADCS %[c], %[c], #0\n\t" + "MOV r1, r9\n\t" + "STM r0!, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "ADCS r2, r2, #0\n\t" + "ADCS r3, r3, #0\n\t" "ADCS r4, r4, #0\n\t" "ADCS r5, r5, #0\n\t" "ADCS r6, r6, #0\n\t" "ADCS r7, r7, #0\n\t" "ADCS r8, r8, #0\n\t" "ADC r9, r9, #0\n\t" - "SUB %[s], %[s], #32\n\t" + "SUB r0, r0, #32\n\t" /* Get 252..503 and 504..507 */ "LSR lr, r9, #24\n\t" "LSL r9, r9, #4\n\t" @@ -7581,36 +8155,36 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "LSL r5, r5, #4\n\t" "ORR r5, r5, r4, LSR #28\n\t" "LSL r4, r4, #4\n\t" - "ORR r4, r4, %[c], LSR #28\n\t" - "LSL %[c], %[c], #4\n\t" - "ORR %[c], %[c], %[b], LSR #28\n\t" - "LSL %[b], %[b], #4\n\t" - "ORR %[b], %[b], %[a], LSR #28\n\t" + "ORR r4, r4, r3, LSR #28\n\t" + "LSL r3, r3, #4\n\t" + "ORR r3, r3, r2, LSR #28\n\t" + "LSL r2, r2, #4\n\t" + "ORR r2, r2, r1, LSR #28\n\t" "BFC r9, #28, #4\n\t" /* Add order times bits 504..507 */ "MOV r10, #0x2c13\n\t" "MOVT r10, #0xa30a\n\t" "MOV r11, #0x9ce5\n\t" "MOVT r11, #0xa7ed\n\t" - "MOV %[a], #0\n\t" - "UMLAL %[b], %[a], r10, lr\n\t" - "ADDS %[c], %[c], %[a]\n\t" - "MOV %[a], #0\n\t" - "ADC %[a], %[a], #0\n\t" - "UMLAL %[c], %[a], r11, lr\n\t" + "MOV r1, #0\n\t" + "UMLAL r2, r1, r10, lr\n\t" + "ADDS r3, r3, r1\n\t" + "MOV r1, #0\n\t" + "ADC r1, r1, #0\n\t" + "UMLAL r3, r1, r11, lr\n\t" "MOV r10, #0x6329\n\t" "MOVT r10, #0x5d08\n\t" "MOV r11, #0x621\n\t" "MOVT r11, #0xeb21\n\t" - "ADDS r4, r4, %[a]\n\t" - "MOV %[a], #0\n\t" - "ADC %[a], %[a], #0\n\t" - "UMLAL r4, %[a], r10, lr\n\t" - "ADDS r5, r5, %[a]\n\t" - "MOV %[a], #0\n\t" - "ADC %[a], %[a], #0\n\t" - "UMLAL r5, %[a], r11, lr\n\t" - "ADDS r6, r6, %[a]\n\t" + "ADDS r4, r4, r1\n\t" + "MOV r1, #0\n\t" + "ADC r1, r1, #0\n\t" + "UMLAL r4, r1, r10, lr\n\t" + "ADDS r5, r5, r1\n\t" + "MOV r1, #0\n\t" + "ADC r1, r1, #0\n\t" + "UMLAL r5, r1, r11, lr\n\t" + "ADDS r6, r6, r1\n\t" "ADCS r7, r7, #0\n\t" "ADCS r8, r8, #0\n\t" "ADC r9, r9, #0\n\t" @@ -7620,176 +8194,176 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "SBC r9, r9, #0\n\t" /* Sub product of top 8 words and order */ "MOV r12, sp\n\t" - "MOV %[a], #0x2c13\n\t" - "MOVT %[a], #0xa30a\n\t" + "MOV r1, #0x2c13\n\t" + "MOVT r1, #0xa30a\n\t" "MOV lr, #0\n\t" - "LDM %[s]!, {r10, r11}\n\t" - "UMLAL r10, lr, %[b], %[a]\n\t" + "LDM r0!, {r10, r11}\n\t" + "UMLAL r10, lr, r2, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, %[c], %[a]\n\t" + "UMLAL r11, lr, r3, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" + "LDM r0!, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r4, %[a]\n\t" + "UMLAL r10, lr, r4, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r5, %[a]\n\t" + "UMLAL r11, lr, r5, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" + "LDM r0!, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r6, %[a]\n\t" + "UMLAL r10, lr, r6, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r7, %[a]\n\t" + "UMLAL r11, lr, r7, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" + "LDM r0!, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r8, %[a]\n\t" + "UMLAL r10, lr, r8, r1\n\t" "BFC r11, #28, #4\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r9, %[a]\n\t" + "UMLAL r11, lr, r9, r1\n\t" "STM r12!, {r10, r11, lr}\n\t" - "SUB %[s], %[s], #16\n\t" + "SUB r0, r0, #16\n\t" "SUB r12, r12, #32\n\t" - "MOV %[a], #0x9ce5\n\t" - "MOVT %[a], #0xa7ed\n\t" + "MOV r1, #0x9ce5\n\t" + "MOVT r1, #0xa7ed\n\t" "MOV lr, #0\n\t" "LDM r12, {r10, r11}\n\t" - "UMLAL r10, lr, %[b], %[a]\n\t" + "UMLAL r10, lr, r2, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, %[c], %[a]\n\t" + "UMLAL r11, lr, r3, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r4, %[a]\n\t" + "UMLAL r10, lr, r4, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r5, %[a]\n\t" + "UMLAL r11, lr, r5, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r6, %[a]\n\t" + "UMLAL r10, lr, r6, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r7, %[a]\n\t" + "UMLAL r11, lr, r7, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r8, %[a]\n\t" + "UMLAL r10, lr, r8, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r9, %[a]\n\t" + "UMLAL r11, lr, r9, r1\n\t" "STM r12!, {r10, r11, lr}\n\t" "SUB r12, r12, #32\n\t" - "MOV %[a], #0x6329\n\t" - "MOVT %[a], #0x5d08\n\t" + "MOV r1, #0x6329\n\t" + "MOVT r1, #0x5d08\n\t" "MOV lr, #0\n\t" "LDM r12, {r10, r11}\n\t" - "UMLAL r10, lr, %[b], %[a]\n\t" + "UMLAL r10, lr, r2, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, %[c], %[a]\n\t" + "UMLAL r11, lr, r3, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r4, %[a]\n\t" + "UMLAL r10, lr, r4, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r5, %[a]\n\t" + "UMLAL r11, lr, r5, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r6, %[a]\n\t" + "UMLAL r10, lr, r6, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r7, %[a]\n\t" + "UMLAL r11, lr, r7, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r8, %[a]\n\t" + "UMLAL r10, lr, r8, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r9, %[a]\n\t" + "UMLAL r11, lr, r9, r1\n\t" "STM r12!, {r10, r11, lr}\n\t" "SUB r12, r12, #32\n\t" - "MOV %[a], #0x621\n\t" - "MOVT %[a], #0xeb21\n\t" + "MOV r1, #0x621\n\t" + "MOVT r1, #0xeb21\n\t" "MOV lr, #0\n\t" "LDM r12, {r10, r11}\n\t" - "UMLAL r10, lr, %[b], %[a]\n\t" + "UMLAL r10, lr, r2, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, %[c], %[a]\n\t" + "UMLAL r11, lr, r3, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r4, %[a]\n\t" + "UMLAL r10, lr, r4, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r5, %[a]\n\t" + "UMLAL r11, lr, r5, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r6, %[a]\n\t" + "UMLAL r10, lr, r6, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r7, %[a]\n\t" + "UMLAL r11, lr, r7, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" "ADDS r10, r10, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r10, lr, r8, %[a]\n\t" + "UMLAL r10, lr, r8, r1\n\t" "ADDS r11, r11, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r11, lr, r9, %[a]\n\t" + "UMLAL r11, lr, r9, r1\n\t" "STM r12!, {r10, r11, lr}\n\t" "SUB r12, r12, #32\n\t" /* Subtract at 4 * 32 */ "LDM r12, {r10, r11}\n\t" - "SUBS r10, r10, %[b]\n\t" - "SBCS r11, r11, %[c]\n\t" + "SUBS r10, r10, r2\n\t" + "SBCS r11, r11, r3\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" "SBCS r10, r10, r4\n\t" @@ -7806,28 +8380,28 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "SUB r12, r12, #36\n\t" "ASR lr, r11, #25\n\t" /* Conditionally subtract order starting at bit 125 */ - "MOV %[a], #0xa0000000\n\t" - "MOV %[b], #0xba7d\n\t" - "MOVT %[b], #0x4b9e\n\t" - "MOV %[c], #0x4c63\n\t" - "MOVT %[c], #0xcb02\n\t" + "MOV r1, #0xa0000000\n\t" + "MOV r2, #0xba7d\n\t" + "MOVT r2, #0x4b9e\n\t" + "MOV r3, #0x4c63\n\t" + "MOVT r3, #0xcb02\n\t" "MOV r4, #0xf39a\n\t" "MOVT r4, #0xd45e\n\t" "MOV r5, #0xdf3b\n\t" "MOVT r5, #0x29b\n\t" "MOV r9, #0x2000000\n\t" - "AND %[a], %[a], lr\n\t" - "AND %[b], %[b], lr\n\t" - "AND %[c], %[c], lr\n\t" + "AND r1, r1, lr\n\t" + "AND r2, r2, lr\n\t" + "AND r3, r3, lr\n\t" "AND r4, r4, lr\n\t" "AND r5, r5, lr\n\t" "AND r9, r9, lr\n\t" "LDM r12, {r10, r11}\n\t" - "ADDS r10, r10, %[a]\n\t" - "ADCS r11, r11, %[b]\n\t" + "ADDS r10, r10, r1\n\t" + "ADCS r11, r11, r2\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" - "ADCS r10, r10, %[c]\n\t" + "ADCS r10, r10, r3\n\t" "ADCS r11, r11, r4\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" @@ -7841,7 +8415,7 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "LDM r12, {r10}\n\t" "ADCS r10, r10, #0\n\t" "STM r12!, {r10}\n\t" - "SUB %[s], %[s], #16\n\t" + "SUB r0, r0, #16\n\t" "MOV r12, sp\n\t" /* Load bits 252-376 */ "ADD r12, r12, #28\n\t" @@ -7849,110 +8423,110 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "LSL r5, r5, #4\n\t" "ORR r5, r5, r4, LSR #28\n\t" "LSL r4, r4, #4\n\t" - "ORR r4, r4, %[c], LSR #28\n\t" - "LSL %[c], %[c], #4\n\t" - "ORR %[c], %[c], %[b], LSR #28\n\t" - "LSL %[b], %[b], #4\n\t" - "ORR %[b], %[b], %[a], LSR #28\n\t" + "ORR r4, r4, r3, LSR #28\n\t" + "LSL r3, r3, #4\n\t" + "ORR r3, r3, r2, LSR #28\n\t" + "LSL r2, r2, #4\n\t" + "ORR r2, r2, r1, LSR #28\n\t" "BFC r5, #29, #3\n\t" "SUB r12, r12, #28\n\t" /* Sub product of top 4 words and order */ - "MOV %[s], sp\n\t" + "MOV r0, sp\n\t" /* * -5cf5d3ed */ - "MOV %[a], #0x2c13\n\t" - "MOVT %[a], #0xa30a\n\t" + "MOV r1, #0x2c13\n\t" + "MOVT r1, #0xa30a\n\t" "MOV lr, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" - "UMLAL r6, lr, %[b], %[a]\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" + "UMLAL r6, lr, r2, r1\n\t" "ADDS r7, r7, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r7, lr, %[c], %[a]\n\t" + "UMLAL r7, lr, r3, r1\n\t" "ADDS r8, r8, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r8, lr, r4, %[a]\n\t" + "UMLAL r8, lr, r4, r1\n\t" "ADDS r9, r9, lr\n\t" "MOV lr, #0\n\t" "ADC lr, lr, #0\n\t" - "UMLAL r9, lr, r5, %[a]\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "UMLAL r9, lr, r5, r1\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -5812631b */ - "MOV %[a], #0x9ce5\n\t" - "MOVT %[a], #0xa7ed\n\t" + "MOV r1, #0x9ce5\n\t" + "MOVT r1, #0xa7ed\n\t" "MOV r10, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" - "UMLAL r6, r10, %[b], %[a]\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" + "UMLAL r6, r10, r2, r1\n\t" "ADDS r7, r7, r10\n\t" "MOV r10, #0\n\t" "ADC r10, r10, #0\n\t" - "UMLAL r7, r10, %[c], %[a]\n\t" + "UMLAL r7, r10, r3, r1\n\t" "ADDS r8, r8, r10\n\t" "MOV r10, #0\n\t" "ADC r10, r10, #0\n\t" - "UMLAL r8, r10, r4, %[a]\n\t" + "UMLAL r8, r10, r4, r1\n\t" "ADDS r9, r9, r10\n\t" "MOV r10, #0\n\t" "ADC r10, r10, #0\n\t" - "UMLAL r9, r10, r5, %[a]\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "UMLAL r9, r10, r5, r1\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -a2f79cd7 */ - "MOV %[a], #0x6329\n\t" - "MOVT %[a], #0x5d08\n\t" + "MOV r1, #0x6329\n\t" + "MOVT r1, #0x5d08\n\t" "MOV r11, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" - "UMLAL r6, r11, %[b], %[a]\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" + "UMLAL r6, r11, r2, r1\n\t" "ADDS r7, r7, r11\n\t" "MOV r11, #0\n\t" "ADC r11, r11, #0\n\t" - "UMLAL r7, r11, %[c], %[a]\n\t" + "UMLAL r7, r11, r3, r1\n\t" "ADDS r8, r8, r11\n\t" "MOV r11, #0\n\t" "ADC r11, r11, #0\n\t" - "UMLAL r8, r11, r4, %[a]\n\t" + "UMLAL r8, r11, r4, r1\n\t" "ADDS r9, r9, r11\n\t" "MOV r11, #0\n\t" "ADC r11, r11, #0\n\t" - "UMLAL r9, r11, r5, %[a]\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "UMLAL r9, r11, r5, r1\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -14def9df */ - "MOV %[a], #0x621\n\t" - "MOVT %[a], #0xeb21\n\t" + "MOV r1, #0x621\n\t" + "MOVT r1, #0xeb21\n\t" "MOV r12, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" - "UMLAL r6, r12, %[b], %[a]\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" + "UMLAL r6, r12, r2, r1\n\t" "ADDS r7, r7, r12\n\t" "MOV r12, #0\n\t" "ADC r12, r12, #0\n\t" - "UMLAL r7, r12, %[c], %[a]\n\t" + "UMLAL r7, r12, r3, r1\n\t" "ADDS r8, r8, r12\n\t" "MOV r12, #0\n\t" "ADC r12, r12, #0\n\t" - "UMLAL r8, r12, r4, %[a]\n\t" + "UMLAL r8, r12, r4, r1\n\t" "ADDS r9, r9, r12\n\t" "MOV r12, #0\n\t" "ADC r12, r12, #0\n\t" - "UMLAL r9, r12, r5, %[a]\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "UMLAL r9, r12, r5, r1\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* Add overflows at 4 * 32 */ - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "BFC r9, #28, #4\n\t" "ADDS r6, r6, lr\n\t" "ADCS r7, r7, r10\n\t" "ADCS r8, r8, r11\n\t" "ADC r9, r9, r12\n\t" /* Subtract top at 4 * 32 */ - "SUBS r6, r6, %[b]\n\t" - "SBCS r7, r7, %[c]\n\t" + "SUBS r6, r6, r2\n\t" + "SBCS r7, r7, r3\n\t" "SBCS r8, r8, r4\n\t" "SBCS r9, r9, r5\n\t" - "SBC %[a], %[a], %[a]\n\t" - "SUB %[s], %[s], #16\n\t" - "LDM %[s], {r2, r3, r4, r5}\n\t" + "SBC r1, r1, r1\n\t" + "SUB r0, r0, #16\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" "MOV r10, #0xd3ed\n\t" "MOVT r10, #0x5cf5\n\t" "MOV r11, #0x631a\n\t" @@ -7961,41 +8535,53 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "MOVT r12, #0xa2f7\n\t" "MOV lr, #0xf9de\n\t" "MOVT lr, #0x14de\n\t" - "AND r10, r10, %[a]\n\t" - "AND r11, r11, %[a]\n\t" - "AND r12, r12, %[a]\n\t" - "AND lr, lr, %[a]\n\t" - "ADDS %[b], %[b], r10\n\t" - "ADCS %[c], %[c], r11\n\t" + "AND r10, r10, r1\n\t" + "AND r11, r11, r1\n\t" + "AND r12, r12, r1\n\t" + "AND lr, lr, r1\n\t" + "ADDS r2, r2, r10\n\t" + "ADCS r3, r3, r11\n\t" "ADCS r4, r4, r12\n\t" "ADCS r5, r5, lr\n\t" "ADCS r6, r6, #0\n\t" "ADCS r7, r7, #0\n\t" - "AND %[a], %[a], #0x10000000\n\t" + "AND r1, r1, #0x10000000\n\t" "ADCS r8, r8, #0\n\t" - "ADC r9, r9, %[a]\n\t" + "ADC r9, r9, r1\n\t" "BFC r9, #28, #4\n\t" - "LDR %[s], [sp, #68]\n\t" + "LDR r0, [sp, #68]\n\t" /* Store result */ - "STR %[b], [%[s]]\n\t" - "STR %[c], [%[s], #4]\n\t" - "STR r4, [%[s], #8]\n\t" - "STR r5, [%[s], #12]\n\t" - "STR r6, [%[s], #16]\n\t" - "STR r7, [%[s], #20]\n\t" - "STR r8, [%[s], #24]\n\t" - "STR r9, [%[s], #28]\n\t" + "STR r2, [r0]\n\t" + "STR r3, [r0, #4]\n\t" + "STR r4, [r0, #8]\n\t" + "STR r5, [r0, #12]\n\t" + "STR r6, [r0, #16]\n\t" + "STR r7, [r0, #20]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #28]\n\t" "ADD sp, sp, #0x50\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [s] "+r" (s), [a] "+r" (a), [b] "+r" (b), [c] "+r" (c) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [s] "r" (s), [a] "r" (a), [b] "r" (b), [c] "r" (c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + s = (byte*)(size_t)L_asm_args[0]; + a = (const byte*)(size_t)L_asm_args[1]; + b = (const byte*)(size_t)L_asm_args[2]; + c = (const byte*)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -8012,137 +8598,146 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, register const byte* a __asm__ ("r1") = (const byte*)a_p; register const byte* b __asm__ ("r2") = (const byte*)b_p; register const byte* c __asm__ ("r3") = (const byte*)c_p; +#else + void* L_asm_args[4] = {(void*)(size_t)s, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)c + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x50\n\t" "ADD lr, sp, #0x44\n\t" - "STM lr, {%[s], %[a], %[c]}\n\t" - "MOV lr, %[b]\n\t" - "LDM %[a], {r0, r1, r2, r3}\n\t" + "STM lr, {r0, r1, r3}\n\t" + "MOV lr, r2\n\t" + "LDM r1, {r0, r1, r2, r3}\n\t" "LDM lr!, {r4, r5, r6}\n\t" - "UMULL r10, r11, %[s], r4\n\t" - "UMULL r12, r7, %[a], r4\n\t" - "UMAAL r11, r12, %[s], r5\n\t" - "UMULL r8, r9, %[b], r4\n\t" - "UMAAL r12, r8, %[a], r5\n\t" - "UMAAL r12, r7, %[s], r6\n\t" - "UMAAL r8, r9, %[c], r4\n\t" + "UMULL r10, r11, r0, r4\n\t" + "UMULL r12, r7, r1, r4\n\t" + "UMAAL r11, r12, r0, r5\n\t" + "UMULL r8, r9, r2, r4\n\t" + "UMAAL r12, r8, r1, r5\n\t" + "UMAAL r12, r7, r0, r6\n\t" + "UMAAL r8, r9, r3, r4\n\t" "STM sp, {r10, r11, r12}\n\t" - "UMAAL r7, r8, %[b], r5\n\t" + "UMAAL r7, r8, r2, r5\n\t" "LDM lr!, {r4}\n\t" - "UMULL r10, r11, %[a], r6\n\t" - "UMAAL r8, r9, %[b], r6\n\t" - "UMAAL r7, r10, %[s], r4\n\t" - "UMAAL r8, r11, %[c], r5\n\t" + "UMULL r10, r11, r1, r6\n\t" + "UMAAL r8, r9, r2, r6\n\t" + "UMAAL r7, r10, r0, r4\n\t" + "UMAAL r8, r11, r3, r5\n\t" "STR r7, [sp, #12]\n\t" - "UMAAL r8, r10, %[a], r4\n\t" - "UMAAL r9, r11, %[c], r6\n\t" - "UMAAL r9, r10, %[b], r4\n\t" - "UMAAL r10, r11, %[c], r4\n\t" + "UMAAL r8, r10, r1, r4\n\t" + "UMAAL r9, r11, r3, r6\n\t" + "UMAAL r9, r10, r2, r4\n\t" + "UMAAL r10, r11, r3, r4\n\t" "LDM lr, {r4, r5, r6, r7}\n\t" "MOV r12, #0\n\t" - "UMLAL r8, r12, %[s], r4\n\t" - "UMAAL r9, r12, %[a], r4\n\t" - "UMAAL r10, r12, %[b], r4\n\t" - "UMAAL r11, r12, %[c], r4\n\t" + "UMLAL r8, r12, r0, r4\n\t" + "UMAAL r9, r12, r1, r4\n\t" + "UMAAL r10, r12, r2, r4\n\t" + "UMAAL r11, r12, r3, r4\n\t" "MOV r4, #0\n\t" - "UMLAL r9, r4, %[s], r5\n\t" - "UMAAL r10, r4, %[a], r5\n\t" - "UMAAL r11, r4, %[b], r5\n\t" - "UMAAL r12, r4, %[c], r5\n\t" + "UMLAL r9, r4, r0, r5\n\t" + "UMAAL r10, r4, r1, r5\n\t" + "UMAAL r11, r4, r2, r5\n\t" + "UMAAL r12, r4, r3, r5\n\t" "MOV r5, #0\n\t" - "UMLAL r10, r5, %[s], r6\n\t" - "UMAAL r11, r5, %[a], r6\n\t" - "UMAAL r12, r5, %[b], r6\n\t" - "UMAAL r4, r5, %[c], r6\n\t" + "UMLAL r10, r5, r0, r6\n\t" + "UMAAL r11, r5, r1, r6\n\t" + "UMAAL r12, r5, r2, r6\n\t" + "UMAAL r4, r5, r3, r6\n\t" "MOV r6, #0\n\t" - "UMLAL r11, r6, %[s], r7\n\t" - "LDR %[s], [sp, #72]\n\t" - "UMAAL r12, r6, %[a], r7\n\t" - "ADD %[s], %[s], #16\n\t" - "UMAAL r4, r6, %[b], r7\n\t" + "UMLAL r11, r6, r0, r7\n\t" + "LDR r0, [sp, #72]\n\t" + "UMAAL r12, r6, r1, r7\n\t" + "ADD r0, r0, #16\n\t" + "UMAAL r4, r6, r2, r7\n\t" "SUB lr, lr, #16\n\t" - "UMAAL r5, r6, %[c], r7\n\t" - "LDM %[s], {r0, r1, r2, r3}\n\t" + "UMAAL r5, r6, r3, r7\n\t" + "LDM r0, {r0, r1, r2, r3}\n\t" "STR r6, [sp, #64]\n\t" "LDM lr!, {r6}\n\t" "MOV r7, #0\n\t" - "UMLAL r8, r7, %[s], r6\n\t" - "UMAAL r9, r7, %[a], r6\n\t" + "UMLAL r8, r7, r0, r6\n\t" + "UMAAL r9, r7, r1, r6\n\t" "STR r8, [sp, #16]\n\t" - "UMAAL r10, r7, %[b], r6\n\t" - "UMAAL r11, r7, %[c], r6\n\t" + "UMAAL r10, r7, r2, r6\n\t" + "UMAAL r11, r7, r3, r6\n\t" "LDM lr!, {r6}\n\t" "MOV r8, #0\n\t" - "UMLAL r9, r8, %[s], r6\n\t" - "UMAAL r10, r8, %[a], r6\n\t" + "UMLAL r9, r8, r0, r6\n\t" + "UMAAL r10, r8, r1, r6\n\t" "STR r9, [sp, #20]\n\t" - "UMAAL r11, r8, %[b], r6\n\t" - "UMAAL r12, r8, %[c], r6\n\t" + "UMAAL r11, r8, r2, r6\n\t" + "UMAAL r12, r8, r3, r6\n\t" "LDM lr!, {r6}\n\t" "MOV r9, #0\n\t" - "UMLAL r10, r9, %[s], r6\n\t" - "UMAAL r11, r9, %[a], r6\n\t" + "UMLAL r10, r9, r0, r6\n\t" + "UMAAL r11, r9, r1, r6\n\t" "STR r10, [sp, #24]\n\t" - "UMAAL r12, r9, %[b], r6\n\t" - "UMAAL r4, r9, %[c], r6\n\t" + "UMAAL r12, r9, r2, r6\n\t" + "UMAAL r4, r9, r3, r6\n\t" "LDM lr!, {r6}\n\t" "MOV r10, #0\n\t" - "UMLAL r11, r10, %[s], r6\n\t" - "UMAAL r12, r10, %[a], r6\n\t" + "UMLAL r11, r10, r0, r6\n\t" + "UMAAL r12, r10, r1, r6\n\t" "STR r11, [sp, #28]\n\t" - "UMAAL r4, r10, %[b], r6\n\t" - "UMAAL r5, r10, %[c], r6\n\t" + "UMAAL r4, r10, r2, r6\n\t" + "UMAAL r5, r10, r3, r6\n\t" "LDM lr!, {r11}\n\t" - "UMAAL r12, r7, %[s], r11\n\t" - "UMAAL r4, r7, %[a], r11\n\t" + "UMAAL r12, r7, r0, r11\n\t" + "UMAAL r4, r7, r1, r11\n\t" "LDR r6, [sp, #64]\n\t" - "UMAAL r5, r7, %[b], r11\n\t" - "UMAAL r6, r7, %[c], r11\n\t" + "UMAAL r5, r7, r2, r11\n\t" + "UMAAL r6, r7, r3, r11\n\t" "LDM lr!, {r11}\n\t" - "UMAAL r4, r8, %[s], r11\n\t" - "UMAAL r5, r8, %[a], r11\n\t" - "UMAAL r6, r8, %[b], r11\n\t" - "UMAAL r7, r8, %[c], r11\n\t" + "UMAAL r4, r8, r0, r11\n\t" + "UMAAL r5, r8, r1, r11\n\t" + "UMAAL r6, r8, r2, r11\n\t" + "UMAAL r7, r8, r3, r11\n\t" "LDM lr, {r11, lr}\n\t" - "UMAAL r5, r9, %[s], r11\n\t" - "UMAAL r6, r10, %[s], lr\n\t" - "UMAAL r6, r9, %[a], r11\n\t" - "UMAAL r7, r10, %[a], lr\n\t" - "UMAAL r7, r9, %[b], r11\n\t" - "UMAAL r8, r10, %[b], lr\n\t" - "UMAAL r8, r9, %[c], r11\n\t" - "UMAAL r9, r10, %[c], lr\n\t" - "MOV %[c], r12\n\t" + "UMAAL r5, r9, r0, r11\n\t" + "UMAAL r6, r10, r0, lr\n\t" + "UMAAL r6, r9, r1, r11\n\t" + "UMAAL r7, r10, r1, lr\n\t" + "UMAAL r7, r9, r2, r11\n\t" + "UMAAL r8, r10, r2, lr\n\t" + "UMAAL r8, r9, r3, r11\n\t" + "UMAAL r9, r10, r3, lr\n\t" + "MOV r3, r12\n\t" "ADD lr, sp, #32\n\t" - "STM lr, {%[c], r4, r5, r6, r7, r8, r9, r10}\n\t" - "MOV %[s], sp\n\t" + "STM lr, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" + "MOV r0, sp\n\t" /* Add c to a * b */ "LDR lr, [sp, #76]\n\t" - "LDM %[s], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "LDM lr!, {r1, r10, r11, r12}\n\t" - "ADDS %[b], %[b], %[a]\n\t" - "ADCS %[c], %[c], r10\n\t" + "ADDS r2, r2, r1\n\t" + "ADCS r3, r3, r10\n\t" "ADCS r4, r4, r11\n\t" "ADCS r5, r5, r12\n\t" "LDM lr!, {r1, r10, r11, r12}\n\t" - "ADCS r6, r6, %[a]\n\t" + "ADCS r6, r6, r1\n\t" "ADCS r7, r7, r10\n\t" "ADCS r8, r8, r11\n\t" "ADCS r9, r9, r12\n\t" - "MOV %[a], r9\n\t" - "STM %[s]!, {%[b], %[c], r4, r5, r6, r7, r8, r9}\n\t" - "LDM %[s], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" - "ADCS %[b], %[b], #0\n\t" - "ADCS %[c], %[c], #0\n\t" + "MOV r1, r9\n\t" + "STM r0!, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "ADCS r2, r2, #0\n\t" + "ADCS r3, r3, #0\n\t" "ADCS r4, r4, #0\n\t" "ADCS r5, r5, #0\n\t" "ADCS r6, r6, #0\n\t" "ADCS r7, r7, #0\n\t" "ADCS r8, r8, #0\n\t" "ADC r9, r9, #0\n\t" - "SUB %[s], %[s], #32\n\t" + "SUB r0, r0, #32\n\t" /* Get 252..503 and 504..507 */ "LSR lr, r9, #24\n\t" "LSL r9, r9, #4\n\t" @@ -8156,27 +8751,27 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "LSL r5, r5, #4\n\t" "ORR r5, r5, r4, LSR #28\n\t" "LSL r4, r4, #4\n\t" - "ORR r4, r4, %[c], LSR #28\n\t" - "LSL %[c], %[c], #4\n\t" - "ORR %[c], %[c], %[b], LSR #28\n\t" - "LSL %[b], %[b], #4\n\t" - "ORR %[b], %[b], %[a], LSR #28\n\t" + "ORR r4, r4, r3, LSR #28\n\t" + "LSL r3, r3, #4\n\t" + "ORR r3, r3, r2, LSR #28\n\t" + "LSL r2, r2, #4\n\t" + "ORR r2, r2, r1, LSR #28\n\t" "BFC r9, #28, #4\n\t" /* Add order times bits 504..507 */ "MOV r10, #0x2c13\n\t" "MOVT r10, #0xa30a\n\t" "MOV r11, #0x9ce5\n\t" "MOVT r11, #0xa7ed\n\t" - "MOV %[a], #0\n\t" - "UMLAL %[b], %[a], r10, lr\n\t" - "UMAAL %[c], %[a], r11, lr\n\t" + "MOV r1, #0\n\t" + "UMLAL r2, r1, r10, lr\n\t" + "UMAAL r3, r1, r11, lr\n\t" "MOV r10, #0x6329\n\t" "MOVT r10, #0x5d08\n\t" "MOV r11, #0x621\n\t" "MOVT r11, #0xeb21\n\t" - "UMAAL r4, %[a], r10, lr\n\t" - "UMAAL r5, %[a], r11, lr\n\t" - "ADDS r6, r6, %[a]\n\t" + "UMAAL r4, r1, r10, lr\n\t" + "UMAAL r5, r1, r11, lr\n\t" + "ADDS r6, r6, r1\n\t" "ADCS r7, r7, #0\n\t" "ADCS r8, r8, #0\n\t" "ADC r9, r9, #0\n\t" @@ -8186,92 +8781,92 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "SBC r9, r9, #0\n\t" /* Sub product of top 8 words and order */ "MOV r12, sp\n\t" - "MOV %[a], #0x2c13\n\t" - "MOVT %[a], #0xa30a\n\t" + "MOV r1, #0x2c13\n\t" + "MOVT r1, #0xa30a\n\t" "MOV lr, #0\n\t" - "LDM %[s]!, {r10, r11}\n\t" - "UMLAL r10, lr, %[b], %[a]\n\t" - "UMAAL r11, lr, %[c], %[a]\n\t" + "LDM r0!, {r10, r11}\n\t" + "UMLAL r10, lr, r2, r1\n\t" + "UMAAL r11, lr, r3, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" - "UMAAL r10, lr, r4, %[a]\n\t" - "UMAAL r11, lr, r5, %[a]\n\t" + "LDM r0!, {r10, r11}\n\t" + "UMAAL r10, lr, r4, r1\n\t" + "UMAAL r11, lr, r5, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" - "UMAAL r10, lr, r6, %[a]\n\t" - "UMAAL r11, lr, r7, %[a]\n\t" + "LDM r0!, {r10, r11}\n\t" + "UMAAL r10, lr, r6, r1\n\t" + "UMAAL r11, lr, r7, r1\n\t" "STM r12!, {r10, r11}\n\t" - "LDM %[s]!, {r10, r11}\n\t" - "UMAAL r10, lr, r8, %[a]\n\t" + "LDM r0!, {r10, r11}\n\t" + "UMAAL r10, lr, r8, r1\n\t" "BFC r11, #28, #4\n\t" - "UMAAL r11, lr, r9, %[a]\n\t" + "UMAAL r11, lr, r9, r1\n\t" "STM r12!, {r10, r11, lr}\n\t" - "SUB %[s], %[s], #16\n\t" + "SUB r0, r0, #16\n\t" "SUB r12, r12, #32\n\t" - "MOV %[a], #0x9ce5\n\t" - "MOVT %[a], #0xa7ed\n\t" + "MOV r1, #0x9ce5\n\t" + "MOVT r1, #0xa7ed\n\t" "MOV lr, #0\n\t" "LDM r12, {r10, r11}\n\t" - "UMLAL r10, lr, %[b], %[a]\n\t" - "UMAAL r11, lr, %[c], %[a]\n\t" + "UMLAL r10, lr, r2, r1\n\t" + "UMAAL r11, lr, r3, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" - "UMAAL r10, lr, r4, %[a]\n\t" - "UMAAL r11, lr, r5, %[a]\n\t" + "UMAAL r10, lr, r4, r1\n\t" + "UMAAL r11, lr, r5, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" - "UMAAL r10, lr, r6, %[a]\n\t" - "UMAAL r11, lr, r7, %[a]\n\t" + "UMAAL r10, lr, r6, r1\n\t" + "UMAAL r11, lr, r7, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" - "UMAAL r10, lr, r8, %[a]\n\t" - "UMAAL r11, lr, r9, %[a]\n\t" + "UMAAL r10, lr, r8, r1\n\t" + "UMAAL r11, lr, r9, r1\n\t" "STM r12!, {r10, r11, lr}\n\t" "SUB r12, r12, #32\n\t" - "MOV %[a], #0x6329\n\t" - "MOVT %[a], #0x5d08\n\t" + "MOV r1, #0x6329\n\t" + "MOVT r1, #0x5d08\n\t" "MOV lr, #0\n\t" "LDM r12, {r10, r11}\n\t" - "UMLAL r10, lr, %[b], %[a]\n\t" - "UMAAL r11, lr, %[c], %[a]\n\t" + "UMLAL r10, lr, r2, r1\n\t" + "UMAAL r11, lr, r3, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" - "UMAAL r10, lr, r4, %[a]\n\t" - "UMAAL r11, lr, r5, %[a]\n\t" + "UMAAL r10, lr, r4, r1\n\t" + "UMAAL r11, lr, r5, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" - "UMAAL r10, lr, r6, %[a]\n\t" - "UMAAL r11, lr, r7, %[a]\n\t" + "UMAAL r10, lr, r6, r1\n\t" + "UMAAL r11, lr, r7, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" - "UMAAL r10, lr, r8, %[a]\n\t" - "UMAAL r11, lr, r9, %[a]\n\t" + "UMAAL r10, lr, r8, r1\n\t" + "UMAAL r11, lr, r9, r1\n\t" "STM r12!, {r10, r11, lr}\n\t" "SUB r12, r12, #32\n\t" - "MOV %[a], #0x621\n\t" - "MOVT %[a], #0xeb21\n\t" + "MOV r1, #0x621\n\t" + "MOVT r1, #0xeb21\n\t" "MOV lr, #0\n\t" "LDM r12, {r10, r11}\n\t" - "UMLAL r10, lr, %[b], %[a]\n\t" - "UMAAL r11, lr, %[c], %[a]\n\t" + "UMLAL r10, lr, r2, r1\n\t" + "UMAAL r11, lr, r3, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" - "UMAAL r10, lr, r4, %[a]\n\t" - "UMAAL r11, lr, r5, %[a]\n\t" + "UMAAL r10, lr, r4, r1\n\t" + "UMAAL r11, lr, r5, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" - "UMAAL r10, lr, r6, %[a]\n\t" - "UMAAL r11, lr, r7, %[a]\n\t" + "UMAAL r10, lr, r6, r1\n\t" + "UMAAL r11, lr, r7, r1\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" - "UMAAL r10, lr, r8, %[a]\n\t" - "UMAAL r11, lr, r9, %[a]\n\t" + "UMAAL r10, lr, r8, r1\n\t" + "UMAAL r11, lr, r9, r1\n\t" "STM r12!, {r10, r11, lr}\n\t" "SUB r12, r12, #32\n\t" /* Subtract at 4 * 32 */ "LDM r12, {r10, r11}\n\t" - "SUBS r10, r10, %[b]\n\t" - "SBCS r11, r11, %[c]\n\t" + "SUBS r10, r10, r2\n\t" + "SBCS r11, r11, r3\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" "SBCS r10, r10, r4\n\t" @@ -8288,28 +8883,28 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "SUB r12, r12, #36\n\t" "ASR lr, r11, #25\n\t" /* Conditionally subtract order starting at bit 125 */ - "MOV %[a], #0xa0000000\n\t" - "MOV %[b], #0xba7d\n\t" - "MOVT %[b], #0x4b9e\n\t" - "MOV %[c], #0x4c63\n\t" - "MOVT %[c], #0xcb02\n\t" + "MOV r1, #0xa0000000\n\t" + "MOV r2, #0xba7d\n\t" + "MOVT r2, #0x4b9e\n\t" + "MOV r3, #0x4c63\n\t" + "MOVT r3, #0xcb02\n\t" "MOV r4, #0xf39a\n\t" "MOVT r4, #0xd45e\n\t" "MOV r5, #0xdf3b\n\t" "MOVT r5, #0x29b\n\t" "MOV r9, #0x2000000\n\t" - "AND %[a], %[a], lr\n\t" - "AND %[b], %[b], lr\n\t" - "AND %[c], %[c], lr\n\t" + "AND r1, r1, lr\n\t" + "AND r2, r2, lr\n\t" + "AND r3, r3, lr\n\t" "AND r4, r4, lr\n\t" "AND r5, r5, lr\n\t" "AND r9, r9, lr\n\t" "LDM r12, {r10, r11}\n\t" - "ADDS r10, r10, %[a]\n\t" - "ADCS r11, r11, %[b]\n\t" + "ADDS r10, r10, r1\n\t" + "ADCS r11, r11, r2\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" - "ADCS r10, r10, %[c]\n\t" + "ADCS r10, r10, r3\n\t" "ADCS r11, r11, r4\n\t" "STM r12!, {r10, r11}\n\t" "LDM r12, {r10, r11}\n\t" @@ -8323,7 +8918,7 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "LDM r12, {r10}\n\t" "ADCS r10, r10, #0\n\t" "STM r12!, {r10}\n\t" - "SUB %[s], %[s], #16\n\t" + "SUB r0, r0, #16\n\t" "MOV r12, sp\n\t" /* Load bits 252-376 */ "ADD r12, r12, #28\n\t" @@ -8331,74 +8926,74 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "LSL r5, r5, #4\n\t" "ORR r5, r5, r4, LSR #28\n\t" "LSL r4, r4, #4\n\t" - "ORR r4, r4, %[c], LSR #28\n\t" - "LSL %[c], %[c], #4\n\t" - "ORR %[c], %[c], %[b], LSR #28\n\t" - "LSL %[b], %[b], #4\n\t" - "ORR %[b], %[b], %[a], LSR #28\n\t" + "ORR r4, r4, r3, LSR #28\n\t" + "LSL r3, r3, #4\n\t" + "ORR r3, r3, r2, LSR #28\n\t" + "LSL r2, r2, #4\n\t" + "ORR r2, r2, r1, LSR #28\n\t" "BFC r5, #29, #3\n\t" "SUB r12, r12, #28\n\t" /* Sub product of top 4 words and order */ - "MOV %[s], sp\n\t" + "MOV r0, sp\n\t" /* * -5cf5d3ed */ - "MOV %[a], #0x2c13\n\t" - "MOVT %[a], #0xa30a\n\t" + "MOV r1, #0x2c13\n\t" + "MOVT r1, #0xa30a\n\t" "MOV lr, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" - "UMLAL r6, lr, %[b], %[a]\n\t" - "UMAAL r7, lr, %[c], %[a]\n\t" - "UMAAL r8, lr, r4, %[a]\n\t" - "UMAAL r9, lr, r5, %[a]\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" + "UMLAL r6, lr, r2, r1\n\t" + "UMAAL r7, lr, r3, r1\n\t" + "UMAAL r8, lr, r4, r1\n\t" + "UMAAL r9, lr, r5, r1\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -5812631b */ - "MOV %[a], #0x9ce5\n\t" - "MOVT %[a], #0xa7ed\n\t" + "MOV r1, #0x9ce5\n\t" + "MOVT r1, #0xa7ed\n\t" "MOV r10, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" - "UMLAL r6, r10, %[b], %[a]\n\t" - "UMAAL r7, r10, %[c], %[a]\n\t" - "UMAAL r8, r10, r4, %[a]\n\t" - "UMAAL r9, r10, r5, %[a]\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" + "UMLAL r6, r10, r2, r1\n\t" + "UMAAL r7, r10, r3, r1\n\t" + "UMAAL r8, r10, r4, r1\n\t" + "UMAAL r9, r10, r5, r1\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -a2f79cd7 */ - "MOV %[a], #0x6329\n\t" - "MOVT %[a], #0x5d08\n\t" + "MOV r1, #0x6329\n\t" + "MOVT r1, #0x5d08\n\t" "MOV r11, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" - "UMLAL r6, r11, %[b], %[a]\n\t" - "UMAAL r7, r11, %[c], %[a]\n\t" - "UMAAL r8, r11, r4, %[a]\n\t" - "UMAAL r9, r11, r5, %[a]\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" + "UMLAL r6, r11, r2, r1\n\t" + "UMAAL r7, r11, r3, r1\n\t" + "UMAAL r8, r11, r4, r1\n\t" + "UMAAL r9, r11, r5, r1\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* * -14def9df */ - "MOV %[a], #0x621\n\t" - "MOVT %[a], #0xeb21\n\t" + "MOV r1, #0x621\n\t" + "MOVT r1, #0xeb21\n\t" "MOV r12, #0\n\t" - "LDM %[s], {r6, r7, r8, r9}\n\t" - "UMLAL r6, r12, %[b], %[a]\n\t" - "UMAAL r7, r12, %[c], %[a]\n\t" - "UMAAL r8, r12, r4, %[a]\n\t" - "UMAAL r9, r12, r5, %[a]\n\t" - "STM %[s], {r6, r7, r8, r9}\n\t" - "ADD %[s], %[s], #4\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" + "UMLAL r6, r12, r2, r1\n\t" + "UMAAL r7, r12, r3, r1\n\t" + "UMAAL r8, r12, r4, r1\n\t" + "UMAAL r9, r12, r5, r1\n\t" + "STM r0, {r6, r7, r8, r9}\n\t" + "ADD r0, r0, #4\n\t" /* Add overflows at 4 * 32 */ - "LDM %[s], {r6, r7, r8, r9}\n\t" + "LDM r0, {r6, r7, r8, r9}\n\t" "BFC r9, #28, #4\n\t" "ADDS r6, r6, lr\n\t" "ADCS r7, r7, r10\n\t" "ADCS r8, r8, r11\n\t" "ADC r9, r9, r12\n\t" /* Subtract top at 4 * 32 */ - "SUBS r6, r6, %[b]\n\t" - "SBCS r7, r7, %[c]\n\t" + "SUBS r6, r6, r2\n\t" + "SBCS r7, r7, r3\n\t" "SBCS r8, r8, r4\n\t" "SBCS r9, r9, r5\n\t" - "SBC %[a], %[a], %[a]\n\t" - "SUB %[s], %[s], #16\n\t" - "LDM %[s], {r2, r3, r4, r5}\n\t" + "SBC r1, r1, r1\n\t" + "SUB r0, r0, #16\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" "MOV r10, #0xd3ed\n\t" "MOVT r10, #0x5cf5\n\t" "MOV r11, #0x631a\n\t" @@ -8407,41 +9002,53 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, "MOVT r12, #0xa2f7\n\t" "MOV lr, #0xf9de\n\t" "MOVT lr, #0x14de\n\t" - "AND r10, r10, %[a]\n\t" - "AND r11, r11, %[a]\n\t" - "AND r12, r12, %[a]\n\t" - "AND lr, lr, %[a]\n\t" - "ADDS %[b], %[b], r10\n\t" - "ADCS %[c], %[c], r11\n\t" + "AND r10, r10, r1\n\t" + "AND r11, r11, r1\n\t" + "AND r12, r12, r1\n\t" + "AND lr, lr, r1\n\t" + "ADDS r2, r2, r10\n\t" + "ADCS r3, r3, r11\n\t" "ADCS r4, r4, r12\n\t" "ADCS r5, r5, lr\n\t" "ADCS r6, r6, #0\n\t" "ADCS r7, r7, #0\n\t" - "AND %[a], %[a], #0x10000000\n\t" + "AND r1, r1, #0x10000000\n\t" "ADCS r8, r8, #0\n\t" - "ADC r9, r9, %[a]\n\t" + "ADC r9, r9, r1\n\t" "BFC r9, #28, #4\n\t" - "LDR %[s], [sp, #68]\n\t" + "LDR r0, [sp, #68]\n\t" /* Store result */ - "STR %[b], [%[s]]\n\t" - "STR %[c], [%[s], #4]\n\t" - "STR r4, [%[s], #8]\n\t" - "STR r5, [%[s], #12]\n\t" - "STR r6, [%[s], #16]\n\t" - "STR r7, [%[s], #20]\n\t" - "STR r8, [%[s], #24]\n\t" - "STR r9, [%[s], #28]\n\t" + "STR r2, [r0]\n\t" + "STR r3, [r0, #4]\n\t" + "STR r4, [r0, #8]\n\t" + "STR r5, [r0, #12]\n\t" + "STR r6, [r0, #16]\n\t" + "STR r7, [r0, #20]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #28]\n\t" "ADD sp, sp, #0x50\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [s] "+r" (s), [a] "+r" (a), [b] "+r" (b), [c] "+r" (c) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [s] "r" (s), [a] "r" (a), [b] "r" (b), [c] "r" (c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + s = (byte*)(size_t)L_asm_args[0]; + a = (const byte*)(size_t)L_asm_args[1]; + b = (const byte*)(size_t)L_asm_args[2]; + c = (const byte*)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_ARM_ARCH_7M */ diff --git a/wolfcrypt/src/port/arm/thumb2-mlkem-asm_c.c b/wolfcrypt/src/port/arm/thumb2-mlkem-asm_c.c index 6eac784c4de..663305a8958 100644 --- a/wolfcrypt/src/port/arm/thumb2-mlkem-asm_c.c +++ b/wolfcrypt/src/port/arm/thumb2-mlkem-asm_c.c @@ -80,13 +80,18 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_ntt(sword16* r) register word16* L_mlkem_thumb2_ntt_zetas_c __asm__ ("r1") = (word16*)&L_mlkem_thumb2_ntt_zetas; #else - register word16* L_mlkem_thumb2_ntt_zetas_c = - (word16*)&L_mlkem_thumb2_ntt_zetas; + void* L_asm_args[2] = {(void*)(size_t)r, + (void*)(size_t)&L_mlkem_thumb2_ntt_zetas + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #8\n\t" - "MOV r1, %[L_mlkem_thumb2_ntt_zetas]\n\t" #ifndef WOLFSSL_ARM_ARCH_7M "MOV r12, #0xd01\n\t" "MOVT r12, #0xcff\n\t" @@ -100,14 +105,14 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_ntt(sword16* r) #endif "STR r2, [sp]\n\t" "LDRH lr, [r1, #2]\n\t" - "LDR r2, [%[r]]\n\t" - "LDR r3, [%[r], #64]\n\t" - "LDR r4, [%[r], #128]\n\t" - "LDR r5, [%[r], #192]\n\t" - "LDR r6, [%[r], #256]\n\t" - "LDR r7, [%[r], #320]\n\t" - "LDR r8, [%[r], #384]\n\t" - "LDR r9, [%[r], #448]\n\t" + "LDR r2, [r0]\n\t" + "LDR r3, [r0, #64]\n\t" + "LDR r4, [r0, #128]\n\t" + "LDR r5, [r0, #192]\n\t" + "LDR r6, [r0, #256]\n\t" + "LDR r7, [r0, #320]\n\t" + "LDR r8, [r0, #384]\n\t" + "LDR r9, [r0, #448]\n\t" #ifndef WOLFSSL_ARM_ARCH_7M "SMULBB r10, lr, r6\n\t" "SMULBT r6, lr, r6\n\t" @@ -519,17 +524,17 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_ntt(sword16* r) "BFI r9, r11, #0, #16\n\t" "BFI r8, r10, #0, #16\n\t" #endif /* !WOLFSSL_ARM_ARCH_7M */ - "STR r2, [%[r]]\n\t" - "STR r3, [%[r], #64]\n\t" - "STR r4, [%[r], #128]\n\t" - "STR r5, [%[r], #192]\n\t" - "STR r6, [%[r], #256]\n\t" - "STR r7, [%[r], #320]\n\t" - "STR r8, [%[r], #384]\n\t" - "STR r9, [%[r], #448]\n\t" + "STR r2, [r0]\n\t" + "STR r3, [r0, #64]\n\t" + "STR r4, [r0, #128]\n\t" + "STR r5, [r0, #192]\n\t" + "STR r6, [r0, #256]\n\t" + "STR r7, [r0, #320]\n\t" + "STR r8, [r0, #384]\n\t" + "STR r9, [r0, #448]\n\t" "LDR r2, [sp]\n\t" "SUBS r2, r2, #1\n\t" - "ADD %[r], %[r], #4\n\t" + "ADD r0, r0, #4\n\t" #if defined(__GNUC__) "BNE L_mlkem_thumb2_ntt_loop_123_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -537,7 +542,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_ntt(sword16* r) #else "BNE.N L_mlkem_thumb2_ntt_loop_123_%=\n\t" #endif - "SUB %[r], %[r], #0x40\n\t" + "SUB r0, r0, #0x40\n\t" "MOV r3, #0\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -556,14 +561,14 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_ntt(sword16* r) "L_mlkem_thumb2_ntt_loop_4_i_%=:\n\t" #endif "STR r2, [sp]\n\t" - "LDR r2, [%[r]]\n\t" - "LDR r3, [%[r], #16]\n\t" - "LDR r4, [%[r], #32]\n\t" - "LDR r5, [%[r], #48]\n\t" - "LDR r6, [%[r], #64]\n\t" - "LDR r7, [%[r], #80]\n\t" - "LDR r8, [%[r], #96]\n\t" - "LDR r9, [%[r], #112]\n\t" + "LDR r2, [r0]\n\t" + "LDR r3, [r0, #16]\n\t" + "LDR r4, [r0, #32]\n\t" + "LDR r5, [r0, #48]\n\t" + "LDR r6, [r0, #64]\n\t" + "LDR r7, [r0, #80]\n\t" + "LDR r8, [r0, #96]\n\t" + "LDR r9, [r0, #112]\n\t" #ifndef WOLFSSL_ARM_ARCH_7M "SMULBB r10, lr, r4\n\t" "SMULBT r4, lr, r4\n\t" @@ -700,17 +705,17 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_ntt(sword16* r) "BFI r9, r11, #0, #16\n\t" "BFI r7, r10, #0, #16\n\t" #endif /* !WOLFSSL_ARM_ARCH_7M */ - "STR r2, [%[r]]\n\t" - "STR r3, [%[r], #16]\n\t" - "STR r4, [%[r], #32]\n\t" - "STR r5, [%[r], #48]\n\t" - "STR r6, [%[r], #64]\n\t" - "STR r7, [%[r], #80]\n\t" - "STR r8, [%[r], #96]\n\t" - "STR r9, [%[r], #112]\n\t" + "STR r2, [r0]\n\t" + "STR r3, [r0, #16]\n\t" + "STR r4, [r0, #32]\n\t" + "STR r5, [r0, #48]\n\t" + "STR r6, [r0, #64]\n\t" + "STR r7, [r0, #80]\n\t" + "STR r8, [r0, #96]\n\t" + "STR r9, [r0, #112]\n\t" "LDRD r2, r3, [sp]\n\t" "SUBS r2, r2, #1\n\t" - "ADD %[r], %[r], #4\n\t" + "ADD r0, r0, #4\n\t" #if defined(__GNUC__) "BNE L_mlkem_thumb2_ntt_loop_4_i_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -720,7 +725,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_ntt(sword16* r) #endif "ADD r3, r3, #0x40\n\t" "RSBS r10, r3, #0x100\n\t" - "ADD %[r], %[r], #0x70\n\t" + "ADD r0, r0, #0x70\n\t" #if defined(__GNUC__) "BNE L_mlkem_thumb2_ntt_loop_4_j_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -728,7 +733,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_ntt(sword16* r) #else "BNE.N L_mlkem_thumb2_ntt_loop_4_j_%=\n\t" #endif - "SUB %[r], %[r], #0x200\n\t" + "SUB r0, r0, #0x200\n\t" "MOV r3, #0\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -739,14 +744,14 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_ntt(sword16* r) "ADD lr, r1, r3, LSR #3\n\t" "STR r3, [sp, #4]\n\t" "LDRH lr, [lr, #32]\n\t" - "LDR r2, [%[r]]\n\t" - "LDR r3, [%[r], #4]\n\t" - "LDR r4, [%[r], #8]\n\t" - "LDR r5, [%[r], #12]\n\t" - "LDR r6, [%[r], #16]\n\t" - "LDR r7, [%[r], #20]\n\t" - "LDR r8, [%[r], #24]\n\t" - "LDR r9, [%[r], #28]\n\t" + "LDR r2, [r0]\n\t" + "LDR r3, [r0, #4]\n\t" + "LDR r4, [r0, #8]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r8, [r0, #24]\n\t" + "LDR r9, [r0, #28]\n\t" #ifndef WOLFSSL_ARM_ARCH_7M "SMULBB r10, lr, r6\n\t" "SMULBT r6, lr, r6\n\t" @@ -1343,18 +1348,18 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_ntt(sword16* r) "MOV r12, #0xd01\n\t" "MOVT r12, #0xcff\n\t" #endif /* !WOLFSSL_ARM_ARCH_7M */ - "STR r2, [%[r]]\n\t" - "STR r3, [%[r], #4]\n\t" - "STR r4, [%[r], #8]\n\t" - "STR r5, [%[r], #12]\n\t" - "STR r6, [%[r], #16]\n\t" - "STR r7, [%[r], #20]\n\t" - "STR r8, [%[r], #24]\n\t" - "STR r9, [%[r], #28]\n\t" + "STR r2, [r0]\n\t" + "STR r3, [r0, #4]\n\t" + "STR r4, [r0, #8]\n\t" + "STR r5, [r0, #12]\n\t" + "STR r6, [r0, #16]\n\t" + "STR r7, [r0, #20]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #28]\n\t" "LDR r3, [sp, #4]\n\t" "ADD r3, r3, #16\n\t" "RSBS r10, r3, #0x100\n\t" - "ADD %[r], %[r], #32\n\t" + "ADD r0, r0, #32\n\t" #if defined(__GNUC__) "BNE L_mlkem_thumb2_ntt_loop_567_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -1363,18 +1368,26 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_ntt(sword16* r) "BNE.N L_mlkem_thumb2_ntt_loop_567_%=\n\t" #endif "ADD sp, sp, #8\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [L_mlkem_thumb2_ntt_zetas] "+r" (L_mlkem_thumb2_ntt_zetas_c) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), - [L_mlkem_thumb2_ntt_zetas] "r" (L_mlkem_thumb2_ntt_zetas_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword16*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } XALIGNED(4) static const word16 L_mlkem_invntt_zetas_inv[] = { @@ -1407,13 +1420,18 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_invntt(sword16* r) register word16* L_mlkem_invntt_zetas_inv_c __asm__ ("r1") = (word16*)&L_mlkem_invntt_zetas_inv; #else - register word16* L_mlkem_invntt_zetas_inv_c = - (word16*)&L_mlkem_invntt_zetas_inv; + void* L_asm_args[2] = {(void*)(size_t)r, + (void*)(size_t)&L_mlkem_invntt_zetas_inv + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #8\n\t" - "MOV r1, %[L_mlkem_invntt_zetas_inv]\n\t" #ifndef WOLFSSL_ARM_ARCH_7M "MOV r12, #0xd01\n\t" "MOVT r12, #0xcff\n\t" @@ -1427,14 +1445,14 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_invntt(sword16* r) #endif "ADD lr, r1, r3, LSR #1\n\t" "STR r3, [sp, #4]\n\t" - "LDR r2, [%[r]]\n\t" - "LDR r3, [%[r], #4]\n\t" - "LDR r4, [%[r], #8]\n\t" - "LDR r5, [%[r], #12]\n\t" - "LDR r6, [%[r], #16]\n\t" - "LDR r7, [%[r], #20]\n\t" - "LDR r8, [%[r], #24]\n\t" - "LDR r9, [%[r], #28]\n\t" + "LDR r2, [r0]\n\t" + "LDR r3, [r0, #4]\n\t" + "LDR r4, [r0, #8]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r8, [r0, #24]\n\t" + "LDR r9, [r0, #28]\n\t" "LDR lr, [lr]\n\t" #ifndef WOLFSSL_ARM_ARCH_7M "SSUB16 r10, r2, r3\n\t" @@ -2003,18 +2021,18 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_invntt(sword16* r) "LSR r11, r11, #16\n\t" "BFI r5, r11, #16, #16\n\t" #endif /* !WOLFSSL_ARM_ARCH_7M */ - "STR r2, [%[r]]\n\t" - "STR r3, [%[r], #4]\n\t" - "STR r4, [%[r], #8]\n\t" - "STR r5, [%[r], #12]\n\t" - "STR r6, [%[r], #16]\n\t" - "STR r7, [%[r], #20]\n\t" - "STR r8, [%[r], #24]\n\t" - "STR r9, [%[r], #28]\n\t" + "STR r2, [r0]\n\t" + "STR r3, [r0, #4]\n\t" + "STR r4, [r0, #8]\n\t" + "STR r5, [r0, #12]\n\t" + "STR r6, [r0, #16]\n\t" + "STR r7, [r0, #20]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #28]\n\t" "LDR r3, [sp, #4]\n\t" "ADD r3, r3, #16\n\t" "RSBS r10, r3, #0x100\n\t" - "ADD %[r], %[r], #32\n\t" + "ADD r0, r0, #32\n\t" #if defined(__GNUC__) "BNE L_mlkem_invntt_loop_765_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2022,7 +2040,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_invntt(sword16* r) #else "BNE.N L_mlkem_invntt_loop_765_%=\n\t" #endif - "SUB %[r], %[r], #0x200\n\t" + "SUB r0, r0, #0x200\n\t" "MOV r3, #0\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2041,14 +2059,14 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_invntt(sword16* r) "L_mlkem_invntt_loop_4_i_%=:\n\t" #endif "STR r2, [sp]\n\t" - "LDR r2, [%[r]]\n\t" - "LDR r3, [%[r], #16]\n\t" - "LDR r4, [%[r], #32]\n\t" - "LDR r5, [%[r], #48]\n\t" - "LDR r6, [%[r], #64]\n\t" - "LDR r7, [%[r], #80]\n\t" - "LDR r8, [%[r], #96]\n\t" - "LDR r9, [%[r], #112]\n\t" + "LDR r2, [r0]\n\t" + "LDR r3, [r0, #16]\n\t" + "LDR r4, [r0, #32]\n\t" + "LDR r5, [r0, #48]\n\t" + "LDR r6, [r0, #64]\n\t" + "LDR r7, [r0, #80]\n\t" + "LDR r8, [r0, #96]\n\t" + "LDR r9, [r0, #112]\n\t" #ifndef WOLFSSL_ARM_ARCH_7M "SSUB16 r10, r2, r4\n\t" "SADD16 r2, r2, r4\n\t" @@ -2205,17 +2223,17 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_invntt(sword16* r) "MLA r9, r12, r11, r9\n\t" "BFI r9, r10, #0, #16\n\t" #endif /* !WOLFSSL_ARM_ARCH_7M */ - "STR r2, [%[r]]\n\t" - "STR r3, [%[r], #16]\n\t" - "STR r4, [%[r], #32]\n\t" - "STR r5, [%[r], #48]\n\t" - "STR r6, [%[r], #64]\n\t" - "STR r7, [%[r], #80]\n\t" - "STR r8, [%[r], #96]\n\t" - "STR r9, [%[r], #112]\n\t" + "STR r2, [r0]\n\t" + "STR r3, [r0, #16]\n\t" + "STR r4, [r0, #32]\n\t" + "STR r5, [r0, #48]\n\t" + "STR r6, [r0, #64]\n\t" + "STR r7, [r0, #80]\n\t" + "STR r8, [r0, #96]\n\t" + "STR r9, [r0, #112]\n\t" "LDRD r2, r3, [sp]\n\t" "SUBS r2, r2, #1\n\t" - "ADD %[r], %[r], #4\n\t" + "ADD r0, r0, #4\n\t" #if defined(__GNUC__) "BNE L_mlkem_invntt_loop_4_i_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2225,7 +2243,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_invntt(sword16* r) #endif "ADD r3, r3, #0x40\n\t" "RSBS r10, r3, #0x100\n\t" - "ADD %[r], %[r], #0x70\n\t" + "ADD r0, r0, #0x70\n\t" #if defined(__GNUC__) "BNE L_mlkem_invntt_loop_4_j_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2233,7 +2251,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_invntt(sword16* r) #else "BNE.N L_mlkem_invntt_loop_4_j_%=\n\t" #endif - "SUB %[r], %[r], #0x200\n\t" + "SUB r0, r0, #0x200\n\t" "MOV r2, #16\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2243,14 +2261,14 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_invntt(sword16* r) #endif "STR r2, [sp]\n\t" "LDRH lr, [r1, #2]\n\t" - "LDR r2, [%[r]]\n\t" - "LDR r3, [%[r], #64]\n\t" - "LDR r4, [%[r], #128]\n\t" - "LDR r5, [%[r], #192]\n\t" - "LDR r6, [%[r], #256]\n\t" - "LDR r7, [%[r], #320]\n\t" - "LDR r8, [%[r], #384]\n\t" - "LDR r9, [%[r], #448]\n\t" + "LDR r2, [r0]\n\t" + "LDR r3, [r0, #64]\n\t" + "LDR r4, [r0, #128]\n\t" + "LDR r5, [r0, #192]\n\t" + "LDR r6, [r0, #256]\n\t" + "LDR r7, [r0, #320]\n\t" + "LDR r8, [r0, #384]\n\t" + "LDR r9, [r0, #448]\n\t" "LDR lr, [r1, #240]\n\t" #ifndef WOLFSSL_ARM_ARCH_7M "SSUB16 r10, r2, r3\n\t" @@ -3038,17 +3056,17 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_invntt(sword16* r) "MLA r9, r12, r11, r9\n\t" "BFI r9, r10, #0, #16\n\t" #endif /* !WOLFSSL_ARM_ARCH_7M */ - "STR r2, [%[r]]\n\t" - "STR r3, [%[r], #64]\n\t" - "STR r4, [%[r], #128]\n\t" - "STR r5, [%[r], #192]\n\t" - "STR r6, [%[r], #256]\n\t" - "STR r7, [%[r], #320]\n\t" - "STR r8, [%[r], #384]\n\t" - "STR r9, [%[r], #448]\n\t" + "STR r2, [r0]\n\t" + "STR r3, [r0, #64]\n\t" + "STR r4, [r0, #128]\n\t" + "STR r5, [r0, #192]\n\t" + "STR r6, [r0, #256]\n\t" + "STR r7, [r0, #320]\n\t" + "STR r8, [r0, #384]\n\t" + "STR r9, [r0, #448]\n\t" "LDR r2, [sp]\n\t" "SUBS r2, r2, #1\n\t" - "ADD %[r], %[r], #4\n\t" + "ADD r0, r0, #4\n\t" #if defined(__GNUC__) "BNE L_mlkem_invntt_loop_321_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -3057,18 +3075,26 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_invntt(sword16* r) "BNE.N L_mlkem_invntt_loop_321_%=\n\t" #endif "ADD sp, sp, #8\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [L_mlkem_invntt_zetas_inv] "+r" (L_mlkem_invntt_zetas_inv_c) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), - [L_mlkem_invntt_zetas_inv] "r" (L_mlkem_invntt_zetas_inv_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword16*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } XALIGNED(4) static const word16 L_mlkem_basemul_mont_zetas[] = { @@ -3105,12 +3131,17 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_basemul_mont(sword16* r, register word16* L_mlkem_basemul_mont_zetas_c __asm__ ("r3") = (word16*)&L_mlkem_basemul_mont_zetas; #else - register word16* L_mlkem_basemul_mont_zetas_c = - (word16*)&L_mlkem_basemul_mont_zetas; + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)&L_mlkem_basemul_mont_zetas + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "MOV r3, %[L_mlkem_basemul_mont_zetas]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "ADD r3, r3, #0x80\n\t" #ifndef WOLFSSL_ARM_ARCH_7M "MOV r12, #0xd01\n\t" @@ -3123,8 +3154,8 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_basemul_mont(sword16* r, #else "L_mlkem_basemul_mont_loop_%=:\n\t" #endif - "LDM %[a]!, {r4, r5}\n\t" - "LDM %[b]!, {r6, r7}\n\t" + "LDM r1!, {r4, r5}\n\t" + "LDM r2!, {r6, r7}\n\t" "LDR lr, [r3, r8]\n\t" "ADD r8, r8, #2\n\t" "PUSH {r8}\n\t" @@ -3222,7 +3253,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_basemul_mont(sword16* r, "ORR r4, r9, r8, LSR #16\n\t" "ORR r5, r11, r10, LSR #16\n\t" #endif /* !WOLFSSL_ARM_ARCH_7M */ - "STM %[r]!, {r4, r5}\n\t" + "STM r0!, {r4, r5}\n\t" "POP {r8}\n\t" #if defined(__GNUC__) "BNE L_mlkem_basemul_mont_loop_%=\n\t" @@ -3231,18 +3262,28 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_basemul_mont(sword16* r, #else "BNE.N L_mlkem_basemul_mont_loop_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [L_mlkem_basemul_mont_zetas] "+r" (L_mlkem_basemul_mont_zetas_c) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), - [L_mlkem_basemul_mont_zetas] "r" (L_mlkem_basemul_mont_zetas_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword16*)(size_t)L_asm_args[0]; + a = (const sword16*)(size_t)L_asm_args[1]; + b = (const sword16*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -3260,12 +3301,17 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_basemul_mont_add(sword16* r, register word16* L_mlkem_basemul_mont_zetas_c __asm__ ("r3") = (word16*)&L_mlkem_basemul_mont_zetas; #else - register word16* L_mlkem_basemul_mont_zetas_c = - (word16*)&L_mlkem_basemul_mont_zetas; + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)&L_mlkem_basemul_mont_zetas + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "MOV r3, %[L_mlkem_basemul_mont_zetas]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "ADD r3, r3, #0x80\n\t" #ifndef WOLFSSL_ARM_ARCH_7M "MOV r12, #0xd01\n\t" @@ -3278,8 +3324,8 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_basemul_mont_add(sword16* r, #else "L_mlkem_thumb2_basemul_mont_add_loop_%=:\n\t" #endif - "LDM %[a]!, {r4, r5}\n\t" - "LDM %[b]!, {r6, r7}\n\t" + "LDM r1!, {r4, r5}\n\t" + "LDM r2!, {r6, r7}\n\t" "LDR lr, [r3, r8]\n\t" "ADD r8, r8, #2\n\t" "PUSH {r8}\n\t" @@ -3308,7 +3354,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_basemul_mont_add(sword16* r, "SMULTB r7, r12, r11\n\t" "SMLABB r9, r12, r6, r9\n\t" "SMLABB r11, r12, r7, r11\n\t" - "LDM %[r], {r4, r5}\n\t" + "LDM r0, {r4, r5}\n\t" "PKHTB r9, r9, r8, ASR #16\n\t" "PKHTB r11, r11, r10, ASR #16\n\t" "SADD16 r4, r4, r9\n\t" @@ -3375,7 +3421,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_basemul_mont_add(sword16* r, "SBFX r5, r7, #0, #16\n\t" "MLA r9, r12, r4, r9\n\t" "MLA r11, r12, r5, r11\n\t" - "LDM %[r], {r4, r5}\n\t" + "LDM r0, {r4, r5}\n\t" "BFC r9, #0, #16\n\t" "BFC r11, #0, #16\n\t" "ORR r9, r9, r8, LSR #16\n\t" @@ -3389,7 +3435,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_basemul_mont_add(sword16* r, "BFI r4, r8, #0, #16\n\t" "BFI r5, r10, #0, #16\n\t" #endif /* !WOLFSSL_ARM_ARCH_7M */ - "STM %[r]!, {r4, r5}\n\t" + "STM r0!, {r4, r5}\n\t" "POP {r8}\n\t" #if defined(__GNUC__) "BNE L_mlkem_thumb2_basemul_mont_add_loop_%=\n\t" @@ -3398,18 +3444,28 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_basemul_mont_add(sword16* r, #else "BNE.N L_mlkem_thumb2_basemul_mont_add_loop_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [L_mlkem_basemul_mont_zetas] "+r" (L_mlkem_basemul_mont_zetas_c) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), - [L_mlkem_basemul_mont_zetas] "r" (L_mlkem_basemul_mont_zetas_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sword16*)(size_t)L_asm_args[0]; + a = (const sword16*)(size_t)L_asm_args[1]; + b = (const sword16*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -3423,11 +3479,17 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_csubq(sword16* p) register word16* L_mlkem_basemul_mont_zetas_c __asm__ ("r1") = (word16*)&L_mlkem_basemul_mont_zetas; #else - register word16* L_mlkem_basemul_mont_zetas_c = - (word16*)&L_mlkem_basemul_mont_zetas; + void* L_asm_args[2] = {(void*)(size_t)p, + (void*)(size_t)&L_mlkem_basemul_mont_zetas + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r11, #0xd01\n\t" "MOV r12, #0xd01\n\t" #ifndef WOLFSSL_ARM_ARCH_7M @@ -3442,7 +3504,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_csubq(sword16* p) #else "L_mlkem_thumb2_csubq_loop_%=:\n\t" #endif - "LDM %[p], {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" #ifndef WOLFSSL_ARM_ARCH_7M "SSUB16 r2, r2, r12\n\t" "SSUB16 r3, r3, r12\n\t" @@ -3506,7 +3568,7 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_csubq(sword16* p) "ADD r5, r5, r9\n\t" "BFI r5, r10, #0, #16\n\t" #endif /* !WOLFSSL_ARM_ARCH_7M */ - "STM %[p]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" "SUBS r1, r1, #8\n\t" #if defined(__GNUC__) "BNE L_mlkem_thumb2_csubq_loop_%=\n\t" @@ -3515,18 +3577,26 @@ WC_OMIT_FRAME_POINTER void mlkem_thumb2_csubq(sword16* p) #else "BNE.N L_mlkem_thumb2_csubq_loop_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [p] "+r" (p), [L_mlkem_basemul_mont_zetas] "+r" (L_mlkem_basemul_mont_zetas_c) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [p] "r" (p), - [L_mlkem_basemul_mont_zetas] "r" (L_mlkem_basemul_mont_zetas_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + p = (sword16*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -3545,11 +3615,18 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, register word16* L_mlkem_basemul_mont_zetas_c __asm__ ("r4") = (word16*)&L_mlkem_basemul_mont_zetas; #else - register word16* L_mlkem_basemul_mont_zetas_c = - (word16*)&L_mlkem_basemul_mont_zetas; + void* L_asm_args[5] = {(void*)(size_t)p, (void*)(size_t)len, + (void*)(size_t)r, (void*)(size_t)rLen, + (void*)(size_t)&L_mlkem_basemul_mont_zetas + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, #0xd01\n\t" "MOV r9, #0\n\t" "\n" @@ -3558,7 +3635,7 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "L_mlkem_thumb2_rej_uniform_loop_no_fail_%=:\n\t" #endif - "CMP %[len], #8\n\t" + "CMP r1, #8\n\t" #if defined(__GNUC__) "BLT L_mlkem_thumb2_rej_uniform_done_no_fail_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -3566,58 +3643,58 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "BLT.N L_mlkem_thumb2_rej_uniform_done_no_fail_%=\n\t" #endif - "LDM %[r]!, {r4, r5, r6}\n\t" + "LDM r2!, {r4, r5, r6}\n\t" "UBFX r7, r4, #0, #12\n\t" - "STRH r7, [%[p], r9]\n\t" + "STRH r7, [r0, r9]\n\t" "SUB r10, r7, r8\n\t" "LSR r10, r10, #31\n\t" - "SUB %[len], %[len], r10\n\t" + "SUB r1, r1, r10\n\t" "ADD r9, r9, r10, LSL #1\n\t" "UBFX r7, r4, #12, #12\n\t" - "STRH r7, [%[p], r9]\n\t" + "STRH r7, [r0, r9]\n\t" "SUB r10, r7, r8\n\t" "LSR r10, r10, #31\n\t" - "SUB %[len], %[len], r10\n\t" + "SUB r1, r1, r10\n\t" "ADD r9, r9, r10, LSL #1\n\t" "UBFX r7, r4, #24, #8\n\t" "BFI r7, r5, #8, #4\n\t" - "STRH r7, [%[p], r9]\n\t" + "STRH r7, [r0, r9]\n\t" "SUB r10, r7, r8\n\t" "LSR r10, r10, #31\n\t" - "SUB %[len], %[len], r10\n\t" + "SUB r1, r1, r10\n\t" "ADD r9, r9, r10, LSL #1\n\t" "UBFX r7, r5, #4, #12\n\t" - "STRH r7, [%[p], r9]\n\t" + "STRH r7, [r0, r9]\n\t" "SUB r10, r7, r8\n\t" "LSR r10, r10, #31\n\t" - "SUB %[len], %[len], r10\n\t" + "SUB r1, r1, r10\n\t" "ADD r9, r9, r10, LSL #1\n\t" "UBFX r7, r5, #16, #12\n\t" - "STRH r7, [%[p], r9]\n\t" + "STRH r7, [r0, r9]\n\t" "SUB r10, r7, r8\n\t" "LSR r10, r10, #31\n\t" - "SUB %[len], %[len], r10\n\t" + "SUB r1, r1, r10\n\t" "ADD r9, r9, r10, LSL #1\n\t" "UBFX r7, r5, #28, #4\n\t" "BFI r7, r6, #4, #8\n\t" - "STRH r7, [%[p], r9]\n\t" + "STRH r7, [r0, r9]\n\t" "SUB r10, r7, r8\n\t" "LSR r10, r10, #31\n\t" - "SUB %[len], %[len], r10\n\t" + "SUB r1, r1, r10\n\t" "ADD r9, r9, r10, LSL #1\n\t" "UBFX r7, r6, #8, #12\n\t" - "STRH r7, [%[p], r9]\n\t" + "STRH r7, [r0, r9]\n\t" "SUB r10, r7, r8\n\t" "LSR r10, r10, #31\n\t" - "SUB %[len], %[len], r10\n\t" + "SUB r1, r1, r10\n\t" "ADD r9, r9, r10, LSL #1\n\t" "UBFX r7, r6, #20, #12\n\t" - "STRH r7, [%[p], r9]\n\t" + "STRH r7, [r0, r9]\n\t" "SUB r10, r7, r8\n\t" "LSR r10, r10, #31\n\t" - "SUB %[len], %[len], r10\n\t" + "SUB r1, r1, r10\n\t" "ADD r9, r9, r10, LSL #1\n\t" - "SUBS %[rLen], %[rLen], #12\n\t" + "SUBS r3, r3, #12\n\t" #if defined(__GNUC__) "BNE L_mlkem_thumb2_rej_uniform_loop_no_fail_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -3638,7 +3715,7 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "L_mlkem_thumb2_rej_uniform_done_no_fail_%=:\n\t" #endif - "CMP %[len], #0\n\t" + "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_mlkem_thumb2_rej_uniform_done_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -3652,7 +3729,7 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "L_mlkem_thumb2_rej_uniform_loop_%=:\n\t" #endif - "LDM %[r]!, {r4, r5, r6}\n\t" + "LDM r2!, {r4, r5, r6}\n\t" "UBFX r7, r4, #0, #12\n\t" "CMP r7, r8\n\t" #if defined(__GNUC__) @@ -3662,8 +3739,8 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "BGE.N L_mlkem_thumb2_rej_uniform_fail_0_%=\n\t" #endif - "STRH r7, [%[p], r9]\n\t" - "SUBS %[len], %[len], #1\n\t" + "STRH r7, [r0, r9]\n\t" + "SUBS r1, r1, #1\n\t" "ADD r9, r9, #2\n\t" #if defined(__GNUC__) "BEQ L_mlkem_thumb2_rej_uniform_done_%=\n\t" @@ -3687,8 +3764,8 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "BGE.N L_mlkem_thumb2_rej_uniform_fail_1_%=\n\t" #endif - "STRH r7, [%[p], r9]\n\t" - "SUBS %[len], %[len], #1\n\t" + "STRH r7, [r0, r9]\n\t" + "SUBS r1, r1, #1\n\t" "ADD r9, r9, #2\n\t" #if defined(__GNUC__) "BEQ L_mlkem_thumb2_rej_uniform_done_%=\n\t" @@ -3713,8 +3790,8 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "BGE.N L_mlkem_thumb2_rej_uniform_fail_2_%=\n\t" #endif - "STRH r7, [%[p], r9]\n\t" - "SUBS %[len], %[len], #1\n\t" + "STRH r7, [r0, r9]\n\t" + "SUBS r1, r1, #1\n\t" "ADD r9, r9, #2\n\t" #if defined(__GNUC__) "BEQ L_mlkem_thumb2_rej_uniform_done_%=\n\t" @@ -3738,8 +3815,8 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "BGE.N L_mlkem_thumb2_rej_uniform_fail_3_%=\n\t" #endif - "STRH r7, [%[p], r9]\n\t" - "SUBS %[len], %[len], #1\n\t" + "STRH r7, [r0, r9]\n\t" + "SUBS r1, r1, #1\n\t" "ADD r9, r9, #2\n\t" #if defined(__GNUC__) "BEQ L_mlkem_thumb2_rej_uniform_done_%=\n\t" @@ -3763,8 +3840,8 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "BGE.N L_mlkem_thumb2_rej_uniform_fail_4_%=\n\t" #endif - "STRH r7, [%[p], r9]\n\t" - "SUBS %[len], %[len], #1\n\t" + "STRH r7, [r0, r9]\n\t" + "SUBS r1, r1, #1\n\t" "ADD r9, r9, #2\n\t" #if defined(__GNUC__) "BEQ L_mlkem_thumb2_rej_uniform_done_%=\n\t" @@ -3789,8 +3866,8 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "BGE.N L_mlkem_thumb2_rej_uniform_fail_5_%=\n\t" #endif - "STRH r7, [%[p], r9]\n\t" - "SUBS %[len], %[len], #1\n\t" + "STRH r7, [r0, r9]\n\t" + "SUBS r1, r1, #1\n\t" "ADD r9, r9, #2\n\t" #if defined(__GNUC__) "BEQ L_mlkem_thumb2_rej_uniform_done_%=\n\t" @@ -3814,8 +3891,8 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "BGE.N L_mlkem_thumb2_rej_uniform_fail_6_%=\n\t" #endif - "STRH r7, [%[p], r9]\n\t" - "SUBS %[len], %[len], #1\n\t" + "STRH r7, [r0, r9]\n\t" + "SUBS r1, r1, #1\n\t" "ADD r9, r9, #2\n\t" #if defined(__GNUC__) "BEQ L_mlkem_thumb2_rej_uniform_done_%=\n\t" @@ -3839,8 +3916,8 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "BGE.N L_mlkem_thumb2_rej_uniform_fail_7_%=\n\t" #endif - "STRH r7, [%[p], r9]\n\t" - "SUBS %[len], %[len], #1\n\t" + "STRH r7, [r0, r9]\n\t" + "SUBS r1, r1, #1\n\t" "ADD r9, r9, #2\n\t" #if defined(__GNUC__) "BEQ L_mlkem_thumb2_rej_uniform_done_%=\n\t" @@ -3855,7 +3932,7 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, #else "L_mlkem_thumb2_rej_uniform_fail_7_%=:\n\t" #endif - "SUBS %[rLen], %[rLen], #12\n\t" + "SUBS r3, r3, #12\n\t" #if defined(__GNUC__) "BGT L_mlkem_thumb2_rej_uniform_loop_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -3870,17 +3947,28 @@ WC_OMIT_FRAME_POINTER unsigned int mlkem_thumb2_rej_uniform(sword16* p, "L_mlkem_thumb2_rej_uniform_done_%=:\n\t" #endif "LSR r0, r9, #1\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [p] "+r" (p), [len] "+r" (len), [r] "+r" (r), [rLen] "+r" (rLen), [L_mlkem_basemul_mont_zetas] "+r" (L_mlkem_basemul_mont_zetas_c) : + : "memory", "cc", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [p] "r" (p), [len] "r" (len), [r] "r" (r), [rLen] "r" (rLen), - [L_mlkem_basemul_mont_zetas] "r" (L_mlkem_basemul_mont_zetas_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + p = (sword16*)(size_t)L_asm_args[0]; + len = (unsigned int)(size_t)L_asm_args[1]; + r = (const byte*)(size_t)L_asm_args[2]; + rLen = (unsigned int)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)p; } diff --git a/wolfcrypt/src/port/arm/thumb2-poly1305-asm_c.c b/wolfcrypt/src/port/arm/thumb2-poly1305-asm_c.c index b8ff2f7c2ec..def9a0f93e2 100644 --- a/wolfcrypt/src/port/arm/thumb2-poly1305-asm_c.c +++ b/wolfcrypt/src/port/arm/thumb2-poly1305-asm_c.c @@ -63,11 +63,20 @@ WC_OMIT_FRAME_POINTER void poly1305_blocks_thumb2_16(Poly1305* ctx, register const byte* m __asm__ ("r1") = (const byte*)m_p; register word32 len __asm__ ("r2") = (word32)len_p; register int notLast __asm__ ("r3") = (int)notLast_p; +#else + void* L_asm_args[4] = {(void*)(size_t)ctx, (void*)(size_t)m, + (void*)(size_t)len, (void*)(size_t)notLast + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #28\n\t" - "CMP %[len], #0\n\t" + "CMP r2, #0\n\t" #if defined(__GNUC__) "BEQ L_poly1305_thumb2_16_done_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -76,9 +85,9 @@ WC_OMIT_FRAME_POINTER void poly1305_blocks_thumb2_16(Poly1305* ctx, "BEQ.N L_poly1305_thumb2_16_done_%=\n\t" #endif "ADD lr, sp, #12\n\t" - "STM lr, {%[ctx], %[m], %[len], %[notLast]}\n\t" + "STM lr, {r0, r1, r2, r3}\n\t" /* Get h pointer */ - "ADD lr, %[ctx], #16\n\t" + "ADD lr, r0, #16\n\t" "LDM lr, {r4, r5, r6, r7, r8}\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -87,17 +96,17 @@ WC_OMIT_FRAME_POINTER void poly1305_blocks_thumb2_16(Poly1305* ctx, "L_poly1305_thumb2_16_loop_%=:\n\t" #endif /* Add m to h */ - "LDR %[m], [sp, #16]\n\t" - "LDR %[len], [%[m]]\n\t" - "LDR %[notLast], [%[m], #4]\n\t" - "LDR r9, [%[m], #8]\n\t" - "LDR r10, [%[m], #12]\n\t" + "LDR r1, [sp, #16]\n\t" + "LDR r2, [r1]\n\t" + "LDR r3, [r1, #4]\n\t" + "LDR r9, [r1, #8]\n\t" + "LDR r10, [r1, #12]\n\t" "LDR r11, [sp, #24]\n\t" - "ADDS r4, r4, %[len]\n\t" - "ADCS r5, r5, %[notLast]\n\t" + "ADDS r4, r4, r2\n\t" + "ADCS r5, r5, r3\n\t" "ADCS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" - "ADD %[m], %[m], #16\n\t" + "ADD r1, r1, #16\n\t" "ADC r8, r8, r11\n\t" #ifdef WOLFSSL_ARM_ARCH_7M "STM lr, {r4, r5, r6, r7, r8}\n\t" @@ -106,168 +115,168 @@ WC_OMIT_FRAME_POINTER void poly1305_blocks_thumb2_16(Poly1305* ctx, "STR r7, [lr, #12]\n\t" "STR r8, [lr, #16]\n\t" #endif /* WOLFSSL_ARM_ARCH_7M */ - "STR %[m], [sp, #16]\n\t" - "LDR %[m], [sp, #12]\n\t" + "STR r1, [sp, #16]\n\t" + "LDR r1, [sp, #12]\n\t" /* Multiply h by r */ #ifdef WOLFSSL_ARM_ARCH_7M /* r0 = #0, r1 = r, lr = h, r2 = h[j], r3 = r[i] */ - "LDR %[notLast], [%[m]]\n\t" - "EOR %[ctx], %[ctx], %[ctx]\n\t" + "LDR r3, [r1]\n\t" + "EOR r0, r0, r0\n\t" /* r[0] * h[0] */ /* h[0] in r4 */ - "UMULL r4, r5, %[notLast], r4\n\t" + "UMULL r4, r5, r3, r4\n\t" /* r[0] * h[2] */ /* h[2] in r6 */ - "UMULL r6, r7, %[notLast], r6\n\t" + "UMULL r6, r7, r3, r6\n\t" /* r[0] * h[4] */ /* h[4] in r8 */ - "MUL r8, %[notLast], r8\n\t" + "MUL r8, r3, r8\n\t" /* r[0] * h[1] */ - "LDR %[len], [lr, #4]\n\t" - "MOV r12, %[ctx]\n\t" - "UMLAL r5, r12, %[notLast], %[len]\n\t" + "LDR r2, [lr, #4]\n\t" + "MOV r12, r0\n\t" + "UMLAL r5, r12, r3, r2\n\t" /* r[0] * h[3] */ - "LDR %[len], [lr, #12]\n\t" + "LDR r2, [lr, #12]\n\t" "ADDS r6, r6, r12\n\t" - "ADC r7, r7, %[ctx]\n\t" - "UMLAL r7, r8, %[notLast], %[len]\n\t" + "ADC r7, r7, r0\n\t" + "UMLAL r7, r8, r3, r2\n\t" /* r[1] * h[0] */ - "LDR %[notLast], [%[m], #4]\n\t" - "LDR %[len], [lr]\n\t" - "MOV r12, %[ctx]\n\t" - "UMLAL r5, r12, %[notLast], %[len]\n\t" + "LDR r3, [r1, #4]\n\t" + "LDR r2, [lr]\n\t" + "MOV r12, r0\n\t" + "UMLAL r5, r12, r3, r2\n\t" /* r[1] * h[1] */ - "LDR %[len], [lr, #4]\n\t" + "LDR r2, [lr, #4]\n\t" "ADDS r6, r6, r12\n\t" - "ADC r12, %[ctx], %[ctx]\n\t" - "UMLAL r6, r12, %[notLast], %[len]\n\t" + "ADC r12, r0, r0\n\t" + "UMLAL r6, r12, r3, r2\n\t" /* r[1] * h[2] */ - "LDR %[len], [lr, #8]\n\t" + "LDR r2, [lr, #8]\n\t" "ADDS r7, r7, r12\n\t" - "ADC r12, %[ctx], %[ctx]\n\t" - "UMLAL r7, r12, %[notLast], %[len]\n\t" + "ADC r12, r0, r0\n\t" + "UMLAL r7, r12, r3, r2\n\t" /* r[1] * h[3] */ - "LDR %[len], [lr, #12]\n\t" + "LDR r2, [lr, #12]\n\t" "ADDS r8, r8, r12\n\t" - "ADC r9, %[ctx], %[ctx]\n\t" - "UMLAL r8, r9, %[notLast], %[len]\n\t" + "ADC r9, r0, r0\n\t" + "UMLAL r8, r9, r3, r2\n\t" /* r[1] * h[4] */ - "LDR %[len], [lr, #16]\n\t" - "MLA r9, %[notLast], %[len], r9\n\t" + "LDR r2, [lr, #16]\n\t" + "MLA r9, r3, r2, r9\n\t" /* r[2] * h[0] */ - "LDR %[notLast], [%[m], #8]\n\t" - "LDR %[len], [lr]\n\t" - "MOV r12, %[ctx]\n\t" - "UMLAL r6, r12, %[notLast], %[len]\n\t" + "LDR r3, [r1, #8]\n\t" + "LDR r2, [lr]\n\t" + "MOV r12, r0\n\t" + "UMLAL r6, r12, r3, r2\n\t" /* r[2] * h[1] */ - "LDR %[len], [lr, #4]\n\t" + "LDR r2, [lr, #4]\n\t" "ADDS r7, r7, r12\n\t" - "ADC r12, %[ctx], %[ctx]\n\t" - "UMLAL r7, r12, %[notLast], %[len]\n\t" + "ADC r12, r0, r0\n\t" + "UMLAL r7, r12, r3, r2\n\t" /* r[2] * h[2] */ - "LDR %[len], [lr, #8]\n\t" + "LDR r2, [lr, #8]\n\t" "ADDS r8, r8, r12\n\t" - "ADC r12, %[ctx], %[ctx]\n\t" - "UMLAL r8, r12, %[notLast], %[len]\n\t" + "ADC r12, r0, r0\n\t" + "UMLAL r8, r12, r3, r2\n\t" /* r[2] * h[3] */ - "LDR %[len], [lr, #12]\n\t" + "LDR r2, [lr, #12]\n\t" "ADDS r9, r9, r12\n\t" - "ADC r10, %[ctx], %[ctx]\n\t" - "UMLAL r9, r10, %[notLast], %[len]\n\t" + "ADC r10, r0, r0\n\t" + "UMLAL r9, r10, r3, r2\n\t" /* r[2] * h[4] */ - "LDR %[len], [lr, #16]\n\t" - "MLA r10, %[notLast], %[len], r10\n\t" + "LDR r2, [lr, #16]\n\t" + "MLA r10, r3, r2, r10\n\t" /* r[3] * h[0] */ - "LDR %[notLast], [%[m], #12]\n\t" - "LDR %[len], [lr]\n\t" - "MOV r12, %[ctx]\n\t" - "UMLAL r7, r12, %[notLast], %[len]\n\t" + "LDR r3, [r1, #12]\n\t" + "LDR r2, [lr]\n\t" + "MOV r12, r0\n\t" + "UMLAL r7, r12, r3, r2\n\t" /* r[3] * h[1] */ - "LDR %[len], [lr, #4]\n\t" + "LDR r2, [lr, #4]\n\t" "ADDS r8, r8, r12\n\t" - "ADC r12, %[ctx], %[ctx]\n\t" - "UMLAL r8, r12, %[notLast], %[len]\n\t" + "ADC r12, r0, r0\n\t" + "UMLAL r8, r12, r3, r2\n\t" /* r[3] * h[2] */ - "LDR %[len], [lr, #8]\n\t" + "LDR r2, [lr, #8]\n\t" "ADDS r9, r9, r12\n\t" - "ADC r10, r10, %[ctx]\n\t" - "UMLAL r9, r10, %[notLast], %[len]\n\t" + "ADC r10, r10, r0\n\t" + "UMLAL r9, r10, r3, r2\n\t" /* r[3] * h[3] */ - "LDR %[len], [lr, #12]\n\t" - "MOV r11, %[ctx]\n\t" - "UMLAL r10, r11, %[notLast], %[len]\n\t" + "LDR r2, [lr, #12]\n\t" + "MOV r11, r0\n\t" + "UMLAL r10, r11, r3, r2\n\t" /* r[3] * h[4] */ - "LDR %[len], [lr, #16]\n\t" - "MOV r12, %[ctx]\n\t" - "MLA r11, %[notLast], %[len], r11\n\t" + "LDR r2, [lr, #16]\n\t" + "MOV r12, r0\n\t" + "MLA r11, r3, r2, r11\n\t" #else - "LDM %[m], {r0, r1, r2, r3}\n\t" + "LDM r1, {r0, r1, r2, r3}\n\t" /* r[0] * h[0] */ - "UMULL r10, r11, %[ctx], r4\n\t" + "UMULL r10, r11, r0, r4\n\t" /* r[1] * h[0] */ - "UMULL r12, r7, %[m], r4\n\t" + "UMULL r12, r7, r1, r4\n\t" /* r[0] * h[1] */ - "UMAAL r11, r12, %[ctx], r5\n\t" + "UMAAL r11, r12, r0, r5\n\t" /* r[2] * h[0] */ - "UMULL r8, r9, %[len], r4\n\t" + "UMULL r8, r9, r2, r4\n\t" /* r[1] * h[1] */ - "UMAAL r12, r8, %[m], r5\n\t" + "UMAAL r12, r8, r1, r5\n\t" /* r[0] * h[2] */ - "UMAAL r12, r7, %[ctx], r6\n\t" + "UMAAL r12, r7, r0, r6\n\t" /* r[3] * h[0] */ - "UMAAL r8, r9, %[notLast], r4\n\t" + "UMAAL r8, r9, r3, r4\n\t" "STM sp, {r10, r11, r12}\n\t" /* r[2] * h[1] */ - "UMAAL r7, r8, %[len], r5\n\t" + "UMAAL r7, r8, r2, r5\n\t" /* Replace h[0] with h[3] */ "LDR r4, [lr, #12]\n\t" /* r[1] * h[2] */ - "UMULL r10, r11, %[m], r6\n\t" + "UMULL r10, r11, r1, r6\n\t" /* r[2] * h[2] */ - "UMAAL r8, r9, %[len], r6\n\t" + "UMAAL r8, r9, r2, r6\n\t" /* r[0] * h[3] */ - "UMAAL r7, r10, %[ctx], r4\n\t" + "UMAAL r7, r10, r0, r4\n\t" /* r[3] * h[1] */ - "UMAAL r8, r11, %[notLast], r5\n\t" + "UMAAL r8, r11, r3, r5\n\t" /* r[1] * h[3] */ - "UMAAL r8, r10, %[m], r4\n\t" + "UMAAL r8, r10, r1, r4\n\t" /* r[3] * h[2] */ - "UMAAL r9, r11, %[notLast], r6\n\t" + "UMAAL r9, r11, r3, r6\n\t" /* r[2] * h[3] */ - "UMAAL r9, r10, %[len], r4\n\t" + "UMAAL r9, r10, r2, r4\n\t" /* Replace h[1] with h[4] */ "LDR r5, [lr, #16]\n\t" /* r[3] * h[3] */ - "UMAAL r10, r11, %[notLast], r4\n\t" + "UMAAL r10, r11, r3, r4\n\t" "MOV r12, #0\n\t" /* r[0] * h[4] */ - "UMAAL r8, r12, %[ctx], r5\n\t" + "UMAAL r8, r12, r0, r5\n\t" /* r[1] * h[4] */ - "UMAAL r9, r12, %[m], r5\n\t" + "UMAAL r9, r12, r1, r5\n\t" /* r[2] * h[4] */ - "UMAAL r10, r12, %[len], r5\n\t" + "UMAAL r10, r12, r2, r5\n\t" /* r[3] * h[4] */ - "UMAAL r11, r12, %[notLast], r5\n\t" + "UMAAL r11, r12, r3, r5\n\t" /* DONE */ "LDM sp, {r4, r5, r6}\n\t" #endif /* WOLFSSL_ARM_ARCH_7M */ /* r12 will be zero because r is masked. */ /* Load length */ - "LDR %[len], [sp, #20]\n\t" + "LDR r2, [sp, #20]\n\t" /* Reduce mod 2^130 - 5 */ - "BIC %[notLast], r8, #3\n\t" + "BIC r3, r8, #3\n\t" "AND r8, r8, #3\n\t" - "ADDS r4, r4, %[notLast]\n\t" - "LSR %[notLast], %[notLast], #2\n\t" + "ADDS r4, r4, r3\n\t" + "LSR r3, r3, #2\n\t" "ADCS r5, r5, r9\n\t" - "ORR %[notLast], %[notLast], r9, LSL #30\n\t" + "ORR r3, r3, r9, LSL #30\n\t" "ADCS r6, r6, r10\n\t" "LSR r9, r9, #2\n\t" "ADCS r7, r7, r11\n\t" "ORR r9, r9, r10, LSL #30\n\t" "ADC r8, r8, r12\n\t" "LSR r10, r10, #2\n\t" - "ADDS r4, r4, %[notLast]\n\t" + "ADDS r4, r4, r3\n\t" "ORR r10, r10, r11, LSL #30\n\t" "ADCS r5, r5, r9\n\t" "LSR r11, r11, #2\n\t" @@ -275,9 +284,9 @@ WC_OMIT_FRAME_POINTER void poly1305_blocks_thumb2_16(Poly1305* ctx, "ADCS r7, r7, r11\n\t" "ADC r8, r8, r12\n\t" /* Sub 16 from length. */ - "SUBS %[len], %[len], #16\n\t" + "SUBS r2, r2, #16\n\t" /* Store length. */ - "STR %[len], [sp, #20]\n\t" + "STR r2, [sp, #20]\n\t" /* Loop again if more message to do. */ #if defined(__GNUC__) "BGT L_poly1305_thumb2_16_loop_%=\n\t" @@ -294,18 +303,29 @@ WC_OMIT_FRAME_POINTER void poly1305_blocks_thumb2_16(Poly1305* ctx, "L_poly1305_thumb2_16_done_%=:\n\t" #endif "ADD sp, sp, #28\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [ctx] "+r" (ctx), [m] "+r" (m), [len] "+r" (len), [notLast] "+r" (notLast) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [ctx] "r" (ctx), [m] "r" (m), [len] "r" (len), - [notLast] "r" (notLast) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + ctx = (Poly1305*)(size_t)L_asm_args[0]; + m = (const byte*)(size_t)L_asm_args[1]; + len = (word32)(size_t)L_asm_args[2]; + notLast = (int)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } XALIGNED(8) static const word32 L_poly1305_thumb2_clamp[] = { @@ -324,53 +344,68 @@ WC_OMIT_FRAME_POINTER void poly1305_set_key(Poly1305* ctx, const byte* key) register word32* L_poly1305_thumb2_clamp_c __asm__ ("r2") = (word32*)&L_poly1305_thumb2_clamp; #else - register word32* L_poly1305_thumb2_clamp_c = - (word32*)&L_poly1305_thumb2_clamp; + void* L_asm_args[3] = {(void*)(size_t)ctx, (void*)(size_t)key, + (void*)(size_t)&L_poly1305_thumb2_clamp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* Load mask. */ - "MOV r10, %[L_poly1305_thumb2_clamp]\n\t" + "MOV r10, r2\n\t" "LDM r10, {r6, r7, r8, r9}\n\t" /* Load and cache padding. */ - "LDR r2, [%[key], #16]\n\t" - "LDR r3, [%[key], #20]\n\t" - "LDR r4, [%[key], #24]\n\t" - "LDR r5, [%[key], #28]\n\t" - "ADD r10, %[ctx], #36\n\t" + "LDR r2, [r1, #16]\n\t" + "LDR r3, [r1, #20]\n\t" + "LDR r4, [r1, #24]\n\t" + "LDR r5, [r1, #28]\n\t" + "ADD r10, r0, #36\n\t" "STM r10, {r2, r3, r4, r5}\n\t" /* Load, mask and store r. */ - "LDR r2, [%[key]]\n\t" - "LDR r3, [%[key], #4]\n\t" - "LDR r4, [%[key], #8]\n\t" - "LDR r5, [%[key], #12]\n\t" + "LDR r2, [r1]\n\t" + "LDR r3, [r1, #4]\n\t" + "LDR r4, [r1, #8]\n\t" + "LDR r5, [r1, #12]\n\t" "AND r2, r2, r6\n\t" "AND r3, r3, r7\n\t" "AND r4, r4, r8\n\t" "AND r5, r5, r9\n\t" - "ADD r10, %[ctx], #0\n\t" + "ADD r10, r0, #0\n\t" "STM r10, {r2, r3, r4, r5}\n\t" /* h (accumulator) = 0 */ "EOR r6, r6, r6\n\t" "EOR r7, r7, r7\n\t" "EOR r8, r8, r8\n\t" "EOR r9, r9, r9\n\t" - "ADD r10, %[ctx], #16\n\t" + "ADD r10, r0, #16\n\t" "EOR r5, r5, r5\n\t" "STM r10, {r5, r6, r7, r8, r9}\n\t" /* Zero leftover */ - "STR r5, [%[ctx], #52]\n\t" + "STR r5, [r0, #52]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [ctx] "+r" (ctx), [key] "+r" (key), [L_poly1305_thumb2_clamp] "+r" (L_poly1305_thumb2_clamp_c) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [ctx] "r" (ctx), [key] "r" (key), - [L_poly1305_thumb2_clamp] "r" (L_poly1305_thumb2_clamp_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + ctx = (Poly1305*)(size_t)L_asm_args[0]; + key = (const byte*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_NO_VAR_ASSIGN_REG @@ -382,10 +417,18 @@ WC_OMIT_FRAME_POINTER void poly1305_final(Poly1305* ctx, byte* mac) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register Poly1305* ctx __asm__ ("r0") = (Poly1305*)ctx_p; register byte* mac __asm__ ("r1") = (byte*)mac_p; +#else + void* L_asm_args[2] = {(void*)(size_t)ctx, (void*)(size_t)mac + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "ADD r11, %[ctx], #16\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "ADD r11, r0, #16\n\t" "LDM r11, {r2, r3, r4, r5, r6}\n\t" /* Add 5 and check for h larger than p. */ "ADDS r7, r2, #5\n\t" @@ -403,41 +446,51 @@ WC_OMIT_FRAME_POINTER void poly1305_final(Poly1305* ctx, byte* mac) "ADCS r4, r4, #0\n\t" "ADC r5, r5, #0\n\t" /* Add padding */ - "ADD r11, %[ctx], #36\n\t" + "ADD r11, r0, #36\n\t" "LDM r11, {r7, r8, r9, r10}\n\t" "ADDS r2, r2, r7\n\t" "ADCS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" "ADC r5, r5, r10\n\t" /* Store MAC */ - "STR r2, [%[mac]]\n\t" - "STR r3, [%[mac], #4]\n\t" - "STR r4, [%[mac], #8]\n\t" - "STR r5, [%[mac], #12]\n\t" + "STR r2, [r1]\n\t" + "STR r3, [r1, #4]\n\t" + "STR r4, [r1, #8]\n\t" + "STR r5, [r1, #12]\n\t" /* Zero out h. */ "EOR r2, r2, r2\n\t" "EOR r3, r3, r3\n\t" "EOR r4, r4, r4\n\t" "EOR r5, r5, r5\n\t" "EOR r6, r6, r6\n\t" - "ADD r11, %[ctx], #16\n\t" + "ADD r11, r0, #16\n\t" "STM r11, {r2, r3, r4, r5, r6}\n\t" /* Zero out r. */ - "ADD r11, %[ctx], #0\n\t" + "ADD r11, r0, #0\n\t" "STM r11, {r2, r3, r4, r5}\n\t" /* Zero out padding. */ - "ADD r11, %[ctx], #36\n\t" + "ADD r11, r0, #36\n\t" "STM r11, {r2, r3, r4, r5}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [ctx] "+r" (ctx), [mac] "+r" (mac) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [ctx] "r" (ctx), [mac] "r" (mac) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + ctx = (Poly1305*)(size_t)L_asm_args[0]; + mac = (byte*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* HAVE_POLY1305 */ diff --git a/wolfcrypt/src/port/arm/thumb2-sha256-asm_c.c b/wolfcrypt/src/port/arm/thumb2-sha256-asm_c.c index 5f26fbf4f9c..224dcd25ce5 100644 --- a/wolfcrypt/src/port/arm/thumb2-sha256-asm_c.c +++ b/wolfcrypt/src/port/arm/thumb2-sha256-asm_c.c @@ -87,18 +87,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, register word32* L_SHA256_transform_len_k_c __asm__ ("r3") = (word32*)&L_SHA256_transform_len_k; #else - register word32* L_SHA256_transform_len_k_c = - (word32*)&L_SHA256_transform_len_k; + void* L_asm_args[4] = {(void*)(size_t)sha256, (void*)(size_t)data, + (void*)(size_t)len, (void*)(size_t)&L_SHA256_transform_len_k + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0xc0\n\t" - "MOV r12, %[L_SHA256_transform_len_k]\n\t" + "MOV r12, r3\n\t" /* Copy digest to add in at end */ - "LDRD r4, r5, [%[sha256]]\n\t" - "LDRD r6, r7, [%[sha256], #8]\n\t" - "LDRD r8, r9, [%[sha256], #16]\n\t" - "LDRD r10, r11, [%[sha256], #24]\n\t" + "LDRD r4, r5, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" + "LDRD r10, r11, [r0, #24]\n\t" "STRD r4, r5, [sp, #64]\n\t" "STRD r6, r7, [sp, #72]\n\t" "STRD r8, r9, [sp, #80]\n\t" @@ -111,14 +117,14 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_begin_%=:\n\t" #endif /* Load, Reverse and Store W - 64 bytes */ - "LDR r4, [%[data]]\n\t" - "LDR r5, [%[data], #4]\n\t" - "LDR r6, [%[data], #8]\n\t" - "LDR r7, [%[data], #12]\n\t" - "LDR r8, [%[data], #16]\n\t" - "LDR r9, [%[data], #20]\n\t" - "LDR r10, [%[data], #24]\n\t" - "LDR r11, [%[data], #28]\n\t" + "LDR r4, [r1]\n\t" + "LDR r5, [r1, #4]\n\t" + "LDR r6, [r1, #8]\n\t" + "LDR r7, [r1, #12]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r11, [r1, #28]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -131,14 +137,14 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "STRD r6, r7, [sp, #8]\n\t" "STRD r8, r9, [sp, #16]\n\t" "STRD r10, r11, [sp, #24]\n\t" - "LDR r4, [%[data], #32]\n\t" - "LDR r5, [%[data], #36]\n\t" - "LDR r6, [%[data], #40]\n\t" - "LDR r7, [%[data], #44]\n\t" - "LDR r8, [%[data], #48]\n\t" - "LDR r9, [%[data], #52]\n\t" - "LDR r10, [%[data], #56]\n\t" - "LDR r11, [%[data], #60]\n\t" + "LDR r4, [r1, #32]\n\t" + "LDR r5, [r1, #36]\n\t" + "LDR r6, [r1, #40]\n\t" + "LDR r7, [r1, #44]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r1, #52]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r11, [r1, #60]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -151,8 +157,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "STRD r6, r7, [sp, #40]\n\t" "STRD r8, r9, [sp, #48]\n\t" "STRD r10, r11, [sp, #56]\n\t" - "LDR r11, [%[sha256], #4]\n\t" - "LDR r4, [%[sha256], #8]\n\t" + "LDR r11, [r0, #4]\n\t" + "LDR r4, [r0, #8]\n\t" "EOR r11, r11, r4\n\t" #ifndef WOLFSSL_ARMASM_SHA256_SMALL "MOV r3, #3\n\t" @@ -164,10 +170,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_start_fast_%=:\n\t" #endif /* Round 0 */ - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r9, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r9, [r0, #28]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -180,10 +186,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r8, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r8, [r0, #12]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -193,8 +199,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #12]\n\t" - "STR r9, [%[sha256], #28]\n\t" + "STR r8, [r0, #12]\n\t" + "STR r9, [r0, #28]\n\t" /* Calc new W[0] */ "LDR r6, [sp, #56]\n\t" "LDR r7, [sp, #36]\n\t" @@ -211,10 +217,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp]\n\t" /* Round 1 */ - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r9, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r9, [r0, #24]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -227,10 +233,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #4]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r8, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -240,8 +246,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #8]\n\t" - "STR r9, [%[sha256], #24]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #24]\n\t" /* Calc new W[1] */ "LDR r6, [sp, #60]\n\t" "LDR r7, [sp, #40]\n\t" @@ -258,10 +264,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #4]\n\t" /* Round 2 */ - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r9, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r9, [r0, #20]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -274,10 +280,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #8]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r8, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r8, [r0, #4]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -287,8 +293,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #4]\n\t" - "STR r9, [%[sha256], #20]\n\t" + "STR r8, [r0, #4]\n\t" + "STR r9, [r0, #20]\n\t" /* Calc new W[2] */ "LDR r6, [sp]\n\t" "LDR r7, [sp, #44]\n\t" @@ -305,10 +311,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #8]\n\t" /* Round 3 */ - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r9, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r9, [r0, #16]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -321,10 +327,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #12]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r8, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r8, [r0]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -334,8 +340,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256]]\n\t" - "STR r9, [%[sha256], #16]\n\t" + "STR r8, [r0]\n\t" + "STR r9, [r0, #16]\n\t" /* Calc new W[3] */ "LDR r6, [sp, #4]\n\t" "LDR r7, [sp, #48]\n\t" @@ -352,10 +358,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #12]\n\t" /* Round 4 */ - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r9, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -368,10 +374,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #16]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r8, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r8, [r0, #28]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -381,8 +387,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #28]\n\t" - "STR r9, [%[sha256], #12]\n\t" + "STR r8, [r0, #28]\n\t" + "STR r9, [r0, #12]\n\t" /* Calc new W[4] */ "LDR r6, [sp, #8]\n\t" "LDR r7, [sp, #52]\n\t" @@ -399,10 +405,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #16]\n\t" /* Round 5 */ - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r9, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r9, [r0, #8]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -415,10 +421,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #20]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r8, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r8, [r0, #24]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -428,8 +434,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #24]\n\t" - "STR r9, [%[sha256], #8]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #8]\n\t" /* Calc new W[5] */ "LDR r6, [sp, #12]\n\t" "LDR r7, [sp, #56]\n\t" @@ -446,10 +452,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #20]\n\t" /* Round 6 */ - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r9, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r9, [r0, #4]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -462,10 +468,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #24]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r8, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r8, [r0, #20]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -475,8 +481,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #20]\n\t" - "STR r9, [%[sha256], #4]\n\t" + "STR r8, [r0, #20]\n\t" + "STR r9, [r0, #4]\n\t" /* Calc new W[6] */ "LDR r6, [sp, #16]\n\t" "LDR r7, [sp, #60]\n\t" @@ -493,10 +499,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #24]\n\t" /* Round 7 */ - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r9, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r9, [r0]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -509,10 +515,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #28]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r8, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r8, [r0, #16]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -522,8 +528,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #16]\n\t" - "STR r9, [%[sha256]]\n\t" + "STR r8, [r0, #16]\n\t" + "STR r9, [r0]\n\t" /* Calc new W[7] */ "LDR r6, [sp, #20]\n\t" "LDR r7, [sp]\n\t" @@ -540,10 +546,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #28]\n\t" /* Round 8 */ - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r9, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r9, [r0, #28]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -556,10 +562,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #32]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r8, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r8, [r0, #12]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -569,8 +575,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #12]\n\t" - "STR r9, [%[sha256], #28]\n\t" + "STR r8, [r0, #12]\n\t" + "STR r9, [r0, #28]\n\t" /* Calc new W[8] */ "LDR r6, [sp, #24]\n\t" "LDR r7, [sp, #4]\n\t" @@ -587,10 +593,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #32]\n\t" /* Round 9 */ - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r9, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r9, [r0, #24]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -603,10 +609,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #36]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r8, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -616,8 +622,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #8]\n\t" - "STR r9, [%[sha256], #24]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #24]\n\t" /* Calc new W[9] */ "LDR r6, [sp, #28]\n\t" "LDR r7, [sp, #8]\n\t" @@ -634,10 +640,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #36]\n\t" /* Round 10 */ - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r9, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r9, [r0, #20]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -650,10 +656,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #40]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r8, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r8, [r0, #4]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -663,8 +669,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #4]\n\t" - "STR r9, [%[sha256], #20]\n\t" + "STR r8, [r0, #4]\n\t" + "STR r9, [r0, #20]\n\t" /* Calc new W[10] */ "LDR r6, [sp, #32]\n\t" "LDR r7, [sp, #12]\n\t" @@ -681,10 +687,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #40]\n\t" /* Round 11 */ - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r9, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r9, [r0, #16]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -697,10 +703,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #44]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r8, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r8, [r0]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -710,8 +716,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256]]\n\t" - "STR r9, [%[sha256], #16]\n\t" + "STR r8, [r0]\n\t" + "STR r9, [r0, #16]\n\t" /* Calc new W[11] */ "LDR r6, [sp, #36]\n\t" "LDR r7, [sp, #16]\n\t" @@ -728,10 +734,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #44]\n\t" /* Round 12 */ - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r9, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -744,10 +750,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #48]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r8, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r8, [r0, #28]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -757,8 +763,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #28]\n\t" - "STR r9, [%[sha256], #12]\n\t" + "STR r8, [r0, #28]\n\t" + "STR r9, [r0, #12]\n\t" /* Calc new W[12] */ "LDR r6, [sp, #40]\n\t" "LDR r7, [sp, #20]\n\t" @@ -775,10 +781,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #48]\n\t" /* Round 13 */ - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r9, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r9, [r0, #8]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -791,10 +797,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #52]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r8, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r8, [r0, #24]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -804,8 +810,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #24]\n\t" - "STR r9, [%[sha256], #8]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #8]\n\t" /* Calc new W[13] */ "LDR r6, [sp, #44]\n\t" "LDR r7, [sp, #24]\n\t" @@ -822,10 +828,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #52]\n\t" /* Round 14 */ - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r9, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r9, [r0, #4]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -838,10 +844,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #56]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r8, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r8, [r0, #20]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -851,8 +857,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #20]\n\t" - "STR r9, [%[sha256], #4]\n\t" + "STR r8, [r0, #20]\n\t" + "STR r9, [r0, #4]\n\t" /* Calc new W[14] */ "LDR r6, [sp, #48]\n\t" "LDR r7, [sp, #28]\n\t" @@ -869,10 +875,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r9, r9, r4\n\t" "STR r9, [sp, #56]\n\t" /* Round 15 */ - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r9, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r9, [r0]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -885,10 +891,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #60]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r8, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r8, [r0, #16]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -898,8 +904,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #16]\n\t" - "STR r9, [%[sha256]]\n\t" + "STR r8, [r0, #16]\n\t" + "STR r9, [r0]\n\t" /* Calc new W[15] */ "LDR r6, [sp, #52]\n\t" "LDR r7, [sp, #32]\n\t" @@ -925,10 +931,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "BNE.W L_SHA256_transform_len_start_fast_%=\n\t" #endif /* Round 0 */ - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r9, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r9, [r0, #28]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -941,10 +947,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r8, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r8, [r0, #12]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -954,13 +960,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #12]\n\t" - "STR r9, [%[sha256], #28]\n\t" + "STR r8, [r0, #12]\n\t" + "STR r9, [r0, #28]\n\t" /* Round 1 */ - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r9, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r9, [r0, #24]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -973,10 +979,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #4]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r8, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -986,13 +992,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #8]\n\t" - "STR r9, [%[sha256], #24]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #24]\n\t" /* Round 2 */ - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r9, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r9, [r0, #20]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1005,10 +1011,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #8]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r8, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r8, [r0, #4]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1018,13 +1024,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #4]\n\t" - "STR r9, [%[sha256], #20]\n\t" + "STR r8, [r0, #4]\n\t" + "STR r9, [r0, #20]\n\t" /* Round 3 */ - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r9, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r9, [r0, #16]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1037,10 +1043,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #12]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r8, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r8, [r0]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1050,13 +1056,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256]]\n\t" - "STR r9, [%[sha256], #16]\n\t" + "STR r8, [r0]\n\t" + "STR r9, [r0, #16]\n\t" /* Round 4 */ - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r9, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1069,10 +1075,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #16]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r8, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r8, [r0, #28]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1082,13 +1088,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #28]\n\t" - "STR r9, [%[sha256], #12]\n\t" + "STR r8, [r0, #28]\n\t" + "STR r9, [r0, #12]\n\t" /* Round 5 */ - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r9, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r9, [r0, #8]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1101,10 +1107,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #20]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r8, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r8, [r0, #24]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1114,13 +1120,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #24]\n\t" - "STR r9, [%[sha256], #8]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #8]\n\t" /* Round 6 */ - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r9, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r9, [r0, #4]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1133,10 +1139,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #24]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r8, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r8, [r0, #20]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1146,13 +1152,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #20]\n\t" - "STR r9, [%[sha256], #4]\n\t" + "STR r8, [r0, #20]\n\t" + "STR r9, [r0, #4]\n\t" /* Round 7 */ - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r9, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r9, [r0]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1165,10 +1171,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #28]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r8, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r8, [r0, #16]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1178,13 +1184,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #16]\n\t" - "STR r9, [%[sha256]]\n\t" + "STR r8, [r0, #16]\n\t" + "STR r9, [r0]\n\t" /* Round 8 */ - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r9, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r9, [r0, #28]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1197,10 +1203,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #32]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r8, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r8, [r0, #12]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1210,13 +1216,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #12]\n\t" - "STR r9, [%[sha256], #28]\n\t" + "STR r8, [r0, #12]\n\t" + "STR r9, [r0, #28]\n\t" /* Round 9 */ - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r9, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r9, [r0, #24]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1229,10 +1235,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #36]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r8, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1242,13 +1248,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #8]\n\t" - "STR r9, [%[sha256], #24]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #24]\n\t" /* Round 10 */ - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r9, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r9, [r0, #20]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1261,10 +1267,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #40]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r8, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r8, [r0, #4]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1274,13 +1280,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #4]\n\t" - "STR r9, [%[sha256], #20]\n\t" + "STR r8, [r0, #4]\n\t" + "STR r9, [r0, #20]\n\t" /* Round 11 */ - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r9, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r9, [r0, #16]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1293,10 +1299,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #44]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r8, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r8, [r0]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1306,13 +1312,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256]]\n\t" - "STR r9, [%[sha256], #16]\n\t" + "STR r8, [r0]\n\t" + "STR r9, [r0, #16]\n\t" /* Round 12 */ - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r9, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1325,10 +1331,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #48]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r8, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r8, [r0, #28]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1338,13 +1344,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #28]\n\t" - "STR r9, [%[sha256], #12]\n\t" + "STR r8, [r0, #28]\n\t" + "STR r9, [r0, #12]\n\t" /* Round 13 */ - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r9, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r9, [r0, #8]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1357,10 +1363,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #52]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r8, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r8, [r0, #24]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1370,13 +1376,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #24]\n\t" - "STR r9, [%[sha256], #8]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #8]\n\t" /* Round 14 */ - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r9, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r9, [r0, #4]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1389,10 +1395,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #56]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r8, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r8, [r0, #20]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1402,13 +1408,13 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #20]\n\t" - "STR r9, [%[sha256], #4]\n\t" + "STR r8, [r0, #20]\n\t" + "STR r9, [r0, #4]\n\t" /* Round 15 */ - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r9, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r9, [r0]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1421,10 +1427,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #60]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r8, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r8, [r0, #16]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1434,8 +1440,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #16]\n\t" - "STR r9, [%[sha256]]\n\t" + "STR r8, [r0, #16]\n\t" + "STR r9, [r0]\n\t" #else "MOV r3, #4\n\t" /* Start of 16 rounds */ @@ -1447,10 +1453,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, #endif "SUB r3, r3, #1\n\t" /* Round 0 */ - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r9, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r9, [r0, #28]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1463,10 +1469,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r8, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r8, [r0, #12]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1476,8 +1482,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #12]\n\t" - "STR r9, [%[sha256], #28]\n\t" + "STR r8, [r0, #12]\n\t" + "STR r9, [r0, #28]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_0_%=\n\t" @@ -1508,10 +1514,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_0_%=:\n\t" #endif /* Round 1 */ - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r9, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r9, [r0, #24]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1524,10 +1530,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #4]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r8, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1537,8 +1543,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #8]\n\t" - "STR r9, [%[sha256], #24]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #24]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_1_%=\n\t" @@ -1569,10 +1575,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_1_%=:\n\t" #endif /* Round 2 */ - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r9, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r9, [r0, #20]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1585,10 +1591,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #8]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r8, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r8, [r0, #4]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1598,8 +1604,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #4]\n\t" - "STR r9, [%[sha256], #20]\n\t" + "STR r8, [r0, #4]\n\t" + "STR r9, [r0, #20]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_2_%=\n\t" @@ -1630,10 +1636,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_2_%=:\n\t" #endif /* Round 3 */ - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r9, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r9, [r0, #16]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1646,10 +1652,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #12]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r8, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r8, [r0]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1659,8 +1665,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256]]\n\t" - "STR r9, [%[sha256], #16]\n\t" + "STR r8, [r0]\n\t" + "STR r9, [r0, #16]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_3_%=\n\t" @@ -1691,10 +1697,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_3_%=:\n\t" #endif /* Round 4 */ - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r9, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1707,10 +1713,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #16]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r8, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r8, [r0, #28]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1720,8 +1726,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #28]\n\t" - "STR r9, [%[sha256], #12]\n\t" + "STR r8, [r0, #28]\n\t" + "STR r9, [r0, #12]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_4_%=\n\t" @@ -1752,10 +1758,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_4_%=:\n\t" #endif /* Round 5 */ - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r9, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r9, [r0, #8]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1768,10 +1774,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #20]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r8, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r8, [r0, #24]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1781,8 +1787,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #24]\n\t" - "STR r9, [%[sha256], #8]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #8]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_5_%=\n\t" @@ -1813,10 +1819,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_5_%=:\n\t" #endif /* Round 6 */ - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r9, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r9, [r0, #4]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1829,10 +1835,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #24]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r8, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r8, [r0, #20]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1842,8 +1848,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #20]\n\t" - "STR r9, [%[sha256], #4]\n\t" + "STR r8, [r0, #20]\n\t" + "STR r9, [r0, #4]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_6_%=\n\t" @@ -1874,10 +1880,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_6_%=:\n\t" #endif /* Round 7 */ - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r9, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r9, [r0]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1890,10 +1896,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #28]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r8, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r8, [r0, #16]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1903,8 +1909,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #16]\n\t" - "STR r9, [%[sha256]]\n\t" + "STR r8, [r0, #16]\n\t" + "STR r9, [r0]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_7_%=\n\t" @@ -1935,10 +1941,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_7_%=:\n\t" #endif /* Round 8 */ - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r9, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r9, [r0, #28]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -1951,10 +1957,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #32]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r8, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r8, [r0, #12]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -1964,8 +1970,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #12]\n\t" - "STR r9, [%[sha256], #28]\n\t" + "STR r8, [r0, #12]\n\t" + "STR r9, [r0, #28]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_8_%=\n\t" @@ -1996,10 +2002,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_8_%=:\n\t" #endif /* Round 9 */ - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r9, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r9, [r0, #24]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -2012,10 +2018,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #36]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r8, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -2025,8 +2031,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #8]\n\t" - "STR r9, [%[sha256], #24]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #24]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_9_%=\n\t" @@ -2057,10 +2063,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_9_%=:\n\t" #endif /* Round 10 */ - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r9, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r9, [r0, #20]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -2073,10 +2079,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #40]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r8, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r8, [r0, #4]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -2086,8 +2092,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #4]\n\t" - "STR r9, [%[sha256], #20]\n\t" + "STR r8, [r0, #4]\n\t" + "STR r9, [r0, #20]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_10_%=\n\t" @@ -2118,10 +2124,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_10_%=:\n\t" #endif /* Round 11 */ - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r9, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r9, [r0, #16]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -2134,10 +2140,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #44]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r8, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r8, [r0]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -2147,8 +2153,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256]]\n\t" - "STR r9, [%[sha256], #16]\n\t" + "STR r8, [r0]\n\t" + "STR r9, [r0, #16]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_11_%=\n\t" @@ -2179,10 +2185,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_11_%=:\n\t" #endif /* Round 12 */ - "LDR r5, [%[sha256]]\n\t" - "LDR r6, [%[sha256], #4]\n\t" - "LDR r7, [%[sha256], #8]\n\t" - "LDR r9, [%[sha256], #12]\n\t" + "LDR r5, [r0]\n\t" + "LDR r6, [r0, #4]\n\t" + "LDR r7, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -2195,10 +2201,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #48]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #16]\n\t" - "LDR r6, [%[sha256], #20]\n\t" - "LDR r7, [%[sha256], #24]\n\t" - "LDR r8, [%[sha256], #28]\n\t" + "LDR r5, [r0, #16]\n\t" + "LDR r6, [r0, #20]\n\t" + "LDR r7, [r0, #24]\n\t" + "LDR r8, [r0, #28]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -2208,8 +2214,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #28]\n\t" - "STR r9, [%[sha256], #12]\n\t" + "STR r8, [r0, #28]\n\t" + "STR r9, [r0, #12]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_12_%=\n\t" @@ -2240,10 +2246,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_12_%=:\n\t" #endif /* Round 13 */ - "LDR r5, [%[sha256], #28]\n\t" - "LDR r6, [%[sha256]]\n\t" - "LDR r7, [%[sha256], #4]\n\t" - "LDR r9, [%[sha256], #8]\n\t" + "LDR r5, [r0, #28]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r9, [r0, #8]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -2256,10 +2262,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #52]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #12]\n\t" - "LDR r6, [%[sha256], #16]\n\t" - "LDR r7, [%[sha256], #20]\n\t" - "LDR r8, [%[sha256], #24]\n\t" + "LDR r5, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" + "LDR r8, [r0, #24]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -2269,8 +2275,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #24]\n\t" - "STR r9, [%[sha256], #8]\n\t" + "STR r8, [r0, #24]\n\t" + "STR r9, [r0, #8]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_13_%=\n\t" @@ -2301,10 +2307,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_13_%=:\n\t" #endif /* Round 14 */ - "LDR r5, [%[sha256], #24]\n\t" - "LDR r6, [%[sha256], #28]\n\t" - "LDR r7, [%[sha256]]\n\t" - "LDR r9, [%[sha256], #4]\n\t" + "LDR r5, [r0, #24]\n\t" + "LDR r6, [r0, #28]\n\t" + "LDR r7, [r0]\n\t" + "LDR r9, [r0, #4]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -2317,10 +2323,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #56]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #8]\n\t" - "LDR r6, [%[sha256], #12]\n\t" - "LDR r7, [%[sha256], #16]\n\t" - "LDR r8, [%[sha256], #20]\n\t" + "LDR r5, [r0, #8]\n\t" + "LDR r6, [r0, #12]\n\t" + "LDR r7, [r0, #16]\n\t" + "LDR r8, [r0, #20]\n\t" "ROR r4, r5, #2\n\t" "EOR r10, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -2330,8 +2336,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r11\n\t" - "STR r8, [%[sha256], #20]\n\t" - "STR r9, [%[sha256], #4]\n\t" + "STR r8, [r0, #20]\n\t" + "STR r9, [r0, #4]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_14_%=\n\t" @@ -2362,10 +2368,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "L_SHA256_transform_len_blk_end_14_%=:\n\t" #endif /* Round 15 */ - "LDR r5, [%[sha256], #20]\n\t" - "LDR r6, [%[sha256], #24]\n\t" - "LDR r7, [%[sha256], #28]\n\t" - "LDR r9, [%[sha256]]\n\t" + "LDR r5, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" + "LDR r9, [r0]\n\t" "ROR r4, r5, #6\n\t" "EOR r6, r6, r7\n\t" "EOR r4, r4, r5, ROR #11\n\t" @@ -2378,10 +2384,10 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "LDR r6, [r12, #60]\n\t" "ADD r9, r9, r5\n\t" "ADD r9, r9, r6\n\t" - "LDR r5, [%[sha256], #4]\n\t" - "LDR r6, [%[sha256], #8]\n\t" - "LDR r7, [%[sha256], #12]\n\t" - "LDR r8, [%[sha256], #16]\n\t" + "LDR r5, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" + "LDR r8, [r0, #16]\n\t" "ROR r4, r5, #2\n\t" "EOR r11, r5, r6\n\t" "EOR r4, r4, r5, ROR #13\n\t" @@ -2391,8 +2397,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "ADD r8, r8, r9\n\t" "ADD r9, r9, r4\n\t" "ADD r9, r9, r10\n\t" - "STR r8, [%[sha256], #16]\n\t" - "STR r9, [%[sha256]]\n\t" + "STR r8, [r0, #16]\n\t" + "STR r9, [r0]\n\t" "CMP r3, #0\n\t" #if defined(__GNUC__) "BEQ L_SHA256_transform_len_blk_end_15_%=\n\t" @@ -2433,37 +2439,37 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, #endif #endif /* !WOLFSSL_ARMASM_SHA256_SMALL */ /* Add in digest from start */ - "LDRD r4, r5, [%[sha256]]\n\t" - "LDRD r6, r7, [%[sha256], #8]\n\t" + "LDRD r4, r5, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" "LDRD r8, r9, [sp, #64]\n\t" "LDRD r10, r11, [sp, #72]\n\t" "ADD r4, r4, r8\n\t" "ADD r5, r5, r9\n\t" "ADD r6, r6, r10\n\t" "ADD r7, r7, r11\n\t" - "STRD r4, r5, [%[sha256]]\n\t" - "STRD r6, r7, [%[sha256], #8]\n\t" + "STRD r4, r5, [r0]\n\t" + "STRD r6, r7, [r0, #8]\n\t" "STRD r4, r5, [sp, #64]\n\t" "STRD r6, r7, [sp, #72]\n\t" - "LDRD r4, r5, [%[sha256], #16]\n\t" - "LDRD r6, r7, [%[sha256], #24]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" "LDRD r8, r9, [sp, #80]\n\t" "LDRD r10, r11, [sp, #88]\n\t" "ADD r4, r4, r8\n\t" "ADD r5, r5, r9\n\t" "ADD r6, r6, r10\n\t" "ADD r7, r7, r11\n\t" - "STRD r4, r5, [%[sha256], #16]\n\t" - "STRD r6, r7, [%[sha256], #24]\n\t" + "STRD r4, r5, [r0, #16]\n\t" + "STRD r6, r7, [r0, #24]\n\t" "STRD r4, r5, [sp, #80]\n\t" "STRD r6, r7, [sp, #88]\n\t" - "SUBS %[len], %[len], #0x40\n\t" + "SUBS r2, r2, #0x40\n\t" #ifndef WOLFSSL_ARMASM_SHA256_SMALL "SUB r12, r12, #0xc0\n\t" #else "SUB r12, r12, #0x100\n\t" #endif /* !WOLFSSL_ARMASM_SHA256_SMALL */ - "ADD %[data], %[data], #0x40\n\t" + "ADD r1, r1, #0x40\n\t" #if defined(__GNUC__) "BNE L_SHA256_transform_len_begin_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2472,18 +2478,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha256_Len_base(wc_Sha256* sha256, "BNE.W L_SHA256_transform_len_begin_%=\n\t" #endif "ADD sp, sp, #0xc0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [sha256] "+r" (sha256), [data] "+r" (data), [len] "+r" (len), [L_SHA256_transform_len_k] "+r" (L_SHA256_transform_len_k_c) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [sha256] "r" (sha256), [data] "r" (data), [len] "r" (len), - [L_SHA256_transform_len_k] "r" (L_SHA256_transform_len_k_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + sha256 = (wc_Sha256*)(size_t)L_asm_args[0]; + data = (const byte*)(size_t)L_asm_args[1]; + len = (word32)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_ARMASM_NO_NEON */ diff --git a/wolfcrypt/src/port/arm/thumb2-sha3-asm_c.c b/wolfcrypt/src/port/arm/thumb2-sha3-asm_c.c index 85ea9b4e2fb..595cdfec707 100644 --- a/wolfcrypt/src/port/arm/thumb2-sha3-asm_c.c +++ b/wolfcrypt/src/port/arm/thumb2-sha3-asm_c.c @@ -76,12 +76,18 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) register word64* L_sha3_thumb2_rt_c __asm__ ("r1") = (word64*)&L_sha3_thumb2_rt; #else - register word64* L_sha3_thumb2_rt_c = (word64*)&L_sha3_thumb2_rt; + void* L_asm_args[2] = {(void*)(size_t)state, + (void*)(size_t)&L_sha3_thumb2_rt + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0xcc\n\t" - "MOV r1, %[L_sha3_thumb2_rt]\n\t" "MOV r2, #12\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -92,12 +98,12 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "STR r2, [sp, #200]\n\t" /* Round even */ /* Calc b[4] */ - "LDRD r4, r5, [%[state], #32]\n\t" - "LDRD r6, r7, [%[state], #72]\n\t" - "LDRD r8, r9, [%[state], #112]\n\t" - "LDRD r10, r11, [%[state], #152]\n\t" - "LDR r12, [%[state], #192]\n\t" - "LDR lr, [%[state], #196]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #72]\n\t" + "LDRD r8, r9, [r0, #112]\n\t" + "LDRD r10, r11, [r0, #152]\n\t" + "LDR r12, [r0, #192]\n\t" + "LDR lr, [r0, #196]\n\t" "EOR r2, r4, r6\n\t" "EOR r3, r5, r7\n\t" "EOR r2, r2, r8\n\t" @@ -108,12 +114,12 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r3, r3, lr\n\t" "STRD r2, r3, [sp, #32]\n\t" /* Calc b[1] */ - "LDRD r4, r5, [%[state], #8]\n\t" - "LDRD r6, r7, [%[state], #48]\n\t" - "LDRD r8, r9, [%[state], #88]\n\t" - "LDRD r10, r11, [%[state], #128]\n\t" - "LDR r12, [%[state], #168]\n\t" - "LDR lr, [%[state], #172]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" + "LDRD r8, r9, [r0, #88]\n\t" + "LDRD r10, r11, [r0, #128]\n\t" + "LDR r12, [r0, #168]\n\t" + "LDR lr, [r0, #172]\n\t" "EOR r4, r4, r6\n\t" "EOR r5, r5, r7\n\t" "EOR r4, r4, r8\n\t" @@ -129,10 +135,10 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r2, r2, r4, LSL #1\n\t" "EOR r3, r3, r5, LSL #1\n\t" /* Calc b[0] and XOR t[0] into s[x*5+0] */ - "LDRD r4, r5, [%[state]]\n\t" - "LDRD r6, r7, [%[state], #40]\n\t" - "LDRD r8, r9, [%[state], #80]\n\t" - "LDRD r10, r11, [%[state], #120]\n\t" + "LDRD r4, r5, [r0]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" + "LDRD r8, r9, [r0, #80]\n\t" + "LDRD r10, r11, [r0, #120]\n\t" "EOR r12, r4, r6\n\t" "EOR lr, r5, r7\n\t" "EOR r12, r12, r8\n\t" @@ -147,25 +153,25 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r9, r9, r3\n\t" "EOR r10, r10, r2\n\t" "EOR r11, r11, r3\n\t" - "STRD r4, r5, [%[state]]\n\t" - "STRD r6, r7, [%[state], #40]\n\t" - "STRD r8, r9, [%[state], #80]\n\t" - "STRD r10, r11, [%[state], #120]\n\t" - "LDRD r10, r11, [%[state], #160]\n\t" + "STRD r4, r5, [r0]\n\t" + "STRD r6, r7, [r0, #40]\n\t" + "STRD r8, r9, [r0, #80]\n\t" + "STRD r10, r11, [r0, #120]\n\t" + "LDRD r10, r11, [r0, #160]\n\t" "EOR r12, r12, r10\n\t" "EOR lr, lr, r11\n\t" "EOR r10, r10, r2\n\t" "EOR r11, r11, r3\n\t" - "STRD r10, r11, [%[state], #160]\n\t" + "STRD r10, r11, [r0, #160]\n\t" "STR r12, [sp]\n\t" "STR lr, [sp, #4]\n\t" /* Calc b[3] */ - "LDRD r4, r5, [%[state], #24]\n\t" - "LDRD r6, r7, [%[state], #64]\n\t" - "LDRD r8, r9, [%[state], #104]\n\t" - "LDRD r10, r11, [%[state], #144]\n\t" - "LDR r12, [%[state], #184]\n\t" - "LDR lr, [%[state], #188]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" + "LDRD r6, r7, [r0, #64]\n\t" + "LDRD r8, r9, [r0, #104]\n\t" + "LDRD r10, r11, [r0, #144]\n\t" + "LDR r12, [r0, #184]\n\t" + "LDR lr, [r0, #188]\n\t" "EOR r4, r4, r6\n\t" "EOR r5, r5, r7\n\t" "EOR r4, r4, r8\n\t" @@ -182,10 +188,10 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r2, r2, r4, LSL #1\n\t" "EOR r3, r3, r5, LSL #1\n\t" /* Calc b[2] and XOR t[2] into s[x*5+2] */ - "LDRD r4, r5, [%[state], #16]\n\t" - "LDRD r6, r7, [%[state], #56]\n\t" - "LDRD r8, r9, [%[state], #96]\n\t" - "LDRD r10, r11, [%[state], #136]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" + "LDRD r8, r9, [r0, #96]\n\t" + "LDRD r10, r11, [r0, #136]\n\t" "EOR r12, r4, r6\n\t" "EOR lr, r5, r7\n\t" "EOR r12, r12, r8\n\t" @@ -200,16 +206,16 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r9, r9, r3\n\t" "EOR r10, r10, r2\n\t" "EOR r11, r11, r3\n\t" - "STRD r4, r5, [%[state], #16]\n\t" - "STRD r6, r7, [%[state], #56]\n\t" - "STRD r8, r9, [%[state], #96]\n\t" - "STRD r10, r11, [%[state], #136]\n\t" - "LDRD r10, r11, [%[state], #176]\n\t" + "STRD r4, r5, [r0, #16]\n\t" + "STRD r6, r7, [r0, #56]\n\t" + "STRD r8, r9, [r0, #96]\n\t" + "STRD r10, r11, [r0, #136]\n\t" + "LDRD r10, r11, [r0, #176]\n\t" "EOR r12, r12, r10\n\t" "EOR lr, lr, r11\n\t" "EOR r10, r10, r2\n\t" "EOR r11, r11, r3\n\t" - "STRD r10, r11, [%[state], #176]\n\t" + "STRD r10, r11, [r0, #176]\n\t" "STR r12, [sp, #16]\n\t" "STR lr, [sp, #20]\n\t" /* Calc t[1] */ @@ -219,12 +225,12 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r2, r2, r12, LSL #1\n\t" "EOR r3, r3, lr, LSL #1\n\t" /* XOR t[1] into s[x*5+1] */ - "LDRD r4, r5, [%[state], #8]\n\t" - "LDRD r6, r7, [%[state], #48]\n\t" - "LDRD r8, r9, [%[state], #88]\n\t" - "LDRD r10, r11, [%[state], #128]\n\t" - "LDR r12, [%[state], #168]\n\t" - "LDR lr, [%[state], #172]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" + "LDRD r8, r9, [r0, #88]\n\t" + "LDRD r10, r11, [r0, #128]\n\t" + "LDR r12, [r0, #168]\n\t" + "LDR lr, [r0, #172]\n\t" "EOR r4, r4, r2\n\t" "EOR r5, r5, r3\n\t" "EOR r6, r6, r2\n\t" @@ -235,12 +241,12 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r11, r11, r3\n\t" "EOR r12, r12, r2\n\t" "EOR lr, lr, r3\n\t" - "STRD r4, r5, [%[state], #8]\n\t" - "STRD r6, r7, [%[state], #48]\n\t" - "STRD r8, r9, [%[state], #88]\n\t" - "STRD r10, r11, [%[state], #128]\n\t" - "STR r12, [%[state], #168]\n\t" - "STR lr, [%[state], #172]\n\t" + "STRD r4, r5, [r0, #8]\n\t" + "STRD r6, r7, [r0, #48]\n\t" + "STRD r8, r9, [r0, #88]\n\t" + "STRD r10, r11, [r0, #128]\n\t" + "STR r12, [r0, #168]\n\t" + "STR lr, [r0, #172]\n\t" /* Calc t[3] */ "LDRD r2, r3, [sp, #16]\n\t" "LDRD r4, r5, [sp, #32]\n\t" @@ -249,12 +255,12 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r2, r2, r4, LSL #1\n\t" "EOR r3, r3, r5, LSL #1\n\t" /* XOR t[3] into s[x*5+3] */ - "LDRD r4, r5, [%[state], #24]\n\t" - "LDRD r6, r7, [%[state], #64]\n\t" - "LDRD r8, r9, [%[state], #104]\n\t" - "LDRD r10, r11, [%[state], #144]\n\t" - "LDR r12, [%[state], #184]\n\t" - "LDR lr, [%[state], #188]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" + "LDRD r6, r7, [r0, #64]\n\t" + "LDRD r8, r9, [r0, #104]\n\t" + "LDRD r10, r11, [r0, #144]\n\t" + "LDR r12, [r0, #184]\n\t" + "LDR lr, [r0, #188]\n\t" "EOR r4, r4, r2\n\t" "EOR r5, r5, r3\n\t" "EOR r6, r6, r2\n\t" @@ -265,12 +271,12 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r11, r11, r3\n\t" "EOR r12, r12, r2\n\t" "EOR lr, lr, r3\n\t" - "STRD r4, r5, [%[state], #24]\n\t" - "STRD r6, r7, [%[state], #64]\n\t" - "STRD r8, r9, [%[state], #104]\n\t" - "STRD r10, r11, [%[state], #144]\n\t" - "STR r12, [%[state], #184]\n\t" - "STR lr, [%[state], #188]\n\t" + "STRD r4, r5, [r0, #24]\n\t" + "STRD r6, r7, [r0, #64]\n\t" + "STRD r8, r9, [r0, #104]\n\t" + "STRD r10, r11, [r0, #144]\n\t" + "STR r12, [r0, #184]\n\t" + "STR lr, [r0, #188]\n\t" /* Calc t[4] */ "LDRD r2, r3, [sp, #24]\n\t" "LDRD r4, r5, [sp]\n\t" @@ -279,12 +285,12 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r2, r2, r4, LSL #1\n\t" "EOR r3, r3, r5, LSL #1\n\t" /* XOR t[4] into s[x*5+4] */ - "LDRD r4, r5, [%[state], #32]\n\t" - "LDRD r6, r7, [%[state], #72]\n\t" - "LDRD r8, r9, [%[state], #112]\n\t" - "LDRD r10, r11, [%[state], #152]\n\t" - "LDR r12, [%[state], #192]\n\t" - "LDR lr, [%[state], #196]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #72]\n\t" + "LDRD r8, r9, [r0, #112]\n\t" + "LDRD r10, r11, [r0, #152]\n\t" + "LDR r12, [r0, #192]\n\t" + "LDR lr, [r0, #196]\n\t" "EOR r4, r4, r2\n\t" "EOR r5, r5, r3\n\t" "EOR r6, r6, r2\n\t" @@ -295,19 +301,19 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r11, r11, r3\n\t" "EOR r12, r12, r2\n\t" "EOR lr, lr, r3\n\t" - "STRD r4, r5, [%[state], #32]\n\t" - "STRD r6, r7, [%[state], #72]\n\t" - "STRD r8, r9, [%[state], #112]\n\t" - "STRD r10, r11, [%[state], #152]\n\t" - "STR r12, [%[state], #192]\n\t" - "STR lr, [%[state], #196]\n\t" + "STRD r4, r5, [r0, #32]\n\t" + "STRD r6, r7, [r0, #72]\n\t" + "STRD r8, r9, [r0, #112]\n\t" + "STRD r10, r11, [r0, #152]\n\t" + "STR r12, [r0, #192]\n\t" + "STR lr, [r0, #196]\n\t" /* Row Mix */ /* Row 0 */ - "LDRD r2, r3, [%[state]]\n\t" - "LDRD r4, r5, [%[state], #48]\n\t" - "LDRD r6, r7, [%[state], #96]\n\t" - "LDRD r8, r9, [%[state], #144]\n\t" - "LDRD r10, r11, [%[state], #192]\n\t" + "LDRD r2, r3, [r0]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" + "LDRD r6, r7, [r0, #96]\n\t" + "LDRD r8, r9, [r0, #144]\n\t" + "LDRD r10, r11, [r0, #192]\n\t" /* s[1] <<< 44 */ "MOV lr, r4\n\t" "LSR r12, r5, #20\n\t" @@ -367,11 +373,11 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "STR r12, [sp]\n\t" "STR lr, [sp, #4]\n\t" /* Row 1 */ - "LDRD r2, r3, [%[state], #24]\n\t" - "LDRD r4, r5, [%[state], #72]\n\t" - "LDRD r6, r7, [%[state], #80]\n\t" - "LDRD r8, r9, [%[state], #128]\n\t" - "LDRD r10, r11, [%[state], #176]\n\t" + "LDRD r2, r3, [r0, #24]\n\t" + "LDRD r4, r5, [r0, #72]\n\t" + "LDRD r6, r7, [r0, #80]\n\t" + "LDRD r8, r9, [r0, #128]\n\t" + "LDRD r10, r11, [r0, #176]\n\t" /* s[0] <<< 28 */ "LSR r12, r3, #4\n\t" "LSR lr, r2, #4\n\t" @@ -430,11 +436,11 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "STR r12, [sp, #40]\n\t" "STR lr, [sp, #44]\n\t" /* Row 2 */ - "LDRD r2, r3, [%[state], #8]\n\t" - "LDRD r4, r5, [%[state], #56]\n\t" - "LDRD r6, r7, [%[state], #104]\n\t" - "LDRD r8, r9, [%[state], #152]\n\t" - "LDRD r10, r11, [%[state], #160]\n\t" + "LDRD r2, r3, [r0, #8]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" + "LDRD r6, r7, [r0, #104]\n\t" + "LDRD r8, r9, [r0, #152]\n\t" + "LDRD r10, r11, [r0, #160]\n\t" /* s[0] <<< 1 */ "LSR r12, r3, #31\n\t" "LSR lr, r2, #31\n\t" @@ -491,11 +497,11 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "STR r12, [sp, #80]\n\t" "STR lr, [sp, #84]\n\t" /* Row 3 */ - "LDRD r2, r3, [%[state], #32]\n\t" - "LDRD r4, r5, [%[state], #40]\n\t" - "LDRD r6, r7, [%[state], #88]\n\t" - "LDRD r8, r9, [%[state], #136]\n\t" - "LDRD r10, r11, [%[state], #184]\n\t" + "LDRD r2, r3, [r0, #32]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" + "LDRD r6, r7, [r0, #88]\n\t" + "LDRD r8, r9, [r0, #136]\n\t" + "LDRD r10, r11, [r0, #184]\n\t" /* s[0] <<< 27 */ "LSR r12, r3, #5\n\t" "LSR lr, r2, #5\n\t" @@ -554,11 +560,11 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "STR r12, [sp, #120]\n\t" "STR lr, [sp, #124]\n\t" /* Row 4 */ - "LDRD r2, r3, [%[state], #16]\n\t" - "LDRD r4, r5, [%[state], #64]\n\t" - "LDRD r6, r7, [%[state], #112]\n\t" - "LDRD r8, r9, [%[state], #120]\n\t" - "LDRD r10, r11, [%[state], #168]\n\t" + "LDRD r2, r3, [r0, #16]\n\t" + "LDRD r4, r5, [r0, #64]\n\t" + "LDRD r6, r7, [r0, #112]\n\t" + "LDRD r8, r9, [r0, #120]\n\t" + "LDRD r10, r11, [r0, #168]\n\t" /* s[0] <<< 62 */ "MOV lr, r2\n\t" "LSR r12, r3, #2\n\t" @@ -634,7 +640,7 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r3, r3, r11\n\t" "EOR r2, r2, r12\n\t" "EOR r3, r3, lr\n\t" - "STRD r2, r3, [%[state], #32]\n\t" + "STRD r2, r3, [r0, #32]\n\t" /* Calc b[1] */ "LDRD r4, r5, [sp, #8]\n\t" "LDRD r6, r7, [sp, #48]\n\t" @@ -650,7 +656,7 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r5, r5, r11\n\t" "EOR r4, r4, r12\n\t" "EOR r5, r5, lr\n\t" - "STRD r4, r5, [%[state], #8]\n\t" + "STRD r4, r5, [r0, #8]\n\t" /* Calc t[0] */ "EOR r2, r2, r5, LSR #31\n\t" "EOR r3, r3, r4, LSR #31\n\t" @@ -685,8 +691,8 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r10, r10, r2\n\t" "EOR r11, r11, r3\n\t" "STRD r10, r11, [sp, #160]\n\t" - "STR r12, [%[state]]\n\t" - "STR lr, [%[state], #4]\n\t" + "STR r12, [r0]\n\t" + "STR lr, [r0, #4]\n\t" /* Calc b[3] */ "LDRD r4, r5, [sp, #24]\n\t" "LDRD r6, r7, [sp, #64]\n\t" @@ -702,9 +708,9 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r5, r5, r11\n\t" "EOR r4, r4, r12\n\t" "EOR r5, r5, lr\n\t" - "STRD r4, r5, [%[state], #24]\n\t" + "STRD r4, r5, [r0, #24]\n\t" /* Calc t[2] */ - "LDRD r2, r3, [%[state], #8]\n\t" + "LDRD r2, r3, [r0, #8]\n\t" "EOR r2, r2, r5, LSR #31\n\t" "EOR r3, r3, r4, LSR #31\n\t" "EOR r2, r2, r4, LSL #1\n\t" @@ -738,10 +744,10 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "EOR r10, r10, r2\n\t" "EOR r11, r11, r3\n\t" "STRD r10, r11, [sp, #176]\n\t" - "STR r12, [%[state], #16]\n\t" - "STR lr, [%[state], #20]\n\t" + "STR r12, [r0, #16]\n\t" + "STR lr, [r0, #20]\n\t" /* Calc t[1] */ - "LDRD r2, r3, [%[state]]\n\t" + "LDRD r2, r3, [r0]\n\t" "EOR r2, r2, lr, LSR #31\n\t" "EOR r3, r3, r12, LSR #31\n\t" "EOR r2, r2, r12, LSL #1\n\t" @@ -770,8 +776,8 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "STR r12, [sp, #168]\n\t" "STR lr, [sp, #172]\n\t" /* Calc t[3] */ - "LDRD r2, r3, [%[state], #16]\n\t" - "LDRD r4, r5, [%[state], #32]\n\t" + "LDRD r2, r3, [r0, #16]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "EOR r2, r2, r5, LSR #31\n\t" "EOR r3, r3, r4, LSR #31\n\t" "EOR r2, r2, r4, LSL #1\n\t" @@ -800,8 +806,8 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "STR r12, [sp, #184]\n\t" "STR lr, [sp, #188]\n\t" /* Calc t[4] */ - "LDRD r2, r3, [%[state], #24]\n\t" - "LDRD r4, r5, [%[state]]\n\t" + "LDRD r2, r3, [r0, #24]\n\t" + "LDRD r4, r5, [r0]\n\t" "EOR r2, r2, r5, LSR #31\n\t" "EOR r3, r3, r4, LSR #31\n\t" "EOR r2, r2, r4, LSL #1\n\t" @@ -862,26 +868,26 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "BIC lr, r9, r7\n\t" "EOR r12, r12, r4\n\t" "EOR lr, lr, r5\n\t" - "STR r12, [%[state], #8]\n\t" - "STR lr, [%[state], #12]\n\t" + "STR r12, [r0, #8]\n\t" + "STR lr, [r0, #12]\n\t" "BIC r12, r10, r8\n\t" "BIC lr, r11, r9\n\t" "EOR r12, r12, r6\n\t" "EOR lr, lr, r7\n\t" - "STR r12, [%[state], #16]\n\t" - "STR lr, [%[state], #20]\n\t" + "STR r12, [r0, #16]\n\t" + "STR lr, [r0, #20]\n\t" "BIC r12, r2, r10\n\t" "BIC lr, r3, r11\n\t" "EOR r12, r12, r8\n\t" "EOR lr, lr, r9\n\t" - "STR r12, [%[state], #24]\n\t" - "STR lr, [%[state], #28]\n\t" + "STR r12, [r0, #24]\n\t" + "STR lr, [r0, #28]\n\t" "BIC r12, r4, r2\n\t" "BIC lr, r5, r3\n\t" "EOR r12, r12, r10\n\t" "EOR lr, lr, r11\n\t" - "STR r12, [%[state], #32]\n\t" - "STR lr, [%[state], #36]\n\t" + "STR r12, [r0, #32]\n\t" + "STR lr, [r0, #36]\n\t" /* Get constant */ "LDRD r10, r11, [r1]\n\t" "ADD r1, r1, #8\n\t" @@ -892,8 +898,8 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) /* XOR in constant */ "EOR r12, r12, r10\n\t" "EOR lr, lr, r11\n\t" - "STR r12, [%[state]]\n\t" - "STR lr, [%[state], #4]\n\t" + "STR r12, [r0]\n\t" + "STR lr, [r0, #4]\n\t" /* Row 1 */ "LDRD r2, r3, [sp, #24]\n\t" "LDRD r4, r5, [sp, #72]\n\t" @@ -931,32 +937,32 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "BIC lr, r9, r7\n\t" "EOR r12, r12, r4\n\t" "EOR lr, lr, r5\n\t" - "STR r12, [%[state], #48]\n\t" - "STR lr, [%[state], #52]\n\t" + "STR r12, [r0, #48]\n\t" + "STR lr, [r0, #52]\n\t" "BIC r12, r10, r8\n\t" "BIC lr, r11, r9\n\t" "EOR r12, r12, r6\n\t" "EOR lr, lr, r7\n\t" - "STR r12, [%[state], #56]\n\t" - "STR lr, [%[state], #60]\n\t" + "STR r12, [r0, #56]\n\t" + "STR lr, [r0, #60]\n\t" "BIC r12, r2, r10\n\t" "BIC lr, r3, r11\n\t" "EOR r12, r12, r8\n\t" "EOR lr, lr, r9\n\t" - "STR r12, [%[state], #64]\n\t" - "STR lr, [%[state], #68]\n\t" + "STR r12, [r0, #64]\n\t" + "STR lr, [r0, #68]\n\t" "BIC r12, r4, r2\n\t" "BIC lr, r5, r3\n\t" "EOR r12, r12, r10\n\t" "EOR lr, lr, r11\n\t" - "STR r12, [%[state], #72]\n\t" - "STR lr, [%[state], #76]\n\t" + "STR r12, [r0, #72]\n\t" + "STR lr, [r0, #76]\n\t" "BIC r12, r6, r4\n\t" "BIC lr, r7, r5\n\t" "EOR r12, r12, r2\n\t" "EOR lr, lr, r3\n\t" - "STR r12, [%[state], #40]\n\t" - "STR lr, [%[state], #44]\n\t" + "STR r12, [r0, #40]\n\t" + "STR lr, [r0, #44]\n\t" /* Row 2 */ "LDRD r2, r3, [sp, #8]\n\t" "LDRD r4, r5, [sp, #56]\n\t" @@ -992,32 +998,32 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "BIC lr, r9, r7\n\t" "EOR r12, r12, r4\n\t" "EOR lr, lr, r5\n\t" - "STR r12, [%[state], #88]\n\t" - "STR lr, [%[state], #92]\n\t" + "STR r12, [r0, #88]\n\t" + "STR lr, [r0, #92]\n\t" "BIC r12, r10, r8\n\t" "BIC lr, r11, r9\n\t" "EOR r12, r12, r6\n\t" "EOR lr, lr, r7\n\t" - "STR r12, [%[state], #96]\n\t" - "STR lr, [%[state], #100]\n\t" + "STR r12, [r0, #96]\n\t" + "STR lr, [r0, #100]\n\t" "BIC r12, r2, r10\n\t" "BIC lr, r3, r11\n\t" "EOR r12, r12, r8\n\t" "EOR lr, lr, r9\n\t" - "STR r12, [%[state], #104]\n\t" - "STR lr, [%[state], #108]\n\t" + "STR r12, [r0, #104]\n\t" + "STR lr, [r0, #108]\n\t" "BIC r12, r4, r2\n\t" "BIC lr, r5, r3\n\t" "EOR r12, r12, r10\n\t" "EOR lr, lr, r11\n\t" - "STR r12, [%[state], #112]\n\t" - "STR lr, [%[state], #116]\n\t" + "STR r12, [r0, #112]\n\t" + "STR lr, [r0, #116]\n\t" "BIC r12, r6, r4\n\t" "BIC lr, r7, r5\n\t" "EOR r12, r12, r2\n\t" "EOR lr, lr, r3\n\t" - "STR r12, [%[state], #80]\n\t" - "STR lr, [%[state], #84]\n\t" + "STR r12, [r0, #80]\n\t" + "STR lr, [r0, #84]\n\t" /* Row 3 */ "LDRD r2, r3, [sp, #32]\n\t" "LDRD r4, r5, [sp, #40]\n\t" @@ -1055,32 +1061,32 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "BIC lr, r9, r7\n\t" "EOR r12, r12, r4\n\t" "EOR lr, lr, r5\n\t" - "STR r12, [%[state], #128]\n\t" - "STR lr, [%[state], #132]\n\t" + "STR r12, [r0, #128]\n\t" + "STR lr, [r0, #132]\n\t" "BIC r12, r10, r8\n\t" "BIC lr, r11, r9\n\t" "EOR r12, r12, r6\n\t" "EOR lr, lr, r7\n\t" - "STR r12, [%[state], #136]\n\t" - "STR lr, [%[state], #140]\n\t" + "STR r12, [r0, #136]\n\t" + "STR lr, [r0, #140]\n\t" "BIC r12, r2, r10\n\t" "BIC lr, r3, r11\n\t" "EOR r12, r12, r8\n\t" "EOR lr, lr, r9\n\t" - "STR r12, [%[state], #144]\n\t" - "STR lr, [%[state], #148]\n\t" + "STR r12, [r0, #144]\n\t" + "STR lr, [r0, #148]\n\t" "BIC r12, r4, r2\n\t" "BIC lr, r5, r3\n\t" "EOR r12, r12, r10\n\t" "EOR lr, lr, r11\n\t" - "STR r12, [%[state], #152]\n\t" - "STR lr, [%[state], #156]\n\t" + "STR r12, [r0, #152]\n\t" + "STR lr, [r0, #156]\n\t" "BIC r12, r6, r4\n\t" "BIC lr, r7, r5\n\t" "EOR r12, r12, r2\n\t" "EOR lr, lr, r3\n\t" - "STR r12, [%[state], #120]\n\t" - "STR lr, [%[state], #124]\n\t" + "STR r12, [r0, #120]\n\t" + "STR lr, [r0, #124]\n\t" /* Row 4 */ "LDRD r2, r3, [sp, #16]\n\t" "LDRD r4, r5, [sp, #64]\n\t" @@ -1120,32 +1126,32 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "BIC lr, r9, r7\n\t" "EOR r12, r12, r4\n\t" "EOR lr, lr, r5\n\t" - "STR r12, [%[state], #168]\n\t" - "STR lr, [%[state], #172]\n\t" + "STR r12, [r0, #168]\n\t" + "STR lr, [r0, #172]\n\t" "BIC r12, r10, r8\n\t" "BIC lr, r11, r9\n\t" "EOR r12, r12, r6\n\t" "EOR lr, lr, r7\n\t" - "STR r12, [%[state], #176]\n\t" - "STR lr, [%[state], #180]\n\t" + "STR r12, [r0, #176]\n\t" + "STR lr, [r0, #180]\n\t" "BIC r12, r2, r10\n\t" "BIC lr, r3, r11\n\t" "EOR r12, r12, r8\n\t" "EOR lr, lr, r9\n\t" - "STR r12, [%[state], #184]\n\t" - "STR lr, [%[state], #188]\n\t" + "STR r12, [r0, #184]\n\t" + "STR lr, [r0, #188]\n\t" "BIC r12, r4, r2\n\t" "BIC lr, r5, r3\n\t" "EOR r12, r12, r10\n\t" "EOR lr, lr, r11\n\t" - "STR r12, [%[state], #192]\n\t" - "STR lr, [%[state], #196]\n\t" + "STR r12, [r0, #192]\n\t" + "STR lr, [r0, #196]\n\t" "BIC r12, r6, r4\n\t" "BIC lr, r7, r5\n\t" "EOR r12, r12, r2\n\t" "EOR lr, lr, r3\n\t" - "STR r12, [%[state], #160]\n\t" - "STR lr, [%[state], #164]\n\t" + "STR r12, [r0, #160]\n\t" + "STR lr, [r0, #164]\n\t" "LDR r2, [sp, #200]\n\t" "SUBS r2, r2, #1\n\t" #if defined(__GNUC__) @@ -1156,16 +1162,25 @@ WC_OMIT_FRAME_POINTER void BlockSha3(word64* state) "BNE.W L_sha3_thumb2_begin_%=\n\t" #endif "ADD sp, sp, #0xcc\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [state] "+r" (state), [L_sha3_thumb2_rt] "+r" (L_sha3_thumb2_rt_c) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [state] "r" (state), [L_sha3_thumb2_rt] "r" (L_sha3_thumb2_rt_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + state = (word64*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SHA3 */ diff --git a/wolfcrypt/src/port/arm/thumb2-sha512-asm_c.c b/wolfcrypt/src/port/arm/thumb2-sha512-asm_c.c index 768a61c06c6..4f870f30a7e 100644 --- a/wolfcrypt/src/port/arm/thumb2-sha512-asm_c.c +++ b/wolfcrypt/src/port/arm/thumb2-sha512-asm_c.c @@ -111,26 +111,31 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, register word64* L_SHA512_transform_len_k_c __asm__ ("r3") = (word64*)&L_SHA512_transform_len_k; #else - register word64* L_SHA512_transform_len_k_c = - (word64*)&L_SHA512_transform_len_k; + void* L_asm_args[4] = {(void*)(size_t)sha512, (void*)(size_t)data, + (void*)(size_t)len, (void*)(size_t)&L_SHA512_transform_len_k + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0xc0\n\t" - "MOV r3, %[L_SHA512_transform_len_k]\n\t" /* Copy digest to add in at end */ - "LDRD r4, r5, [%[sha512]]\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" - "LDRD r10, r11, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" + "LDRD r10, r11, [r0, #24]\n\t" "STRD r4, r5, [sp, #128]\n\t" "STRD r6, r7, [sp, #136]\n\t" "STRD r8, r9, [sp, #144]\n\t" "STRD r10, r11, [sp, #152]\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" - "LDRD r10, r11, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" + "LDRD r10, r11, [r0, #56]\n\t" "STRD r4, r5, [sp, #160]\n\t" "STRD r6, r7, [sp, #168]\n\t" "STRD r8, r9, [sp, #176]\n\t" @@ -143,14 +148,14 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "L_SHA512_transform_len_begin_%=:\n\t" #endif /* Load, Reverse and Store W */ - "LDR r4, [%[data]]\n\t" - "LDR r5, [%[data], #4]\n\t" - "LDR r6, [%[data], #8]\n\t" - "LDR r7, [%[data], #12]\n\t" - "LDR r8, [%[data], #16]\n\t" - "LDR r9, [%[data], #20]\n\t" - "LDR r10, [%[data], #24]\n\t" - "LDR r11, [%[data], #28]\n\t" + "LDR r4, [r1]\n\t" + "LDR r5, [r1, #4]\n\t" + "LDR r6, [r1, #8]\n\t" + "LDR r7, [r1, #12]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r11, [r1, #28]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -167,14 +172,14 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "STR r8, [sp, #20]\n\t" "STR r11, [sp, #24]\n\t" "STR r10, [sp, #28]\n\t" - "LDR r4, [%[data], #32]\n\t" - "LDR r5, [%[data], #36]\n\t" - "LDR r6, [%[data], #40]\n\t" - "LDR r7, [%[data], #44]\n\t" - "LDR r8, [%[data], #48]\n\t" - "LDR r9, [%[data], #52]\n\t" - "LDR r10, [%[data], #56]\n\t" - "LDR r11, [%[data], #60]\n\t" + "LDR r4, [r1, #32]\n\t" + "LDR r5, [r1, #36]\n\t" + "LDR r6, [r1, #40]\n\t" + "LDR r7, [r1, #44]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r1, #52]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r11, [r1, #60]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -191,14 +196,14 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "STR r8, [sp, #52]\n\t" "STR r11, [sp, #56]\n\t" "STR r10, [sp, #60]\n\t" - "LDR r4, [%[data], #64]\n\t" - "LDR r5, [%[data], #68]\n\t" - "LDR r6, [%[data], #72]\n\t" - "LDR r7, [%[data], #76]\n\t" - "LDR r8, [%[data], #80]\n\t" - "LDR r9, [%[data], #84]\n\t" - "LDR r10, [%[data], #88]\n\t" - "LDR r11, [%[data], #92]\n\t" + "LDR r4, [r1, #64]\n\t" + "LDR r5, [r1, #68]\n\t" + "LDR r6, [r1, #72]\n\t" + "LDR r7, [r1, #76]\n\t" + "LDR r8, [r1, #80]\n\t" + "LDR r9, [r1, #84]\n\t" + "LDR r10, [r1, #88]\n\t" + "LDR r11, [r1, #92]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -215,14 +220,14 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "STR r8, [sp, #84]\n\t" "STR r11, [sp, #88]\n\t" "STR r10, [sp, #92]\n\t" - "LDR r4, [%[data], #96]\n\t" - "LDR r5, [%[data], #100]\n\t" - "LDR r6, [%[data], #104]\n\t" - "LDR r7, [%[data], #108]\n\t" - "LDR r8, [%[data], #112]\n\t" - "LDR r9, [%[data], #116]\n\t" - "LDR r10, [%[data], #120]\n\t" - "LDR r11, [%[data], #124]\n\t" + "LDR r4, [r1, #96]\n\t" + "LDR r5, [r1, #100]\n\t" + "LDR r6, [r1, #104]\n\t" + "LDR r7, [r1, #108]\n\t" + "LDR r8, [r1, #112]\n\t" + "LDR r9, [r1, #116]\n\t" + "LDR r10, [r1, #120]\n\t" + "LDR r11, [r1, #124]\n\t" "REV r4, r4\n\t" "REV r5, r5\n\t" "REV r6, r6\n\t" @@ -240,8 +245,8 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "STR r11, [sp, #120]\n\t" "STR r10, [sp, #124]\n\t" /* Pre-calc: b ^ c */ - "LDRD r10, r11, [%[sha512], #8]\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r10, r11, [r0, #8]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "EOR r10, r10, r4\n\t" "EOR r11, r11, r5\n\t" "MOV r12, #4\n\t" @@ -253,7 +258,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "L_SHA512_transform_len_start_%=:\n\t" #endif /* Round 0 */ - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -268,36 +273,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" + "STRD r4, r5, [r0, #56]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "LDRD r8, r9, [sp]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" + "STRD r4, r5, [r0, #56]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" - "STRD r8, r9, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0]\n\t" + "STRD r8, r9, [r0, #24]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -312,24 +317,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r8, r9, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" + "STRD r4, r5, [r0, #56]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #56]\n\t" + "STRD r6, r7, [r0, #56]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[0] */ @@ -377,7 +382,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp]\n\t" /* Round 1 */ - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -392,36 +397,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" + "STRD r4, r5, [r0, #48]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "LDRD r8, r9, [sp, #8]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #8]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" + "STRD r4, r5, [r0, #48]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" - "STRD r8, r9, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" + "STRD r8, r9, [r0, #16]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -436,24 +441,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" + "LDRD r6, r7, [r0]\n\t" + "STRD r4, r5, [r0, #48]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #48]\n\t" + "STRD r6, r7, [r0, #48]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[1] */ @@ -501,7 +506,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #8]\n\t" /* Round 2 */ - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -516,36 +521,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" + "STRD r4, r5, [r0, #40]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "LDRD r8, r9, [sp, #16]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #16]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" + "STRD r4, r5, [r0, #40]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" - "STRD r8, r9, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" + "STRD r8, r9, [r0, #8]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -560,24 +565,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" + "STRD r4, r5, [r0, #40]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #40]\n\t" + "STRD r6, r7, [r0, #40]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[2] */ @@ -625,7 +630,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #16]\n\t" /* Round 3 */ - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -640,36 +645,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" + "STRD r4, r5, [r0, #32]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "LDRD r8, r9, [sp, #24]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #24]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" + "LDRD r8, r9, [r0]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" + "STRD r4, r5, [r0, #32]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" - "STRD r8, r9, [%[sha512]]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" + "STRD r8, r9, [r0]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -684,24 +689,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" + "STRD r4, r5, [r0, #32]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #32]\n\t" + "STRD r6, r7, [r0, #32]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[3] */ @@ -749,7 +754,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #24]\n\t" /* Round 4 */ - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -764,36 +769,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" + "STRD r4, r5, [r0, #24]\n\t" + "LDRD r4, r5, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "LDRD r8, r9, [sp, #32]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #32]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" + "STRD r4, r5, [r0, #24]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" - "STRD r8, r9, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "STRD r8, r9, [r0, #56]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -808,24 +813,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" + "STRD r4, r5, [r0, #24]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #24]\n\t" + "STRD r6, r7, [r0, #24]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[4] */ @@ -873,7 +878,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #32]\n\t" /* Round 5 */ - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -888,36 +893,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" + "STRD r4, r5, [r0, #16]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" + "LDRD r6, r7, [r0]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "LDRD r8, r9, [sp, #40]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #40]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" + "STRD r4, r5, [r0, #16]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" - "STRD r8, r9, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" + "STRD r8, r9, [r0, #48]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -932,24 +937,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" + "STRD r4, r5, [r0, #16]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #16]\n\t" + "STRD r6, r7, [r0, #16]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[5] */ @@ -997,7 +1002,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #40]\n\t" /* Round 6 */ - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -1012,36 +1017,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" + "STRD r4, r5, [r0, #8]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" + "LDRD r8, r9, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "LDRD r8, r9, [sp, #48]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #48]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" + "STRD r4, r5, [r0, #8]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" - "STRD r8, r9, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" + "STRD r8, r9, [r0, #40]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -1056,24 +1061,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" + "STRD r4, r5, [r0, #8]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #8]\n\t" + "STRD r6, r7, [r0, #8]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[6] */ @@ -1121,7 +1126,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #48]\n\t" /* Round 7 */ - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -1136,36 +1141,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512]]\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" + "STRD r4, r5, [r0]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "LDRD r8, r9, [sp, #56]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #56]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512]]\n\t" + "STRD r4, r5, [r0]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" - "STRD r8, r9, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" + "STRD r8, r9, [r0, #32]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -1180,24 +1185,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" - "STRD r4, r5, [%[sha512]]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" + "STRD r4, r5, [r0]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" + "LDRD r6, r7, [r0]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512]]\n\t" + "STRD r6, r7, [r0]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[7] */ @@ -1245,7 +1250,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #56]\n\t" /* Round 8 */ - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -1260,36 +1265,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" + "STRD r4, r5, [r0, #56]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "LDRD r8, r9, [sp, #64]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #64]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" + "STRD r4, r5, [r0, #56]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" - "STRD r8, r9, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0]\n\t" + "STRD r8, r9, [r0, #24]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -1304,24 +1309,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r8, r9, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" + "STRD r4, r5, [r0, #56]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #56]\n\t" + "STRD r6, r7, [r0, #56]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[8] */ @@ -1369,7 +1374,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #64]\n\t" /* Round 9 */ - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -1384,36 +1389,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" + "STRD r4, r5, [r0, #48]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "LDRD r8, r9, [sp, #72]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #72]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" + "STRD r4, r5, [r0, #48]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" - "STRD r8, r9, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" + "STRD r8, r9, [r0, #16]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -1428,24 +1433,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" + "LDRD r6, r7, [r0]\n\t" + "STRD r4, r5, [r0, #48]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #48]\n\t" + "STRD r6, r7, [r0, #48]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[9] */ @@ -1493,7 +1498,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #72]\n\t" /* Round 10 */ - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -1508,36 +1513,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" + "STRD r4, r5, [r0, #40]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "LDRD r8, r9, [sp, #80]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #80]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" + "STRD r4, r5, [r0, #40]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" - "STRD r8, r9, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" + "STRD r8, r9, [r0, #8]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -1552,24 +1557,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" + "STRD r4, r5, [r0, #40]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #40]\n\t" + "STRD r6, r7, [r0, #40]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[10] */ @@ -1617,7 +1622,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #80]\n\t" /* Round 11 */ - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -1632,36 +1637,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" + "STRD r4, r5, [r0, #32]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "LDRD r8, r9, [sp, #88]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #88]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" + "LDRD r8, r9, [r0]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" + "STRD r4, r5, [r0, #32]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" - "STRD r8, r9, [%[sha512]]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" + "STRD r8, r9, [r0]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -1676,24 +1681,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" + "STRD r4, r5, [r0, #32]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #32]\n\t" + "STRD r6, r7, [r0, #32]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[11] */ @@ -1741,7 +1746,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #88]\n\t" /* Round 12 */ - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -1756,36 +1761,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" + "STRD r4, r5, [r0, #24]\n\t" + "LDRD r4, r5, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "LDRD r8, r9, [sp, #96]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #96]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" + "STRD r4, r5, [r0, #24]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" - "STRD r8, r9, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "STRD r8, r9, [r0, #56]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -1800,24 +1805,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" + "STRD r4, r5, [r0, #24]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #24]\n\t" + "STRD r6, r7, [r0, #24]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[12] */ @@ -1865,7 +1870,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #96]\n\t" /* Round 13 */ - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -1880,36 +1885,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" + "STRD r4, r5, [r0, #16]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" + "LDRD r6, r7, [r0]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "LDRD r8, r9, [sp, #104]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #104]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" + "STRD r4, r5, [r0, #16]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" - "STRD r8, r9, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" + "STRD r8, r9, [r0, #48]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -1924,24 +1929,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" + "STRD r4, r5, [r0, #16]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #16]\n\t" + "STRD r6, r7, [r0, #16]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[13] */ @@ -1989,7 +1994,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #104]\n\t" /* Round 14 */ - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2004,36 +2009,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" + "STRD r4, r5, [r0, #8]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" + "LDRD r8, r9, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "LDRD r8, r9, [sp, #112]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #112]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" + "STRD r4, r5, [r0, #8]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" - "STRD r8, r9, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" + "STRD r8, r9, [r0, #40]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -2048,24 +2053,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" + "STRD r4, r5, [r0, #8]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #8]\n\t" + "STRD r6, r7, [r0, #8]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[14] */ @@ -2113,7 +2118,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "ADC r5, r5, r7\n\t" "STRD r4, r5, [sp, #112]\n\t" /* Round 15 */ - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2128,36 +2133,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512]]\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" + "STRD r4, r5, [r0]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "LDRD r8, r9, [sp, #120]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #120]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512]]\n\t" + "STRD r4, r5, [r0]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" - "STRD r8, r9, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" + "STRD r8, r9, [r0, #32]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -2172,24 +2177,24 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" - "STRD r4, r5, [%[sha512]]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" + "STRD r4, r5, [r0]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" + "LDRD r6, r7, [r0]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512]]\n\t" + "STRD r6, r7, [r0]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Calc new W[15] */ @@ -2246,7 +2251,7 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "BNE.W L_SHA512_transform_len_start_%=\n\t" #endif /* Round 0 */ - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2261,36 +2266,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" + "STRD r4, r5, [r0, #56]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "LDRD r8, r9, [sp]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" + "STRD r4, r5, [r0, #56]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" - "STRD r8, r9, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0]\n\t" + "STRD r8, r9, [r0, #24]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -2305,28 +2310,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r8, r9, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" + "STRD r4, r5, [r0, #56]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #56]\n\t" + "STRD r6, r7, [r0, #56]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 1 */ - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2341,36 +2346,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" + "STRD r4, r5, [r0, #48]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "LDRD r8, r9, [sp, #8]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #8]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" + "STRD r4, r5, [r0, #48]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" - "STRD r8, r9, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" + "STRD r8, r9, [r0, #16]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -2385,28 +2390,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" + "LDRD r6, r7, [r0]\n\t" + "STRD r4, r5, [r0, #48]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #48]\n\t" + "STRD r6, r7, [r0, #48]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 2 */ - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2421,36 +2426,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" + "STRD r4, r5, [r0, #40]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "LDRD r8, r9, [sp, #16]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #16]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" + "STRD r4, r5, [r0, #40]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" - "STRD r8, r9, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" + "STRD r8, r9, [r0, #8]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -2465,28 +2470,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" + "STRD r4, r5, [r0, #40]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #40]\n\t" + "STRD r6, r7, [r0, #40]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 3 */ - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2501,36 +2506,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" + "STRD r4, r5, [r0, #32]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "LDRD r8, r9, [sp, #24]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #24]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" + "LDRD r8, r9, [r0]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" + "STRD r4, r5, [r0, #32]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" - "STRD r8, r9, [%[sha512]]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" + "STRD r8, r9, [r0]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -2545,28 +2550,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" + "STRD r4, r5, [r0, #32]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #32]\n\t" + "STRD r6, r7, [r0, #32]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 4 */ - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2581,36 +2586,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" + "STRD r4, r5, [r0, #24]\n\t" + "LDRD r4, r5, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "LDRD r8, r9, [sp, #32]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #32]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" + "STRD r4, r5, [r0, #24]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" - "STRD r8, r9, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "STRD r8, r9, [r0, #56]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -2625,28 +2630,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" + "STRD r4, r5, [r0, #24]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #24]\n\t" + "STRD r6, r7, [r0, #24]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 5 */ - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2661,36 +2666,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" + "STRD r4, r5, [r0, #16]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" + "LDRD r6, r7, [r0]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "LDRD r8, r9, [sp, #40]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #40]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" + "STRD r4, r5, [r0, #16]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" - "STRD r8, r9, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" + "STRD r8, r9, [r0, #48]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -2705,28 +2710,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" + "STRD r4, r5, [r0, #16]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #16]\n\t" + "STRD r6, r7, [r0, #16]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 6 */ - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2741,36 +2746,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" + "STRD r4, r5, [r0, #8]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" + "LDRD r8, r9, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "LDRD r8, r9, [sp, #48]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #48]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" + "STRD r4, r5, [r0, #8]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" - "STRD r8, r9, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" + "STRD r8, r9, [r0, #40]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -2785,28 +2790,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" + "STRD r4, r5, [r0, #8]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #8]\n\t" + "STRD r6, r7, [r0, #8]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 7 */ - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2821,36 +2826,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512]]\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" + "STRD r4, r5, [r0]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "LDRD r8, r9, [sp, #56]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #56]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512]]\n\t" + "STRD r4, r5, [r0]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" - "STRD r8, r9, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" + "STRD r8, r9, [r0, #32]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -2865,28 +2870,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" - "STRD r4, r5, [%[sha512]]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" + "STRD r4, r5, [r0]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" + "LDRD r6, r7, [r0]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512]]\n\t" + "STRD r6, r7, [r0]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 8 */ - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2901,36 +2906,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" + "STRD r4, r5, [r0, #56]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "LDRD r8, r9, [sp, #64]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #64]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" + "STRD r4, r5, [r0, #56]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" - "STRD r8, r9, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0]\n\t" + "STRD r8, r9, [r0, #24]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -2945,28 +2950,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" - "STRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r8, r9, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" + "STRD r4, r5, [r0, #56]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #56]\n\t" + "STRD r6, r7, [r0, #56]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 9 */ - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -2981,36 +2986,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" + "STRD r4, r5, [r0, #48]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "LDRD r8, r9, [sp, #72]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #72]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" + "STRD r4, r5, [r0, #48]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" - "STRD r8, r9, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" + "STRD r8, r9, [r0, #16]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -3025,28 +3030,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" + "LDRD r6, r7, [r0]\n\t" + "STRD r4, r5, [r0, #48]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #48]\n\t" + "STRD r6, r7, [r0, #48]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 10 */ - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -3061,36 +3066,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" + "STRD r4, r5, [r0, #40]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "LDRD r8, r9, [sp, #80]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #80]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" + "STRD r4, r5, [r0, #40]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" - "STRD r8, r9, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" + "STRD r8, r9, [r0, #8]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -3105,28 +3110,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" - "STRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" + "STRD r4, r5, [r0, #40]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #40]\n\t" + "STRD r6, r7, [r0, #40]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 11 */ - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -3141,36 +3146,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" + "STRD r4, r5, [r0, #32]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "LDRD r8, r9, [sp, #88]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #88]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" + "LDRD r8, r9, [r0]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" + "STRD r4, r5, [r0, #32]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" - "STRD r8, r9, [%[sha512]]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" + "STRD r8, r9, [r0]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -3185,28 +3190,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" + "STRD r4, r5, [r0, #32]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #32]\n\t" + "STRD r6, r7, [r0, #32]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 12 */ - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -3221,36 +3226,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" + "STRD r4, r5, [r0, #24]\n\t" + "LDRD r4, r5, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "LDRD r8, r9, [sp, #96]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #96]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" + "STRD r4, r5, [r0, #24]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" - "STRD r8, r9, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "STRD r8, r9, [r0, #56]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -3265,28 +3270,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" - "STRD r4, r5, [%[sha512], #24]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" + "STRD r4, r5, [r0, #24]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #24]\n\t" + "STRD r6, r7, [r0, #24]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 13 */ - "LDRD r4, r5, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -3301,36 +3306,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" - "LDRD r4, r5, [%[sha512], #56]\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" + "STRD r4, r5, [r0, #16]\n\t" + "LDRD r4, r5, [r0, #56]\n\t" + "LDRD r6, r7, [r0]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "LDRD r8, r9, [sp, #104]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #104]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #48]\n\t" + "LDRD r8, r9, [r0, #48]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" + "STRD r4, r5, [r0, #16]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #24]\n\t" - "STRD r8, r9, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #24]\n\t" + "STRD r8, r9, [r0, #48]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -3345,28 +3350,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #24]\n\t" - "LDRD r6, r7, [%[sha512], #32]\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" + "LDRD r8, r9, [r0, #24]\n\t" + "LDRD r6, r7, [r0, #32]\n\t" + "STRD r4, r5, [r0, #16]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #16]\n\t" + "STRD r6, r7, [r0, #16]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 14 */ - "LDRD r4, r5, [%[sha512], #48]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -3381,36 +3386,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" - "LDRD r8, r9, [%[sha512]]\n\t" + "STRD r4, r5, [r0, #8]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" + "LDRD r8, r9, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "LDRD r8, r9, [sp, #112]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #112]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #40]\n\t" + "LDRD r8, r9, [r0, #40]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" + "STRD r4, r5, [r0, #8]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" - "STRD r8, r9, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" + "STRD r8, r9, [r0, #40]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -3425,28 +3430,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #16]\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" - "STRD r4, r5, [%[sha512], #8]\n\t" + "LDRD r8, r9, [r0, #16]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" + "STRD r4, r5, [r0, #8]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512], #8]\n\t" + "STRD r6, r7, [r0, #8]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Round 15 */ - "LDRD r4, r5, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" "LSRS r6, r4, #14\n\t" "LSRS r7, r5, #14\n\t" "ORR r7, r7, r4, LSL #18\n\t" @@ -3461,36 +3466,36 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #23\n\t" "ORR r9, r9, r4, LSR #9\n\t" "ORR r8, r8, r5, LSR #9\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512]]\n\t" - "LDRD r4, r5, [%[sha512], #40]\n\t" - "LDRD r6, r7, [%[sha512], #48]\n\t" - "LDRD r8, r9, [%[sha512], #56]\n\t" + "STRD r4, r5, [r0]\n\t" + "LDRD r4, r5, [r0, #40]\n\t" + "LDRD r6, r7, [r0, #48]\n\t" + "LDRD r8, r9, [r0, #56]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "AND r6, r6, r4\n\t" "AND r7, r7, r5\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "LDRD r8, r9, [sp, #120]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" "LDRD r6, r7, [r3, #120]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" - "LDRD r8, r9, [%[sha512], #32]\n\t" + "LDRD r8, r9, [r0, #32]\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "STRD r4, r5, [%[sha512]]\n\t" + "STRD r4, r5, [r0]\n\t" "ADDS r8, r8, r4\n\t" "ADC r9, r9, r5\n\t" - "LDRD r4, r5, [%[sha512], #8]\n\t" - "STRD r8, r9, [%[sha512], #32]\n\t" + "LDRD r4, r5, [r0, #8]\n\t" + "STRD r8, r9, [r0, #32]\n\t" "LSRS r6, r4, #28\n\t" "LSRS r7, r5, #28\n\t" "ORR r7, r7, r4, LSL #4\n\t" @@ -3505,78 +3510,78 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, "LSLS r9, r5, #25\n\t" "ORR r9, r9, r4, LSR #7\n\t" "ORR r8, r8, r5, LSR #7\n\t" - "LDRD r4, r5, [%[sha512]]\n\t" + "LDRD r4, r5, [r0]\n\t" "EOR r6, r6, r8\n\t" "EOR r7, r7, r9\n\t" "ADDS r4, r4, r6\n\t" "ADC r5, r5, r7\n\t" - "LDRD r8, r9, [%[sha512], #8]\n\t" - "LDRD r6, r7, [%[sha512], #16]\n\t" - "STRD r4, r5, [%[sha512]]\n\t" + "LDRD r8, r9, [r0, #8]\n\t" + "LDRD r6, r7, [r0, #16]\n\t" + "STRD r4, r5, [r0]\n\t" "EOR r8, r8, r6\n\t" "EOR r9, r9, r7\n\t" "AND r10, r10, r8\n\t" "AND r11, r11, r9\n\t" "EOR r10, r10, r6\n\t" "EOR r11, r11, r7\n\t" - "LDRD r6, r7, [%[sha512]]\n\t" + "LDRD r6, r7, [r0]\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r6, r7, [%[sha512]]\n\t" + "STRD r6, r7, [r0]\n\t" "MOV r10, r8\n\t" "MOV r11, r9\n\t" /* Add in digest from start */ - "LDRD r4, r5, [%[sha512]]\n\t" - "LDRD r6, r7, [%[sha512], #8]\n\t" + "LDRD r4, r5, [r0]\n\t" + "LDRD r6, r7, [r0, #8]\n\t" "LDRD r8, r9, [sp, #128]\n\t" "LDRD r10, r11, [sp, #136]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r4, r5, [%[sha512]]\n\t" - "STRD r6, r7, [%[sha512], #8]\n\t" + "STRD r4, r5, [r0]\n\t" + "STRD r6, r7, [r0, #8]\n\t" "STRD r4, r5, [sp, #128]\n\t" "STRD r6, r7, [sp, #136]\n\t" - "LDRD r4, r5, [%[sha512], #16]\n\t" - "LDRD r6, r7, [%[sha512], #24]\n\t" + "LDRD r4, r5, [r0, #16]\n\t" + "LDRD r6, r7, [r0, #24]\n\t" "LDRD r8, r9, [sp, #144]\n\t" "LDRD r10, r11, [sp, #152]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r4, r5, [%[sha512], #16]\n\t" - "STRD r6, r7, [%[sha512], #24]\n\t" + "STRD r4, r5, [r0, #16]\n\t" + "STRD r6, r7, [r0, #24]\n\t" "STRD r4, r5, [sp, #144]\n\t" "STRD r6, r7, [sp, #152]\n\t" - "LDRD r4, r5, [%[sha512], #32]\n\t" - "LDRD r6, r7, [%[sha512], #40]\n\t" + "LDRD r4, r5, [r0, #32]\n\t" + "LDRD r6, r7, [r0, #40]\n\t" "LDRD r8, r9, [sp, #160]\n\t" "LDRD r10, r11, [sp, #168]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r4, r5, [%[sha512], #32]\n\t" - "STRD r6, r7, [%[sha512], #40]\n\t" + "STRD r4, r5, [r0, #32]\n\t" + "STRD r6, r7, [r0, #40]\n\t" "STRD r4, r5, [sp, #160]\n\t" "STRD r6, r7, [sp, #168]\n\t" - "LDRD r4, r5, [%[sha512], #48]\n\t" - "LDRD r6, r7, [%[sha512], #56]\n\t" + "LDRD r4, r5, [r0, #48]\n\t" + "LDRD r6, r7, [r0, #56]\n\t" "LDRD r8, r9, [sp, #176]\n\t" "LDRD r10, r11, [sp, #184]\n\t" "ADDS r4, r4, r8\n\t" "ADC r5, r5, r9\n\t" "ADDS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STRD r4, r5, [%[sha512], #48]\n\t" - "STRD r6, r7, [%[sha512], #56]\n\t" + "STRD r4, r5, [r0, #48]\n\t" + "STRD r6, r7, [r0, #56]\n\t" "STRD r4, r5, [sp, #176]\n\t" "STRD r6, r7, [sp, #184]\n\t" - "SUBS %[len], %[len], #0x80\n\t" + "SUBS r2, r2, #0x80\n\t" "SUB r3, r3, #0x200\n\t" - "ADD %[data], %[data], #0x80\n\t" + "ADD r1, r1, #0x80\n\t" #if defined(__GNUC__) "BNE L_SHA512_transform_len_begin_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -3586,18 +3591,28 @@ WC_OMIT_FRAME_POINTER void Transform_Sha512_Len_base(wc_Sha512* sha512, #endif "EOR r0, r0, r0\n\t" "ADD sp, sp, #0xc0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [sha512] "+r" (sha512), [data] "+r" (data), [len] "+r" (len), [L_SHA512_transform_len_k] "+r" (L_SHA512_transform_len_k_c) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [sha512] "r" (sha512), [data] "r" (data), [len] "r" (len), - [L_SHA512_transform_len_k] "r" (L_SHA512_transform_len_k_c) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + sha512 = (wc_Sha512*)(size_t)L_asm_args[0]; + data = (const byte*)(size_t)L_asm_args[1]; + len = (word32)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_ARMASM_NO_NEON */ diff --git a/wolfcrypt/src/sp_cortexm.c b/wolfcrypt/src/sp_cortexm.c index 101c974bf19..39788939d1d 100644 --- a/wolfcrypt/src/sp_cortexm.c +++ b/wolfcrypt/src/sp_cortexm.c @@ -325,352 +325,371 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mul_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #36\n\t" - "STR %[r], [sp, #32]\n\t" - "MOV %[r], #0\n\t" - "LDR r12, [%[a]]\n\t" + "STR r0, [sp, #32]\n\t" + "MOV r0, #0\n\t" + "LDR r12, [r1]\n\t" /* A[0] * B[0] */ - "LDR lr, [%[b]]\n\t" + "LDR lr, [r2]\n\t" "UMULL r3, r4, r12, lr\n\t" /* A[0] * B[2] */ - "LDR lr, [%[b], #8]\n\t" + "LDR lr, [r2, #8]\n\t" "UMULL r5, r6, r12, lr\n\t" /* A[0] * B[4] */ - "LDR lr, [%[b], #16]\n\t" + "LDR lr, [r2, #16]\n\t" "UMULL r7, r8, r12, lr\n\t" /* A[0] * B[6] */ - "LDR lr, [%[b], #24]\n\t" + "LDR lr, [r2, #24]\n\t" "UMULL r9, r10, r12, lr\n\t" "STR r3, [sp]\n\t" /* A[0] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "MOV r11, %[r]\n\t" + "LDR lr, [r2, #4]\n\t" + "MOV r11, r0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[0] * B[3] */ - "LDR lr, [%[b], #12]\n\t" + "LDR lr, [r2, #12]\n\t" "ADCS r6, r6, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[0] * B[5] */ - "LDR lr, [%[b], #20]\n\t" + "LDR lr, [r2, #20]\n\t" "ADCS r8, r8, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[0] * B[7] */ - "LDR lr, [%[b], #28]\n\t" + "LDR lr, [r2, #28]\n\t" "ADCS r10, r10, #0\n\t" - "ADC r3, %[r], #0\n\t" + "ADC r3, r0, #0\n\t" "UMLAL r10, r3, r12, lr\n\t" /* A[1] * B[0] */ - "LDR r12, [%[a], #4]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #4]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "STR r4, [sp, #4]\n\t" "ADDS r5, r5, r11\n\t" /* A[1] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[1] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[1] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[1] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[1] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[1] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[1] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r4, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r4, r0, #0\n\t" "UMLAL r3, r4, r12, lr\n\t" /* A[2] * B[0] */ - "LDR r12, [%[a], #8]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #8]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "STR r5, [sp, #8]\n\t" "ADDS r6, r6, r11\n\t" /* A[2] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[2] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[2] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[2] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[2] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[2] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[2] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r5, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r5, r0, #0\n\t" "UMLAL r4, r5, r12, lr\n\t" /* A[3] * B[0] */ - "LDR r12, [%[a], #12]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #12]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "STR r6, [sp, #12]\n\t" "ADDS r7, r7, r11\n\t" /* A[3] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[3] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[3] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[3] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[3] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[3] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[3] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r6, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r6, r0, #0\n\t" "UMLAL r5, r6, r12, lr\n\t" /* A[4] * B[0] */ - "LDR r12, [%[a], #16]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #16]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "STR r7, [sp, #16]\n\t" "ADDS r8, r8, r11\n\t" /* A[4] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[4] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[4] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[4] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[4] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[4] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[4] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r7, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r7, r0, #0\n\t" "UMLAL r6, r7, r12, lr\n\t" /* A[5] * B[0] */ - "LDR r12, [%[a], #20]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "STR r8, [sp, #20]\n\t" "ADDS r9, r9, r11\n\t" /* A[5] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[5] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[5] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[5] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[5] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[5] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[5] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r8, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r8, r0, #0\n\t" "UMLAL r7, r8, r12, lr\n\t" /* A[6] * B[0] */ - "LDR r12, [%[a], #24]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "STR r9, [sp, #24]\n\t" "ADDS r10, r10, r11\n\t" /* A[6] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[6] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[6] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[6] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[6] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[6] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[6] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r9, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r9, r0, #0\n\t" "UMLAL r8, r9, r12, lr\n\t" /* A[7] * B[0] */ - "LDR r12, [%[a], #28]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "STR r10, [sp, #28]\n\t" "ADDS r3, r3, r11\n\t" /* A[7] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[7] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[7] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[7] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[7] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[7] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[7] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r10, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r10, r0, #0\n\t" "UMLAL r9, r10, r12, lr\n\t" - "LDR %[r], [sp, #32]\n\t" - "ADD %[r], %[r], #32\n\t" - "STM %[r], {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" + "LDR r0, [sp, #32]\n\t" + "ADD r0, r0, #32\n\t" + "STM r0, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "LDM sp, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" - "SUB %[r], %[r], #32\n\t" - "STM %[r], {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" + "SUB r0, r0, #32\n\t" + "STM r0, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "ADD sp, sp, #36\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -692,18 +711,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mul_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #44\n\t" #ifndef WOLFSSL_NO_VAR_ASSIGN_REG - "STRD %[r], %[a], [sp, #36]\n\t" + "STRD r0, r1, [sp, #36]\n\t" #else - "STR %[r], [sp, #36]\n\t" - "STR %[a], [sp, #40]\n\t" + "STR r0, [sp, #36]\n\t" + "STR r1, [sp, #40]\n\t" #endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ - "MOV lr, %[b]\n\t" - "LDM %[a], {r0, r1, r2, r3}\n\t" + "MOV lr, r2\n\t" + "LDM r1, {r0, r1, r2, r3}\n\t" "LDM lr!, {r4, r5, r6}\n\t" "UMULL r10, r11, r0, r4\n\t" "UMULL r12, r7, r1, r4\n\t" @@ -806,16 +833,27 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mul_8(sp_digit* r, "LDM sp, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "STM lr, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "ADD sp, sp, #44\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r10", "r11", "r12", "r7", + "r8", "r9", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r10", "r11", "r12", "r7", - "r8", "r9", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_ARM_ARCH_7M */ @@ -837,34 +875,53 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -884,47 +941,65 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_16(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SUBS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "SBC %[a], r9, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "SBC r0, r9, r9\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -946,48 +1021,67 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_16(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -1072,379 +1166,434 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_32(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - - __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SUBS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "SBC %[a], r9, r9\n\t" -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG - : [a] "+r" (a), [b] "+r" (b) - : #else - : - : [a] "r" (a), [b] "r" (b) -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" - ); - return (word32)(size_t)a; -} - -/* Add b to a into r. (r = a + b) - * - * @param [out] r A single precision integer. - * @param [in] a A single precision integer. - * @param [in] b A single precision integer. - */ -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG -WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_32(sp_digit* r_p, - const sp_digit* a_p, const sp_digit* b_p) -#else -WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_32(sp_digit* r, - const sp_digit* a, const sp_digit* b) -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ -{ -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG - register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; - register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; - register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - - __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" - "ADDS r3, r3, r7\n\t" - "ADCS r4, r4, r8\n\t" - "ADCS r5, r5, r9\n\t" - "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" - "ADCS r3, r3, r7\n\t" - "ADCS r4, r4, r8\n\t" - "ADCS r5, r5, r9\n\t" - "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" - "ADCS r3, r3, r7\n\t" - "ADCS r4, r4, r8\n\t" - "ADCS r5, r5, r9\n\t" - "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" - "ADCS r3, r3, r7\n\t" - "ADCS r4, r4, r8\n\t" - "ADCS r5, r5, r9\n\t" - "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" - "ADCS r3, r3, r7\n\t" - "ADCS r4, r4, r8\n\t" - "ADCS r5, r5, r9\n\t" - "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" - "ADCS r3, r3, r7\n\t" - "ADCS r4, r4, r8\n\t" - "ADCS r5, r5, r9\n\t" - "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" - "ADCS r3, r3, r7\n\t" - "ADCS r4, r4, r8\n\t" - "ADCS r5, r5, r9\n\t" - "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" - "ADCS r3, r3, r7\n\t" - "ADCS r4, r4, r8\n\t" - "ADCS r5, r5, r9\n\t" - "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG - : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) - : -#else - : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" - ); - return (word32)(size_t)r; -} - -/* AND m into each word of a and store in r. - * - * @param [out] r A single precision integer. - * @param [in] a A single precision integer. - * @param [in] m Mask to AND against each digit. - */ -static void sp_2048_mask_16(sp_digit* r, const sp_digit* a, sp_digit m) -{ -#ifdef WOLFSSL_SP_SMALL - int i; - - for (i=0; i<16; i++) { - r[i] = a[i] & m; - } -#else - int i; - - for (i = 0; i < 16; i += 8) { - r[i+0] = a[i+0] & m; - r[i+1] = a[i+1] & m; - r[i+2] = a[i+2] & m; - r[i+3] = a[i+3] & m; - r[i+4] = a[i+4] & m; - r[i+5] = a[i+5] & m; - r[i+6] = a[i+6] & m; - r[i+7] = a[i+7] & m; - } -#endif -} - -/* Multiply a and b into r. (r = a * b) - * - * @param [out] r A single precision integer. - * @param [in] a A single precision integer. - * @param [in] b A single precision integer. - */ -SP_NOINLINE static void sp_2048_mul_32(sp_digit* r, const sp_digit* a, - const sp_digit* b) -{ - sp_digit* z0 = r; - sp_digit z1[32]; - sp_digit a1[16]; - sp_digit b1[16]; - sp_digit* z2 = r + 32; - sp_digit u; - sp_digit ca; - sp_digit cb; - - ca = sp_2048_add_16(a1, a, &a[16]); - cb = sp_2048_add_16(b1, b, &b[16]); - u = ca & cb; - - sp_2048_mul_16(z2, &a[16], &b[16]); - sp_2048_mul_16(z0, a, b); - sp_2048_mul_16(z1, a1, b1); - - u += sp_2048_sub_in_place_32(z1, z0); - u += sp_2048_sub_in_place_32(z1, z2); - sp_2048_mask_16(a1, a1, 0 - cb); - u += sp_2048_add_16(z1 + 16, z1 + 16, a1); - sp_2048_mask_16(b1, b1, 0 - ca); - u += sp_2048_add_16(z1 + 16, z1 + 16, b1); - - u += sp_2048_add_32(r + 16, r + 16, z1); - XMEMSET(a1 + 1, 0, sizeof(sp_digit) * (16 - 1)); - a1[0] = u; - (void)sp_2048_add_16(r + 48, r + 48, a1); -} - -/* Sub b from a into a. (a -= b) - * - * @param [in, out] a A single precision integer and result. - * @param [in] b A single precision integer. - */ -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG -WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_64(sp_digit* a_p, - const sp_digit* b_p) -#else -WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_64(sp_digit* a, - const sp_digit* b) -#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ -{ -#ifndef WOLFSSL_NO_VAR_ASSIGN_REG - register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; - register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SUBS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" - "SBCS r2, r2, r6\n\t" - "SBCS r3, r3, r7\n\t" - "SBCS r4, r4, r8\n\t" - "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "SBC r0, r9, r9\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ +#ifndef WOLFSSL_NO_VAR_ASSIGN_REG + : [a] "+r" (a), [b] "+r" (b) + : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" +#else + : [L_asm_args] "+r" (L_asm_args_p) + : + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" +#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ + ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + return (word32)(size_t)a; +} + +/* Add b to a into r. (r = a + b) + * + * @param [out] r A single precision integer. + * @param [in] a A single precision integer. + * @param [in] b A single precision integer. + */ +#ifndef WOLFSSL_NO_VAR_ASSIGN_REG +WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_32(sp_digit* r_p, + const sp_digit* a_p, const sp_digit* b_p) +#else +WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_32(sp_digit* r, + const sp_digit* a, const sp_digit* b) +#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ +{ +#ifndef WOLFSSL_NO_VAR_ASSIGN_REG + register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; + register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; + register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; +#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ + + __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" + "ADDS r3, r3, r7\n\t" + "ADCS r4, r4, r8\n\t" + "ADCS r5, r5, r9\n\t" + "ADCS r6, r6, r10\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" + "ADCS r3, r3, r7\n\t" + "ADCS r4, r4, r8\n\t" + "ADCS r5, r5, r9\n\t" + "ADCS r6, r6, r10\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" + "ADCS r3, r3, r7\n\t" + "ADCS r4, r4, r8\n\t" + "ADCS r5, r5, r9\n\t" + "ADCS r6, r6, r10\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" + "ADCS r3, r3, r7\n\t" + "ADCS r4, r4, r8\n\t" + "ADCS r5, r5, r9\n\t" + "ADCS r6, r6, r10\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" + "ADCS r3, r3, r7\n\t" + "ADCS r4, r4, r8\n\t" + "ADCS r5, r5, r9\n\t" + "ADCS r6, r6, r10\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" + "ADCS r3, r3, r7\n\t" + "ADCS r4, r4, r8\n\t" + "ADCS r5, r5, r9\n\t" + "ADCS r6, r6, r10\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" + "ADCS r3, r3, r7\n\t" + "ADCS r4, r4, r8\n\t" + "ADCS r5, r5, r9\n\t" + "ADCS r6, r6, r10\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" + "ADCS r3, r3, r7\n\t" + "ADCS r4, r4, r8\n\t" + "ADCS r5, r5, r9\n\t" + "ADCS r6, r6, r10\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ +#ifndef WOLFSSL_NO_VAR_ASSIGN_REG + : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) + : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" +#else + : [L_asm_args] "+r" (L_asm_args_p) + : + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" +#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ + ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + return (word32)(size_t)r; +} + +/* AND m into each word of a and store in r. + * + * @param [out] r A single precision integer. + * @param [in] a A single precision integer. + * @param [in] m Mask to AND against each digit. + */ +static void sp_2048_mask_16(sp_digit* r, const sp_digit* a, sp_digit m) +{ +#ifdef WOLFSSL_SP_SMALL + int i; + + for (i=0; i<16; i++) { + r[i] = a[i] & m; + } +#else + int i; + + for (i = 0; i < 16; i += 8) { + r[i+0] = a[i+0] & m; + r[i+1] = a[i+1] & m; + r[i+2] = a[i+2] & m; + r[i+3] = a[i+3] & m; + r[i+4] = a[i+4] & m; + r[i+5] = a[i+5] & m; + r[i+6] = a[i+6] & m; + r[i+7] = a[i+7] & m; + } +#endif +} + +/* Multiply a and b into r. (r = a * b) + * + * @param [out] r A single precision integer. + * @param [in] a A single precision integer. + * @param [in] b A single precision integer. + */ +SP_NOINLINE static void sp_2048_mul_32(sp_digit* r, const sp_digit* a, + const sp_digit* b) +{ + sp_digit* z0 = r; + sp_digit z1[32]; + sp_digit a1[16]; + sp_digit b1[16]; + sp_digit* z2 = r + 32; + sp_digit u; + sp_digit ca; + sp_digit cb; + + ca = sp_2048_add_16(a1, a, &a[16]); + cb = sp_2048_add_16(b1, b, &b[16]); + u = ca & cb; + + sp_2048_mul_16(z2, &a[16], &b[16]); + sp_2048_mul_16(z0, a, b); + sp_2048_mul_16(z1, a1, b1); + + u += sp_2048_sub_in_place_32(z1, z0); + u += sp_2048_sub_in_place_32(z1, z2); + sp_2048_mask_16(a1, a1, 0 - cb); + u += sp_2048_add_16(z1 + 16, z1 + 16, a1); + sp_2048_mask_16(b1, b1, 0 - ca); + u += sp_2048_add_16(z1 + 16, z1 + 16, b1); + + u += sp_2048_add_32(r + 16, r + 16, z1); + XMEMSET(a1 + 1, 0, sizeof(sp_digit) * (16 - 1)); + a1[0] = u; + (void)sp_2048_add_16(r + 48, r + 48, a1); +} + +/* Sub b from a into a. (a -= b) + * + * @param [in, out] a A single precision integer and result. + * @param [in] b A single precision integer. + */ +#ifndef WOLFSSL_NO_VAR_ASSIGN_REG +WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_64(sp_digit* a_p, + const sp_digit* b_p) +#else +WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_64(sp_digit* a, + const sp_digit* b) +#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ +{ +#ifndef WOLFSSL_NO_VAR_ASSIGN_REG + register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; + register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; +#endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ + + __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SUBS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "SBC %[a], r9, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" + "SBCS r2, r2, r6\n\t" + "SBCS r3, r3, r7\n\t" + "SBCS r4, r4, r8\n\t" + "SBCS r5, r5, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "SBC r0, r9, r9\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -1466,132 +1615,151 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_64(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -1681,153 +1849,161 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_sqr_8(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x44\n\t" - "STR %[r], [sp, #64]\n\t" - "MOV %[r], #0\n\t" - "LDR r12, [%[a]]\n\t" + "STR r0, [sp, #64]\n\t" + "MOV r0, #0\n\t" + "LDR r12, [r1]\n\t" /* A[0] * A[1] */ - "LDR lr, [%[a], #4]\n\t" + "LDR lr, [r1, #4]\n\t" "UMULL r4, r5, r12, lr\n\t" /* A[0] * A[3] */ - "LDR lr, [%[a], #12]\n\t" + "LDR lr, [r1, #12]\n\t" "UMULL r6, r7, r12, lr\n\t" /* A[0] * A[5] */ - "LDR lr, [%[a], #20]\n\t" + "LDR lr, [r1, #20]\n\t" "UMULL r8, r9, r12, lr\n\t" /* A[0] * A[7] */ - "LDR lr, [%[a], #28]\n\t" + "LDR lr, [r1, #28]\n\t" "UMULL r10, r3, r12, lr\n\t" /* A[0] * A[2] */ - "LDR lr, [%[a], #8]\n\t" + "LDR lr, [r1, #8]\n\t" "MOV r11, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[0] * A[4] */ - "LDR lr, [%[a], #16]\n\t" + "LDR lr, [r1, #16]\n\t" "ADCS r7, r7, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[0] * A[6] */ - "LDR lr, [%[a], #24]\n\t" + "LDR lr, [r1, #24]\n\t" "ADCS r9, r9, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" "ADCS r3, r3, #0\n\t" "STR r4, [sp, #4]\n\t" "STR r5, [sp, #8]\n\t" /* A[1] * A[2] */ - "LDR r12, [%[a], #4]\n\t" - "LDR lr, [%[a], #8]\n\t" + "LDR r12, [r1, #4]\n\t" + "LDR lr, [r1, #8]\n\t" "MOV r11, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "STR r6, [sp, #12]\n\t" "ADDS r7, r7, r11\n\t" /* A[1] * A[3] */ - "LDR lr, [%[a], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "STR r7, [sp, #16]\n\t" "ADDS r8, r8, r11\n\t" /* A[1] * A[4] */ - "LDR lr, [%[a], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[1] * A[5] */ - "LDR lr, [%[a], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[1] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[1] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r4, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r4, r0, #0\n\t" "UMLAL r3, r4, r12, lr\n\t" /* A[2] * A[3] */ - "LDR r12, [%[a], #8]\n\t" - "LDR lr, [%[a], #12]\n\t" + "LDR r12, [r1, #8]\n\t" + "LDR lr, [r1, #12]\n\t" "MOV r11, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "STR r8, [sp, #20]\n\t" "ADDS r9, r9, r11\n\t" /* A[2] * A[4] */ - "LDR lr, [%[a], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "STR r9, [sp, #24]\n\t" "ADDS r10, r10, r11\n\t" /* A[2] * A[5] */ - "LDR lr, [%[a], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[2] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[2] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r5, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r5, r0, #0\n\t" "UMLAL r4, r5, r12, lr\n\t" /* A[3] * A[4] */ - "LDR r12, [%[a], #12]\n\t" - "LDR lr, [%[a], #16]\n\t" + "LDR r12, [r1, #12]\n\t" + "LDR lr, [r1, #16]\n\t" "MOV r11, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "STR r10, [sp, #28]\n\t" "ADDS r3, r3, r11\n\t" /* A[3] * A[5] */ - "LDR lr, [%[a], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[3] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[3] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r6, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r6, r0, #0\n\t" "UMLAL r5, r6, r12, lr\n\t" /* A[4] * A[5] */ - "LDR r12, [%[a], #16]\n\t" - "LDR lr, [%[a], #20]\n\t" + "LDR r12, [r1, #16]\n\t" + "LDR lr, [r1, #20]\n\t" "MOV r11, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[4] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[4] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r7, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r7, r0, #0\n\t" "UMLAL r6, r7, r12, lr\n\t" /* A[5] * A[6] */ - "LDR r12, [%[a], #20]\n\t" - "LDR lr, [%[a], #24]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR lr, [r1, #24]\n\t" "MOV r11, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[5] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r8, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r8, r0, #0\n\t" "UMLAL r7, r8, r12, lr\n\t" /* A[6] * A[7] */ - "LDR r12, [%[a], #24]\n\t" - "LDR lr, [%[a], #28]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR lr, [r1, #28]\n\t" "MOV r9, #0\n\t" "UMLAL r8, r9, r12, lr\n\t" "ADD lr, sp, #32\n\t" @@ -1850,75 +2026,85 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_sqr_8(sp_digit* r, "ADCS r7, r7, r7\n\t" "ADCS r8, r8, r8\n\t" "ADCS r9, r9, r9\n\t" - "ADC r10, %[r], #0\n\t" + "ADC r10, r0, #0\n\t" "STM lr, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "ADD lr, sp, #4\n\t" "LDM lr, {r4, r5, r6, r7, r8, r9, r10}\n\t" "MOV lr, sp\n\t" /* A[0] * A[0] */ - "LDR r12, [%[a]]\n\t" + "LDR r12, [r1]\n\t" "UMULL r3, r11, r12, r12\n\t" "ADDS r4, r4, r11\n\t" /* A[1] * A[1] */ - "LDR r12, [%[a], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "ADCS r5, r5, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, r12\n\t" "ADDS r6, r6, r11\n\t" /* A[2] * A[2] */ - "LDR r12, [%[a], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "ADCS r7, r7, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, r12\n\t" "ADDS r8, r8, r11\n\t" /* A[3] * A[3] */ - "LDR r12, [%[a], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "ADCS r9, r9, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, r12\n\t" "ADDS r10, r10, r11\n\t" "STM lr!, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "LDM lr, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" /* A[4] * A[4] */ - "LDR r12, [%[a], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "ADCS r3, r3, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, r12\n\t" "ADDS r4, r4, r11\n\t" /* A[5] * A[5] */ - "LDR r12, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" "ADCS r5, r5, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, r12\n\t" "ADDS r6, r6, r11\n\t" /* A[6] * A[6] */ - "LDR r12, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" "ADCS r7, r7, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, r12\n\t" "ADDS r8, r8, r11\n\t" /* A[7] * A[7] */ - "LDR r12, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" "ADCS r9, r9, #0\n\t" "ADC r10, r10, #0\n\t" "UMLAL r9, r10, r12, r12\n\t" - "LDR %[r], [sp, #64]\n\t" - "ADD %[r], %[r], #32\n\t" - "STM %[r], {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" + "LDR r0, [sp, #64]\n\t" + "ADD r0, r0, #32\n\t" + "STM r0, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "LDM sp, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" - "SUB %[r], %[r], #32\n\t" - "STM %[r], {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" + "SUB r0, r0, #32\n\t" + "STM r0, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "ADD sp, sp, #0x44\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -1938,12 +2124,20 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_sqr_8(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #32\n\t" - "STR %[r], [sp, #28]\n\t" - "LDM %[a], {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" + "STR r0, [sp, #28]\n\t" + "LDM r1, {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" "UMULL r9, r10, r0, r0\n\t" "UMULL r11, r12, r0, r1\n\t" "ADDS r11, r11, r11\n\t" @@ -2034,16 +2228,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_sqr_8(sp_digit* r, "LDM sp, {r0, r1, r2, r3, r4, r5, r6}\n\t" "STM lr, {r0, r1, r2, r3, r4, r5, r6}\n\t" "ADD sp, sp, #32\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_ARM_ARCH_7M */ @@ -2065,33 +2269,52 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -2149,47 +2372,66 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_16(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -2247,75 +2489,94 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_32(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -2375,11 +2636,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_64(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r3, #0\n\t" - "ADD r12, %[a], #0x100\n\t" + "ADD r12, r1, #0x100\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_2048_add_64_word:\n\t" @@ -2387,16 +2656,16 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_64(sp_digit* r, "L_sp_2048_add_64_word_%=:\n\t" #endif "ADDS r3, r3, #0xffffffff\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "MOV r4, #0\n\t" "ADC r3, r4, #0\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_2048_add_64_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2404,17 +2673,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_64(sp_digit* r, #else "BNE.N L_sp_2048_add_64_word_%=\n\t" #endif - "MOV %[r], r3\n\t" + "MOV r0, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -2436,11 +2716,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_64(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "ADD r11, %[a], #0x100\n\t" + "ADD r11, r0, #0x100\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_2048_sub_in_place_64_word:\n\t" @@ -2448,15 +2736,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_64(sp_digit* a, "L_sp_2048_sub_in_place_64_word_%=:\n\t" #endif "RSBS r10, r10, #0\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" "SBC r10, r10, r10\n\t" - "CMP %[a], r11\n\t" + "CMP r0, r11\n\t" #if defined(__GNUC__) "BNE L_sp_2048_sub_in_place_64_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2464,17 +2752,27 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_64(sp_digit* a, #else "BNE.N L_sp_2048_sub_in_place_64_word_%=\n\t" #endif - "MOV %[a], r10\n\t" + "MOV r0, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -2498,12 +2796,20 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_64(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x200\n\t" - "LDR lr, [%[a]]\n\t" - "LDR r11, [%[b]]\n\t" + "LDR lr, [r1]\n\t" + "LDR r11, [r2]\n\t" "UMULL r8, r6, lr, r11\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -2525,14 +2831,14 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_64(sp_digit* r, const sp_digit* a, #else "L_sp_2048_mul_64_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" "ADC r8, r8, #0\n\t" - "LDR lr, [%[a], r4]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r4]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -2554,8 +2860,8 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_64(sp_digit* r, const sp_digit* a, #else "BLT.N L_sp_2048_mul_64_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -2579,8 +2885,8 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_64(sp_digit* r, const sp_digit* a, #else "BLE.N L_sp_2048_mul_64_outer_%=\n\t" #endif - "LDR lr, [%[a], #252]\n\t" - "LDR r11, [%[b], #252]\n\t" + "LDR lr, [r1, #252]\n\t" + "LDR r11, [r2, #252]\n\t" "UMLAL r6, r7, lr, r11\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -2592,7 +2898,7 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_64(sp_digit* r, const sp_digit* a, "L_sp_2048_mul_64_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_2048_mul_64_store_%=\n\t" @@ -2601,16 +2907,27 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_64(sp_digit* r, const sp_digit* a, #else "BGT.N L_sp_2048_mul_64_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Square a and put result in r. (r = a * a) @@ -2628,11 +2945,19 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_64(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x200\n\t" - "LDR lr, [%[a]]\n\t" + "LDR lr, [r1]\n\t" "UMULL r8, r6, lr, lr\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -2654,8 +2979,8 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_64(sp_digit* r, const sp_digit* a) #else "L_sp_2048_sqr_64_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[a], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r1, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -2680,7 +3005,7 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_64(sp_digit* r, const sp_digit* a) #else "BLT.N L_sp_2048_sqr_64_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" + "LDR lr, [r1, r3]\n\t" "UMULL r9, r10, lr, lr\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -2704,7 +3029,7 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_64(sp_digit* r, const sp_digit* a) #else "BLE.N L_sp_2048_sqr_64_outer_%=\n\t" #endif - "LDR lr, [%[a], #252]\n\t" + "LDR lr, [r1, #252]\n\t" "UMLAL r6, r7, lr, lr\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -2716,7 +3041,7 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_64(sp_digit* r, const sp_digit* a) "L_sp_2048_sqr_64_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_2048_sqr_64_store_%=\n\t" @@ -2725,16 +3050,26 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_64(sp_digit* r, const sp_digit* a) #else "BGT.N L_sp_2048_sqr_64_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -2775,11 +3110,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_32(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r3, #0\n\t" - "ADD r12, %[a], #0x80\n\t" + "ADD r12, r1, #0x80\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_2048_add_32_word:\n\t" @@ -2787,16 +3130,16 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_32(sp_digit* r, "L_sp_2048_add_32_word_%=:\n\t" #endif "ADDS r3, r3, #0xffffffff\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "MOV r4, #0\n\t" "ADC r3, r4, #0\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_2048_add_32_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2804,17 +3147,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_add_32(sp_digit* r, #else "BNE.N L_sp_2048_add_32_word_%=\n\t" #endif - "MOV %[r], r3\n\t" + "MOV r0, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -2836,11 +3190,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_32(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "ADD r11, %[a], #0x80\n\t" + "ADD r11, r0, #0x80\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_2048_sub_in_place_32_word:\n\t" @@ -2848,15 +3210,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_32(sp_digit* a, "L_sp_2048_sub_in_place_32_word_%=:\n\t" #endif "RSBS r10, r10, #0\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" "SBC r10, r10, r10\n\t" - "CMP %[a], r11\n\t" + "CMP r0, r11\n\t" #if defined(__GNUC__) "BNE L_sp_2048_sub_in_place_32_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -2864,17 +3226,27 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_in_place_32(sp_digit* a, #else "BNE.N L_sp_2048_sub_in_place_32_word_%=\n\t" #endif - "MOV %[a], r10\n\t" + "MOV r0, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -2898,12 +3270,20 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_32(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x100\n\t" - "LDR lr, [%[a]]\n\t" - "LDR r11, [%[b]]\n\t" + "LDR lr, [r1]\n\t" + "LDR r11, [r2]\n\t" "UMULL r8, r6, lr, r11\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -2925,14 +3305,14 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_32(sp_digit* r, const sp_digit* a, #else "L_sp_2048_mul_32_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" "ADC r8, r8, #0\n\t" - "LDR lr, [%[a], r4]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r4]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -2954,8 +3334,8 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_32(sp_digit* r, const sp_digit* a, #else "BLT.N L_sp_2048_mul_32_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -2979,8 +3359,8 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_32(sp_digit* r, const sp_digit* a, #else "BLE.N L_sp_2048_mul_32_outer_%=\n\t" #endif - "LDR lr, [%[a], #124]\n\t" - "LDR r11, [%[b], #124]\n\t" + "LDR lr, [r1, #124]\n\t" + "LDR r11, [r2, #124]\n\t" "UMLAL r6, r7, lr, r11\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -2992,7 +3372,7 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_32(sp_digit* r, const sp_digit* a, "L_sp_2048_mul_32_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_2048_mul_32_store_%=\n\t" @@ -3001,16 +3381,27 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_32(sp_digit* r, const sp_digit* a, #else "BGT.N L_sp_2048_mul_32_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Square a and put result in r. (r = a * a) @@ -3028,11 +3419,19 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_32(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x100\n\t" - "LDR lr, [%[a]]\n\t" + "LDR lr, [r1]\n\t" "UMULL r8, r6, lr, lr\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -3054,8 +3453,8 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_32(sp_digit* r, const sp_digit* a) #else "L_sp_2048_sqr_32_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[a], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r1, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -3080,7 +3479,7 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_32(sp_digit* r, const sp_digit* a) #else "BLT.N L_sp_2048_sqr_32_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" + "LDR lr, [r1, r3]\n\t" "UMULL r9, r10, lr, lr\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -3104,7 +3503,7 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_32(sp_digit* r, const sp_digit* a) #else "BLE.N L_sp_2048_sqr_32_outer_%=\n\t" #endif - "LDR lr, [%[a], #124]\n\t" + "LDR lr, [r1, #124]\n\t" "UMLAL r6, r7, lr, lr\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -3116,7 +3515,7 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_32(sp_digit* r, const sp_digit* a) "L_sp_2048_sqr_32_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_2048_sqr_32_store_%=\n\t" @@ -3125,16 +3524,26 @@ WC_OMIT_FRAME_POINTER static void sp_2048_sqr_32(sp_digit* r, const sp_digit* a) #else "BGT.N L_sp_2048_sqr_32_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -3179,14 +3588,22 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_d_64(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDR r8, [%[a]]\n\t" - "UMULL r5, r3, %[b], r8\n\t" + "LDR r8, [r1]\n\t" + "UMULL r5, r3, r2, r8\n\t" "MOV r4, #0\n\t" - "STR r5, [%[r]]\n\t" + "STR r5, [r0]\n\t" "MOV r5, #0\n\t" "MOV r9, #4\n\t" "\n" @@ -3196,12 +3613,12 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_d_64(sp_digit* r, "L_sp_2048_mul_d_64_word_%=:\n\t" #endif /* A[i] * B */ - "LDR r8, [%[a], r9]\n\t" - "UMULL r6, r7, %[b], r8\n\t" + "LDR r8, [r1, r9]\n\t" + "UMULL r6, r7, r2, r8\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], r9]\n\t" + "STR r3, [r0, r9]\n\t" "MOV r3, r4\n\t" "MOV r4, r5\n\t" "MOV r5, #0\n\t" @@ -3214,16 +3631,27 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_d_64(sp_digit* r, #else "BLT.N L_sp_2048_mul_d_64_word_%=\n\t" #endif - "STR r3, [%[r], #256]\n\t" + "STR r3, [r0, #256]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -3245,338 +3673,357 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_d_64(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDM %[a]!, {r8}\n\t" - "UMULL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMULL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[1] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[2] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[3] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[4] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[5] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[6] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[7] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[8] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[9] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[10] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[11] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[12] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[13] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[14] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[15] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[16] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[17] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[18] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[19] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[20] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[21] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[22] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[23] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[24] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[25] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[26] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[27] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[28] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[29] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[30] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[31] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[32] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[33] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[34] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[35] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[36] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[37] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[38] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[39] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[40] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[41] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[42] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[43] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[44] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[45] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[46] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[47] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[48] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[49] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[50] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[51] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[52] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[53] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[54] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[55] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[56] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[57] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[58] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[59] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[60] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[61] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[62] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[63] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" - "STR r4, [%[r]]\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" + "STR r4, [r0]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -3618,9 +4065,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_sub_32(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, #0\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -3631,12 +4087,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_sub_32(sp_digit* r, "L_sp_2048_cond_sub_32_words_%=:\n\t" #endif "SUBS r4, r8, r4\n\t" - "LDR r6, [%[a], r5]\n\t" - "LDR r7, [%[b], r5]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r5]\n\t" + "LDR r7, [r2, r5]\n\t" + "AND r7, r7, r3\n\t" "SBCS r6, r6, r7\n\t" "SBC r4, r8, r8\n\t" - "STR r6, [%[r], r5]\n\t" + "STR r6, [r0, r5]\n\t" "ADD r5, r5, #4\n\t" "CMP r5, #0x80\n\t" #if defined(__GNUC__) @@ -3646,16 +4102,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_sub_32(sp_digit* r, #else "BLT.N L_sp_2048_cond_sub_32_words_%=\n\t" #endif - "MOV %[r], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -3682,132 +4150,153 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_sub_32(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SUBS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "SBC %[r], r5, r5\n\t" + "STM r0!, {r6, r7}\n\t" + "SBC r0, r5, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -3833,15 +4322,24 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR lr, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR lr, [r1]\n\t" /* i = 0 */ "MOV r11, #0\n\t" "MOV r3, #0\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[a], #4]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_2048_mont_reduce_32_word:\n\t" @@ -3849,265 +4347,265 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( "L_sp_2048_mont_reduce_32_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL r10, %[mp], r4\n\t" + "MUL r10, r2, r4\n\t" /* a[i+0] += m[0] * mu */ "MOV r7, #0\n\t" "UMLAL r4, r7, r10, lr\n\t" /* a[i+1] += m[1] * mu */ - "LDR r9, [%[m], #4]\n\t" + "LDR r9, [r1, #4]\n\t" "MOV r6, #0\n\t" "UMLAL r5, r6, r10, r9\n\t" "MOV r4, r5\n\t" "ADDS r4, r4, r7\n\t" "ADC r6, r6, #0\n\t" /* a[i+2] += m[2] * mu */ - "LDR r9, [%[m], #8]\n\t" - "LDR r5, [%[a], #8]\n\t" + "LDR r9, [r1, #8]\n\t" + "LDR r5, [r0, #8]\n\t" "MOV r7, #0\n\t" "UMLAL r5, r7, r10, r9\n\t" "ADDS r5, r5, r6\n\t" "ADC r7, r7, #0\n\t" /* a[i+3] += m[3] * mu */ - "LDR r9, [%[m], #12]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r9, [r1, #12]\n\t" + "LDR r12, [r0, #12]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #12]\n\t" + "STR r12, [r0, #12]\n\t" "ADC r6, r6, #0\n\t" /* a[i+4] += m[4] * mu */ - "LDR r9, [%[m], #16]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r9, [r1, #16]\n\t" + "LDR r12, [r0, #16]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #16]\n\t" + "STR r12, [r0, #16]\n\t" "ADC r7, r7, #0\n\t" /* a[i+5] += m[5] * mu */ - "LDR r9, [%[m], #20]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r12, [r0, #20]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #20]\n\t" + "STR r12, [r0, #20]\n\t" "ADC r6, r6, #0\n\t" /* a[i+6] += m[6] * mu */ - "LDR r9, [%[m], #24]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r9, [r1, #24]\n\t" + "LDR r12, [r0, #24]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #24]\n\t" + "STR r12, [r0, #24]\n\t" "ADC r7, r7, #0\n\t" /* a[i+7] += m[7] * mu */ - "LDR r9, [%[m], #28]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r9, [r1, #28]\n\t" + "LDR r12, [r0, #28]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #28]\n\t" + "STR r12, [r0, #28]\n\t" "ADC r6, r6, #0\n\t" /* a[i+8] += m[8] * mu */ - "LDR r9, [%[m], #32]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r9, [r1, #32]\n\t" + "LDR r12, [r0, #32]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #32]\n\t" + "STR r12, [r0, #32]\n\t" "ADC r7, r7, #0\n\t" /* a[i+9] += m[9] * mu */ - "LDR r9, [%[m], #36]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r9, [r1, #36]\n\t" + "LDR r12, [r0, #36]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #36]\n\t" + "STR r12, [r0, #36]\n\t" "ADC r6, r6, #0\n\t" /* a[i+10] += m[10] * mu */ - "LDR r9, [%[m], #40]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r9, [r1, #40]\n\t" + "LDR r12, [r0, #40]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #40]\n\t" + "STR r12, [r0, #40]\n\t" "ADC r7, r7, #0\n\t" /* a[i+11] += m[11] * mu */ - "LDR r9, [%[m], #44]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r9, [r1, #44]\n\t" + "LDR r12, [r0, #44]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #44]\n\t" + "STR r12, [r0, #44]\n\t" "ADC r6, r6, #0\n\t" /* a[i+12] += m[12] * mu */ - "LDR r9, [%[m], #48]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r9, [r1, #48]\n\t" + "LDR r12, [r0, #48]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #48]\n\t" + "STR r12, [r0, #48]\n\t" "ADC r7, r7, #0\n\t" /* a[i+13] += m[13] * mu */ - "LDR r9, [%[m], #52]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r9, [r1, #52]\n\t" + "LDR r12, [r0, #52]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #52]\n\t" + "STR r12, [r0, #52]\n\t" "ADC r6, r6, #0\n\t" /* a[i+14] += m[14] * mu */ - "LDR r9, [%[m], #56]\n\t" - "LDR r12, [%[a], #56]\n\t" + "LDR r9, [r1, #56]\n\t" + "LDR r12, [r0, #56]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #56]\n\t" + "STR r12, [r0, #56]\n\t" "ADC r7, r7, #0\n\t" /* a[i+15] += m[15] * mu */ - "LDR r9, [%[m], #60]\n\t" - "LDR r12, [%[a], #60]\n\t" + "LDR r9, [r1, #60]\n\t" + "LDR r12, [r0, #60]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #60]\n\t" + "STR r12, [r0, #60]\n\t" "ADC r6, r6, #0\n\t" /* a[i+16] += m[16] * mu */ - "LDR r9, [%[m], #64]\n\t" - "LDR r12, [%[a], #64]\n\t" + "LDR r9, [r1, #64]\n\t" + "LDR r12, [r0, #64]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #64]\n\t" + "STR r12, [r0, #64]\n\t" "ADC r7, r7, #0\n\t" /* a[i+17] += m[17] * mu */ - "LDR r9, [%[m], #68]\n\t" - "LDR r12, [%[a], #68]\n\t" + "LDR r9, [r1, #68]\n\t" + "LDR r12, [r0, #68]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #68]\n\t" + "STR r12, [r0, #68]\n\t" "ADC r6, r6, #0\n\t" /* a[i+18] += m[18] * mu */ - "LDR r9, [%[m], #72]\n\t" - "LDR r12, [%[a], #72]\n\t" + "LDR r9, [r1, #72]\n\t" + "LDR r12, [r0, #72]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #72]\n\t" + "STR r12, [r0, #72]\n\t" "ADC r7, r7, #0\n\t" /* a[i+19] += m[19] * mu */ - "LDR r9, [%[m], #76]\n\t" - "LDR r12, [%[a], #76]\n\t" + "LDR r9, [r1, #76]\n\t" + "LDR r12, [r0, #76]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #76]\n\t" + "STR r12, [r0, #76]\n\t" "ADC r6, r6, #0\n\t" /* a[i+20] += m[20] * mu */ - "LDR r9, [%[m], #80]\n\t" - "LDR r12, [%[a], #80]\n\t" + "LDR r9, [r1, #80]\n\t" + "LDR r12, [r0, #80]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #80]\n\t" + "STR r12, [r0, #80]\n\t" "ADC r7, r7, #0\n\t" /* a[i+21] += m[21] * mu */ - "LDR r9, [%[m], #84]\n\t" - "LDR r12, [%[a], #84]\n\t" + "LDR r9, [r1, #84]\n\t" + "LDR r12, [r0, #84]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #84]\n\t" + "STR r12, [r0, #84]\n\t" "ADC r6, r6, #0\n\t" /* a[i+22] += m[22] * mu */ - "LDR r9, [%[m], #88]\n\t" - "LDR r12, [%[a], #88]\n\t" + "LDR r9, [r1, #88]\n\t" + "LDR r12, [r0, #88]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #88]\n\t" + "STR r12, [r0, #88]\n\t" "ADC r7, r7, #0\n\t" /* a[i+23] += m[23] * mu */ - "LDR r9, [%[m], #92]\n\t" - "LDR r12, [%[a], #92]\n\t" + "LDR r9, [r1, #92]\n\t" + "LDR r12, [r0, #92]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #92]\n\t" + "STR r12, [r0, #92]\n\t" "ADC r6, r6, #0\n\t" /* a[i+24] += m[24] * mu */ - "LDR r9, [%[m], #96]\n\t" - "LDR r12, [%[a], #96]\n\t" + "LDR r9, [r1, #96]\n\t" + "LDR r12, [r0, #96]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #96]\n\t" + "STR r12, [r0, #96]\n\t" "ADC r7, r7, #0\n\t" /* a[i+25] += m[25] * mu */ - "LDR r9, [%[m], #100]\n\t" - "LDR r12, [%[a], #100]\n\t" + "LDR r9, [r1, #100]\n\t" + "LDR r12, [r0, #100]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #100]\n\t" + "STR r12, [r0, #100]\n\t" "ADC r6, r6, #0\n\t" /* a[i+26] += m[26] * mu */ - "LDR r9, [%[m], #104]\n\t" - "LDR r12, [%[a], #104]\n\t" + "LDR r9, [r1, #104]\n\t" + "LDR r12, [r0, #104]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #104]\n\t" + "STR r12, [r0, #104]\n\t" "ADC r7, r7, #0\n\t" /* a[i+27] += m[27] * mu */ - "LDR r9, [%[m], #108]\n\t" - "LDR r12, [%[a], #108]\n\t" + "LDR r9, [r1, #108]\n\t" + "LDR r12, [r0, #108]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #108]\n\t" + "STR r12, [r0, #108]\n\t" "ADC r6, r6, #0\n\t" /* a[i+28] += m[28] * mu */ - "LDR r9, [%[m], #112]\n\t" - "LDR r12, [%[a], #112]\n\t" + "LDR r9, [r1, #112]\n\t" + "LDR r12, [r0, #112]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #112]\n\t" + "STR r12, [r0, #112]\n\t" "ADC r7, r7, #0\n\t" /* a[i+29] += m[29] * mu */ - "LDR r9, [%[m], #116]\n\t" - "LDR r12, [%[a], #116]\n\t" + "LDR r9, [r1, #116]\n\t" + "LDR r12, [r0, #116]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #116]\n\t" + "STR r12, [r0, #116]\n\t" "ADC r6, r6, #0\n\t" /* a[i+30] += m[30] * mu */ - "LDR r9, [%[m], #120]\n\t" - "LDR r12, [%[a], #120]\n\t" + "LDR r9, [r1, #120]\n\t" + "LDR r12, [r0, #120]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #120]\n\t" + "STR r12, [r0, #120]\n\t" "ADC r7, r7, #0\n\t" /* a[i+31] += m[31] * mu */ - "LDR r9, [%[m], #124]\n\t" - "LDR r12, [%[a], #124]\n\t" + "LDR r9, [r1, #124]\n\t" + "LDR r12, [r0, #124]\n\t" "UMULL r8, r9, r10, r9\n\t" "ADDS r7, r7, r8\n\t" "ADCS r6, r9, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, r3\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #124]\n\t" - "LDR r12, [%[a], #128]\n\t" + "STR r12, [r0, #124]\n\t" + "LDR r12, [r0, #128]\n\t" "ADCS r12, r12, r6\n\t" - "STR r12, [%[a], #128]\n\t" + "STR r12, [r0, #128]\n\t" "ADC r3, r3, #0\n\t" /* i += 1 */ "ADD r11, r11, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r11, #0x80\n\t" #if defined(__GNUC__) "BLT L_sp_2048_mont_reduce_32_word_%=\n\t" @@ -4117,19 +4615,30 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( "BLT.W L_sp_2048_mont_reduce_32_word_%=\n\t" #endif /* Loop Done */ - "STR r4, [%[a]]\n\t" - "STR r5, [%[a], #4]\n\t" - "MOV %[mp], r3\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_2048_cond_sub_32(a - 32, a, m, (sp_digit)0 - mp); } @@ -4153,10 +4662,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r11, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r11, [r1]\n\t" /* i = 0 */ "MOV r9, #0\n\t" /* ca = 0 */ @@ -4168,8 +4686,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( "L_sp_2048_mont_reduce_32_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "LDR r10, [%[a]]\n\t" - "MUL r8, %[mp], r10\n\t" + "LDR r10, [r0]\n\t" + "MUL r8, r2, r10\n\t" /* j = 0 */ "MOV r12, #0\n\t" "MOV r4, #0\n\t" @@ -4180,42 +4698,42 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( "L_sp_2048_mont_reduce_32_mul_%=:\n\t" #endif /* a[i+j+0] += m[j+0] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+1] += m[j+1] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+2] += m[j+2] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+3] += m[j+3] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" @@ -4227,16 +4745,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( #else "BLT.N L_sp_2048_mont_reduce_32_mul_%=\n\t" #endif - "LDR r10, [%[a], #128]\n\t" + "LDR r10, [r0, #128]\n\t" "ADDS r4, r4, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" "ADDS r10, r10, r4\n\t" "ADC r3, r3, r3\n\t" - "STR r10, [%[a], #128]\n\t" + "STR r10, [r0, #128]\n\t" /* i += 1 */ "ADD r9, r9, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r9, #0x80\n\t" #if defined(__GNUC__) "BLT L_sp_2048_mont_reduce_32_word_%=\n\t" @@ -4246,17 +4764,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( "BLT.N L_sp_2048_mont_reduce_32_word_%=\n\t" #endif /* Loop Done */ - "MOV %[mp], r3\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_2048_cond_sub_32(a - 32, a, m, (sp_digit)0 - mp); } @@ -4282,17 +4811,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* i = 0 */ "MOV r4, #0\n\t" "MOV r5, #0\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r7, [%[a], #4]\n\t" - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[a], #12]\n\t" - "LDR r10, [%[a], #16]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" + "LDR r10, [r0, #16]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_2048_mont_reduce_32_word:\n\t" @@ -4300,170 +4838,170 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( "L_sp_2048_mont_reduce_32_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL lr, %[mp], r6\n\t" + "MUL lr, r2, r6\n\t" /* a[i+0] += m[0] * mu */ - "LDR r12, [%[m]]\n\t" + "LDR r12, [r1]\n\t" "MOV r3, #0\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+1] += m[1] * mu */ - "LDR r12, [%[m], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "MOV r6, r7\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+2] += m[2] * mu */ - "LDR r12, [%[m], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "MOV r7, r8\n\t" "UMAAL r7, r3, lr, r12\n\t" /* a[i+3] += m[3] * mu */ - "LDR r12, [%[m], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "MOV r8, r9\n\t" "UMAAL r8, r3, lr, r12\n\t" /* a[i+4] += m[4] * mu */ - "LDR r12, [%[m], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "MOV r9, r10\n\t" "UMAAL r9, r3, lr, r12\n\t" /* a[i+5] += m[5] * mu */ - "LDR r12, [%[m], #20]\n\t" - "LDR r10, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR r10, [r0, #20]\n\t" "UMAAL r10, r3, lr, r12\n\t" /* a[i+6] += m[6] * mu */ - "LDR r12, [%[m], #24]\n\t" - "LDR r11, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR r11, [r0, #24]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #24]\n\t" + "STR r11, [r0, #24]\n\t" /* a[i+7] += m[7] * mu */ - "LDR r12, [%[m], #28]\n\t" - "LDR r11, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR r11, [r0, #28]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #28]\n\t" + "STR r11, [r0, #28]\n\t" /* a[i+8] += m[8] * mu */ - "LDR r12, [%[m], #32]\n\t" - "LDR r11, [%[a], #32]\n\t" + "LDR r12, [r1, #32]\n\t" + "LDR r11, [r0, #32]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #32]\n\t" + "STR r11, [r0, #32]\n\t" /* a[i+9] += m[9] * mu */ - "LDR r12, [%[m], #36]\n\t" - "LDR r11, [%[a], #36]\n\t" + "LDR r12, [r1, #36]\n\t" + "LDR r11, [r0, #36]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #36]\n\t" + "STR r11, [r0, #36]\n\t" /* a[i+10] += m[10] * mu */ - "LDR r12, [%[m], #40]\n\t" - "LDR r11, [%[a], #40]\n\t" + "LDR r12, [r1, #40]\n\t" + "LDR r11, [r0, #40]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #40]\n\t" + "STR r11, [r0, #40]\n\t" /* a[i+11] += m[11] * mu */ - "LDR r12, [%[m], #44]\n\t" - "LDR r11, [%[a], #44]\n\t" + "LDR r12, [r1, #44]\n\t" + "LDR r11, [r0, #44]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #44]\n\t" + "STR r11, [r0, #44]\n\t" /* a[i+12] += m[12] * mu */ - "LDR r12, [%[m], #48]\n\t" - "LDR r11, [%[a], #48]\n\t" + "LDR r12, [r1, #48]\n\t" + "LDR r11, [r0, #48]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #48]\n\t" + "STR r11, [r0, #48]\n\t" /* a[i+13] += m[13] * mu */ - "LDR r12, [%[m], #52]\n\t" - "LDR r11, [%[a], #52]\n\t" + "LDR r12, [r1, #52]\n\t" + "LDR r11, [r0, #52]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #52]\n\t" + "STR r11, [r0, #52]\n\t" /* a[i+14] += m[14] * mu */ - "LDR r12, [%[m], #56]\n\t" - "LDR r11, [%[a], #56]\n\t" + "LDR r12, [r1, #56]\n\t" + "LDR r11, [r0, #56]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #56]\n\t" + "STR r11, [r0, #56]\n\t" /* a[i+15] += m[15] * mu */ - "LDR r12, [%[m], #60]\n\t" - "LDR r11, [%[a], #60]\n\t" + "LDR r12, [r1, #60]\n\t" + "LDR r11, [r0, #60]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #60]\n\t" + "STR r11, [r0, #60]\n\t" /* a[i+16] += m[16] * mu */ - "LDR r12, [%[m], #64]\n\t" - "LDR r11, [%[a], #64]\n\t" + "LDR r12, [r1, #64]\n\t" + "LDR r11, [r0, #64]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #64]\n\t" + "STR r11, [r0, #64]\n\t" /* a[i+17] += m[17] * mu */ - "LDR r12, [%[m], #68]\n\t" - "LDR r11, [%[a], #68]\n\t" + "LDR r12, [r1, #68]\n\t" + "LDR r11, [r0, #68]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #68]\n\t" + "STR r11, [r0, #68]\n\t" /* a[i+18] += m[18] * mu */ - "LDR r12, [%[m], #72]\n\t" - "LDR r11, [%[a], #72]\n\t" + "LDR r12, [r1, #72]\n\t" + "LDR r11, [r0, #72]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #72]\n\t" + "STR r11, [r0, #72]\n\t" /* a[i+19] += m[19] * mu */ - "LDR r12, [%[m], #76]\n\t" - "LDR r11, [%[a], #76]\n\t" + "LDR r12, [r1, #76]\n\t" + "LDR r11, [r0, #76]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #76]\n\t" + "STR r11, [r0, #76]\n\t" /* a[i+20] += m[20] * mu */ - "LDR r12, [%[m], #80]\n\t" - "LDR r11, [%[a], #80]\n\t" + "LDR r12, [r1, #80]\n\t" + "LDR r11, [r0, #80]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #80]\n\t" + "STR r11, [r0, #80]\n\t" /* a[i+21] += m[21] * mu */ - "LDR r12, [%[m], #84]\n\t" - "LDR r11, [%[a], #84]\n\t" + "LDR r12, [r1, #84]\n\t" + "LDR r11, [r0, #84]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #84]\n\t" + "STR r11, [r0, #84]\n\t" /* a[i+22] += m[22] * mu */ - "LDR r12, [%[m], #88]\n\t" - "LDR r11, [%[a], #88]\n\t" + "LDR r12, [r1, #88]\n\t" + "LDR r11, [r0, #88]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #88]\n\t" + "STR r11, [r0, #88]\n\t" /* a[i+23] += m[23] * mu */ - "LDR r12, [%[m], #92]\n\t" - "LDR r11, [%[a], #92]\n\t" + "LDR r12, [r1, #92]\n\t" + "LDR r11, [r0, #92]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #92]\n\t" + "STR r11, [r0, #92]\n\t" /* a[i+24] += m[24] * mu */ - "LDR r12, [%[m], #96]\n\t" - "LDR r11, [%[a], #96]\n\t" + "LDR r12, [r1, #96]\n\t" + "LDR r11, [r0, #96]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #96]\n\t" + "STR r11, [r0, #96]\n\t" /* a[i+25] += m[25] * mu */ - "LDR r12, [%[m], #100]\n\t" - "LDR r11, [%[a], #100]\n\t" + "LDR r12, [r1, #100]\n\t" + "LDR r11, [r0, #100]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #100]\n\t" + "STR r11, [r0, #100]\n\t" /* a[i+26] += m[26] * mu */ - "LDR r12, [%[m], #104]\n\t" - "LDR r11, [%[a], #104]\n\t" + "LDR r12, [r1, #104]\n\t" + "LDR r11, [r0, #104]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #104]\n\t" + "STR r11, [r0, #104]\n\t" /* a[i+27] += m[27] * mu */ - "LDR r12, [%[m], #108]\n\t" - "LDR r11, [%[a], #108]\n\t" + "LDR r12, [r1, #108]\n\t" + "LDR r11, [r0, #108]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #108]\n\t" + "STR r11, [r0, #108]\n\t" /* a[i+28] += m[28] * mu */ - "LDR r12, [%[m], #112]\n\t" - "LDR r11, [%[a], #112]\n\t" + "LDR r12, [r1, #112]\n\t" + "LDR r11, [r0, #112]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #112]\n\t" + "STR r11, [r0, #112]\n\t" /* a[i+29] += m[29] * mu */ - "LDR r12, [%[m], #116]\n\t" - "LDR r11, [%[a], #116]\n\t" + "LDR r12, [r1, #116]\n\t" + "LDR r11, [r0, #116]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #116]\n\t" + "STR r11, [r0, #116]\n\t" /* a[i+30] += m[30] * mu */ - "LDR r12, [%[m], #120]\n\t" - "LDR r11, [%[a], #120]\n\t" + "LDR r12, [r1, #120]\n\t" + "LDR r11, [r0, #120]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #120]\n\t" + "STR r11, [r0, #120]\n\t" /* a[i+31] += m[31] * mu */ - "LDR r12, [%[m], #124]\n\t" - "LDR r11, [%[a], #124]\n\t" + "LDR r12, [r1, #124]\n\t" + "LDR r11, [r0, #124]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "LDR lr, [%[a], #128]\n\t" + "LDR lr, [r0, #128]\n\t" "MOV r12, #0\n\t" "UMAAL r3, lr, r12, r12\n\t" - "STR r11, [%[a], #124]\n\t" + "STR r11, [r0, #124]\n\t" "ADDS r3, r3, r5\n\t" "ADC r5, lr, #0\n\t" - "STR r3, [%[a], #128]\n\t" + "STR r3, [r0, #128]\n\t" /* i += 1 */ "ADD r4, r4, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r4, #0x80\n\t" #if defined(__GNUC__) "BLT L_sp_2048_mont_reduce_32_word_%=\n\t" @@ -4473,22 +5011,33 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( "BLT.W L_sp_2048_mont_reduce_32_word_%=\n\t" #endif /* Loop Done */ - "STR r6, [%[a]]\n\t" - "STR r7, [%[a], #4]\n\t" - "STR r8, [%[a], #8]\n\t" - "STR r9, [%[a], #12]\n\t" - "STR r10, [%[a], #16]\n\t" - "MOV %[mp], r5\n\t" + "STR r6, [r0]\n\t" + "STR r7, [r0, #4]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #12]\n\t" + "STR r10, [r0, #16]\n\t" + "MOV r2, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_2048_cond_sub_32(a - 32, a, m, (sp_digit)0 - mp); } @@ -4512,10 +5061,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r11, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r11, [r1]\n\t" /* i = 0 */ "MOV r9, #0\n\t" /* ca = 0 */ @@ -4527,8 +5085,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( "L_sp_2048_mont_reduce_32_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "LDR r10, [%[a]]\n\t" - "MUL r8, %[mp], r10\n\t" + "LDR r10, [r0]\n\t" + "MUL r8, r2, r10\n\t" /* j = 0 */ "MOV r12, #0\n\t" "MOV r4, #0\n\t" @@ -4539,31 +5097,31 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( "L_sp_2048_mont_reduce_32_mul_%=:\n\t" #endif /* a[i+j+0] += m[j+0] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+1] += m[j+1] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+2] += m[j+2] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+3] += m[j+3] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" "CMP r12, #0x80\n\t" @@ -4574,16 +5132,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( #else "BLT.N L_sp_2048_mont_reduce_32_mul_%=\n\t" #endif - "LDR r10, [%[a], #128]\n\t" + "LDR r10, [r0, #128]\n\t" "ADDS r4, r4, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" "ADDS r10, r10, r4\n\t" "ADC r3, r3, r3\n\t" - "STR r10, [%[a], #128]\n\t" + "STR r10, [r0, #128]\n\t" /* i += 1 */ "ADD r9, r9, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r9, #0x80\n\t" #if defined(__GNUC__) "BLT L_sp_2048_mont_reduce_32_word_%=\n\t" @@ -4593,17 +5151,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_32( "BLT.N L_sp_2048_mont_reduce_32_word_%=\n\t" #endif /* Loop Done */ - "MOV %[mp], r3\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_2048_cond_sub_32(a - 32, a, m, (sp_digit)0 - mp); } @@ -4658,14 +5227,22 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_d_32(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDR r8, [%[a]]\n\t" - "UMULL r5, r3, %[b], r8\n\t" + "LDR r8, [r1]\n\t" + "UMULL r5, r3, r2, r8\n\t" "MOV r4, #0\n\t" - "STR r5, [%[r]]\n\t" + "STR r5, [r0]\n\t" "MOV r5, #0\n\t" "MOV r9, #4\n\t" "\n" @@ -4675,12 +5252,12 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_d_32(sp_digit* r, "L_sp_2048_mul_d_32_word_%=:\n\t" #endif /* A[i] * B */ - "LDR r8, [%[a], r9]\n\t" - "UMULL r6, r7, %[b], r8\n\t" + "LDR r8, [r1, r9]\n\t" + "UMULL r6, r7, r2, r8\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], r9]\n\t" + "STR r3, [r0, r9]\n\t" "MOV r3, r4\n\t" "MOV r4, r5\n\t" "MOV r5, #0\n\t" @@ -4693,16 +5270,27 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_d_32(sp_digit* r, #else "BLT.N L_sp_2048_mul_d_32_word_%=\n\t" #endif - "STR r3, [%[r], #128]\n\t" + "STR r3, [r0, #128]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -4724,178 +5312,197 @@ WC_OMIT_FRAME_POINTER static void sp_2048_mul_d_32(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDM %[a]!, {r8}\n\t" - "UMULL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMULL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[1] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[2] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[3] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[4] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[5] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[6] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[7] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[8] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[9] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[10] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[11] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[12] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[13] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[14] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[15] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[16] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[17] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[18] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[19] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[20] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[21] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[22] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[23] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[24] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[25] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[26] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[27] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[28] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[29] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[30] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[31] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" - "STR r5, [%[r]]\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" + "STR r5, [r0]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -4922,53 +5529,73 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_2048_word_32(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r8, %[div], #16\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r8, r2, #16\n\t" "ADD r5, r8, #1\n\t" - "UDIV r6, %[d1], r5\n\t" - "LSL r7, %[div], #16\n\t" + "UDIV r6, r0, r5\n\t" + "LSL r7, r2, #16\n\t" "LSL r6, r6, #16\n\t" - "UMULL r3, r4, %[div], r6\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "SUBS r3, %[d1], r5\n\t" + "UMULL r3, r4, r2, r6\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "SUBS r3, r0, r5\n\t" "SBC r9, r9, r9\n\t" "ADD r9, r9, #1\n\t" "RSB r10, r9, #0\n\t" "LSL r9, r9, #16\n\t" "AND r7, r7, r10\n\t" "AND r8, r8, r10\n\t" - "SUBS %[d0], %[d0], r7\n\t" + "SUBS r1, r1, r7\n\t" "ADD r6, r6, r9\n\t" - "SBC %[d1], %[d1], r8\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "SBC r0, r0, r8\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "UMULL r3, r4, %[div], r3\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "UMULL r3, r4, r2, r3\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "MUL r3, %[div], r3\n\t" - "SUB %[d0], %[d0], r3\n\t" - "UDIV r3, %[d0], %[div]\n\t" - "ADD %[d1], r6, r3\n\t" + "MUL r3, r2, r3\n\t" + "SUB r1, r1, r3\n\t" + "UDIV r3, r1, r2\n\t" + "ADD r0, r6, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -4995,13 +5622,22 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_2048_word_32(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r5, %[div], #1\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r5, r2, #1\n\t" "ADD r5, r5, #1\n\t" - "MOV r6, %[d0]\n\t" - "MOV r7, %[d1]\n\t" + "MOV r6, r1\n\t" + "MOV r7, r0\n\t" /* Do top 32 */ "SUBS r8, r5, r7\n\t" "SBC r8, r8, r8\n\t" @@ -5035,29 +5671,40 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_2048_word_32(sp_digit d1, #endif "ADD r3, r3, r3\n\t" "ADD r3, r3, #1\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "SUBS r8, r9, %[div]\n\t" - "ADC %[d1], r3, #0\n\t" + "SUBS r8, r9, r2\n\t" + "ADC r0, r3, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -5081,9 +5728,17 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0xffffffff\n\t" "MOV r8, #1\n\t" "MOV r7, #0\n\t" @@ -5096,8 +5751,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, #else "L_sp_2048_cmp_32_words_%=:\n\t" #endif - "LDR r4, [%[a], r6]\n\t" - "LDR r5, [%[b], r6]\n\t" + "LDR r4, [r0, r6]\n\t" + "LDR r5, [r1, r6]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5115,8 +5770,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, #endif "EOR r2, r2, r3\n\t" #else - "LDR r4, [%[a], #124]\n\t" - "LDR r5, [%[b], #124]\n\t" + "LDR r4, [r0, #124]\n\t" + "LDR r5, [r1, #124]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5126,8 +5781,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #120]\n\t" - "LDR r5, [%[b], #120]\n\t" + "LDR r4, [r0, #120]\n\t" + "LDR r5, [r1, #120]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5137,8 +5792,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #116]\n\t" - "LDR r5, [%[b], #116]\n\t" + "LDR r4, [r0, #116]\n\t" + "LDR r5, [r1, #116]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5148,8 +5803,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #112]\n\t" - "LDR r5, [%[b], #112]\n\t" + "LDR r4, [r0, #112]\n\t" + "LDR r5, [r1, #112]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5159,8 +5814,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #108]\n\t" - "LDR r5, [%[b], #108]\n\t" + "LDR r4, [r0, #108]\n\t" + "LDR r5, [r1, #108]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5170,8 +5825,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #104]\n\t" - "LDR r5, [%[b], #104]\n\t" + "LDR r4, [r0, #104]\n\t" + "LDR r5, [r1, #104]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5181,8 +5836,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #100]\n\t" - "LDR r5, [%[b], #100]\n\t" + "LDR r4, [r0, #100]\n\t" + "LDR r5, [r1, #100]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5192,8 +5847,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #96]\n\t" - "LDR r5, [%[b], #96]\n\t" + "LDR r4, [r0, #96]\n\t" + "LDR r5, [r1, #96]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5203,8 +5858,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #92]\n\t" - "LDR r5, [%[b], #92]\n\t" + "LDR r4, [r0, #92]\n\t" + "LDR r5, [r1, #92]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5214,8 +5869,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #88]\n\t" - "LDR r5, [%[b], #88]\n\t" + "LDR r4, [r0, #88]\n\t" + "LDR r5, [r1, #88]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5225,8 +5880,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #84]\n\t" - "LDR r5, [%[b], #84]\n\t" + "LDR r4, [r0, #84]\n\t" + "LDR r5, [r1, #84]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5236,8 +5891,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #80]\n\t" - "LDR r5, [%[b], #80]\n\t" + "LDR r4, [r0, #80]\n\t" + "LDR r5, [r1, #80]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5247,8 +5902,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #76]\n\t" - "LDR r5, [%[b], #76]\n\t" + "LDR r4, [r0, #76]\n\t" + "LDR r5, [r1, #76]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5258,8 +5913,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #72]\n\t" - "LDR r5, [%[b], #72]\n\t" + "LDR r4, [r0, #72]\n\t" + "LDR r5, [r1, #72]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5269,8 +5924,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #68]\n\t" - "LDR r5, [%[b], #68]\n\t" + "LDR r4, [r0, #68]\n\t" + "LDR r5, [r1, #68]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5280,8 +5935,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #64]\n\t" - "LDR r5, [%[b], #64]\n\t" + "LDR r4, [r0, #64]\n\t" + "LDR r5, [r1, #64]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5291,8 +5946,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #60]\n\t" - "LDR r5, [%[b], #60]\n\t" + "LDR r4, [r0, #60]\n\t" + "LDR r5, [r1, #60]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5302,8 +5957,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #56]\n\t" - "LDR r5, [%[b], #56]\n\t" + "LDR r4, [r0, #56]\n\t" + "LDR r5, [r1, #56]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5313,8 +5968,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #52]\n\t" - "LDR r5, [%[b], #52]\n\t" + "LDR r4, [r0, #52]\n\t" + "LDR r5, [r1, #52]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5324,8 +5979,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #48]\n\t" - "LDR r5, [%[b], #48]\n\t" + "LDR r4, [r0, #48]\n\t" + "LDR r5, [r1, #48]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5335,8 +5990,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #44]\n\t" - "LDR r5, [%[b], #44]\n\t" + "LDR r4, [r0, #44]\n\t" + "LDR r5, [r1, #44]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5346,8 +6001,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #40]\n\t" - "LDR r5, [%[b], #40]\n\t" + "LDR r4, [r0, #40]\n\t" + "LDR r5, [r1, #40]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5357,8 +6012,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #36]\n\t" - "LDR r5, [%[b], #36]\n\t" + "LDR r4, [r0, #36]\n\t" + "LDR r5, [r1, #36]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5368,8 +6023,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #32]\n\t" - "LDR r5, [%[b], #32]\n\t" + "LDR r4, [r0, #32]\n\t" + "LDR r5, [r1, #32]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5379,8 +6034,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #28]\n\t" - "LDR r5, [%[b], #28]\n\t" + "LDR r4, [r0, #28]\n\t" + "LDR r5, [r1, #28]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5390,8 +6045,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #24]\n\t" - "LDR r5, [%[b], #24]\n\t" + "LDR r4, [r0, #24]\n\t" + "LDR r5, [r1, #24]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5401,8 +6056,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #20]\n\t" - "LDR r5, [%[b], #20]\n\t" + "LDR r4, [r0, #20]\n\t" + "LDR r5, [r1, #20]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5412,8 +6067,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #16]\n\t" - "LDR r5, [%[b], #16]\n\t" + "LDR r4, [r0, #16]\n\t" + "LDR r5, [r1, #16]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5423,8 +6078,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #12]\n\t" - "LDR r5, [%[b], #12]\n\t" + "LDR r4, [r0, #12]\n\t" + "LDR r5, [r1, #12]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5434,8 +6089,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #8]\n\t" - "LDR r5, [%[b], #8]\n\t" + "LDR r4, [r0, #8]\n\t" + "LDR r5, [r1, #8]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5445,8 +6100,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #4]\n\t" - "LDR r5, [%[b], #4]\n\t" + "LDR r4, [r0, #4]\n\t" + "LDR r5, [r1, #4]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5456,8 +6111,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[b]]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r1]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -5469,16 +6124,26 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_32(const sp_digit* a, "movne r3, r7\n\t" "EOR r2, r2, r3\n\t" #endif /*WOLFSSL_SP_SMALL */ - "MOV %[a], r2\n\t" + "MOV r0, r2\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -5879,9 +6544,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_sub_64(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, #0\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -5892,12 +6566,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_sub_64(sp_digit* r, "L_sp_2048_cond_sub_64_words_%=:\n\t" #endif "SUBS r4, r8, r4\n\t" - "LDR r6, [%[a], r5]\n\t" - "LDR r7, [%[b], r5]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r5]\n\t" + "LDR r7, [r2, r5]\n\t" + "AND r7, r7, r3\n\t" "SBCS r6, r6, r7\n\t" "SBC r4, r8, r8\n\t" - "STR r6, [%[r], r5]\n\t" + "STR r6, [r0, r5]\n\t" "ADD r5, r5, #4\n\t" "CMP r5, #0x100\n\t" #if defined(__GNUC__) @@ -5907,16 +6581,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_sub_64(sp_digit* r, #else "BLT.N L_sp_2048_cond_sub_64_words_%=\n\t" #endif - "MOV %[r], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -5943,244 +6629,265 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_sub_64(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SUBS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "SBC %[r], r5, r5\n\t" + "STM r0!, {r6, r7}\n\t" + "SBC r0, r5, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -6206,15 +6913,24 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR lr, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR lr, [r1]\n\t" /* i = 0 */ "MOV r11, #0\n\t" "MOV r3, #0\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[a], #4]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_2048_mont_reduce_64_word:\n\t" @@ -6222,521 +6938,521 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( "L_sp_2048_mont_reduce_64_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL r10, %[mp], r4\n\t" + "MUL r10, r2, r4\n\t" /* a[i+0] += m[0] * mu */ "MOV r7, #0\n\t" "UMLAL r4, r7, r10, lr\n\t" /* a[i+1] += m[1] * mu */ - "LDR r9, [%[m], #4]\n\t" + "LDR r9, [r1, #4]\n\t" "MOV r6, #0\n\t" "UMLAL r5, r6, r10, r9\n\t" "MOV r4, r5\n\t" "ADDS r4, r4, r7\n\t" "ADC r6, r6, #0\n\t" /* a[i+2] += m[2] * mu */ - "LDR r9, [%[m], #8]\n\t" - "LDR r5, [%[a], #8]\n\t" + "LDR r9, [r1, #8]\n\t" + "LDR r5, [r0, #8]\n\t" "MOV r7, #0\n\t" "UMLAL r5, r7, r10, r9\n\t" "ADDS r5, r5, r6\n\t" "ADC r7, r7, #0\n\t" /* a[i+3] += m[3] * mu */ - "LDR r9, [%[m], #12]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r9, [r1, #12]\n\t" + "LDR r12, [r0, #12]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #12]\n\t" + "STR r12, [r0, #12]\n\t" "ADC r6, r6, #0\n\t" /* a[i+4] += m[4] * mu */ - "LDR r9, [%[m], #16]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r9, [r1, #16]\n\t" + "LDR r12, [r0, #16]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #16]\n\t" + "STR r12, [r0, #16]\n\t" "ADC r7, r7, #0\n\t" /* a[i+5] += m[5] * mu */ - "LDR r9, [%[m], #20]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r12, [r0, #20]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #20]\n\t" + "STR r12, [r0, #20]\n\t" "ADC r6, r6, #0\n\t" /* a[i+6] += m[6] * mu */ - "LDR r9, [%[m], #24]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r9, [r1, #24]\n\t" + "LDR r12, [r0, #24]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #24]\n\t" + "STR r12, [r0, #24]\n\t" "ADC r7, r7, #0\n\t" /* a[i+7] += m[7] * mu */ - "LDR r9, [%[m], #28]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r9, [r1, #28]\n\t" + "LDR r12, [r0, #28]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #28]\n\t" + "STR r12, [r0, #28]\n\t" "ADC r6, r6, #0\n\t" /* a[i+8] += m[8] * mu */ - "LDR r9, [%[m], #32]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r9, [r1, #32]\n\t" + "LDR r12, [r0, #32]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #32]\n\t" + "STR r12, [r0, #32]\n\t" "ADC r7, r7, #0\n\t" /* a[i+9] += m[9] * mu */ - "LDR r9, [%[m], #36]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r9, [r1, #36]\n\t" + "LDR r12, [r0, #36]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #36]\n\t" + "STR r12, [r0, #36]\n\t" "ADC r6, r6, #0\n\t" /* a[i+10] += m[10] * mu */ - "LDR r9, [%[m], #40]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r9, [r1, #40]\n\t" + "LDR r12, [r0, #40]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #40]\n\t" + "STR r12, [r0, #40]\n\t" "ADC r7, r7, #0\n\t" /* a[i+11] += m[11] * mu */ - "LDR r9, [%[m], #44]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r9, [r1, #44]\n\t" + "LDR r12, [r0, #44]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #44]\n\t" + "STR r12, [r0, #44]\n\t" "ADC r6, r6, #0\n\t" /* a[i+12] += m[12] * mu */ - "LDR r9, [%[m], #48]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r9, [r1, #48]\n\t" + "LDR r12, [r0, #48]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #48]\n\t" + "STR r12, [r0, #48]\n\t" "ADC r7, r7, #0\n\t" /* a[i+13] += m[13] * mu */ - "LDR r9, [%[m], #52]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r9, [r1, #52]\n\t" + "LDR r12, [r0, #52]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #52]\n\t" + "STR r12, [r0, #52]\n\t" "ADC r6, r6, #0\n\t" /* a[i+14] += m[14] * mu */ - "LDR r9, [%[m], #56]\n\t" - "LDR r12, [%[a], #56]\n\t" + "LDR r9, [r1, #56]\n\t" + "LDR r12, [r0, #56]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #56]\n\t" + "STR r12, [r0, #56]\n\t" "ADC r7, r7, #0\n\t" /* a[i+15] += m[15] * mu */ - "LDR r9, [%[m], #60]\n\t" - "LDR r12, [%[a], #60]\n\t" + "LDR r9, [r1, #60]\n\t" + "LDR r12, [r0, #60]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #60]\n\t" + "STR r12, [r0, #60]\n\t" "ADC r6, r6, #0\n\t" /* a[i+16] += m[16] * mu */ - "LDR r9, [%[m], #64]\n\t" - "LDR r12, [%[a], #64]\n\t" + "LDR r9, [r1, #64]\n\t" + "LDR r12, [r0, #64]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #64]\n\t" + "STR r12, [r0, #64]\n\t" "ADC r7, r7, #0\n\t" /* a[i+17] += m[17] * mu */ - "LDR r9, [%[m], #68]\n\t" - "LDR r12, [%[a], #68]\n\t" + "LDR r9, [r1, #68]\n\t" + "LDR r12, [r0, #68]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #68]\n\t" + "STR r12, [r0, #68]\n\t" "ADC r6, r6, #0\n\t" /* a[i+18] += m[18] * mu */ - "LDR r9, [%[m], #72]\n\t" - "LDR r12, [%[a], #72]\n\t" + "LDR r9, [r1, #72]\n\t" + "LDR r12, [r0, #72]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #72]\n\t" + "STR r12, [r0, #72]\n\t" "ADC r7, r7, #0\n\t" /* a[i+19] += m[19] * mu */ - "LDR r9, [%[m], #76]\n\t" - "LDR r12, [%[a], #76]\n\t" + "LDR r9, [r1, #76]\n\t" + "LDR r12, [r0, #76]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #76]\n\t" + "STR r12, [r0, #76]\n\t" "ADC r6, r6, #0\n\t" /* a[i+20] += m[20] * mu */ - "LDR r9, [%[m], #80]\n\t" - "LDR r12, [%[a], #80]\n\t" + "LDR r9, [r1, #80]\n\t" + "LDR r12, [r0, #80]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #80]\n\t" + "STR r12, [r0, #80]\n\t" "ADC r7, r7, #0\n\t" /* a[i+21] += m[21] * mu */ - "LDR r9, [%[m], #84]\n\t" - "LDR r12, [%[a], #84]\n\t" + "LDR r9, [r1, #84]\n\t" + "LDR r12, [r0, #84]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #84]\n\t" + "STR r12, [r0, #84]\n\t" "ADC r6, r6, #0\n\t" /* a[i+22] += m[22] * mu */ - "LDR r9, [%[m], #88]\n\t" - "LDR r12, [%[a], #88]\n\t" + "LDR r9, [r1, #88]\n\t" + "LDR r12, [r0, #88]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #88]\n\t" + "STR r12, [r0, #88]\n\t" "ADC r7, r7, #0\n\t" /* a[i+23] += m[23] * mu */ - "LDR r9, [%[m], #92]\n\t" - "LDR r12, [%[a], #92]\n\t" + "LDR r9, [r1, #92]\n\t" + "LDR r12, [r0, #92]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #92]\n\t" + "STR r12, [r0, #92]\n\t" "ADC r6, r6, #0\n\t" /* a[i+24] += m[24] * mu */ - "LDR r9, [%[m], #96]\n\t" - "LDR r12, [%[a], #96]\n\t" + "LDR r9, [r1, #96]\n\t" + "LDR r12, [r0, #96]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #96]\n\t" + "STR r12, [r0, #96]\n\t" "ADC r7, r7, #0\n\t" /* a[i+25] += m[25] * mu */ - "LDR r9, [%[m], #100]\n\t" - "LDR r12, [%[a], #100]\n\t" + "LDR r9, [r1, #100]\n\t" + "LDR r12, [r0, #100]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #100]\n\t" + "STR r12, [r0, #100]\n\t" "ADC r6, r6, #0\n\t" /* a[i+26] += m[26] * mu */ - "LDR r9, [%[m], #104]\n\t" - "LDR r12, [%[a], #104]\n\t" + "LDR r9, [r1, #104]\n\t" + "LDR r12, [r0, #104]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #104]\n\t" + "STR r12, [r0, #104]\n\t" "ADC r7, r7, #0\n\t" /* a[i+27] += m[27] * mu */ - "LDR r9, [%[m], #108]\n\t" - "LDR r12, [%[a], #108]\n\t" + "LDR r9, [r1, #108]\n\t" + "LDR r12, [r0, #108]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #108]\n\t" + "STR r12, [r0, #108]\n\t" "ADC r6, r6, #0\n\t" /* a[i+28] += m[28] * mu */ - "LDR r9, [%[m], #112]\n\t" - "LDR r12, [%[a], #112]\n\t" + "LDR r9, [r1, #112]\n\t" + "LDR r12, [r0, #112]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #112]\n\t" + "STR r12, [r0, #112]\n\t" "ADC r7, r7, #0\n\t" /* a[i+29] += m[29] * mu */ - "LDR r9, [%[m], #116]\n\t" - "LDR r12, [%[a], #116]\n\t" + "LDR r9, [r1, #116]\n\t" + "LDR r12, [r0, #116]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #116]\n\t" + "STR r12, [r0, #116]\n\t" "ADC r6, r6, #0\n\t" /* a[i+30] += m[30] * mu */ - "LDR r9, [%[m], #120]\n\t" - "LDR r12, [%[a], #120]\n\t" + "LDR r9, [r1, #120]\n\t" + "LDR r12, [r0, #120]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #120]\n\t" + "STR r12, [r0, #120]\n\t" "ADC r7, r7, #0\n\t" /* a[i+31] += m[31] * mu */ - "LDR r9, [%[m], #124]\n\t" - "LDR r12, [%[a], #124]\n\t" + "LDR r9, [r1, #124]\n\t" + "LDR r12, [r0, #124]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #124]\n\t" + "STR r12, [r0, #124]\n\t" "ADC r6, r6, #0\n\t" /* a[i+32] += m[32] * mu */ - "LDR r9, [%[m], #128]\n\t" - "LDR r12, [%[a], #128]\n\t" + "LDR r9, [r1, #128]\n\t" + "LDR r12, [r0, #128]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #128]\n\t" + "STR r12, [r0, #128]\n\t" "ADC r7, r7, #0\n\t" /* a[i+33] += m[33] * mu */ - "LDR r9, [%[m], #132]\n\t" - "LDR r12, [%[a], #132]\n\t" + "LDR r9, [r1, #132]\n\t" + "LDR r12, [r0, #132]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #132]\n\t" + "STR r12, [r0, #132]\n\t" "ADC r6, r6, #0\n\t" /* a[i+34] += m[34] * mu */ - "LDR r9, [%[m], #136]\n\t" - "LDR r12, [%[a], #136]\n\t" + "LDR r9, [r1, #136]\n\t" + "LDR r12, [r0, #136]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #136]\n\t" + "STR r12, [r0, #136]\n\t" "ADC r7, r7, #0\n\t" /* a[i+35] += m[35] * mu */ - "LDR r9, [%[m], #140]\n\t" - "LDR r12, [%[a], #140]\n\t" + "LDR r9, [r1, #140]\n\t" + "LDR r12, [r0, #140]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #140]\n\t" + "STR r12, [r0, #140]\n\t" "ADC r6, r6, #0\n\t" /* a[i+36] += m[36] * mu */ - "LDR r9, [%[m], #144]\n\t" - "LDR r12, [%[a], #144]\n\t" + "LDR r9, [r1, #144]\n\t" + "LDR r12, [r0, #144]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #144]\n\t" + "STR r12, [r0, #144]\n\t" "ADC r7, r7, #0\n\t" /* a[i+37] += m[37] * mu */ - "LDR r9, [%[m], #148]\n\t" - "LDR r12, [%[a], #148]\n\t" + "LDR r9, [r1, #148]\n\t" + "LDR r12, [r0, #148]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #148]\n\t" + "STR r12, [r0, #148]\n\t" "ADC r6, r6, #0\n\t" /* a[i+38] += m[38] * mu */ - "LDR r9, [%[m], #152]\n\t" - "LDR r12, [%[a], #152]\n\t" + "LDR r9, [r1, #152]\n\t" + "LDR r12, [r0, #152]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #152]\n\t" + "STR r12, [r0, #152]\n\t" "ADC r7, r7, #0\n\t" /* a[i+39] += m[39] * mu */ - "LDR r9, [%[m], #156]\n\t" - "LDR r12, [%[a], #156]\n\t" + "LDR r9, [r1, #156]\n\t" + "LDR r12, [r0, #156]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #156]\n\t" + "STR r12, [r0, #156]\n\t" "ADC r6, r6, #0\n\t" /* a[i+40] += m[40] * mu */ - "LDR r9, [%[m], #160]\n\t" - "LDR r12, [%[a], #160]\n\t" + "LDR r9, [r1, #160]\n\t" + "LDR r12, [r0, #160]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #160]\n\t" + "STR r12, [r0, #160]\n\t" "ADC r7, r7, #0\n\t" /* a[i+41] += m[41] * mu */ - "LDR r9, [%[m], #164]\n\t" - "LDR r12, [%[a], #164]\n\t" + "LDR r9, [r1, #164]\n\t" + "LDR r12, [r0, #164]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #164]\n\t" + "STR r12, [r0, #164]\n\t" "ADC r6, r6, #0\n\t" /* a[i+42] += m[42] * mu */ - "LDR r9, [%[m], #168]\n\t" - "LDR r12, [%[a], #168]\n\t" + "LDR r9, [r1, #168]\n\t" + "LDR r12, [r0, #168]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #168]\n\t" + "STR r12, [r0, #168]\n\t" "ADC r7, r7, #0\n\t" /* a[i+43] += m[43] * mu */ - "LDR r9, [%[m], #172]\n\t" - "LDR r12, [%[a], #172]\n\t" + "LDR r9, [r1, #172]\n\t" + "LDR r12, [r0, #172]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #172]\n\t" + "STR r12, [r0, #172]\n\t" "ADC r6, r6, #0\n\t" /* a[i+44] += m[44] * mu */ - "LDR r9, [%[m], #176]\n\t" - "LDR r12, [%[a], #176]\n\t" + "LDR r9, [r1, #176]\n\t" + "LDR r12, [r0, #176]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #176]\n\t" + "STR r12, [r0, #176]\n\t" "ADC r7, r7, #0\n\t" /* a[i+45] += m[45] * mu */ - "LDR r9, [%[m], #180]\n\t" - "LDR r12, [%[a], #180]\n\t" + "LDR r9, [r1, #180]\n\t" + "LDR r12, [r0, #180]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #180]\n\t" + "STR r12, [r0, #180]\n\t" "ADC r6, r6, #0\n\t" /* a[i+46] += m[46] * mu */ - "LDR r9, [%[m], #184]\n\t" - "LDR r12, [%[a], #184]\n\t" + "LDR r9, [r1, #184]\n\t" + "LDR r12, [r0, #184]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #184]\n\t" + "STR r12, [r0, #184]\n\t" "ADC r7, r7, #0\n\t" /* a[i+47] += m[47] * mu */ - "LDR r9, [%[m], #188]\n\t" - "LDR r12, [%[a], #188]\n\t" + "LDR r9, [r1, #188]\n\t" + "LDR r12, [r0, #188]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #188]\n\t" + "STR r12, [r0, #188]\n\t" "ADC r6, r6, #0\n\t" /* a[i+48] += m[48] * mu */ - "LDR r9, [%[m], #192]\n\t" - "LDR r12, [%[a], #192]\n\t" + "LDR r9, [r1, #192]\n\t" + "LDR r12, [r0, #192]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #192]\n\t" + "STR r12, [r0, #192]\n\t" "ADC r7, r7, #0\n\t" /* a[i+49] += m[49] * mu */ - "LDR r9, [%[m], #196]\n\t" - "LDR r12, [%[a], #196]\n\t" + "LDR r9, [r1, #196]\n\t" + "LDR r12, [r0, #196]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #196]\n\t" + "STR r12, [r0, #196]\n\t" "ADC r6, r6, #0\n\t" /* a[i+50] += m[50] * mu */ - "LDR r9, [%[m], #200]\n\t" - "LDR r12, [%[a], #200]\n\t" + "LDR r9, [r1, #200]\n\t" + "LDR r12, [r0, #200]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #200]\n\t" + "STR r12, [r0, #200]\n\t" "ADC r7, r7, #0\n\t" /* a[i+51] += m[51] * mu */ - "LDR r9, [%[m], #204]\n\t" - "LDR r12, [%[a], #204]\n\t" + "LDR r9, [r1, #204]\n\t" + "LDR r12, [r0, #204]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #204]\n\t" + "STR r12, [r0, #204]\n\t" "ADC r6, r6, #0\n\t" /* a[i+52] += m[52] * mu */ - "LDR r9, [%[m], #208]\n\t" - "LDR r12, [%[a], #208]\n\t" + "LDR r9, [r1, #208]\n\t" + "LDR r12, [r0, #208]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #208]\n\t" + "STR r12, [r0, #208]\n\t" "ADC r7, r7, #0\n\t" /* a[i+53] += m[53] * mu */ - "LDR r9, [%[m], #212]\n\t" - "LDR r12, [%[a], #212]\n\t" + "LDR r9, [r1, #212]\n\t" + "LDR r12, [r0, #212]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #212]\n\t" + "STR r12, [r0, #212]\n\t" "ADC r6, r6, #0\n\t" /* a[i+54] += m[54] * mu */ - "LDR r9, [%[m], #216]\n\t" - "LDR r12, [%[a], #216]\n\t" + "LDR r9, [r1, #216]\n\t" + "LDR r12, [r0, #216]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #216]\n\t" + "STR r12, [r0, #216]\n\t" "ADC r7, r7, #0\n\t" /* a[i+55] += m[55] * mu */ - "LDR r9, [%[m], #220]\n\t" - "LDR r12, [%[a], #220]\n\t" + "LDR r9, [r1, #220]\n\t" + "LDR r12, [r0, #220]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #220]\n\t" + "STR r12, [r0, #220]\n\t" "ADC r6, r6, #0\n\t" /* a[i+56] += m[56] * mu */ - "LDR r9, [%[m], #224]\n\t" - "LDR r12, [%[a], #224]\n\t" + "LDR r9, [r1, #224]\n\t" + "LDR r12, [r0, #224]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #224]\n\t" + "STR r12, [r0, #224]\n\t" "ADC r7, r7, #0\n\t" /* a[i+57] += m[57] * mu */ - "LDR r9, [%[m], #228]\n\t" - "LDR r12, [%[a], #228]\n\t" + "LDR r9, [r1, #228]\n\t" + "LDR r12, [r0, #228]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #228]\n\t" + "STR r12, [r0, #228]\n\t" "ADC r6, r6, #0\n\t" /* a[i+58] += m[58] * mu */ - "LDR r9, [%[m], #232]\n\t" - "LDR r12, [%[a], #232]\n\t" + "LDR r9, [r1, #232]\n\t" + "LDR r12, [r0, #232]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #232]\n\t" + "STR r12, [r0, #232]\n\t" "ADC r7, r7, #0\n\t" /* a[i+59] += m[59] * mu */ - "LDR r9, [%[m], #236]\n\t" - "LDR r12, [%[a], #236]\n\t" + "LDR r9, [r1, #236]\n\t" + "LDR r12, [r0, #236]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #236]\n\t" + "STR r12, [r0, #236]\n\t" "ADC r6, r6, #0\n\t" /* a[i+60] += m[60] * mu */ - "LDR r9, [%[m], #240]\n\t" - "LDR r12, [%[a], #240]\n\t" + "LDR r9, [r1, #240]\n\t" + "LDR r12, [r0, #240]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #240]\n\t" + "STR r12, [r0, #240]\n\t" "ADC r7, r7, #0\n\t" /* a[i+61] += m[61] * mu */ - "LDR r9, [%[m], #244]\n\t" - "LDR r12, [%[a], #244]\n\t" + "LDR r9, [r1, #244]\n\t" + "LDR r12, [r0, #244]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #244]\n\t" + "STR r12, [r0, #244]\n\t" "ADC r6, r6, #0\n\t" /* a[i+62] += m[62] * mu */ - "LDR r9, [%[m], #248]\n\t" - "LDR r12, [%[a], #248]\n\t" + "LDR r9, [r1, #248]\n\t" + "LDR r12, [r0, #248]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #248]\n\t" + "STR r12, [r0, #248]\n\t" "ADC r7, r7, #0\n\t" /* a[i+63] += m[63] * mu */ - "LDR r9, [%[m], #252]\n\t" - "LDR r12, [%[a], #252]\n\t" + "LDR r9, [r1, #252]\n\t" + "LDR r12, [r0, #252]\n\t" "UMULL r8, r9, r10, r9\n\t" "ADDS r7, r7, r8\n\t" "ADCS r6, r9, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, r3\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #252]\n\t" - "LDR r12, [%[a], #256]\n\t" + "STR r12, [r0, #252]\n\t" + "LDR r12, [r0, #256]\n\t" "ADCS r12, r12, r6\n\t" - "STR r12, [%[a], #256]\n\t" + "STR r12, [r0, #256]\n\t" "ADC r3, r3, #0\n\t" /* i += 1 */ "ADD r11, r11, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r11, #0x100\n\t" #if defined(__GNUC__) "BLT L_sp_2048_mont_reduce_64_word_%=\n\t" @@ -6746,19 +7462,30 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( "BLT.W L_sp_2048_mont_reduce_64_word_%=\n\t" #endif /* Loop Done */ - "STR r4, [%[a]]\n\t" - "STR r5, [%[a], #4]\n\t" - "MOV %[mp], r3\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_2048_cond_sub_64(a - 64, a, m, (sp_digit)0 - mp); } @@ -6782,10 +7509,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r11, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r11, [r1]\n\t" /* i = 0 */ "MOV r9, #0\n\t" /* ca = 0 */ @@ -6797,8 +7533,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( "L_sp_2048_mont_reduce_64_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "LDR r10, [%[a]]\n\t" - "MUL r8, %[mp], r10\n\t" + "LDR r10, [r0]\n\t" + "MUL r8, r2, r10\n\t" /* j = 0 */ "MOV r12, #0\n\t" "MOV r4, #0\n\t" @@ -6809,42 +7545,42 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( "L_sp_2048_mont_reduce_64_mul_%=:\n\t" #endif /* a[i+j+0] += m[j+0] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+1] += m[j+1] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+2] += m[j+2] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+3] += m[j+3] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" @@ -6856,16 +7592,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( #else "BLT.N L_sp_2048_mont_reduce_64_mul_%=\n\t" #endif - "LDR r10, [%[a], #256]\n\t" + "LDR r10, [r0, #256]\n\t" "ADDS r4, r4, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" "ADDS r10, r10, r4\n\t" "ADC r3, r3, r3\n\t" - "STR r10, [%[a], #256]\n\t" + "STR r10, [r0, #256]\n\t" /* i += 1 */ "ADD r9, r9, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r9, #0x100\n\t" #if defined(__GNUC__) "BLT L_sp_2048_mont_reduce_64_word_%=\n\t" @@ -6875,17 +7611,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( "BLT.N L_sp_2048_mont_reduce_64_word_%=\n\t" #endif /* Loop Done */ - "MOV %[mp], r3\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_2048_cond_sub_64(a - 64, a, m, (sp_digit)0 - mp); } @@ -6911,17 +7658,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* i = 0 */ "MOV r4, #0\n\t" "MOV r5, #0\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r7, [%[a], #4]\n\t" - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[a], #12]\n\t" - "LDR r10, [%[a], #16]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" + "LDR r10, [r0, #16]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_2048_mont_reduce_64_word:\n\t" @@ -6929,330 +7685,330 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( "L_sp_2048_mont_reduce_64_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL lr, %[mp], r6\n\t" + "MUL lr, r2, r6\n\t" /* a[i+0] += m[0] * mu */ - "LDR r12, [%[m]]\n\t" + "LDR r12, [r1]\n\t" "MOV r3, #0\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+1] += m[1] * mu */ - "LDR r12, [%[m], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "MOV r6, r7\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+2] += m[2] * mu */ - "LDR r12, [%[m], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "MOV r7, r8\n\t" "UMAAL r7, r3, lr, r12\n\t" /* a[i+3] += m[3] * mu */ - "LDR r12, [%[m], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "MOV r8, r9\n\t" "UMAAL r8, r3, lr, r12\n\t" /* a[i+4] += m[4] * mu */ - "LDR r12, [%[m], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "MOV r9, r10\n\t" "UMAAL r9, r3, lr, r12\n\t" /* a[i+5] += m[5] * mu */ - "LDR r12, [%[m], #20]\n\t" - "LDR r10, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR r10, [r0, #20]\n\t" "UMAAL r10, r3, lr, r12\n\t" /* a[i+6] += m[6] * mu */ - "LDR r12, [%[m], #24]\n\t" - "LDR r11, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR r11, [r0, #24]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #24]\n\t" + "STR r11, [r0, #24]\n\t" /* a[i+7] += m[7] * mu */ - "LDR r12, [%[m], #28]\n\t" - "LDR r11, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR r11, [r0, #28]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #28]\n\t" + "STR r11, [r0, #28]\n\t" /* a[i+8] += m[8] * mu */ - "LDR r12, [%[m], #32]\n\t" - "LDR r11, [%[a], #32]\n\t" + "LDR r12, [r1, #32]\n\t" + "LDR r11, [r0, #32]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #32]\n\t" + "STR r11, [r0, #32]\n\t" /* a[i+9] += m[9] * mu */ - "LDR r12, [%[m], #36]\n\t" - "LDR r11, [%[a], #36]\n\t" + "LDR r12, [r1, #36]\n\t" + "LDR r11, [r0, #36]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #36]\n\t" + "STR r11, [r0, #36]\n\t" /* a[i+10] += m[10] * mu */ - "LDR r12, [%[m], #40]\n\t" - "LDR r11, [%[a], #40]\n\t" + "LDR r12, [r1, #40]\n\t" + "LDR r11, [r0, #40]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #40]\n\t" + "STR r11, [r0, #40]\n\t" /* a[i+11] += m[11] * mu */ - "LDR r12, [%[m], #44]\n\t" - "LDR r11, [%[a], #44]\n\t" + "LDR r12, [r1, #44]\n\t" + "LDR r11, [r0, #44]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #44]\n\t" + "STR r11, [r0, #44]\n\t" /* a[i+12] += m[12] * mu */ - "LDR r12, [%[m], #48]\n\t" - "LDR r11, [%[a], #48]\n\t" + "LDR r12, [r1, #48]\n\t" + "LDR r11, [r0, #48]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #48]\n\t" + "STR r11, [r0, #48]\n\t" /* a[i+13] += m[13] * mu */ - "LDR r12, [%[m], #52]\n\t" - "LDR r11, [%[a], #52]\n\t" + "LDR r12, [r1, #52]\n\t" + "LDR r11, [r0, #52]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #52]\n\t" + "STR r11, [r0, #52]\n\t" /* a[i+14] += m[14] * mu */ - "LDR r12, [%[m], #56]\n\t" - "LDR r11, [%[a], #56]\n\t" + "LDR r12, [r1, #56]\n\t" + "LDR r11, [r0, #56]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #56]\n\t" + "STR r11, [r0, #56]\n\t" /* a[i+15] += m[15] * mu */ - "LDR r12, [%[m], #60]\n\t" - "LDR r11, [%[a], #60]\n\t" + "LDR r12, [r1, #60]\n\t" + "LDR r11, [r0, #60]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #60]\n\t" + "STR r11, [r0, #60]\n\t" /* a[i+16] += m[16] * mu */ - "LDR r12, [%[m], #64]\n\t" - "LDR r11, [%[a], #64]\n\t" + "LDR r12, [r1, #64]\n\t" + "LDR r11, [r0, #64]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #64]\n\t" + "STR r11, [r0, #64]\n\t" /* a[i+17] += m[17] * mu */ - "LDR r12, [%[m], #68]\n\t" - "LDR r11, [%[a], #68]\n\t" + "LDR r12, [r1, #68]\n\t" + "LDR r11, [r0, #68]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #68]\n\t" + "STR r11, [r0, #68]\n\t" /* a[i+18] += m[18] * mu */ - "LDR r12, [%[m], #72]\n\t" - "LDR r11, [%[a], #72]\n\t" + "LDR r12, [r1, #72]\n\t" + "LDR r11, [r0, #72]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #72]\n\t" + "STR r11, [r0, #72]\n\t" /* a[i+19] += m[19] * mu */ - "LDR r12, [%[m], #76]\n\t" - "LDR r11, [%[a], #76]\n\t" + "LDR r12, [r1, #76]\n\t" + "LDR r11, [r0, #76]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #76]\n\t" + "STR r11, [r0, #76]\n\t" /* a[i+20] += m[20] * mu */ - "LDR r12, [%[m], #80]\n\t" - "LDR r11, [%[a], #80]\n\t" + "LDR r12, [r1, #80]\n\t" + "LDR r11, [r0, #80]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #80]\n\t" + "STR r11, [r0, #80]\n\t" /* a[i+21] += m[21] * mu */ - "LDR r12, [%[m], #84]\n\t" - "LDR r11, [%[a], #84]\n\t" + "LDR r12, [r1, #84]\n\t" + "LDR r11, [r0, #84]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #84]\n\t" + "STR r11, [r0, #84]\n\t" /* a[i+22] += m[22] * mu */ - "LDR r12, [%[m], #88]\n\t" - "LDR r11, [%[a], #88]\n\t" + "LDR r12, [r1, #88]\n\t" + "LDR r11, [r0, #88]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #88]\n\t" + "STR r11, [r0, #88]\n\t" /* a[i+23] += m[23] * mu */ - "LDR r12, [%[m], #92]\n\t" - "LDR r11, [%[a], #92]\n\t" + "LDR r12, [r1, #92]\n\t" + "LDR r11, [r0, #92]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #92]\n\t" + "STR r11, [r0, #92]\n\t" /* a[i+24] += m[24] * mu */ - "LDR r12, [%[m], #96]\n\t" - "LDR r11, [%[a], #96]\n\t" + "LDR r12, [r1, #96]\n\t" + "LDR r11, [r0, #96]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #96]\n\t" + "STR r11, [r0, #96]\n\t" /* a[i+25] += m[25] * mu */ - "LDR r12, [%[m], #100]\n\t" - "LDR r11, [%[a], #100]\n\t" + "LDR r12, [r1, #100]\n\t" + "LDR r11, [r0, #100]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #100]\n\t" + "STR r11, [r0, #100]\n\t" /* a[i+26] += m[26] * mu */ - "LDR r12, [%[m], #104]\n\t" - "LDR r11, [%[a], #104]\n\t" + "LDR r12, [r1, #104]\n\t" + "LDR r11, [r0, #104]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #104]\n\t" + "STR r11, [r0, #104]\n\t" /* a[i+27] += m[27] * mu */ - "LDR r12, [%[m], #108]\n\t" - "LDR r11, [%[a], #108]\n\t" + "LDR r12, [r1, #108]\n\t" + "LDR r11, [r0, #108]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #108]\n\t" + "STR r11, [r0, #108]\n\t" /* a[i+28] += m[28] * mu */ - "LDR r12, [%[m], #112]\n\t" - "LDR r11, [%[a], #112]\n\t" + "LDR r12, [r1, #112]\n\t" + "LDR r11, [r0, #112]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #112]\n\t" + "STR r11, [r0, #112]\n\t" /* a[i+29] += m[29] * mu */ - "LDR r12, [%[m], #116]\n\t" - "LDR r11, [%[a], #116]\n\t" + "LDR r12, [r1, #116]\n\t" + "LDR r11, [r0, #116]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #116]\n\t" + "STR r11, [r0, #116]\n\t" /* a[i+30] += m[30] * mu */ - "LDR r12, [%[m], #120]\n\t" - "LDR r11, [%[a], #120]\n\t" + "LDR r12, [r1, #120]\n\t" + "LDR r11, [r0, #120]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #120]\n\t" + "STR r11, [r0, #120]\n\t" /* a[i+31] += m[31] * mu */ - "LDR r12, [%[m], #124]\n\t" - "LDR r11, [%[a], #124]\n\t" + "LDR r12, [r1, #124]\n\t" + "LDR r11, [r0, #124]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #124]\n\t" + "STR r11, [r0, #124]\n\t" /* a[i+32] += m[32] * mu */ - "LDR r12, [%[m], #128]\n\t" - "LDR r11, [%[a], #128]\n\t" + "LDR r12, [r1, #128]\n\t" + "LDR r11, [r0, #128]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #128]\n\t" + "STR r11, [r0, #128]\n\t" /* a[i+33] += m[33] * mu */ - "LDR r12, [%[m], #132]\n\t" - "LDR r11, [%[a], #132]\n\t" + "LDR r12, [r1, #132]\n\t" + "LDR r11, [r0, #132]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #132]\n\t" + "STR r11, [r0, #132]\n\t" /* a[i+34] += m[34] * mu */ - "LDR r12, [%[m], #136]\n\t" - "LDR r11, [%[a], #136]\n\t" + "LDR r12, [r1, #136]\n\t" + "LDR r11, [r0, #136]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #136]\n\t" + "STR r11, [r0, #136]\n\t" /* a[i+35] += m[35] * mu */ - "LDR r12, [%[m], #140]\n\t" - "LDR r11, [%[a], #140]\n\t" + "LDR r12, [r1, #140]\n\t" + "LDR r11, [r0, #140]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #140]\n\t" + "STR r11, [r0, #140]\n\t" /* a[i+36] += m[36] * mu */ - "LDR r12, [%[m], #144]\n\t" - "LDR r11, [%[a], #144]\n\t" + "LDR r12, [r1, #144]\n\t" + "LDR r11, [r0, #144]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #144]\n\t" + "STR r11, [r0, #144]\n\t" /* a[i+37] += m[37] * mu */ - "LDR r12, [%[m], #148]\n\t" - "LDR r11, [%[a], #148]\n\t" + "LDR r12, [r1, #148]\n\t" + "LDR r11, [r0, #148]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #148]\n\t" + "STR r11, [r0, #148]\n\t" /* a[i+38] += m[38] * mu */ - "LDR r12, [%[m], #152]\n\t" - "LDR r11, [%[a], #152]\n\t" + "LDR r12, [r1, #152]\n\t" + "LDR r11, [r0, #152]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #152]\n\t" + "STR r11, [r0, #152]\n\t" /* a[i+39] += m[39] * mu */ - "LDR r12, [%[m], #156]\n\t" - "LDR r11, [%[a], #156]\n\t" + "LDR r12, [r1, #156]\n\t" + "LDR r11, [r0, #156]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #156]\n\t" + "STR r11, [r0, #156]\n\t" /* a[i+40] += m[40] * mu */ - "LDR r12, [%[m], #160]\n\t" - "LDR r11, [%[a], #160]\n\t" + "LDR r12, [r1, #160]\n\t" + "LDR r11, [r0, #160]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #160]\n\t" + "STR r11, [r0, #160]\n\t" /* a[i+41] += m[41] * mu */ - "LDR r12, [%[m], #164]\n\t" - "LDR r11, [%[a], #164]\n\t" + "LDR r12, [r1, #164]\n\t" + "LDR r11, [r0, #164]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #164]\n\t" + "STR r11, [r0, #164]\n\t" /* a[i+42] += m[42] * mu */ - "LDR r12, [%[m], #168]\n\t" - "LDR r11, [%[a], #168]\n\t" + "LDR r12, [r1, #168]\n\t" + "LDR r11, [r0, #168]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #168]\n\t" + "STR r11, [r0, #168]\n\t" /* a[i+43] += m[43] * mu */ - "LDR r12, [%[m], #172]\n\t" - "LDR r11, [%[a], #172]\n\t" + "LDR r12, [r1, #172]\n\t" + "LDR r11, [r0, #172]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #172]\n\t" + "STR r11, [r0, #172]\n\t" /* a[i+44] += m[44] * mu */ - "LDR r12, [%[m], #176]\n\t" - "LDR r11, [%[a], #176]\n\t" + "LDR r12, [r1, #176]\n\t" + "LDR r11, [r0, #176]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #176]\n\t" + "STR r11, [r0, #176]\n\t" /* a[i+45] += m[45] * mu */ - "LDR r12, [%[m], #180]\n\t" - "LDR r11, [%[a], #180]\n\t" + "LDR r12, [r1, #180]\n\t" + "LDR r11, [r0, #180]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #180]\n\t" + "STR r11, [r0, #180]\n\t" /* a[i+46] += m[46] * mu */ - "LDR r12, [%[m], #184]\n\t" - "LDR r11, [%[a], #184]\n\t" + "LDR r12, [r1, #184]\n\t" + "LDR r11, [r0, #184]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #184]\n\t" + "STR r11, [r0, #184]\n\t" /* a[i+47] += m[47] * mu */ - "LDR r12, [%[m], #188]\n\t" - "LDR r11, [%[a], #188]\n\t" + "LDR r12, [r1, #188]\n\t" + "LDR r11, [r0, #188]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #188]\n\t" + "STR r11, [r0, #188]\n\t" /* a[i+48] += m[48] * mu */ - "LDR r12, [%[m], #192]\n\t" - "LDR r11, [%[a], #192]\n\t" + "LDR r12, [r1, #192]\n\t" + "LDR r11, [r0, #192]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #192]\n\t" + "STR r11, [r0, #192]\n\t" /* a[i+49] += m[49] * mu */ - "LDR r12, [%[m], #196]\n\t" - "LDR r11, [%[a], #196]\n\t" + "LDR r12, [r1, #196]\n\t" + "LDR r11, [r0, #196]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #196]\n\t" + "STR r11, [r0, #196]\n\t" /* a[i+50] += m[50] * mu */ - "LDR r12, [%[m], #200]\n\t" - "LDR r11, [%[a], #200]\n\t" + "LDR r12, [r1, #200]\n\t" + "LDR r11, [r0, #200]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #200]\n\t" + "STR r11, [r0, #200]\n\t" /* a[i+51] += m[51] * mu */ - "LDR r12, [%[m], #204]\n\t" - "LDR r11, [%[a], #204]\n\t" + "LDR r12, [r1, #204]\n\t" + "LDR r11, [r0, #204]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #204]\n\t" + "STR r11, [r0, #204]\n\t" /* a[i+52] += m[52] * mu */ - "LDR r12, [%[m], #208]\n\t" - "LDR r11, [%[a], #208]\n\t" + "LDR r12, [r1, #208]\n\t" + "LDR r11, [r0, #208]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #208]\n\t" + "STR r11, [r0, #208]\n\t" /* a[i+53] += m[53] * mu */ - "LDR r12, [%[m], #212]\n\t" - "LDR r11, [%[a], #212]\n\t" + "LDR r12, [r1, #212]\n\t" + "LDR r11, [r0, #212]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #212]\n\t" + "STR r11, [r0, #212]\n\t" /* a[i+54] += m[54] * mu */ - "LDR r12, [%[m], #216]\n\t" - "LDR r11, [%[a], #216]\n\t" + "LDR r12, [r1, #216]\n\t" + "LDR r11, [r0, #216]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #216]\n\t" + "STR r11, [r0, #216]\n\t" /* a[i+55] += m[55] * mu */ - "LDR r12, [%[m], #220]\n\t" - "LDR r11, [%[a], #220]\n\t" + "LDR r12, [r1, #220]\n\t" + "LDR r11, [r0, #220]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #220]\n\t" + "STR r11, [r0, #220]\n\t" /* a[i+56] += m[56] * mu */ - "LDR r12, [%[m], #224]\n\t" - "LDR r11, [%[a], #224]\n\t" + "LDR r12, [r1, #224]\n\t" + "LDR r11, [r0, #224]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #224]\n\t" + "STR r11, [r0, #224]\n\t" /* a[i+57] += m[57] * mu */ - "LDR r12, [%[m], #228]\n\t" - "LDR r11, [%[a], #228]\n\t" + "LDR r12, [r1, #228]\n\t" + "LDR r11, [r0, #228]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #228]\n\t" + "STR r11, [r0, #228]\n\t" /* a[i+58] += m[58] * mu */ - "LDR r12, [%[m], #232]\n\t" - "LDR r11, [%[a], #232]\n\t" + "LDR r12, [r1, #232]\n\t" + "LDR r11, [r0, #232]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #232]\n\t" + "STR r11, [r0, #232]\n\t" /* a[i+59] += m[59] * mu */ - "LDR r12, [%[m], #236]\n\t" - "LDR r11, [%[a], #236]\n\t" + "LDR r12, [r1, #236]\n\t" + "LDR r11, [r0, #236]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #236]\n\t" + "STR r11, [r0, #236]\n\t" /* a[i+60] += m[60] * mu */ - "LDR r12, [%[m], #240]\n\t" - "LDR r11, [%[a], #240]\n\t" + "LDR r12, [r1, #240]\n\t" + "LDR r11, [r0, #240]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #240]\n\t" + "STR r11, [r0, #240]\n\t" /* a[i+61] += m[61] * mu */ - "LDR r12, [%[m], #244]\n\t" - "LDR r11, [%[a], #244]\n\t" + "LDR r12, [r1, #244]\n\t" + "LDR r11, [r0, #244]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #244]\n\t" + "STR r11, [r0, #244]\n\t" /* a[i+62] += m[62] * mu */ - "LDR r12, [%[m], #248]\n\t" - "LDR r11, [%[a], #248]\n\t" + "LDR r12, [r1, #248]\n\t" + "LDR r11, [r0, #248]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #248]\n\t" + "STR r11, [r0, #248]\n\t" /* a[i+63] += m[63] * mu */ - "LDR r12, [%[m], #252]\n\t" - "LDR r11, [%[a], #252]\n\t" + "LDR r12, [r1, #252]\n\t" + "LDR r11, [r0, #252]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "LDR lr, [%[a], #256]\n\t" + "LDR lr, [r0, #256]\n\t" "MOV r12, #0\n\t" "UMAAL r3, lr, r12, r12\n\t" - "STR r11, [%[a], #252]\n\t" + "STR r11, [r0, #252]\n\t" "ADDS r3, r3, r5\n\t" "ADC r5, lr, #0\n\t" - "STR r3, [%[a], #256]\n\t" + "STR r3, [r0, #256]\n\t" /* i += 1 */ "ADD r4, r4, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r4, #0x100\n\t" #if defined(__GNUC__) "BLT L_sp_2048_mont_reduce_64_word_%=\n\t" @@ -7262,22 +8018,33 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( "BLT.W L_sp_2048_mont_reduce_64_word_%=\n\t" #endif /* Loop Done */ - "STR r6, [%[a]]\n\t" - "STR r7, [%[a], #4]\n\t" - "STR r8, [%[a], #8]\n\t" - "STR r9, [%[a], #12]\n\t" - "STR r10, [%[a], #16]\n\t" - "MOV %[mp], r5\n\t" + "STR r6, [r0]\n\t" + "STR r7, [r0, #4]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #12]\n\t" + "STR r10, [r0, #16]\n\t" + "MOV r2, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_2048_cond_sub_64(a - 64, a, m, (sp_digit)0 - mp); } @@ -7301,10 +8068,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r11, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r11, [r1]\n\t" /* i = 0 */ "MOV r9, #0\n\t" /* ca = 0 */ @@ -7316,8 +8092,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( "L_sp_2048_mont_reduce_64_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "LDR r10, [%[a]]\n\t" - "MUL r8, %[mp], r10\n\t" + "LDR r10, [r0]\n\t" + "MUL r8, r2, r10\n\t" /* j = 0 */ "MOV r12, #0\n\t" "MOV r4, #0\n\t" @@ -7328,31 +8104,31 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( "L_sp_2048_mont_reduce_64_mul_%=:\n\t" #endif /* a[i+j+0] += m[j+0] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+1] += m[j+1] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+2] += m[j+2] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+3] += m[j+3] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" "CMP r12, #0x100\n\t" @@ -7363,16 +8139,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( #else "BLT.N L_sp_2048_mont_reduce_64_mul_%=\n\t" #endif - "LDR r10, [%[a], #256]\n\t" + "LDR r10, [r0, #256]\n\t" "ADDS r4, r4, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" "ADDS r10, r10, r4\n\t" "ADC r3, r3, r3\n\t" - "STR r10, [%[a], #256]\n\t" + "STR r10, [r0, #256]\n\t" /* i += 1 */ "ADD r9, r9, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r9, #0x100\n\t" #if defined(__GNUC__) "BLT L_sp_2048_mont_reduce_64_word_%=\n\t" @@ -7382,17 +8158,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_2048_mont_reduce_64( "BLT.N L_sp_2048_mont_reduce_64_word_%=\n\t" #endif /* Loop Done */ - "MOV %[mp], r3\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_2048_cond_sub_64(a - 64, a, m, (sp_digit)0 - mp); } @@ -7447,11 +8234,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_64(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r11, #0\n\t" - "ADD r12, %[a], #0x100\n\t" + "ADD r12, r1, #0x100\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_2048_sub_64_word:\n\t" @@ -7459,15 +8254,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_64(sp_digit* r, "L_sp_2048_sub_64_word_%=:\n\t" #endif "RSBS r11, r11, #0\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "SBC r11, r3, r3\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_2048_sub_64_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -7475,17 +8270,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_64(sp_digit* r, #else "BNE.N L_sp_2048_sub_64_word_%=\n\t" #endif - "MOV %[r], r11\n\t" + "MOV r0, r11\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -7508,131 +8314,150 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_sub_64(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -7660,53 +8485,73 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_2048_word_64(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r8, %[div], #16\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r8, r2, #16\n\t" "ADD r5, r8, #1\n\t" - "UDIV r6, %[d1], r5\n\t" - "LSL r7, %[div], #16\n\t" + "UDIV r6, r0, r5\n\t" + "LSL r7, r2, #16\n\t" "LSL r6, r6, #16\n\t" - "UMULL r3, r4, %[div], r6\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "SUBS r3, %[d1], r5\n\t" + "UMULL r3, r4, r2, r6\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "SUBS r3, r0, r5\n\t" "SBC r9, r9, r9\n\t" "ADD r9, r9, #1\n\t" "RSB r10, r9, #0\n\t" "LSL r9, r9, #16\n\t" "AND r7, r7, r10\n\t" "AND r8, r8, r10\n\t" - "SUBS %[d0], %[d0], r7\n\t" + "SUBS r1, r1, r7\n\t" "ADD r6, r6, r9\n\t" - "SBC %[d1], %[d1], r8\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "SBC r0, r0, r8\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "UMULL r3, r4, %[div], r3\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "UMULL r3, r4, r2, r3\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "MUL r3, %[div], r3\n\t" - "SUB %[d0], %[d0], r3\n\t" - "UDIV r3, %[d0], %[div]\n\t" - "ADD %[d1], r6, r3\n\t" + "MUL r3, r2, r3\n\t" + "SUB r1, r1, r3\n\t" + "UDIV r3, r1, r2\n\t" + "ADD r0, r6, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -7733,13 +8578,22 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_2048_word_64(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r5, %[div], #1\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r5, r2, #1\n\t" "ADD r5, r5, #1\n\t" - "MOV r6, %[d0]\n\t" - "MOV r7, %[d1]\n\t" + "MOV r6, r1\n\t" + "MOV r7, r0\n\t" /* Do top 32 */ "SUBS r8, r5, r7\n\t" "SBC r8, r8, r8\n\t" @@ -7773,29 +8627,40 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_2048_word_64(sp_digit d1, #endif "ADD r3, r3, r3\n\t" "ADD r3, r3, #1\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "SUBS r8, r9, %[div]\n\t" - "ADC %[d1], r3, #0\n\t" + "SUBS r8, r9, r2\n\t" + "ADC r0, r3, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -7924,9 +8789,17 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0xffffffff\n\t" "MOV r8, #1\n\t" "MOV r7, #0\n\t" @@ -7939,8 +8812,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, #else "L_sp_2048_cmp_64_words_%=:\n\t" #endif - "LDR r4, [%[a], r6]\n\t" - "LDR r5, [%[b], r6]\n\t" + "LDR r4, [r0, r6]\n\t" + "LDR r5, [r1, r6]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -7958,8 +8831,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, #endif "EOR r2, r2, r3\n\t" #else - "LDR r4, [%[a], #252]\n\t" - "LDR r5, [%[b], #252]\n\t" + "LDR r4, [r0, #252]\n\t" + "LDR r5, [r1, #252]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -7969,8 +8842,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #248]\n\t" - "LDR r5, [%[b], #248]\n\t" + "LDR r4, [r0, #248]\n\t" + "LDR r5, [r1, #248]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -7980,8 +8853,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #244]\n\t" - "LDR r5, [%[b], #244]\n\t" + "LDR r4, [r0, #244]\n\t" + "LDR r5, [r1, #244]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -7991,8 +8864,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #240]\n\t" - "LDR r5, [%[b], #240]\n\t" + "LDR r4, [r0, #240]\n\t" + "LDR r5, [r1, #240]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8002,8 +8875,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #236]\n\t" - "LDR r5, [%[b], #236]\n\t" + "LDR r4, [r0, #236]\n\t" + "LDR r5, [r1, #236]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8013,8 +8886,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #232]\n\t" - "LDR r5, [%[b], #232]\n\t" + "LDR r4, [r0, #232]\n\t" + "LDR r5, [r1, #232]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8024,8 +8897,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #228]\n\t" - "LDR r5, [%[b], #228]\n\t" + "LDR r4, [r0, #228]\n\t" + "LDR r5, [r1, #228]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8035,8 +8908,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #224]\n\t" - "LDR r5, [%[b], #224]\n\t" + "LDR r4, [r0, #224]\n\t" + "LDR r5, [r1, #224]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8046,8 +8919,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #220]\n\t" - "LDR r5, [%[b], #220]\n\t" + "LDR r4, [r0, #220]\n\t" + "LDR r5, [r1, #220]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8057,8 +8930,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #216]\n\t" - "LDR r5, [%[b], #216]\n\t" + "LDR r4, [r0, #216]\n\t" + "LDR r5, [r1, #216]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8068,8 +8941,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #212]\n\t" - "LDR r5, [%[b], #212]\n\t" + "LDR r4, [r0, #212]\n\t" + "LDR r5, [r1, #212]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8079,8 +8952,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #208]\n\t" - "LDR r5, [%[b], #208]\n\t" + "LDR r4, [r0, #208]\n\t" + "LDR r5, [r1, #208]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8090,8 +8963,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #204]\n\t" - "LDR r5, [%[b], #204]\n\t" + "LDR r4, [r0, #204]\n\t" + "LDR r5, [r1, #204]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8101,8 +8974,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #200]\n\t" - "LDR r5, [%[b], #200]\n\t" + "LDR r4, [r0, #200]\n\t" + "LDR r5, [r1, #200]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8112,8 +8985,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #196]\n\t" - "LDR r5, [%[b], #196]\n\t" + "LDR r4, [r0, #196]\n\t" + "LDR r5, [r1, #196]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8123,8 +8996,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #192]\n\t" - "LDR r5, [%[b], #192]\n\t" + "LDR r4, [r0, #192]\n\t" + "LDR r5, [r1, #192]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8134,8 +9007,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #188]\n\t" - "LDR r5, [%[b], #188]\n\t" + "LDR r4, [r0, #188]\n\t" + "LDR r5, [r1, #188]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8145,8 +9018,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #184]\n\t" - "LDR r5, [%[b], #184]\n\t" + "LDR r4, [r0, #184]\n\t" + "LDR r5, [r1, #184]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8156,8 +9029,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #180]\n\t" - "LDR r5, [%[b], #180]\n\t" + "LDR r4, [r0, #180]\n\t" + "LDR r5, [r1, #180]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8167,8 +9040,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #176]\n\t" - "LDR r5, [%[b], #176]\n\t" + "LDR r4, [r0, #176]\n\t" + "LDR r5, [r1, #176]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8178,8 +9051,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #172]\n\t" - "LDR r5, [%[b], #172]\n\t" + "LDR r4, [r0, #172]\n\t" + "LDR r5, [r1, #172]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8189,8 +9062,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #168]\n\t" - "LDR r5, [%[b], #168]\n\t" + "LDR r4, [r0, #168]\n\t" + "LDR r5, [r1, #168]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8200,8 +9073,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #164]\n\t" - "LDR r5, [%[b], #164]\n\t" + "LDR r4, [r0, #164]\n\t" + "LDR r5, [r1, #164]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8211,8 +9084,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #160]\n\t" - "LDR r5, [%[b], #160]\n\t" + "LDR r4, [r0, #160]\n\t" + "LDR r5, [r1, #160]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8222,8 +9095,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #156]\n\t" - "LDR r5, [%[b], #156]\n\t" + "LDR r4, [r0, #156]\n\t" + "LDR r5, [r1, #156]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8233,8 +9106,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #152]\n\t" - "LDR r5, [%[b], #152]\n\t" + "LDR r4, [r0, #152]\n\t" + "LDR r5, [r1, #152]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8244,8 +9117,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #148]\n\t" - "LDR r5, [%[b], #148]\n\t" + "LDR r4, [r0, #148]\n\t" + "LDR r5, [r1, #148]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8255,8 +9128,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #144]\n\t" - "LDR r5, [%[b], #144]\n\t" + "LDR r4, [r0, #144]\n\t" + "LDR r5, [r1, #144]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8266,8 +9139,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #140]\n\t" - "LDR r5, [%[b], #140]\n\t" + "LDR r4, [r0, #140]\n\t" + "LDR r5, [r1, #140]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8277,8 +9150,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #136]\n\t" - "LDR r5, [%[b], #136]\n\t" + "LDR r4, [r0, #136]\n\t" + "LDR r5, [r1, #136]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8288,8 +9161,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #132]\n\t" - "LDR r5, [%[b], #132]\n\t" + "LDR r4, [r0, #132]\n\t" + "LDR r5, [r1, #132]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8299,8 +9172,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #128]\n\t" - "LDR r5, [%[b], #128]\n\t" + "LDR r4, [r0, #128]\n\t" + "LDR r5, [r1, #128]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8310,8 +9183,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #124]\n\t" - "LDR r5, [%[b], #124]\n\t" + "LDR r4, [r0, #124]\n\t" + "LDR r5, [r1, #124]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8321,8 +9194,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #120]\n\t" - "LDR r5, [%[b], #120]\n\t" + "LDR r4, [r0, #120]\n\t" + "LDR r5, [r1, #120]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8332,8 +9205,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #116]\n\t" - "LDR r5, [%[b], #116]\n\t" + "LDR r4, [r0, #116]\n\t" + "LDR r5, [r1, #116]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8343,8 +9216,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #112]\n\t" - "LDR r5, [%[b], #112]\n\t" + "LDR r4, [r0, #112]\n\t" + "LDR r5, [r1, #112]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8354,8 +9227,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #108]\n\t" - "LDR r5, [%[b], #108]\n\t" + "LDR r4, [r0, #108]\n\t" + "LDR r5, [r1, #108]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8365,8 +9238,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #104]\n\t" - "LDR r5, [%[b], #104]\n\t" + "LDR r4, [r0, #104]\n\t" + "LDR r5, [r1, #104]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8376,8 +9249,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #100]\n\t" - "LDR r5, [%[b], #100]\n\t" + "LDR r4, [r0, #100]\n\t" + "LDR r5, [r1, #100]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8387,8 +9260,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #96]\n\t" - "LDR r5, [%[b], #96]\n\t" + "LDR r4, [r0, #96]\n\t" + "LDR r5, [r1, #96]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8398,8 +9271,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #92]\n\t" - "LDR r5, [%[b], #92]\n\t" + "LDR r4, [r0, #92]\n\t" + "LDR r5, [r1, #92]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8409,8 +9282,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #88]\n\t" - "LDR r5, [%[b], #88]\n\t" + "LDR r4, [r0, #88]\n\t" + "LDR r5, [r1, #88]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8420,8 +9293,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #84]\n\t" - "LDR r5, [%[b], #84]\n\t" + "LDR r4, [r0, #84]\n\t" + "LDR r5, [r1, #84]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8431,8 +9304,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #80]\n\t" - "LDR r5, [%[b], #80]\n\t" + "LDR r4, [r0, #80]\n\t" + "LDR r5, [r1, #80]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8442,8 +9315,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #76]\n\t" - "LDR r5, [%[b], #76]\n\t" + "LDR r4, [r0, #76]\n\t" + "LDR r5, [r1, #76]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8453,8 +9326,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #72]\n\t" - "LDR r5, [%[b], #72]\n\t" + "LDR r4, [r0, #72]\n\t" + "LDR r5, [r1, #72]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8464,8 +9337,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #68]\n\t" - "LDR r5, [%[b], #68]\n\t" + "LDR r4, [r0, #68]\n\t" + "LDR r5, [r1, #68]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8475,8 +9348,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #64]\n\t" - "LDR r5, [%[b], #64]\n\t" + "LDR r4, [r0, #64]\n\t" + "LDR r5, [r1, #64]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8486,8 +9359,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #60]\n\t" - "LDR r5, [%[b], #60]\n\t" + "LDR r4, [r0, #60]\n\t" + "LDR r5, [r1, #60]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8497,8 +9370,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #56]\n\t" - "LDR r5, [%[b], #56]\n\t" + "LDR r4, [r0, #56]\n\t" + "LDR r5, [r1, #56]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8508,8 +9381,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #52]\n\t" - "LDR r5, [%[b], #52]\n\t" + "LDR r4, [r0, #52]\n\t" + "LDR r5, [r1, #52]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8519,8 +9392,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #48]\n\t" - "LDR r5, [%[b], #48]\n\t" + "LDR r4, [r0, #48]\n\t" + "LDR r5, [r1, #48]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8530,8 +9403,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #44]\n\t" - "LDR r5, [%[b], #44]\n\t" + "LDR r4, [r0, #44]\n\t" + "LDR r5, [r1, #44]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8541,8 +9414,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #40]\n\t" - "LDR r5, [%[b], #40]\n\t" + "LDR r4, [r0, #40]\n\t" + "LDR r5, [r1, #40]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8552,8 +9425,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #36]\n\t" - "LDR r5, [%[b], #36]\n\t" + "LDR r4, [r0, #36]\n\t" + "LDR r5, [r1, #36]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8563,8 +9436,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #32]\n\t" - "LDR r5, [%[b], #32]\n\t" + "LDR r4, [r0, #32]\n\t" + "LDR r5, [r1, #32]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8574,8 +9447,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #28]\n\t" - "LDR r5, [%[b], #28]\n\t" + "LDR r4, [r0, #28]\n\t" + "LDR r5, [r1, #28]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8585,8 +9458,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #24]\n\t" - "LDR r5, [%[b], #24]\n\t" + "LDR r4, [r0, #24]\n\t" + "LDR r5, [r1, #24]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8596,8 +9469,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #20]\n\t" - "LDR r5, [%[b], #20]\n\t" + "LDR r4, [r0, #20]\n\t" + "LDR r5, [r1, #20]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8607,8 +9480,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #16]\n\t" - "LDR r5, [%[b], #16]\n\t" + "LDR r4, [r0, #16]\n\t" + "LDR r5, [r1, #16]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8618,8 +9491,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #12]\n\t" - "LDR r5, [%[b], #12]\n\t" + "LDR r4, [r0, #12]\n\t" + "LDR r5, [r1, #12]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8629,8 +9502,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #8]\n\t" - "LDR r5, [%[b], #8]\n\t" + "LDR r4, [r0, #8]\n\t" + "LDR r5, [r1, #8]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8640,8 +9513,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #4]\n\t" - "LDR r5, [%[b], #4]\n\t" + "LDR r4, [r0, #4]\n\t" + "LDR r5, [r1, #4]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8651,8 +9524,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[b]]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r1]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -8664,16 +9537,26 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_2048_cmp_64(const sp_digit* a, "movne r3, r7\n\t" "EOR r2, r2, r3\n\t" #endif /*WOLFSSL_SP_SMALL */ - "MOV %[a], r2\n\t" + "MOV r0, r2\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -9187,9 +10070,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_add_32(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" "MOV r8, #0\n\t" "MOV r4, #0\n\t" @@ -9200,12 +10092,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_add_32(sp_digit* r, "L_sp_2048_cond_add_32_words_%=:\n\t" #endif "ADDS r5, r5, #0xffffffff\n\t" - "LDR r6, [%[a], r4]\n\t" - "LDR r7, [%[b], r4]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r4]\n\t" + "LDR r7, [r2, r4]\n\t" + "AND r7, r7, r3\n\t" "ADCS r6, r6, r7\n\t" "ADC r5, r8, r8\n\t" - "STR r6, [%[r], r4]\n\t" + "STR r6, [r0, r4]\n\t" "ADD r4, r4, #4\n\t" "CMP r4, #0x80\n\t" #if defined(__GNUC__) @@ -9215,16 +10107,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_add_32(sp_digit* r, #else "BLT.N L_sp_2048_cond_add_32_words_%=\n\t" #endif - "MOV %[r], r5\n\t" + "MOV r0, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -9251,132 +10155,153 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_2048_cond_add_32(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADDS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "ADC %[r], r10, r10\n\t" + "STM r0!, {r6, r7}\n\t" + "ADC r0, r10, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -9678,403 +10603,422 @@ WC_OMIT_FRAME_POINTER static void sp_2048_lshift_64(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register byte n __asm__ ("r2") = (byte)n_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)n + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "RSB r7, %[n], #31\n\t" - "LDR r5, [%[a], #252]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "RSB r7, r2, #31\n\t" + "LDR r5, [r1, #252]\n\t" "LSR r6, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r6, r6, r7\n\t" - "LDR r4, [%[a], #248]\n\t" - "STR r6, [%[r], #256]\n\t" + "LDR r4, [r1, #248]\n\t" + "STR r6, [r0, #256]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #244]\n\t" - "STR r5, [%[r], #252]\n\t" + "LDR r6, [r1, #244]\n\t" + "STR r5, [r0, #252]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #240]\n\t" - "STR r4, [%[r], #248]\n\t" + "LDR r5, [r1, #240]\n\t" + "STR r4, [r0, #248]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #236]\n\t" - "STR r6, [%[r], #244]\n\t" + "LDR r4, [r1, #236]\n\t" + "STR r6, [r0, #244]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #232]\n\t" - "STR r5, [%[r], #240]\n\t" + "LDR r6, [r1, #232]\n\t" + "STR r5, [r0, #240]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #228]\n\t" - "STR r4, [%[r], #236]\n\t" + "LDR r5, [r1, #228]\n\t" + "STR r4, [r0, #236]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #224]\n\t" - "STR r6, [%[r], #232]\n\t" + "LDR r4, [r1, #224]\n\t" + "STR r6, [r0, #232]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #220]\n\t" - "STR r5, [%[r], #228]\n\t" + "LDR r6, [r1, #220]\n\t" + "STR r5, [r0, #228]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #216]\n\t" - "STR r4, [%[r], #224]\n\t" + "LDR r5, [r1, #216]\n\t" + "STR r4, [r0, #224]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #212]\n\t" - "STR r6, [%[r], #220]\n\t" + "LDR r4, [r1, #212]\n\t" + "STR r6, [r0, #220]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #208]\n\t" - "STR r5, [%[r], #216]\n\t" + "LDR r6, [r1, #208]\n\t" + "STR r5, [r0, #216]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #204]\n\t" - "STR r4, [%[r], #212]\n\t" + "LDR r5, [r1, #204]\n\t" + "STR r4, [r0, #212]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #200]\n\t" - "STR r6, [%[r], #208]\n\t" + "LDR r4, [r1, #200]\n\t" + "STR r6, [r0, #208]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #196]\n\t" - "STR r5, [%[r], #204]\n\t" + "LDR r6, [r1, #196]\n\t" + "STR r5, [r0, #204]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #192]\n\t" - "STR r4, [%[r], #200]\n\t" + "LDR r5, [r1, #192]\n\t" + "STR r4, [r0, #200]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #188]\n\t" - "STR r6, [%[r], #196]\n\t" + "LDR r4, [r1, #188]\n\t" + "STR r6, [r0, #196]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #184]\n\t" - "STR r5, [%[r], #192]\n\t" + "LDR r6, [r1, #184]\n\t" + "STR r5, [r0, #192]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #180]\n\t" - "STR r4, [%[r], #188]\n\t" + "LDR r5, [r1, #180]\n\t" + "STR r4, [r0, #188]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #176]\n\t" - "STR r6, [%[r], #184]\n\t" + "LDR r4, [r1, #176]\n\t" + "STR r6, [r0, #184]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #172]\n\t" - "STR r5, [%[r], #180]\n\t" + "LDR r6, [r1, #172]\n\t" + "STR r5, [r0, #180]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #168]\n\t" - "STR r4, [%[r], #176]\n\t" + "LDR r5, [r1, #168]\n\t" + "STR r4, [r0, #176]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #164]\n\t" - "STR r6, [%[r], #172]\n\t" + "LDR r4, [r1, #164]\n\t" + "STR r6, [r0, #172]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #160]\n\t" - "STR r5, [%[r], #168]\n\t" + "LDR r6, [r1, #160]\n\t" + "STR r5, [r0, #168]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #156]\n\t" - "STR r4, [%[r], #164]\n\t" + "LDR r5, [r1, #156]\n\t" + "STR r4, [r0, #164]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #152]\n\t" - "STR r6, [%[r], #160]\n\t" + "LDR r4, [r1, #152]\n\t" + "STR r6, [r0, #160]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #148]\n\t" - "STR r5, [%[r], #156]\n\t" + "LDR r6, [r1, #148]\n\t" + "STR r5, [r0, #156]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #144]\n\t" - "STR r4, [%[r], #152]\n\t" + "LDR r5, [r1, #144]\n\t" + "STR r4, [r0, #152]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #140]\n\t" - "STR r6, [%[r], #148]\n\t" + "LDR r4, [r1, #140]\n\t" + "STR r6, [r0, #148]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #136]\n\t" - "STR r5, [%[r], #144]\n\t" + "LDR r6, [r1, #136]\n\t" + "STR r5, [r0, #144]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #132]\n\t" - "STR r4, [%[r], #140]\n\t" + "LDR r5, [r1, #132]\n\t" + "STR r4, [r0, #140]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #128]\n\t" - "STR r6, [%[r], #136]\n\t" + "LDR r4, [r1, #128]\n\t" + "STR r6, [r0, #136]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #124]\n\t" - "STR r5, [%[r], #132]\n\t" + "LDR r6, [r1, #124]\n\t" + "STR r5, [r0, #132]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #120]\n\t" - "STR r4, [%[r], #128]\n\t" + "LDR r5, [r1, #120]\n\t" + "STR r4, [r0, #128]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #116]\n\t" - "STR r6, [%[r], #124]\n\t" + "LDR r4, [r1, #116]\n\t" + "STR r6, [r0, #124]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #112]\n\t" - "STR r5, [%[r], #120]\n\t" + "LDR r6, [r1, #112]\n\t" + "STR r5, [r0, #120]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #108]\n\t" - "STR r4, [%[r], #116]\n\t" + "LDR r5, [r1, #108]\n\t" + "STR r4, [r0, #116]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #104]\n\t" - "STR r6, [%[r], #112]\n\t" + "LDR r4, [r1, #104]\n\t" + "STR r6, [r0, #112]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #100]\n\t" - "STR r5, [%[r], #108]\n\t" + "LDR r6, [r1, #100]\n\t" + "STR r5, [r0, #108]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #96]\n\t" - "STR r4, [%[r], #104]\n\t" + "LDR r5, [r1, #96]\n\t" + "STR r4, [r0, #104]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #92]\n\t" - "STR r6, [%[r], #100]\n\t" + "LDR r4, [r1, #92]\n\t" + "STR r6, [r0, #100]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #88]\n\t" - "STR r5, [%[r], #96]\n\t" + "LDR r6, [r1, #88]\n\t" + "STR r5, [r0, #96]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #84]\n\t" - "STR r4, [%[r], #92]\n\t" + "LDR r5, [r1, #84]\n\t" + "STR r4, [r0, #92]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #80]\n\t" - "STR r6, [%[r], #88]\n\t" + "LDR r4, [r1, #80]\n\t" + "STR r6, [r0, #88]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #76]\n\t" - "STR r5, [%[r], #84]\n\t" + "LDR r6, [r1, #76]\n\t" + "STR r5, [r0, #84]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #72]\n\t" - "STR r4, [%[r], #80]\n\t" + "LDR r5, [r1, #72]\n\t" + "STR r4, [r0, #80]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #68]\n\t" - "STR r6, [%[r], #76]\n\t" + "LDR r4, [r1, #68]\n\t" + "STR r6, [r0, #76]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #64]\n\t" - "STR r5, [%[r], #72]\n\t" + "LDR r6, [r1, #64]\n\t" + "STR r5, [r0, #72]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #60]\n\t" - "STR r4, [%[r], #68]\n\t" + "LDR r5, [r1, #60]\n\t" + "STR r4, [r0, #68]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #56]\n\t" - "STR r6, [%[r], #64]\n\t" + "LDR r4, [r1, #56]\n\t" + "STR r6, [r0, #64]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #52]\n\t" - "STR r5, [%[r], #60]\n\t" + "LDR r6, [r1, #52]\n\t" + "STR r5, [r0, #60]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #48]\n\t" - "STR r4, [%[r], #56]\n\t" + "LDR r5, [r1, #48]\n\t" + "STR r4, [r0, #56]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #44]\n\t" - "STR r6, [%[r], #52]\n\t" + "LDR r4, [r1, #44]\n\t" + "STR r6, [r0, #52]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #40]\n\t" - "STR r5, [%[r], #48]\n\t" + "LDR r6, [r1, #40]\n\t" + "STR r5, [r0, #48]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #36]\n\t" - "STR r4, [%[r], #44]\n\t" + "LDR r5, [r1, #36]\n\t" + "STR r4, [r0, #44]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #32]\n\t" - "STR r6, [%[r], #40]\n\t" + "LDR r4, [r1, #32]\n\t" + "STR r6, [r0, #40]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #28]\n\t" - "STR r5, [%[r], #36]\n\t" + "LDR r6, [r1, #28]\n\t" + "STR r5, [r0, #36]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #24]\n\t" - "STR r4, [%[r], #32]\n\t" + "LDR r5, [r1, #24]\n\t" + "STR r4, [r0, #32]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #20]\n\t" - "STR r6, [%[r], #28]\n\t" + "LDR r4, [r1, #20]\n\t" + "STR r6, [r0, #28]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #16]\n\t" - "STR r5, [%[r], #24]\n\t" + "LDR r6, [r1, #16]\n\t" + "STR r5, [r0, #24]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #12]\n\t" - "STR r4, [%[r], #20]\n\t" + "LDR r5, [r1, #12]\n\t" + "STR r4, [r0, #20]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #8]\n\t" - "STR r6, [%[r], #16]\n\t" + "LDR r4, [r1, #8]\n\t" + "STR r6, [r0, #16]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #4]\n\t" - "STR r5, [%[r], #12]\n\t" + "LDR r6, [r1, #4]\n\t" + "STR r5, [r0, #12]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a]]\n\t" - "STR r4, [%[r], #8]\n\t" + "LDR r5, [r1]\n\t" + "STR r4, [r0, #8]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "STR r5, [%[r]]\n\t" - "STR r6, [%[r], #4]\n\t" + "STR r5, [r0]\n\t" + "STR r6, [r0, #4]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [n] "+r" (n) : + : "memory", "cc", "r4", "r5", "r6", "r3", "r7" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [n] "r" (n) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r3", "r7" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + n = (byte)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Modular exponentiate 2 to the e mod m. (r = 2^e mod m) @@ -10505,967 +11449,975 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_12(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #48\n\t" /* A[0] * B[0] */ - "LDR r11, [%[a]]\n\t" - "LDR r12, [%[b]]\n\t" + "LDR r11, [r1]\n\t" + "LDR r12, [r2]\n\t" "UMULL r3, r4, r11, r12\n\t" "MOV r5, #0\n\t" "STR r3, [sp]\n\t" /* A[0] * B[1] */ - "LDR r9, [%[b], #4]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[0] */ - "LDR r8, [%[a], #4]\n\t" + "LDR r8, [r1, #4]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #4]\n\t" /* A[2] * B[0] */ - "LDR r8, [%[a], #8]\n\t" + "LDR r8, [r1, #8]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[1] */ - "LDR r11, [%[a], #4]\n\t" - "LDR r12, [%[b], #4]\n\t" + "LDR r11, [r1, #4]\n\t" + "LDR r12, [r2, #4]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[0] * B[2] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #8]\n\t" /* A[0] * B[3] */ - "LDR r9, [%[b], #12]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[2] */ - "LDR r9, [%[b], #8]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[1] */ - "LDR r8, [%[a], #8]\n\t" + "LDR r8, [r1, #8]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[0] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #12]\n\t" /* A[4] * B[0] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[1] */ - "LDR r8, [%[a], #12]\n\t" + "LDR r8, [r1, #12]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[2] */ - "LDR r11, [%[a], #8]\n\t" - "LDR r12, [%[b], #8]\n\t" + "LDR r11, [r1, #8]\n\t" + "LDR r12, [r2, #8]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[3] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[0] * B[4] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #16]\n\t" /* A[0] * B[5] */ - "LDR r9, [%[b], #20]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[4] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[3] */ - "LDR r9, [%[b], #12]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[2] */ - "LDR r8, [%[a], #12]\n\t" + "LDR r8, [r1, #12]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[1] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[0] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #20]\n\t" /* A[6] * B[0] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[1] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[2] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[3] */ - "LDR r11, [%[a], #12]\n\t" - "LDR r12, [%[b], #12]\n\t" + "LDR r11, [r1, #12]\n\t" + "LDR r12, [r2, #12]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[4] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[5] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[0] * B[6] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #24]\n\t" /* A[0] * B[7] */ - "LDR r9, [%[b], #28]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[6] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[5] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[4] */ - "LDR r9, [%[b], #16]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[3] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[2] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[1] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[0] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #28]\n\t" /* A[8] * B[0] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[1] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[2] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[3] */ - "LDR r8, [%[a], #20]\n\t" + "LDR r8, [r1, #20]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[4] */ - "LDR r11, [%[a], #16]\n\t" - "LDR r12, [%[b], #16]\n\t" + "LDR r11, [r1, #16]\n\t" + "LDR r12, [r2, #16]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[5] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[6] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[7] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[0] * B[8] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #32]\n\t" /* A[0] * B[9] */ - "LDR r9, [%[b], #36]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[8] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[7] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[6] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[5] */ - "LDR r9, [%[b], #20]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[4] */ - "LDR r8, [%[a], #20]\n\t" + "LDR r8, [r1, #20]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[3] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[2] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[1] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[0] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #36]\n\t" /* A[10] * B[0] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[1] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[2] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[3] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[4] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[5] */ - "LDR r11, [%[a], #20]\n\t" - "LDR r12, [%[b], #20]\n\t" + "LDR r11, [r1, #20]\n\t" + "LDR r12, [r2, #20]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[6] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[7] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[8] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[9] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[0] * B[10] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #40]\n\t" /* A[0] * B[11] */ - "LDR r9, [%[b], #44]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[10] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[9] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[8] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[7] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[6] */ - "LDR r9, [%[b], #24]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[5] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[4] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[3] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[2] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[1] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[0] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #44]\n\t" /* A[11] * B[1] */ - "LDR r9, [%[b], #4]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[2] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[3] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[4] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[5] */ - "LDR r8, [%[a], #28]\n\t" + "LDR r8, [r1, #28]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[6] */ - "LDR r11, [%[a], #24]\n\t" - "LDR r12, [%[b], #24]\n\t" + "LDR r11, [r1, #24]\n\t" + "LDR r12, [r2, #24]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[7] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[8] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[9] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[10] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[11] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #48]\n\t" + "STR r3, [r0, #48]\n\t" /* A[2] * B[11] */ - "LDR r8, [%[a], #8]\n\t" + "LDR r8, [r1, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[10] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[9] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[8] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[7] */ - "LDR r9, [%[b], #28]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[6] */ - "LDR r8, [%[a], #28]\n\t" + "LDR r8, [r1, #28]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[5] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[4] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[3] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[2] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #52]\n\t" + "STR r4, [r0, #52]\n\t" /* A[11] * B[3] */ - "LDR r9, [%[b], #12]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[4] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[5] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[6] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[7] */ - "LDR r11, [%[a], #28]\n\t" - "LDR r12, [%[b], #28]\n\t" + "LDR r11, [r1, #28]\n\t" + "LDR r12, [r2, #28]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[8] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[9] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[10] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[11] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #56]\n\t" + "STR r5, [r0, #56]\n\t" /* A[4] * B[11] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[10] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[9] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[8] */ - "LDR r9, [%[b], #32]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[7] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[6] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[5] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[4] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #60]\n\t" + "STR r3, [r0, #60]\n\t" /* A[11] * B[5] */ - "LDR r9, [%[b], #20]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[6] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[7] */ - "LDR r8, [%[a], #36]\n\t" + "LDR r8, [r1, #36]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[8] */ - "LDR r11, [%[a], #32]\n\t" - "LDR r12, [%[b], #32]\n\t" + "LDR r11, [r1, #32]\n\t" + "LDR r12, [r2, #32]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[9] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[10] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[11] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #64]\n\t" + "STR r4, [r0, #64]\n\t" /* A[6] * B[11] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[10] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[9] */ - "LDR r9, [%[b], #36]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[8] */ - "LDR r8, [%[a], #36]\n\t" + "LDR r8, [r1, #36]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[7] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[6] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #68]\n\t" + "STR r5, [r0, #68]\n\t" /* A[11] * B[7] */ - "LDR r9, [%[b], #28]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[8] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[9] */ - "LDR r11, [%[a], #36]\n\t" - "LDR r12, [%[b], #36]\n\t" + "LDR r11, [r1, #36]\n\t" + "LDR r12, [r2, #36]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[10] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[11] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #72]\n\t" + "STR r3, [r0, #72]\n\t" /* A[8] * B[11] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[10] */ - "LDR r9, [%[b], #40]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[9] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[8] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #76]\n\t" + "STR r4, [r0, #76]\n\t" /* A[11] * B[9] */ "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" @@ -11473,20 +12425,20 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_12(sp_digit* r, const sp_digit* a, "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[10] */ - "LDR r11, [%[a], #40]\n\t" - "LDR r12, [%[b], #40]\n\t" + "LDR r11, [r1, #40]\n\t" + "LDR r12, [r2, #40]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[11] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #80]\n\t" + "STR r5, [r0, #80]\n\t" /* A[10] * B[11] */ "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" @@ -11494,32 +12446,43 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_12(sp_digit* r, const sp_digit* a, "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[10] */ - "LDR r8, [%[a], #44]\n\t" + "LDR r8, [r1, #44]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #84]\n\t" + "STR r3, [r0, #84]\n\t" /* A[11] * B[11] */ "UMLAL r4, r5, r8, r9\n\t" - "STR r4, [%[r], #88]\n\t" - "STR r5, [%[r], #92]\n\t" + "STR r4, [r0, #88]\n\t" + "STR r5, [r0, #92]\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r11", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r11", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Add b to a into r. (r = a + b) @@ -11540,41 +12503,60 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_add_12(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -11594,61 +12576,79 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_in_place_24(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SUBS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "SBC %[a], r9, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "SBC r0, r9, r9\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -11670,62 +12670,81 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_add_24(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -11814,103 +12833,121 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_in_place_48(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SUBS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "SBC %[a], r9, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "SBC r0, r9, r9\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -11932,104 +12969,123 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_add_48(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -12118,187 +13174,205 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_in_place_96(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SUBS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "SBC %[a], r9, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "SBC r0, r9, r9\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -12320,188 +13394,207 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_add_96(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -12589,18 +13682,26 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #48\n\t" /* A[0] * A[0] */ - "LDR r10, [%[a]]\n\t" + "LDR r10, [r1]\n\t" "UMULL r8, r3, r10, r10\n\t" "MOV r4, #0\n\t" "STR r8, [sp]\n\t" /* A[0] * A[1] */ - "LDR r10, [%[a], #4]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #4]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -12612,8 +13713,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADC r2, r2, #0\n\t" "STR r3, [sp, #4]\n\t" /* A[0] * A[2] */ - "LDR r10, [%[a], #8]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #8]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" @@ -12624,15 +13725,15 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * A[1] */ - "LDR r10, [%[a], #4]\n\t" + "LDR r10, [r1, #4]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #8]\n\t" /* A[0] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -12643,8 +13744,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * A[2] */ - "LDR r10, [%[a], #8]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #8]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -12654,8 +13755,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADC r4, r4, #0\n\t" "STR r2, [sp, #12]\n\t" /* A[0] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -12666,8 +13767,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "MOV r2, #0\n\t" "ADC r2, r2, #0\n\t" /* A[1] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -12676,28 +13777,28 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" /* A[2] * A[2] */ - "LDR r10, [%[a], #8]\n\t" + "LDR r10, [r1, #8]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" "STR r3, [sp, #16]\n\t" /* A[0] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -12710,27 +13811,27 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #20]\n\t" /* A[0] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[3] */ - "LDR r10, [%[a], #12]\n\t" + "LDR r10, [r1, #12]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -12743,28 +13844,28 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #24]\n\t" /* A[0] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -12777,34 +13878,34 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADC r2, r2, r7\n\t" "STR r3, [sp, #28]\n\t" /* A[0] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[4] */ - "LDR r10, [%[a], #16]\n\t" + "LDR r10, [r1, #16]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -12817,35 +13918,35 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #32]\n\t" /* A[0] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -12858,41 +13959,41 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #36]\n\t" /* A[0] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[5] */ - "LDR r10, [%[a], #20]\n\t" + "LDR r10, [r1, #20]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -12905,42 +14006,42 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADC r2, r2, r7\n\t" "STR r3, [sp, #40]\n\t" /* A[0] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -12953,41 +14054,41 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #44]\n\t" /* A[1] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[2] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[6] */ - "LDR r10, [%[a], #24]\n\t" + "LDR r10, [r1, #24]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -12998,37 +14099,37 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r5\n\t" "ADCS r3, r3, r6\n\t" "ADC r4, r4, r7\n\t" - "STR r2, [%[r], #48]\n\t" + "STR r2, [r0, #48]\n\t" /* A[2] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[3] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -13039,36 +14140,36 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r5\n\t" "ADCS r4, r4, r6\n\t" "ADC r2, r2, r7\n\t" - "STR r3, [%[r], #52]\n\t" + "STR r3, [r0, #52]\n\t" /* A[3] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[4] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[7] */ - "LDR r10, [%[a], #28]\n\t" + "LDR r10, [r1, #28]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -13079,30 +14180,30 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r5\n\t" "ADCS r2, r2, r6\n\t" "ADC r3, r3, r7\n\t" - "STR r4, [%[r], #56]\n\t" + "STR r4, [r0, #56]\n\t" /* A[4] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[5] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -13113,29 +14214,29 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r5\n\t" "ADCS r3, r3, r6\n\t" "ADC r4, r4, r7\n\t" - "STR r2, [%[r], #60]\n\t" + "STR r2, [r0, #60]\n\t" /* A[5] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[6] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[8] */ - "LDR r10, [%[a], #32]\n\t" + "LDR r10, [r1, #32]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -13146,23 +14247,23 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r5\n\t" "ADCS r4, r4, r6\n\t" "ADC r2, r2, r7\n\t" - "STR r3, [%[r], #64]\n\t" + "STR r3, [r0, #64]\n\t" /* A[6] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[7] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -13173,10 +14274,10 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r5\n\t" "ADCS r2, r2, r6\n\t" "ADC r3, r3, r7\n\t" - "STR r4, [%[r], #68]\n\t" + "STR r4, [r0, #68]\n\t" /* A[7] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -13187,8 +14288,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[8] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -13197,15 +14298,15 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADCS r3, r3, r9\n\t" "ADC r4, r4, #0\n\t" /* A[9] * A[9] */ - "LDR r10, [%[a], #36]\n\t" + "LDR r10, [r1, #36]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" "ADC r4, r4, #0\n\t" - "STR r2, [%[r], #72]\n\t" + "STR r2, [r0, #72]\n\t" /* A[8] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -13216,8 +14317,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "MOV r2, #0\n\t" "ADC r2, r2, #0\n\t" /* A[9] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -13225,10 +14326,10 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" - "STR r3, [%[r], #76]\n\t" + "STR r3, [r0, #76]\n\t" /* A[9] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" @@ -13239,15 +14340,15 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[10] * A[10] */ - "LDR r10, [%[a], #40]\n\t" + "LDR r10, [r1, #40]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #80]\n\t" + "STR r4, [r0, #80]\n\t" /* A[10] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -13257,28 +14358,38 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_12(sp_digit* r, const sp_digit* a) "ADCS r3, r3, r9\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" - "STR r2, [%[r], #84]\n\t" + "STR r2, [r0, #84]\n\t" /* A[11] * A[11] */ - "LDR r10, [%[a], #44]\n\t" + "LDR r10, [r1, #44]\n\t" "UMLAL r3, r4, r10, r10\n\t" - "STR r3, [%[r], #88]\n\t" - "STR r4, [%[r], #92]\n\t" + "STR r3, [r0, #88]\n\t" + "STR r4, [r0, #92]\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Sub b from a into r. (r = a - b) @@ -13299,40 +14410,59 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_12(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -13390,61 +14520,80 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_24(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -13502,103 +14651,122 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_48(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -13658,11 +14826,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_add_96(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r3, #0\n\t" - "ADD r12, %[a], #0x180\n\t" + "ADD r12, r1, #0x180\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_3072_add_96_word:\n\t" @@ -13670,16 +14846,16 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_add_96(sp_digit* r, "L_sp_3072_add_96_word_%=:\n\t" #endif "ADDS r3, r3, #0xffffffff\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "MOV r4, #0\n\t" "ADC r3, r4, #0\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_3072_add_96_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -13687,17 +14863,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_add_96(sp_digit* r, #else "BNE.N L_sp_3072_add_96_word_%=\n\t" #endif - "MOV %[r], r3\n\t" + "MOV r0, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -13719,11 +14906,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_in_place_96(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "ADD r11, %[a], #0x180\n\t" + "ADD r11, r0, #0x180\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_3072_sub_in_place_96_word:\n\t" @@ -13731,15 +14926,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_in_place_96(sp_digit* a, "L_sp_3072_sub_in_place_96_word_%=:\n\t" #endif "RSBS r10, r10, #0\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" "SBC r10, r10, r10\n\t" - "CMP %[a], r11\n\t" + "CMP r0, r11\n\t" #if defined(__GNUC__) "BNE L_sp_3072_sub_in_place_96_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -13747,17 +14942,27 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_in_place_96(sp_digit* a, #else "BNE.N L_sp_3072_sub_in_place_96_word_%=\n\t" #endif - "MOV %[a], r10\n\t" + "MOV r0, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -13781,12 +14986,20 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_96(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x300\n\t" - "LDR lr, [%[a]]\n\t" - "LDR r11, [%[b]]\n\t" + "LDR lr, [r1]\n\t" + "LDR r11, [r2]\n\t" "UMULL r8, r6, lr, r11\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -13808,14 +15021,14 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_96(sp_digit* r, const sp_digit* a, #else "L_sp_3072_mul_96_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" "ADC r8, r8, #0\n\t" - "LDR lr, [%[a], r4]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r4]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -13837,8 +15050,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_96(sp_digit* r, const sp_digit* a, #else "BLT.N L_sp_3072_mul_96_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -13862,8 +15075,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_96(sp_digit* r, const sp_digit* a, #else "BLE.N L_sp_3072_mul_96_outer_%=\n\t" #endif - "LDR lr, [%[a], #380]\n\t" - "LDR r11, [%[b], #380]\n\t" + "LDR lr, [r1, #380]\n\t" + "LDR r11, [r2, #380]\n\t" "UMLAL r6, r7, lr, r11\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -13875,7 +15088,7 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_96(sp_digit* r, const sp_digit* a, "L_sp_3072_mul_96_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_3072_mul_96_store_%=\n\t" @@ -13884,16 +15097,27 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_96(sp_digit* r, const sp_digit* a, #else "BGT.N L_sp_3072_mul_96_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Square a and put result in r. (r = a * a) @@ -13911,11 +15135,19 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_96(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x300\n\t" - "LDR lr, [%[a]]\n\t" + "LDR lr, [r1]\n\t" "UMULL r8, r6, lr, lr\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -13937,8 +15169,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_96(sp_digit* r, const sp_digit* a) #else "L_sp_3072_sqr_96_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[a], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r1, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -13963,7 +15195,7 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_96(sp_digit* r, const sp_digit* a) #else "BLT.N L_sp_3072_sqr_96_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" + "LDR lr, [r1, r3]\n\t" "UMULL r9, r10, lr, lr\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -13987,7 +15219,7 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_96(sp_digit* r, const sp_digit* a) #else "BLE.N L_sp_3072_sqr_96_outer_%=\n\t" #endif - "LDR lr, [%[a], #380]\n\t" + "LDR lr, [r1, #380]\n\t" "UMLAL r6, r7, lr, lr\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -13999,7 +15231,7 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_96(sp_digit* r, const sp_digit* a) "L_sp_3072_sqr_96_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_3072_sqr_96_store_%=\n\t" @@ -14008,16 +15240,26 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_96(sp_digit* r, const sp_digit* a) #else "BGT.N L_sp_3072_sqr_96_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -14058,11 +15300,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_add_48(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r3, #0\n\t" - "ADD r12, %[a], #0xc0\n\t" + "ADD r12, r1, #0xc0\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_3072_add_48_word:\n\t" @@ -14070,16 +15320,16 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_add_48(sp_digit* r, "L_sp_3072_add_48_word_%=:\n\t" #endif "ADDS r3, r3, #0xffffffff\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "MOV r4, #0\n\t" "ADC r3, r4, #0\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_3072_add_48_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -14087,17 +15337,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_add_48(sp_digit* r, #else "BNE.N L_sp_3072_add_48_word_%=\n\t" #endif - "MOV %[r], r3\n\t" + "MOV r0, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -14119,11 +15380,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_in_place_48(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "ADD r11, %[a], #0xc0\n\t" + "ADD r11, r0, #0xc0\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_3072_sub_in_place_48_word:\n\t" @@ -14131,15 +15400,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_in_place_48(sp_digit* a, "L_sp_3072_sub_in_place_48_word_%=:\n\t" #endif "RSBS r10, r10, #0\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" "SBC r10, r10, r10\n\t" - "CMP %[a], r11\n\t" + "CMP r0, r11\n\t" #if defined(__GNUC__) "BNE L_sp_3072_sub_in_place_48_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -14147,17 +15416,27 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_in_place_48(sp_digit* a, #else "BNE.N L_sp_3072_sub_in_place_48_word_%=\n\t" #endif - "MOV %[a], r10\n\t" + "MOV r0, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -14181,12 +15460,20 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_48(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x180\n\t" - "LDR lr, [%[a]]\n\t" - "LDR r11, [%[b]]\n\t" + "LDR lr, [r1]\n\t" + "LDR r11, [r2]\n\t" "UMULL r8, r6, lr, r11\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -14208,14 +15495,14 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_48(sp_digit* r, const sp_digit* a, #else "L_sp_3072_mul_48_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" "ADC r8, r8, #0\n\t" - "LDR lr, [%[a], r4]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r4]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -14237,8 +15524,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_48(sp_digit* r, const sp_digit* a, #else "BLT.N L_sp_3072_mul_48_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -14262,8 +15549,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_48(sp_digit* r, const sp_digit* a, #else "BLE.N L_sp_3072_mul_48_outer_%=\n\t" #endif - "LDR lr, [%[a], #188]\n\t" - "LDR r11, [%[b], #188]\n\t" + "LDR lr, [r1, #188]\n\t" + "LDR r11, [r2, #188]\n\t" "UMLAL r6, r7, lr, r11\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -14275,7 +15562,7 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_48(sp_digit* r, const sp_digit* a, "L_sp_3072_mul_48_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_3072_mul_48_store_%=\n\t" @@ -14284,16 +15571,27 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_48(sp_digit* r, const sp_digit* a, #else "BGT.N L_sp_3072_mul_48_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Square a and put result in r. (r = a * a) @@ -14311,11 +15609,19 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_48(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x180\n\t" - "LDR lr, [%[a]]\n\t" + "LDR lr, [r1]\n\t" "UMULL r8, r6, lr, lr\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -14337,8 +15643,8 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_48(sp_digit* r, const sp_digit* a) #else "L_sp_3072_sqr_48_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[a], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r1, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -14363,7 +15669,7 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_48(sp_digit* r, const sp_digit* a) #else "BLT.N L_sp_3072_sqr_48_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" + "LDR lr, [r1, r3]\n\t" "UMULL r9, r10, lr, lr\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -14387,7 +15693,7 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_48(sp_digit* r, const sp_digit* a) #else "BLE.N L_sp_3072_sqr_48_outer_%=\n\t" #endif - "LDR lr, [%[a], #188]\n\t" + "LDR lr, [r1, #188]\n\t" "UMLAL r6, r7, lr, lr\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -14399,7 +15705,7 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_48(sp_digit* r, const sp_digit* a) "L_sp_3072_sqr_48_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_3072_sqr_48_store_%=\n\t" @@ -14408,16 +15714,26 @@ WC_OMIT_FRAME_POINTER static void sp_3072_sqr_48(sp_digit* r, const sp_digit* a) #else "BGT.N L_sp_3072_sqr_48_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -14462,14 +15778,22 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_d_96(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDR r8, [%[a]]\n\t" - "UMULL r5, r3, %[b], r8\n\t" + "LDR r8, [r1]\n\t" + "UMULL r5, r3, r2, r8\n\t" "MOV r4, #0\n\t" - "STR r5, [%[r]]\n\t" + "STR r5, [r0]\n\t" "MOV r5, #0\n\t" "MOV r9, #4\n\t" "\n" @@ -14479,12 +15803,12 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_d_96(sp_digit* r, "L_sp_3072_mul_d_96_word_%=:\n\t" #endif /* A[i] * B */ - "LDR r8, [%[a], r9]\n\t" - "UMULL r6, r7, %[b], r8\n\t" + "LDR r8, [r1, r9]\n\t" + "UMULL r6, r7, r2, r8\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], r9]\n\t" + "STR r3, [r0, r9]\n\t" "MOV r3, r4\n\t" "MOV r4, r5\n\t" "MOV r5, #0\n\t" @@ -14497,16 +15821,27 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_d_96(sp_digit* r, #else "BLT.N L_sp_3072_mul_d_96_word_%=\n\t" #endif - "STR r3, [%[r], #384]\n\t" + "STR r3, [r0, #384]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -14528,498 +15863,517 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_d_96(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDM %[a]!, {r8}\n\t" - "UMULL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMULL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[1] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[2] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[3] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[4] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[5] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[6] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[7] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[8] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[9] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[10] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[11] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[12] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[13] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[14] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[15] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[16] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[17] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[18] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[19] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[20] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[21] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[22] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[23] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[24] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[25] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[26] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[27] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[28] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[29] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[30] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[31] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[32] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[33] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[34] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[35] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[36] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[37] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[38] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[39] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[40] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[41] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[42] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[43] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[44] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[45] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[46] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[47] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[48] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[49] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[50] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[51] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[52] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[53] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[54] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[55] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[56] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[57] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[58] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[59] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[60] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[61] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[62] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[63] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[64] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[65] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[66] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[67] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[68] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[69] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[70] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[71] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[72] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[73] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[74] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[75] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[76] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[77] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[78] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[79] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[80] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[81] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[82] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[83] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[84] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[85] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[86] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[87] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[88] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[89] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[90] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[91] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[92] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[93] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[94] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[95] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" - "STR r3, [%[r]]\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" + "STR r3, [r0]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -15061,9 +16415,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_sub_48(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, #0\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -15074,12 +16437,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_sub_48(sp_digit* r, "L_sp_3072_cond_sub_48_words_%=:\n\t" #endif "SUBS r4, r8, r4\n\t" - "LDR r6, [%[a], r5]\n\t" - "LDR r7, [%[b], r5]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r5]\n\t" + "LDR r7, [r2, r5]\n\t" + "AND r7, r7, r3\n\t" "SBCS r6, r6, r7\n\t" "SBC r4, r8, r8\n\t" - "STR r6, [%[r], r5]\n\t" + "STR r6, [r0, r5]\n\t" "ADD r5, r5, #4\n\t" "CMP r5, #0xc0\n\t" #if defined(__GNUC__) @@ -15089,16 +16452,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_sub_48(sp_digit* r, #else "BLT.N L_sp_3072_cond_sub_48_words_%=\n\t" #endif - "MOV %[r], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -15125,188 +16500,209 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_sub_48(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SUBS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "SBC %[r], r5, r5\n\t" + "STM r0!, {r6, r7}\n\t" + "SBC r0, r5, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -15332,15 +16728,24 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR lr, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR lr, [r1]\n\t" /* i = 0 */ "MOV r11, #0\n\t" "MOV r3, #0\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[a], #4]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_3072_mont_reduce_48_word:\n\t" @@ -15348,393 +16753,393 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( "L_sp_3072_mont_reduce_48_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL r10, %[mp], r4\n\t" + "MUL r10, r2, r4\n\t" /* a[i+0] += m[0] * mu */ "MOV r7, #0\n\t" "UMLAL r4, r7, r10, lr\n\t" /* a[i+1] += m[1] * mu */ - "LDR r9, [%[m], #4]\n\t" + "LDR r9, [r1, #4]\n\t" "MOV r6, #0\n\t" "UMLAL r5, r6, r10, r9\n\t" "MOV r4, r5\n\t" "ADDS r4, r4, r7\n\t" "ADC r6, r6, #0\n\t" /* a[i+2] += m[2] * mu */ - "LDR r9, [%[m], #8]\n\t" - "LDR r5, [%[a], #8]\n\t" + "LDR r9, [r1, #8]\n\t" + "LDR r5, [r0, #8]\n\t" "MOV r7, #0\n\t" "UMLAL r5, r7, r10, r9\n\t" "ADDS r5, r5, r6\n\t" "ADC r7, r7, #0\n\t" /* a[i+3] += m[3] * mu */ - "LDR r9, [%[m], #12]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r9, [r1, #12]\n\t" + "LDR r12, [r0, #12]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #12]\n\t" + "STR r12, [r0, #12]\n\t" "ADC r6, r6, #0\n\t" /* a[i+4] += m[4] * mu */ - "LDR r9, [%[m], #16]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r9, [r1, #16]\n\t" + "LDR r12, [r0, #16]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #16]\n\t" + "STR r12, [r0, #16]\n\t" "ADC r7, r7, #0\n\t" /* a[i+5] += m[5] * mu */ - "LDR r9, [%[m], #20]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r12, [r0, #20]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #20]\n\t" + "STR r12, [r0, #20]\n\t" "ADC r6, r6, #0\n\t" /* a[i+6] += m[6] * mu */ - "LDR r9, [%[m], #24]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r9, [r1, #24]\n\t" + "LDR r12, [r0, #24]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #24]\n\t" + "STR r12, [r0, #24]\n\t" "ADC r7, r7, #0\n\t" /* a[i+7] += m[7] * mu */ - "LDR r9, [%[m], #28]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r9, [r1, #28]\n\t" + "LDR r12, [r0, #28]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #28]\n\t" + "STR r12, [r0, #28]\n\t" "ADC r6, r6, #0\n\t" /* a[i+8] += m[8] * mu */ - "LDR r9, [%[m], #32]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r9, [r1, #32]\n\t" + "LDR r12, [r0, #32]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #32]\n\t" + "STR r12, [r0, #32]\n\t" "ADC r7, r7, #0\n\t" /* a[i+9] += m[9] * mu */ - "LDR r9, [%[m], #36]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r9, [r1, #36]\n\t" + "LDR r12, [r0, #36]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #36]\n\t" + "STR r12, [r0, #36]\n\t" "ADC r6, r6, #0\n\t" /* a[i+10] += m[10] * mu */ - "LDR r9, [%[m], #40]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r9, [r1, #40]\n\t" + "LDR r12, [r0, #40]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #40]\n\t" + "STR r12, [r0, #40]\n\t" "ADC r7, r7, #0\n\t" /* a[i+11] += m[11] * mu */ - "LDR r9, [%[m], #44]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r9, [r1, #44]\n\t" + "LDR r12, [r0, #44]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #44]\n\t" + "STR r12, [r0, #44]\n\t" "ADC r6, r6, #0\n\t" /* a[i+12] += m[12] * mu */ - "LDR r9, [%[m], #48]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r9, [r1, #48]\n\t" + "LDR r12, [r0, #48]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #48]\n\t" + "STR r12, [r0, #48]\n\t" "ADC r7, r7, #0\n\t" /* a[i+13] += m[13] * mu */ - "LDR r9, [%[m], #52]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r9, [r1, #52]\n\t" + "LDR r12, [r0, #52]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #52]\n\t" + "STR r12, [r0, #52]\n\t" "ADC r6, r6, #0\n\t" /* a[i+14] += m[14] * mu */ - "LDR r9, [%[m], #56]\n\t" - "LDR r12, [%[a], #56]\n\t" + "LDR r9, [r1, #56]\n\t" + "LDR r12, [r0, #56]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #56]\n\t" + "STR r12, [r0, #56]\n\t" "ADC r7, r7, #0\n\t" /* a[i+15] += m[15] * mu */ - "LDR r9, [%[m], #60]\n\t" - "LDR r12, [%[a], #60]\n\t" + "LDR r9, [r1, #60]\n\t" + "LDR r12, [r0, #60]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #60]\n\t" + "STR r12, [r0, #60]\n\t" "ADC r6, r6, #0\n\t" /* a[i+16] += m[16] * mu */ - "LDR r9, [%[m], #64]\n\t" - "LDR r12, [%[a], #64]\n\t" + "LDR r9, [r1, #64]\n\t" + "LDR r12, [r0, #64]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #64]\n\t" + "STR r12, [r0, #64]\n\t" "ADC r7, r7, #0\n\t" /* a[i+17] += m[17] * mu */ - "LDR r9, [%[m], #68]\n\t" - "LDR r12, [%[a], #68]\n\t" + "LDR r9, [r1, #68]\n\t" + "LDR r12, [r0, #68]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #68]\n\t" + "STR r12, [r0, #68]\n\t" "ADC r6, r6, #0\n\t" /* a[i+18] += m[18] * mu */ - "LDR r9, [%[m], #72]\n\t" - "LDR r12, [%[a], #72]\n\t" + "LDR r9, [r1, #72]\n\t" + "LDR r12, [r0, #72]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #72]\n\t" + "STR r12, [r0, #72]\n\t" "ADC r7, r7, #0\n\t" /* a[i+19] += m[19] * mu */ - "LDR r9, [%[m], #76]\n\t" - "LDR r12, [%[a], #76]\n\t" + "LDR r9, [r1, #76]\n\t" + "LDR r12, [r0, #76]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #76]\n\t" + "STR r12, [r0, #76]\n\t" "ADC r6, r6, #0\n\t" /* a[i+20] += m[20] * mu */ - "LDR r9, [%[m], #80]\n\t" - "LDR r12, [%[a], #80]\n\t" + "LDR r9, [r1, #80]\n\t" + "LDR r12, [r0, #80]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #80]\n\t" + "STR r12, [r0, #80]\n\t" "ADC r7, r7, #0\n\t" /* a[i+21] += m[21] * mu */ - "LDR r9, [%[m], #84]\n\t" - "LDR r12, [%[a], #84]\n\t" + "LDR r9, [r1, #84]\n\t" + "LDR r12, [r0, #84]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #84]\n\t" + "STR r12, [r0, #84]\n\t" "ADC r6, r6, #0\n\t" /* a[i+22] += m[22] * mu */ - "LDR r9, [%[m], #88]\n\t" - "LDR r12, [%[a], #88]\n\t" + "LDR r9, [r1, #88]\n\t" + "LDR r12, [r0, #88]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #88]\n\t" + "STR r12, [r0, #88]\n\t" "ADC r7, r7, #0\n\t" /* a[i+23] += m[23] * mu */ - "LDR r9, [%[m], #92]\n\t" - "LDR r12, [%[a], #92]\n\t" + "LDR r9, [r1, #92]\n\t" + "LDR r12, [r0, #92]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #92]\n\t" + "STR r12, [r0, #92]\n\t" "ADC r6, r6, #0\n\t" /* a[i+24] += m[24] * mu */ - "LDR r9, [%[m], #96]\n\t" - "LDR r12, [%[a], #96]\n\t" + "LDR r9, [r1, #96]\n\t" + "LDR r12, [r0, #96]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #96]\n\t" + "STR r12, [r0, #96]\n\t" "ADC r7, r7, #0\n\t" /* a[i+25] += m[25] * mu */ - "LDR r9, [%[m], #100]\n\t" - "LDR r12, [%[a], #100]\n\t" + "LDR r9, [r1, #100]\n\t" + "LDR r12, [r0, #100]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #100]\n\t" + "STR r12, [r0, #100]\n\t" "ADC r6, r6, #0\n\t" /* a[i+26] += m[26] * mu */ - "LDR r9, [%[m], #104]\n\t" - "LDR r12, [%[a], #104]\n\t" + "LDR r9, [r1, #104]\n\t" + "LDR r12, [r0, #104]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #104]\n\t" + "STR r12, [r0, #104]\n\t" "ADC r7, r7, #0\n\t" /* a[i+27] += m[27] * mu */ - "LDR r9, [%[m], #108]\n\t" - "LDR r12, [%[a], #108]\n\t" + "LDR r9, [r1, #108]\n\t" + "LDR r12, [r0, #108]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #108]\n\t" + "STR r12, [r0, #108]\n\t" "ADC r6, r6, #0\n\t" /* a[i+28] += m[28] * mu */ - "LDR r9, [%[m], #112]\n\t" - "LDR r12, [%[a], #112]\n\t" + "LDR r9, [r1, #112]\n\t" + "LDR r12, [r0, #112]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #112]\n\t" + "STR r12, [r0, #112]\n\t" "ADC r7, r7, #0\n\t" /* a[i+29] += m[29] * mu */ - "LDR r9, [%[m], #116]\n\t" - "LDR r12, [%[a], #116]\n\t" + "LDR r9, [r1, #116]\n\t" + "LDR r12, [r0, #116]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #116]\n\t" + "STR r12, [r0, #116]\n\t" "ADC r6, r6, #0\n\t" /* a[i+30] += m[30] * mu */ - "LDR r9, [%[m], #120]\n\t" - "LDR r12, [%[a], #120]\n\t" + "LDR r9, [r1, #120]\n\t" + "LDR r12, [r0, #120]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #120]\n\t" + "STR r12, [r0, #120]\n\t" "ADC r7, r7, #0\n\t" /* a[i+31] += m[31] * mu */ - "LDR r9, [%[m], #124]\n\t" - "LDR r12, [%[a], #124]\n\t" + "LDR r9, [r1, #124]\n\t" + "LDR r12, [r0, #124]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #124]\n\t" + "STR r12, [r0, #124]\n\t" "ADC r6, r6, #0\n\t" /* a[i+32] += m[32] * mu */ - "LDR r9, [%[m], #128]\n\t" - "LDR r12, [%[a], #128]\n\t" + "LDR r9, [r1, #128]\n\t" + "LDR r12, [r0, #128]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #128]\n\t" + "STR r12, [r0, #128]\n\t" "ADC r7, r7, #0\n\t" /* a[i+33] += m[33] * mu */ - "LDR r9, [%[m], #132]\n\t" - "LDR r12, [%[a], #132]\n\t" + "LDR r9, [r1, #132]\n\t" + "LDR r12, [r0, #132]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #132]\n\t" + "STR r12, [r0, #132]\n\t" "ADC r6, r6, #0\n\t" /* a[i+34] += m[34] * mu */ - "LDR r9, [%[m], #136]\n\t" - "LDR r12, [%[a], #136]\n\t" + "LDR r9, [r1, #136]\n\t" + "LDR r12, [r0, #136]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #136]\n\t" + "STR r12, [r0, #136]\n\t" "ADC r7, r7, #0\n\t" /* a[i+35] += m[35] * mu */ - "LDR r9, [%[m], #140]\n\t" - "LDR r12, [%[a], #140]\n\t" + "LDR r9, [r1, #140]\n\t" + "LDR r12, [r0, #140]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #140]\n\t" + "STR r12, [r0, #140]\n\t" "ADC r6, r6, #0\n\t" /* a[i+36] += m[36] * mu */ - "LDR r9, [%[m], #144]\n\t" - "LDR r12, [%[a], #144]\n\t" + "LDR r9, [r1, #144]\n\t" + "LDR r12, [r0, #144]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #144]\n\t" + "STR r12, [r0, #144]\n\t" "ADC r7, r7, #0\n\t" /* a[i+37] += m[37] * mu */ - "LDR r9, [%[m], #148]\n\t" - "LDR r12, [%[a], #148]\n\t" + "LDR r9, [r1, #148]\n\t" + "LDR r12, [r0, #148]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #148]\n\t" + "STR r12, [r0, #148]\n\t" "ADC r6, r6, #0\n\t" /* a[i+38] += m[38] * mu */ - "LDR r9, [%[m], #152]\n\t" - "LDR r12, [%[a], #152]\n\t" + "LDR r9, [r1, #152]\n\t" + "LDR r12, [r0, #152]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #152]\n\t" + "STR r12, [r0, #152]\n\t" "ADC r7, r7, #0\n\t" /* a[i+39] += m[39] * mu */ - "LDR r9, [%[m], #156]\n\t" - "LDR r12, [%[a], #156]\n\t" + "LDR r9, [r1, #156]\n\t" + "LDR r12, [r0, #156]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #156]\n\t" + "STR r12, [r0, #156]\n\t" "ADC r6, r6, #0\n\t" /* a[i+40] += m[40] * mu */ - "LDR r9, [%[m], #160]\n\t" - "LDR r12, [%[a], #160]\n\t" + "LDR r9, [r1, #160]\n\t" + "LDR r12, [r0, #160]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #160]\n\t" + "STR r12, [r0, #160]\n\t" "ADC r7, r7, #0\n\t" /* a[i+41] += m[41] * mu */ - "LDR r9, [%[m], #164]\n\t" - "LDR r12, [%[a], #164]\n\t" + "LDR r9, [r1, #164]\n\t" + "LDR r12, [r0, #164]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #164]\n\t" + "STR r12, [r0, #164]\n\t" "ADC r6, r6, #0\n\t" /* a[i+42] += m[42] * mu */ - "LDR r9, [%[m], #168]\n\t" - "LDR r12, [%[a], #168]\n\t" + "LDR r9, [r1, #168]\n\t" + "LDR r12, [r0, #168]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #168]\n\t" + "STR r12, [r0, #168]\n\t" "ADC r7, r7, #0\n\t" /* a[i+43] += m[43] * mu */ - "LDR r9, [%[m], #172]\n\t" - "LDR r12, [%[a], #172]\n\t" + "LDR r9, [r1, #172]\n\t" + "LDR r12, [r0, #172]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #172]\n\t" + "STR r12, [r0, #172]\n\t" "ADC r6, r6, #0\n\t" /* a[i+44] += m[44] * mu */ - "LDR r9, [%[m], #176]\n\t" - "LDR r12, [%[a], #176]\n\t" + "LDR r9, [r1, #176]\n\t" + "LDR r12, [r0, #176]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #176]\n\t" + "STR r12, [r0, #176]\n\t" "ADC r7, r7, #0\n\t" /* a[i+45] += m[45] * mu */ - "LDR r9, [%[m], #180]\n\t" - "LDR r12, [%[a], #180]\n\t" + "LDR r9, [r1, #180]\n\t" + "LDR r12, [r0, #180]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #180]\n\t" + "STR r12, [r0, #180]\n\t" "ADC r6, r6, #0\n\t" /* a[i+46] += m[46] * mu */ - "LDR r9, [%[m], #184]\n\t" - "LDR r12, [%[a], #184]\n\t" + "LDR r9, [r1, #184]\n\t" + "LDR r12, [r0, #184]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #184]\n\t" + "STR r12, [r0, #184]\n\t" "ADC r7, r7, #0\n\t" /* a[i+47] += m[47] * mu */ - "LDR r9, [%[m], #188]\n\t" - "LDR r12, [%[a], #188]\n\t" + "LDR r9, [r1, #188]\n\t" + "LDR r12, [r0, #188]\n\t" "UMULL r8, r9, r10, r9\n\t" "ADDS r7, r7, r8\n\t" "ADCS r6, r9, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, r3\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #188]\n\t" - "LDR r12, [%[a], #192]\n\t" + "STR r12, [r0, #188]\n\t" + "LDR r12, [r0, #192]\n\t" "ADCS r12, r12, r6\n\t" - "STR r12, [%[a], #192]\n\t" + "STR r12, [r0, #192]\n\t" "ADC r3, r3, #0\n\t" /* i += 1 */ "ADD r11, r11, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r11, #0xc0\n\t" #if defined(__GNUC__) "BLT L_sp_3072_mont_reduce_48_word_%=\n\t" @@ -15744,19 +17149,30 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( "BLT.W L_sp_3072_mont_reduce_48_word_%=\n\t" #endif /* Loop Done */ - "STR r4, [%[a]]\n\t" - "STR r5, [%[a], #4]\n\t" - "MOV %[mp], r3\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_3072_cond_sub_48(a - 48, a, m, (sp_digit)0 - mp); } @@ -15780,10 +17196,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r11, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r11, [r1]\n\t" /* i = 0 */ "MOV r9, #0\n\t" /* ca = 0 */ @@ -15795,8 +17220,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( "L_sp_3072_mont_reduce_48_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "LDR r10, [%[a]]\n\t" - "MUL r8, %[mp], r10\n\t" + "LDR r10, [r0]\n\t" + "MUL r8, r2, r10\n\t" /* j = 0 */ "MOV r12, #0\n\t" "MOV r4, #0\n\t" @@ -15807,42 +17232,42 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( "L_sp_3072_mont_reduce_48_mul_%=:\n\t" #endif /* a[i+j+0] += m[j+0] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+1] += m[j+1] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+2] += m[j+2] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+3] += m[j+3] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" @@ -15854,16 +17279,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( #else "BLT.N L_sp_3072_mont_reduce_48_mul_%=\n\t" #endif - "LDR r10, [%[a], #192]\n\t" + "LDR r10, [r0, #192]\n\t" "ADDS r4, r4, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" "ADDS r10, r10, r4\n\t" "ADC r3, r3, r3\n\t" - "STR r10, [%[a], #192]\n\t" + "STR r10, [r0, #192]\n\t" /* i += 1 */ "ADD r9, r9, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r9, #0xc0\n\t" #if defined(__GNUC__) "BLT L_sp_3072_mont_reduce_48_word_%=\n\t" @@ -15873,17 +17298,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( "BLT.N L_sp_3072_mont_reduce_48_word_%=\n\t" #endif /* Loop Done */ - "MOV %[mp], r3\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_3072_cond_sub_48(a - 48, a, m, (sp_digit)0 - mp); } @@ -15909,17 +17345,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* i = 0 */ "MOV r4, #0\n\t" "MOV r5, #0\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r7, [%[a], #4]\n\t" - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[a], #12]\n\t" - "LDR r10, [%[a], #16]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" + "LDR r10, [r0, #16]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_3072_mont_reduce_48_word:\n\t" @@ -15927,250 +17372,250 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( "L_sp_3072_mont_reduce_48_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL lr, %[mp], r6\n\t" + "MUL lr, r2, r6\n\t" /* a[i+0] += m[0] * mu */ - "LDR r12, [%[m]]\n\t" + "LDR r12, [r1]\n\t" "MOV r3, #0\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+1] += m[1] * mu */ - "LDR r12, [%[m], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "MOV r6, r7\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+2] += m[2] * mu */ - "LDR r12, [%[m], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "MOV r7, r8\n\t" "UMAAL r7, r3, lr, r12\n\t" /* a[i+3] += m[3] * mu */ - "LDR r12, [%[m], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "MOV r8, r9\n\t" "UMAAL r8, r3, lr, r12\n\t" /* a[i+4] += m[4] * mu */ - "LDR r12, [%[m], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "MOV r9, r10\n\t" "UMAAL r9, r3, lr, r12\n\t" /* a[i+5] += m[5] * mu */ - "LDR r12, [%[m], #20]\n\t" - "LDR r10, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR r10, [r0, #20]\n\t" "UMAAL r10, r3, lr, r12\n\t" /* a[i+6] += m[6] * mu */ - "LDR r12, [%[m], #24]\n\t" - "LDR r11, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR r11, [r0, #24]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #24]\n\t" + "STR r11, [r0, #24]\n\t" /* a[i+7] += m[7] * mu */ - "LDR r12, [%[m], #28]\n\t" - "LDR r11, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR r11, [r0, #28]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #28]\n\t" + "STR r11, [r0, #28]\n\t" /* a[i+8] += m[8] * mu */ - "LDR r12, [%[m], #32]\n\t" - "LDR r11, [%[a], #32]\n\t" + "LDR r12, [r1, #32]\n\t" + "LDR r11, [r0, #32]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #32]\n\t" + "STR r11, [r0, #32]\n\t" /* a[i+9] += m[9] * mu */ - "LDR r12, [%[m], #36]\n\t" - "LDR r11, [%[a], #36]\n\t" + "LDR r12, [r1, #36]\n\t" + "LDR r11, [r0, #36]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #36]\n\t" + "STR r11, [r0, #36]\n\t" /* a[i+10] += m[10] * mu */ - "LDR r12, [%[m], #40]\n\t" - "LDR r11, [%[a], #40]\n\t" + "LDR r12, [r1, #40]\n\t" + "LDR r11, [r0, #40]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #40]\n\t" + "STR r11, [r0, #40]\n\t" /* a[i+11] += m[11] * mu */ - "LDR r12, [%[m], #44]\n\t" - "LDR r11, [%[a], #44]\n\t" + "LDR r12, [r1, #44]\n\t" + "LDR r11, [r0, #44]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #44]\n\t" + "STR r11, [r0, #44]\n\t" /* a[i+12] += m[12] * mu */ - "LDR r12, [%[m], #48]\n\t" - "LDR r11, [%[a], #48]\n\t" + "LDR r12, [r1, #48]\n\t" + "LDR r11, [r0, #48]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #48]\n\t" + "STR r11, [r0, #48]\n\t" /* a[i+13] += m[13] * mu */ - "LDR r12, [%[m], #52]\n\t" - "LDR r11, [%[a], #52]\n\t" + "LDR r12, [r1, #52]\n\t" + "LDR r11, [r0, #52]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #52]\n\t" + "STR r11, [r0, #52]\n\t" /* a[i+14] += m[14] * mu */ - "LDR r12, [%[m], #56]\n\t" - "LDR r11, [%[a], #56]\n\t" + "LDR r12, [r1, #56]\n\t" + "LDR r11, [r0, #56]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #56]\n\t" + "STR r11, [r0, #56]\n\t" /* a[i+15] += m[15] * mu */ - "LDR r12, [%[m], #60]\n\t" - "LDR r11, [%[a], #60]\n\t" + "LDR r12, [r1, #60]\n\t" + "LDR r11, [r0, #60]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #60]\n\t" + "STR r11, [r0, #60]\n\t" /* a[i+16] += m[16] * mu */ - "LDR r12, [%[m], #64]\n\t" - "LDR r11, [%[a], #64]\n\t" + "LDR r12, [r1, #64]\n\t" + "LDR r11, [r0, #64]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #64]\n\t" + "STR r11, [r0, #64]\n\t" /* a[i+17] += m[17] * mu */ - "LDR r12, [%[m], #68]\n\t" - "LDR r11, [%[a], #68]\n\t" + "LDR r12, [r1, #68]\n\t" + "LDR r11, [r0, #68]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #68]\n\t" + "STR r11, [r0, #68]\n\t" /* a[i+18] += m[18] * mu */ - "LDR r12, [%[m], #72]\n\t" - "LDR r11, [%[a], #72]\n\t" + "LDR r12, [r1, #72]\n\t" + "LDR r11, [r0, #72]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #72]\n\t" + "STR r11, [r0, #72]\n\t" /* a[i+19] += m[19] * mu */ - "LDR r12, [%[m], #76]\n\t" - "LDR r11, [%[a], #76]\n\t" + "LDR r12, [r1, #76]\n\t" + "LDR r11, [r0, #76]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #76]\n\t" + "STR r11, [r0, #76]\n\t" /* a[i+20] += m[20] * mu */ - "LDR r12, [%[m], #80]\n\t" - "LDR r11, [%[a], #80]\n\t" + "LDR r12, [r1, #80]\n\t" + "LDR r11, [r0, #80]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #80]\n\t" + "STR r11, [r0, #80]\n\t" /* a[i+21] += m[21] * mu */ - "LDR r12, [%[m], #84]\n\t" - "LDR r11, [%[a], #84]\n\t" + "LDR r12, [r1, #84]\n\t" + "LDR r11, [r0, #84]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #84]\n\t" + "STR r11, [r0, #84]\n\t" /* a[i+22] += m[22] * mu */ - "LDR r12, [%[m], #88]\n\t" - "LDR r11, [%[a], #88]\n\t" + "LDR r12, [r1, #88]\n\t" + "LDR r11, [r0, #88]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #88]\n\t" + "STR r11, [r0, #88]\n\t" /* a[i+23] += m[23] * mu */ - "LDR r12, [%[m], #92]\n\t" - "LDR r11, [%[a], #92]\n\t" + "LDR r12, [r1, #92]\n\t" + "LDR r11, [r0, #92]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #92]\n\t" + "STR r11, [r0, #92]\n\t" /* a[i+24] += m[24] * mu */ - "LDR r12, [%[m], #96]\n\t" - "LDR r11, [%[a], #96]\n\t" + "LDR r12, [r1, #96]\n\t" + "LDR r11, [r0, #96]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #96]\n\t" + "STR r11, [r0, #96]\n\t" /* a[i+25] += m[25] * mu */ - "LDR r12, [%[m], #100]\n\t" - "LDR r11, [%[a], #100]\n\t" + "LDR r12, [r1, #100]\n\t" + "LDR r11, [r0, #100]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #100]\n\t" + "STR r11, [r0, #100]\n\t" /* a[i+26] += m[26] * mu */ - "LDR r12, [%[m], #104]\n\t" - "LDR r11, [%[a], #104]\n\t" + "LDR r12, [r1, #104]\n\t" + "LDR r11, [r0, #104]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #104]\n\t" + "STR r11, [r0, #104]\n\t" /* a[i+27] += m[27] * mu */ - "LDR r12, [%[m], #108]\n\t" - "LDR r11, [%[a], #108]\n\t" + "LDR r12, [r1, #108]\n\t" + "LDR r11, [r0, #108]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #108]\n\t" + "STR r11, [r0, #108]\n\t" /* a[i+28] += m[28] * mu */ - "LDR r12, [%[m], #112]\n\t" - "LDR r11, [%[a], #112]\n\t" + "LDR r12, [r1, #112]\n\t" + "LDR r11, [r0, #112]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #112]\n\t" + "STR r11, [r0, #112]\n\t" /* a[i+29] += m[29] * mu */ - "LDR r12, [%[m], #116]\n\t" - "LDR r11, [%[a], #116]\n\t" + "LDR r12, [r1, #116]\n\t" + "LDR r11, [r0, #116]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #116]\n\t" + "STR r11, [r0, #116]\n\t" /* a[i+30] += m[30] * mu */ - "LDR r12, [%[m], #120]\n\t" - "LDR r11, [%[a], #120]\n\t" + "LDR r12, [r1, #120]\n\t" + "LDR r11, [r0, #120]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #120]\n\t" + "STR r11, [r0, #120]\n\t" /* a[i+31] += m[31] * mu */ - "LDR r12, [%[m], #124]\n\t" - "LDR r11, [%[a], #124]\n\t" + "LDR r12, [r1, #124]\n\t" + "LDR r11, [r0, #124]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #124]\n\t" + "STR r11, [r0, #124]\n\t" /* a[i+32] += m[32] * mu */ - "LDR r12, [%[m], #128]\n\t" - "LDR r11, [%[a], #128]\n\t" + "LDR r12, [r1, #128]\n\t" + "LDR r11, [r0, #128]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #128]\n\t" + "STR r11, [r0, #128]\n\t" /* a[i+33] += m[33] * mu */ - "LDR r12, [%[m], #132]\n\t" - "LDR r11, [%[a], #132]\n\t" + "LDR r12, [r1, #132]\n\t" + "LDR r11, [r0, #132]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #132]\n\t" + "STR r11, [r0, #132]\n\t" /* a[i+34] += m[34] * mu */ - "LDR r12, [%[m], #136]\n\t" - "LDR r11, [%[a], #136]\n\t" + "LDR r12, [r1, #136]\n\t" + "LDR r11, [r0, #136]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #136]\n\t" + "STR r11, [r0, #136]\n\t" /* a[i+35] += m[35] * mu */ - "LDR r12, [%[m], #140]\n\t" - "LDR r11, [%[a], #140]\n\t" + "LDR r12, [r1, #140]\n\t" + "LDR r11, [r0, #140]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #140]\n\t" + "STR r11, [r0, #140]\n\t" /* a[i+36] += m[36] * mu */ - "LDR r12, [%[m], #144]\n\t" - "LDR r11, [%[a], #144]\n\t" + "LDR r12, [r1, #144]\n\t" + "LDR r11, [r0, #144]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #144]\n\t" + "STR r11, [r0, #144]\n\t" /* a[i+37] += m[37] * mu */ - "LDR r12, [%[m], #148]\n\t" - "LDR r11, [%[a], #148]\n\t" + "LDR r12, [r1, #148]\n\t" + "LDR r11, [r0, #148]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #148]\n\t" + "STR r11, [r0, #148]\n\t" /* a[i+38] += m[38] * mu */ - "LDR r12, [%[m], #152]\n\t" - "LDR r11, [%[a], #152]\n\t" + "LDR r12, [r1, #152]\n\t" + "LDR r11, [r0, #152]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #152]\n\t" + "STR r11, [r0, #152]\n\t" /* a[i+39] += m[39] * mu */ - "LDR r12, [%[m], #156]\n\t" - "LDR r11, [%[a], #156]\n\t" + "LDR r12, [r1, #156]\n\t" + "LDR r11, [r0, #156]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #156]\n\t" + "STR r11, [r0, #156]\n\t" /* a[i+40] += m[40] * mu */ - "LDR r12, [%[m], #160]\n\t" - "LDR r11, [%[a], #160]\n\t" + "LDR r12, [r1, #160]\n\t" + "LDR r11, [r0, #160]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #160]\n\t" + "STR r11, [r0, #160]\n\t" /* a[i+41] += m[41] * mu */ - "LDR r12, [%[m], #164]\n\t" - "LDR r11, [%[a], #164]\n\t" + "LDR r12, [r1, #164]\n\t" + "LDR r11, [r0, #164]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #164]\n\t" + "STR r11, [r0, #164]\n\t" /* a[i+42] += m[42] * mu */ - "LDR r12, [%[m], #168]\n\t" - "LDR r11, [%[a], #168]\n\t" + "LDR r12, [r1, #168]\n\t" + "LDR r11, [r0, #168]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #168]\n\t" + "STR r11, [r0, #168]\n\t" /* a[i+43] += m[43] * mu */ - "LDR r12, [%[m], #172]\n\t" - "LDR r11, [%[a], #172]\n\t" + "LDR r12, [r1, #172]\n\t" + "LDR r11, [r0, #172]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #172]\n\t" + "STR r11, [r0, #172]\n\t" /* a[i+44] += m[44] * mu */ - "LDR r12, [%[m], #176]\n\t" - "LDR r11, [%[a], #176]\n\t" + "LDR r12, [r1, #176]\n\t" + "LDR r11, [r0, #176]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #176]\n\t" + "STR r11, [r0, #176]\n\t" /* a[i+45] += m[45] * mu */ - "LDR r12, [%[m], #180]\n\t" - "LDR r11, [%[a], #180]\n\t" + "LDR r12, [r1, #180]\n\t" + "LDR r11, [r0, #180]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #180]\n\t" + "STR r11, [r0, #180]\n\t" /* a[i+46] += m[46] * mu */ - "LDR r12, [%[m], #184]\n\t" - "LDR r11, [%[a], #184]\n\t" + "LDR r12, [r1, #184]\n\t" + "LDR r11, [r0, #184]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #184]\n\t" + "STR r11, [r0, #184]\n\t" /* a[i+47] += m[47] * mu */ - "LDR r12, [%[m], #188]\n\t" - "LDR r11, [%[a], #188]\n\t" + "LDR r12, [r1, #188]\n\t" + "LDR r11, [r0, #188]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "LDR lr, [%[a], #192]\n\t" + "LDR lr, [r0, #192]\n\t" "MOV r12, #0\n\t" "UMAAL r3, lr, r12, r12\n\t" - "STR r11, [%[a], #188]\n\t" + "STR r11, [r0, #188]\n\t" "ADDS r3, r3, r5\n\t" "ADC r5, lr, #0\n\t" - "STR r3, [%[a], #192]\n\t" + "STR r3, [r0, #192]\n\t" /* i += 1 */ "ADD r4, r4, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r4, #0xc0\n\t" #if defined(__GNUC__) "BLT L_sp_3072_mont_reduce_48_word_%=\n\t" @@ -16180,22 +17625,33 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( "BLT.W L_sp_3072_mont_reduce_48_word_%=\n\t" #endif /* Loop Done */ - "STR r6, [%[a]]\n\t" - "STR r7, [%[a], #4]\n\t" - "STR r8, [%[a], #8]\n\t" - "STR r9, [%[a], #12]\n\t" - "STR r10, [%[a], #16]\n\t" - "MOV %[mp], r5\n\t" + "STR r6, [r0]\n\t" + "STR r7, [r0, #4]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #12]\n\t" + "STR r10, [r0, #16]\n\t" + "MOV r2, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_3072_cond_sub_48(a - 48, a, m, (sp_digit)0 - mp); } @@ -16219,10 +17675,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r11, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r11, [r1]\n\t" /* i = 0 */ "MOV r9, #0\n\t" /* ca = 0 */ @@ -16234,8 +17699,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( "L_sp_3072_mont_reduce_48_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "LDR r10, [%[a]]\n\t" - "MUL r8, %[mp], r10\n\t" + "LDR r10, [r0]\n\t" + "MUL r8, r2, r10\n\t" /* j = 0 */ "MOV r12, #0\n\t" "MOV r4, #0\n\t" @@ -16246,31 +17711,31 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( "L_sp_3072_mont_reduce_48_mul_%=:\n\t" #endif /* a[i+j+0] += m[j+0] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+1] += m[j+1] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+2] += m[j+2] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+3] += m[j+3] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" "CMP r12, #0xc0\n\t" @@ -16281,16 +17746,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( #else "BLT.N L_sp_3072_mont_reduce_48_mul_%=\n\t" #endif - "LDR r10, [%[a], #192]\n\t" + "LDR r10, [r0, #192]\n\t" "ADDS r4, r4, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" "ADDS r10, r10, r4\n\t" "ADC r3, r3, r3\n\t" - "STR r10, [%[a], #192]\n\t" + "STR r10, [r0, #192]\n\t" /* i += 1 */ "ADD r9, r9, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r9, #0xc0\n\t" #if defined(__GNUC__) "BLT L_sp_3072_mont_reduce_48_word_%=\n\t" @@ -16300,17 +17765,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_48( "BLT.N L_sp_3072_mont_reduce_48_word_%=\n\t" #endif /* Loop Done */ - "MOV %[mp], r3\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_3072_cond_sub_48(a - 48, a, m, (sp_digit)0 - mp); } @@ -16365,14 +17841,22 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_d_48(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDR r8, [%[a]]\n\t" - "UMULL r5, r3, %[b], r8\n\t" + "LDR r8, [r1]\n\t" + "UMULL r5, r3, r2, r8\n\t" "MOV r4, #0\n\t" - "STR r5, [%[r]]\n\t" + "STR r5, [r0]\n\t" "MOV r5, #0\n\t" "MOV r9, #4\n\t" "\n" @@ -16382,12 +17866,12 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_d_48(sp_digit* r, "L_sp_3072_mul_d_48_word_%=:\n\t" #endif /* A[i] * B */ - "LDR r8, [%[a], r9]\n\t" - "UMULL r6, r7, %[b], r8\n\t" + "LDR r8, [r1, r9]\n\t" + "UMULL r6, r7, r2, r8\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], r9]\n\t" + "STR r3, [r0, r9]\n\t" "MOV r3, r4\n\t" "MOV r4, r5\n\t" "MOV r5, #0\n\t" @@ -16400,16 +17884,27 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_d_48(sp_digit* r, #else "BLT.N L_sp_3072_mul_d_48_word_%=\n\t" #endif - "STR r3, [%[r], #192]\n\t" + "STR r3, [r0, #192]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -16431,258 +17926,277 @@ WC_OMIT_FRAME_POINTER static void sp_3072_mul_d_48(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDM %[a]!, {r8}\n\t" - "UMULL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMULL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[1] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[2] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[3] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[4] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[5] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[6] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[7] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[8] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[9] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[10] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[11] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[12] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[13] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[14] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[15] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[16] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[17] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[18] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[19] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[20] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[21] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[22] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[23] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[24] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[25] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[26] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[27] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[28] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[29] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[30] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[31] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[32] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[33] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[34] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[35] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[36] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[37] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[38] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[39] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[40] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[41] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[42] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[43] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[44] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[45] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[46] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[47] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" - "STR r3, [%[r]]\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" + "STR r3, [r0]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -16709,53 +18223,73 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_3072_word_48(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r8, %[div], #16\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r8, r2, #16\n\t" "ADD r5, r8, #1\n\t" - "UDIV r6, %[d1], r5\n\t" - "LSL r7, %[div], #16\n\t" + "UDIV r6, r0, r5\n\t" + "LSL r7, r2, #16\n\t" "LSL r6, r6, #16\n\t" - "UMULL r3, r4, %[div], r6\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "SUBS r3, %[d1], r5\n\t" + "UMULL r3, r4, r2, r6\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "SUBS r3, r0, r5\n\t" "SBC r9, r9, r9\n\t" "ADD r9, r9, #1\n\t" "RSB r10, r9, #0\n\t" "LSL r9, r9, #16\n\t" "AND r7, r7, r10\n\t" "AND r8, r8, r10\n\t" - "SUBS %[d0], %[d0], r7\n\t" + "SUBS r1, r1, r7\n\t" "ADD r6, r6, r9\n\t" - "SBC %[d1], %[d1], r8\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "SBC r0, r0, r8\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "UMULL r3, r4, %[div], r3\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "UMULL r3, r4, r2, r3\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "MUL r3, %[div], r3\n\t" - "SUB %[d0], %[d0], r3\n\t" - "UDIV r3, %[d0], %[div]\n\t" - "ADD %[d1], r6, r3\n\t" + "MUL r3, r2, r3\n\t" + "SUB r1, r1, r3\n\t" + "UDIV r3, r1, r2\n\t" + "ADD r0, r6, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -16782,13 +18316,22 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_3072_word_48(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r5, %[div], #1\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r5, r2, #1\n\t" "ADD r5, r5, #1\n\t" - "MOV r6, %[d0]\n\t" - "MOV r7, %[d1]\n\t" + "MOV r6, r1\n\t" + "MOV r7, r0\n\t" /* Do top 32 */ "SUBS r8, r5, r7\n\t" "SBC r8, r8, r8\n\t" @@ -16822,29 +18365,40 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_3072_word_48(sp_digit d1, #endif "ADD r3, r3, r3\n\t" "ADD r3, r3, #1\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "SUBS r8, r9, %[div]\n\t" - "ADC %[d1], r3, #0\n\t" + "SUBS r8, r9, r2\n\t" + "ADC r0, r3, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -16868,9 +18422,17 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0xffffffff\n\t" "MOV r8, #1\n\t" "MOV r7, #0\n\t" @@ -16883,8 +18445,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, #else "L_sp_3072_cmp_48_words_%=:\n\t" #endif - "LDR r4, [%[a], r6]\n\t" - "LDR r5, [%[b], r6]\n\t" + "LDR r4, [r0, r6]\n\t" + "LDR r5, [r1, r6]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -16902,8 +18464,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, #endif "EOR r2, r2, r3\n\t" #else - "LDR r4, [%[a], #188]\n\t" - "LDR r5, [%[b], #188]\n\t" + "LDR r4, [r0, #188]\n\t" + "LDR r5, [r1, #188]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -16913,8 +18475,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #184]\n\t" - "LDR r5, [%[b], #184]\n\t" + "LDR r4, [r0, #184]\n\t" + "LDR r5, [r1, #184]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -16924,8 +18486,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #180]\n\t" - "LDR r5, [%[b], #180]\n\t" + "LDR r4, [r0, #180]\n\t" + "LDR r5, [r1, #180]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -16935,8 +18497,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #176]\n\t" - "LDR r5, [%[b], #176]\n\t" + "LDR r4, [r0, #176]\n\t" + "LDR r5, [r1, #176]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -16946,8 +18508,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #172]\n\t" - "LDR r5, [%[b], #172]\n\t" + "LDR r4, [r0, #172]\n\t" + "LDR r5, [r1, #172]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -16957,8 +18519,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #168]\n\t" - "LDR r5, [%[b], #168]\n\t" + "LDR r4, [r0, #168]\n\t" + "LDR r5, [r1, #168]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -16968,8 +18530,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #164]\n\t" - "LDR r5, [%[b], #164]\n\t" + "LDR r4, [r0, #164]\n\t" + "LDR r5, [r1, #164]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -16979,8 +18541,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #160]\n\t" - "LDR r5, [%[b], #160]\n\t" + "LDR r4, [r0, #160]\n\t" + "LDR r5, [r1, #160]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -16990,8 +18552,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #156]\n\t" - "LDR r5, [%[b], #156]\n\t" + "LDR r4, [r0, #156]\n\t" + "LDR r5, [r1, #156]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17001,8 +18563,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #152]\n\t" - "LDR r5, [%[b], #152]\n\t" + "LDR r4, [r0, #152]\n\t" + "LDR r5, [r1, #152]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17012,8 +18574,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #148]\n\t" - "LDR r5, [%[b], #148]\n\t" + "LDR r4, [r0, #148]\n\t" + "LDR r5, [r1, #148]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17023,8 +18585,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #144]\n\t" - "LDR r5, [%[b], #144]\n\t" + "LDR r4, [r0, #144]\n\t" + "LDR r5, [r1, #144]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17034,8 +18596,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #140]\n\t" - "LDR r5, [%[b], #140]\n\t" + "LDR r4, [r0, #140]\n\t" + "LDR r5, [r1, #140]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17045,8 +18607,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #136]\n\t" - "LDR r5, [%[b], #136]\n\t" + "LDR r4, [r0, #136]\n\t" + "LDR r5, [r1, #136]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17056,8 +18618,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #132]\n\t" - "LDR r5, [%[b], #132]\n\t" + "LDR r4, [r0, #132]\n\t" + "LDR r5, [r1, #132]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17067,8 +18629,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #128]\n\t" - "LDR r5, [%[b], #128]\n\t" + "LDR r4, [r0, #128]\n\t" + "LDR r5, [r1, #128]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17078,8 +18640,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #124]\n\t" - "LDR r5, [%[b], #124]\n\t" + "LDR r4, [r0, #124]\n\t" + "LDR r5, [r1, #124]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17089,8 +18651,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #120]\n\t" - "LDR r5, [%[b], #120]\n\t" + "LDR r4, [r0, #120]\n\t" + "LDR r5, [r1, #120]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17100,8 +18662,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #116]\n\t" - "LDR r5, [%[b], #116]\n\t" + "LDR r4, [r0, #116]\n\t" + "LDR r5, [r1, #116]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17111,8 +18673,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #112]\n\t" - "LDR r5, [%[b], #112]\n\t" + "LDR r4, [r0, #112]\n\t" + "LDR r5, [r1, #112]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17122,8 +18684,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #108]\n\t" - "LDR r5, [%[b], #108]\n\t" + "LDR r4, [r0, #108]\n\t" + "LDR r5, [r1, #108]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17133,8 +18695,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #104]\n\t" - "LDR r5, [%[b], #104]\n\t" + "LDR r4, [r0, #104]\n\t" + "LDR r5, [r1, #104]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17144,8 +18706,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #100]\n\t" - "LDR r5, [%[b], #100]\n\t" + "LDR r4, [r0, #100]\n\t" + "LDR r5, [r1, #100]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17155,8 +18717,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #96]\n\t" - "LDR r5, [%[b], #96]\n\t" + "LDR r4, [r0, #96]\n\t" + "LDR r5, [r1, #96]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17166,8 +18728,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #92]\n\t" - "LDR r5, [%[b], #92]\n\t" + "LDR r4, [r0, #92]\n\t" + "LDR r5, [r1, #92]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17177,8 +18739,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #88]\n\t" - "LDR r5, [%[b], #88]\n\t" + "LDR r4, [r0, #88]\n\t" + "LDR r5, [r1, #88]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17188,8 +18750,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #84]\n\t" - "LDR r5, [%[b], #84]\n\t" + "LDR r4, [r0, #84]\n\t" + "LDR r5, [r1, #84]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17199,8 +18761,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #80]\n\t" - "LDR r5, [%[b], #80]\n\t" + "LDR r4, [r0, #80]\n\t" + "LDR r5, [r1, #80]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17210,8 +18772,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #76]\n\t" - "LDR r5, [%[b], #76]\n\t" + "LDR r4, [r0, #76]\n\t" + "LDR r5, [r1, #76]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17221,8 +18783,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #72]\n\t" - "LDR r5, [%[b], #72]\n\t" + "LDR r4, [r0, #72]\n\t" + "LDR r5, [r1, #72]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17232,8 +18794,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #68]\n\t" - "LDR r5, [%[b], #68]\n\t" + "LDR r4, [r0, #68]\n\t" + "LDR r5, [r1, #68]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17243,8 +18805,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #64]\n\t" - "LDR r5, [%[b], #64]\n\t" + "LDR r4, [r0, #64]\n\t" + "LDR r5, [r1, #64]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17254,8 +18816,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #60]\n\t" - "LDR r5, [%[b], #60]\n\t" + "LDR r4, [r0, #60]\n\t" + "LDR r5, [r1, #60]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17265,8 +18827,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #56]\n\t" - "LDR r5, [%[b], #56]\n\t" + "LDR r4, [r0, #56]\n\t" + "LDR r5, [r1, #56]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17276,8 +18838,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #52]\n\t" - "LDR r5, [%[b], #52]\n\t" + "LDR r4, [r0, #52]\n\t" + "LDR r5, [r1, #52]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17287,8 +18849,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #48]\n\t" - "LDR r5, [%[b], #48]\n\t" + "LDR r4, [r0, #48]\n\t" + "LDR r5, [r1, #48]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17298,8 +18860,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #44]\n\t" - "LDR r5, [%[b], #44]\n\t" + "LDR r4, [r0, #44]\n\t" + "LDR r5, [r1, #44]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17309,8 +18871,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #40]\n\t" - "LDR r5, [%[b], #40]\n\t" + "LDR r4, [r0, #40]\n\t" + "LDR r5, [r1, #40]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17320,8 +18882,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #36]\n\t" - "LDR r5, [%[b], #36]\n\t" + "LDR r4, [r0, #36]\n\t" + "LDR r5, [r1, #36]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17331,8 +18893,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #32]\n\t" - "LDR r5, [%[b], #32]\n\t" + "LDR r4, [r0, #32]\n\t" + "LDR r5, [r1, #32]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17342,8 +18904,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #28]\n\t" - "LDR r5, [%[b], #28]\n\t" + "LDR r4, [r0, #28]\n\t" + "LDR r5, [r1, #28]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17353,8 +18915,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #24]\n\t" - "LDR r5, [%[b], #24]\n\t" + "LDR r4, [r0, #24]\n\t" + "LDR r5, [r1, #24]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17364,8 +18926,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #20]\n\t" - "LDR r5, [%[b], #20]\n\t" + "LDR r4, [r0, #20]\n\t" + "LDR r5, [r1, #20]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17375,8 +18937,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #16]\n\t" - "LDR r5, [%[b], #16]\n\t" + "LDR r4, [r0, #16]\n\t" + "LDR r5, [r1, #16]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17386,8 +18948,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #12]\n\t" - "LDR r5, [%[b], #12]\n\t" + "LDR r4, [r0, #12]\n\t" + "LDR r5, [r1, #12]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17397,8 +18959,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #8]\n\t" - "LDR r5, [%[b], #8]\n\t" + "LDR r4, [r0, #8]\n\t" + "LDR r5, [r1, #8]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17408,8 +18970,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #4]\n\t" - "LDR r5, [%[b], #4]\n\t" + "LDR r4, [r0, #4]\n\t" + "LDR r5, [r1, #4]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17419,8 +18981,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[b]]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r1]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -17432,16 +18994,26 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_48(const sp_digit* a, "movne r3, r7\n\t" "EOR r2, r2, r3\n\t" #endif /*WOLFSSL_SP_SMALL */ - "MOV %[a], r2\n\t" + "MOV r0, r2\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -17842,9 +19414,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_sub_96(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, #0\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -17855,12 +19436,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_sub_96(sp_digit* r, "L_sp_3072_cond_sub_96_words_%=:\n\t" #endif "SUBS r4, r8, r4\n\t" - "LDR r6, [%[a], r5]\n\t" - "LDR r7, [%[b], r5]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r5]\n\t" + "LDR r7, [r2, r5]\n\t" + "AND r7, r7, r3\n\t" "SBCS r6, r6, r7\n\t" "SBC r4, r8, r8\n\t" - "STR r6, [%[r], r5]\n\t" + "STR r6, [r0, r5]\n\t" "ADD r5, r5, #4\n\t" "CMP r5, #0x180\n\t" #if defined(__GNUC__) @@ -17870,16 +19451,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_sub_96(sp_digit* r, #else "BLT.N L_sp_3072_cond_sub_96_words_%=\n\t" #endif - "MOV %[r], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -17906,356 +19499,377 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_sub_96(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SUBS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "SBC %[r], r5, r5\n\t" + "STM r0!, {r6, r7}\n\t" + "SBC r0, r5, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -18281,15 +19895,24 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR lr, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR lr, [r1]\n\t" /* i = 0 */ "MOV r11, #0\n\t" "MOV r3, #0\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[a], #4]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_3072_mont_reduce_96_word:\n\t" @@ -18297,777 +19920,777 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( "L_sp_3072_mont_reduce_96_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL r10, %[mp], r4\n\t" + "MUL r10, r2, r4\n\t" /* a[i+0] += m[0] * mu */ "MOV r7, #0\n\t" "UMLAL r4, r7, r10, lr\n\t" /* a[i+1] += m[1] * mu */ - "LDR r9, [%[m], #4]\n\t" + "LDR r9, [r1, #4]\n\t" "MOV r6, #0\n\t" "UMLAL r5, r6, r10, r9\n\t" "MOV r4, r5\n\t" "ADDS r4, r4, r7\n\t" "ADC r6, r6, #0\n\t" /* a[i+2] += m[2] * mu */ - "LDR r9, [%[m], #8]\n\t" - "LDR r5, [%[a], #8]\n\t" + "LDR r9, [r1, #8]\n\t" + "LDR r5, [r0, #8]\n\t" "MOV r7, #0\n\t" "UMLAL r5, r7, r10, r9\n\t" "ADDS r5, r5, r6\n\t" "ADC r7, r7, #0\n\t" /* a[i+3] += m[3] * mu */ - "LDR r9, [%[m], #12]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r9, [r1, #12]\n\t" + "LDR r12, [r0, #12]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #12]\n\t" + "STR r12, [r0, #12]\n\t" "ADC r6, r6, #0\n\t" /* a[i+4] += m[4] * mu */ - "LDR r9, [%[m], #16]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r9, [r1, #16]\n\t" + "LDR r12, [r0, #16]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #16]\n\t" + "STR r12, [r0, #16]\n\t" "ADC r7, r7, #0\n\t" /* a[i+5] += m[5] * mu */ - "LDR r9, [%[m], #20]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r12, [r0, #20]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #20]\n\t" + "STR r12, [r0, #20]\n\t" "ADC r6, r6, #0\n\t" /* a[i+6] += m[6] * mu */ - "LDR r9, [%[m], #24]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r9, [r1, #24]\n\t" + "LDR r12, [r0, #24]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #24]\n\t" + "STR r12, [r0, #24]\n\t" "ADC r7, r7, #0\n\t" /* a[i+7] += m[7] * mu */ - "LDR r9, [%[m], #28]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r9, [r1, #28]\n\t" + "LDR r12, [r0, #28]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #28]\n\t" + "STR r12, [r0, #28]\n\t" "ADC r6, r6, #0\n\t" /* a[i+8] += m[8] * mu */ - "LDR r9, [%[m], #32]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r9, [r1, #32]\n\t" + "LDR r12, [r0, #32]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #32]\n\t" + "STR r12, [r0, #32]\n\t" "ADC r7, r7, #0\n\t" /* a[i+9] += m[9] * mu */ - "LDR r9, [%[m], #36]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r9, [r1, #36]\n\t" + "LDR r12, [r0, #36]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #36]\n\t" + "STR r12, [r0, #36]\n\t" "ADC r6, r6, #0\n\t" /* a[i+10] += m[10] * mu */ - "LDR r9, [%[m], #40]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r9, [r1, #40]\n\t" + "LDR r12, [r0, #40]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #40]\n\t" + "STR r12, [r0, #40]\n\t" "ADC r7, r7, #0\n\t" /* a[i+11] += m[11] * mu */ - "LDR r9, [%[m], #44]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r9, [r1, #44]\n\t" + "LDR r12, [r0, #44]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #44]\n\t" + "STR r12, [r0, #44]\n\t" "ADC r6, r6, #0\n\t" /* a[i+12] += m[12] * mu */ - "LDR r9, [%[m], #48]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r9, [r1, #48]\n\t" + "LDR r12, [r0, #48]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #48]\n\t" + "STR r12, [r0, #48]\n\t" "ADC r7, r7, #0\n\t" /* a[i+13] += m[13] * mu */ - "LDR r9, [%[m], #52]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r9, [r1, #52]\n\t" + "LDR r12, [r0, #52]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #52]\n\t" + "STR r12, [r0, #52]\n\t" "ADC r6, r6, #0\n\t" /* a[i+14] += m[14] * mu */ - "LDR r9, [%[m], #56]\n\t" - "LDR r12, [%[a], #56]\n\t" + "LDR r9, [r1, #56]\n\t" + "LDR r12, [r0, #56]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #56]\n\t" + "STR r12, [r0, #56]\n\t" "ADC r7, r7, #0\n\t" /* a[i+15] += m[15] * mu */ - "LDR r9, [%[m], #60]\n\t" - "LDR r12, [%[a], #60]\n\t" + "LDR r9, [r1, #60]\n\t" + "LDR r12, [r0, #60]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #60]\n\t" + "STR r12, [r0, #60]\n\t" "ADC r6, r6, #0\n\t" /* a[i+16] += m[16] * mu */ - "LDR r9, [%[m], #64]\n\t" - "LDR r12, [%[a], #64]\n\t" + "LDR r9, [r1, #64]\n\t" + "LDR r12, [r0, #64]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #64]\n\t" + "STR r12, [r0, #64]\n\t" "ADC r7, r7, #0\n\t" /* a[i+17] += m[17] * mu */ - "LDR r9, [%[m], #68]\n\t" - "LDR r12, [%[a], #68]\n\t" + "LDR r9, [r1, #68]\n\t" + "LDR r12, [r0, #68]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #68]\n\t" + "STR r12, [r0, #68]\n\t" "ADC r6, r6, #0\n\t" /* a[i+18] += m[18] * mu */ - "LDR r9, [%[m], #72]\n\t" - "LDR r12, [%[a], #72]\n\t" + "LDR r9, [r1, #72]\n\t" + "LDR r12, [r0, #72]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #72]\n\t" + "STR r12, [r0, #72]\n\t" "ADC r7, r7, #0\n\t" /* a[i+19] += m[19] * mu */ - "LDR r9, [%[m], #76]\n\t" - "LDR r12, [%[a], #76]\n\t" + "LDR r9, [r1, #76]\n\t" + "LDR r12, [r0, #76]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #76]\n\t" + "STR r12, [r0, #76]\n\t" "ADC r6, r6, #0\n\t" /* a[i+20] += m[20] * mu */ - "LDR r9, [%[m], #80]\n\t" - "LDR r12, [%[a], #80]\n\t" + "LDR r9, [r1, #80]\n\t" + "LDR r12, [r0, #80]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #80]\n\t" + "STR r12, [r0, #80]\n\t" "ADC r7, r7, #0\n\t" /* a[i+21] += m[21] * mu */ - "LDR r9, [%[m], #84]\n\t" - "LDR r12, [%[a], #84]\n\t" + "LDR r9, [r1, #84]\n\t" + "LDR r12, [r0, #84]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #84]\n\t" + "STR r12, [r0, #84]\n\t" "ADC r6, r6, #0\n\t" /* a[i+22] += m[22] * mu */ - "LDR r9, [%[m], #88]\n\t" - "LDR r12, [%[a], #88]\n\t" + "LDR r9, [r1, #88]\n\t" + "LDR r12, [r0, #88]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #88]\n\t" + "STR r12, [r0, #88]\n\t" "ADC r7, r7, #0\n\t" /* a[i+23] += m[23] * mu */ - "LDR r9, [%[m], #92]\n\t" - "LDR r12, [%[a], #92]\n\t" + "LDR r9, [r1, #92]\n\t" + "LDR r12, [r0, #92]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #92]\n\t" + "STR r12, [r0, #92]\n\t" "ADC r6, r6, #0\n\t" /* a[i+24] += m[24] * mu */ - "LDR r9, [%[m], #96]\n\t" - "LDR r12, [%[a], #96]\n\t" + "LDR r9, [r1, #96]\n\t" + "LDR r12, [r0, #96]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #96]\n\t" + "STR r12, [r0, #96]\n\t" "ADC r7, r7, #0\n\t" /* a[i+25] += m[25] * mu */ - "LDR r9, [%[m], #100]\n\t" - "LDR r12, [%[a], #100]\n\t" + "LDR r9, [r1, #100]\n\t" + "LDR r12, [r0, #100]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #100]\n\t" + "STR r12, [r0, #100]\n\t" "ADC r6, r6, #0\n\t" /* a[i+26] += m[26] * mu */ - "LDR r9, [%[m], #104]\n\t" - "LDR r12, [%[a], #104]\n\t" + "LDR r9, [r1, #104]\n\t" + "LDR r12, [r0, #104]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #104]\n\t" + "STR r12, [r0, #104]\n\t" "ADC r7, r7, #0\n\t" /* a[i+27] += m[27] * mu */ - "LDR r9, [%[m], #108]\n\t" - "LDR r12, [%[a], #108]\n\t" + "LDR r9, [r1, #108]\n\t" + "LDR r12, [r0, #108]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #108]\n\t" + "STR r12, [r0, #108]\n\t" "ADC r6, r6, #0\n\t" /* a[i+28] += m[28] * mu */ - "LDR r9, [%[m], #112]\n\t" - "LDR r12, [%[a], #112]\n\t" + "LDR r9, [r1, #112]\n\t" + "LDR r12, [r0, #112]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #112]\n\t" + "STR r12, [r0, #112]\n\t" "ADC r7, r7, #0\n\t" /* a[i+29] += m[29] * mu */ - "LDR r9, [%[m], #116]\n\t" - "LDR r12, [%[a], #116]\n\t" + "LDR r9, [r1, #116]\n\t" + "LDR r12, [r0, #116]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #116]\n\t" + "STR r12, [r0, #116]\n\t" "ADC r6, r6, #0\n\t" /* a[i+30] += m[30] * mu */ - "LDR r9, [%[m], #120]\n\t" - "LDR r12, [%[a], #120]\n\t" + "LDR r9, [r1, #120]\n\t" + "LDR r12, [r0, #120]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #120]\n\t" + "STR r12, [r0, #120]\n\t" "ADC r7, r7, #0\n\t" /* a[i+31] += m[31] * mu */ - "LDR r9, [%[m], #124]\n\t" - "LDR r12, [%[a], #124]\n\t" + "LDR r9, [r1, #124]\n\t" + "LDR r12, [r0, #124]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #124]\n\t" + "STR r12, [r0, #124]\n\t" "ADC r6, r6, #0\n\t" /* a[i+32] += m[32] * mu */ - "LDR r9, [%[m], #128]\n\t" - "LDR r12, [%[a], #128]\n\t" + "LDR r9, [r1, #128]\n\t" + "LDR r12, [r0, #128]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #128]\n\t" + "STR r12, [r0, #128]\n\t" "ADC r7, r7, #0\n\t" /* a[i+33] += m[33] * mu */ - "LDR r9, [%[m], #132]\n\t" - "LDR r12, [%[a], #132]\n\t" + "LDR r9, [r1, #132]\n\t" + "LDR r12, [r0, #132]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #132]\n\t" + "STR r12, [r0, #132]\n\t" "ADC r6, r6, #0\n\t" /* a[i+34] += m[34] * mu */ - "LDR r9, [%[m], #136]\n\t" - "LDR r12, [%[a], #136]\n\t" + "LDR r9, [r1, #136]\n\t" + "LDR r12, [r0, #136]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #136]\n\t" + "STR r12, [r0, #136]\n\t" "ADC r7, r7, #0\n\t" /* a[i+35] += m[35] * mu */ - "LDR r9, [%[m], #140]\n\t" - "LDR r12, [%[a], #140]\n\t" + "LDR r9, [r1, #140]\n\t" + "LDR r12, [r0, #140]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #140]\n\t" + "STR r12, [r0, #140]\n\t" "ADC r6, r6, #0\n\t" /* a[i+36] += m[36] * mu */ - "LDR r9, [%[m], #144]\n\t" - "LDR r12, [%[a], #144]\n\t" + "LDR r9, [r1, #144]\n\t" + "LDR r12, [r0, #144]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #144]\n\t" + "STR r12, [r0, #144]\n\t" "ADC r7, r7, #0\n\t" /* a[i+37] += m[37] * mu */ - "LDR r9, [%[m], #148]\n\t" - "LDR r12, [%[a], #148]\n\t" + "LDR r9, [r1, #148]\n\t" + "LDR r12, [r0, #148]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #148]\n\t" + "STR r12, [r0, #148]\n\t" "ADC r6, r6, #0\n\t" /* a[i+38] += m[38] * mu */ - "LDR r9, [%[m], #152]\n\t" - "LDR r12, [%[a], #152]\n\t" + "LDR r9, [r1, #152]\n\t" + "LDR r12, [r0, #152]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #152]\n\t" + "STR r12, [r0, #152]\n\t" "ADC r7, r7, #0\n\t" /* a[i+39] += m[39] * mu */ - "LDR r9, [%[m], #156]\n\t" - "LDR r12, [%[a], #156]\n\t" + "LDR r9, [r1, #156]\n\t" + "LDR r12, [r0, #156]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #156]\n\t" + "STR r12, [r0, #156]\n\t" "ADC r6, r6, #0\n\t" /* a[i+40] += m[40] * mu */ - "LDR r9, [%[m], #160]\n\t" - "LDR r12, [%[a], #160]\n\t" + "LDR r9, [r1, #160]\n\t" + "LDR r12, [r0, #160]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #160]\n\t" + "STR r12, [r0, #160]\n\t" "ADC r7, r7, #0\n\t" /* a[i+41] += m[41] * mu */ - "LDR r9, [%[m], #164]\n\t" - "LDR r12, [%[a], #164]\n\t" + "LDR r9, [r1, #164]\n\t" + "LDR r12, [r0, #164]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #164]\n\t" + "STR r12, [r0, #164]\n\t" "ADC r6, r6, #0\n\t" /* a[i+42] += m[42] * mu */ - "LDR r9, [%[m], #168]\n\t" - "LDR r12, [%[a], #168]\n\t" + "LDR r9, [r1, #168]\n\t" + "LDR r12, [r0, #168]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #168]\n\t" + "STR r12, [r0, #168]\n\t" "ADC r7, r7, #0\n\t" /* a[i+43] += m[43] * mu */ - "LDR r9, [%[m], #172]\n\t" - "LDR r12, [%[a], #172]\n\t" + "LDR r9, [r1, #172]\n\t" + "LDR r12, [r0, #172]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #172]\n\t" + "STR r12, [r0, #172]\n\t" "ADC r6, r6, #0\n\t" /* a[i+44] += m[44] * mu */ - "LDR r9, [%[m], #176]\n\t" - "LDR r12, [%[a], #176]\n\t" + "LDR r9, [r1, #176]\n\t" + "LDR r12, [r0, #176]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #176]\n\t" + "STR r12, [r0, #176]\n\t" "ADC r7, r7, #0\n\t" /* a[i+45] += m[45] * mu */ - "LDR r9, [%[m], #180]\n\t" - "LDR r12, [%[a], #180]\n\t" + "LDR r9, [r1, #180]\n\t" + "LDR r12, [r0, #180]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #180]\n\t" + "STR r12, [r0, #180]\n\t" "ADC r6, r6, #0\n\t" /* a[i+46] += m[46] * mu */ - "LDR r9, [%[m], #184]\n\t" - "LDR r12, [%[a], #184]\n\t" + "LDR r9, [r1, #184]\n\t" + "LDR r12, [r0, #184]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #184]\n\t" + "STR r12, [r0, #184]\n\t" "ADC r7, r7, #0\n\t" /* a[i+47] += m[47] * mu */ - "LDR r9, [%[m], #188]\n\t" - "LDR r12, [%[a], #188]\n\t" + "LDR r9, [r1, #188]\n\t" + "LDR r12, [r0, #188]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #188]\n\t" + "STR r12, [r0, #188]\n\t" "ADC r6, r6, #0\n\t" /* a[i+48] += m[48] * mu */ - "LDR r9, [%[m], #192]\n\t" - "LDR r12, [%[a], #192]\n\t" + "LDR r9, [r1, #192]\n\t" + "LDR r12, [r0, #192]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #192]\n\t" + "STR r12, [r0, #192]\n\t" "ADC r7, r7, #0\n\t" /* a[i+49] += m[49] * mu */ - "LDR r9, [%[m], #196]\n\t" - "LDR r12, [%[a], #196]\n\t" + "LDR r9, [r1, #196]\n\t" + "LDR r12, [r0, #196]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #196]\n\t" + "STR r12, [r0, #196]\n\t" "ADC r6, r6, #0\n\t" /* a[i+50] += m[50] * mu */ - "LDR r9, [%[m], #200]\n\t" - "LDR r12, [%[a], #200]\n\t" + "LDR r9, [r1, #200]\n\t" + "LDR r12, [r0, #200]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #200]\n\t" + "STR r12, [r0, #200]\n\t" "ADC r7, r7, #0\n\t" /* a[i+51] += m[51] * mu */ - "LDR r9, [%[m], #204]\n\t" - "LDR r12, [%[a], #204]\n\t" + "LDR r9, [r1, #204]\n\t" + "LDR r12, [r0, #204]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #204]\n\t" + "STR r12, [r0, #204]\n\t" "ADC r6, r6, #0\n\t" /* a[i+52] += m[52] * mu */ - "LDR r9, [%[m], #208]\n\t" - "LDR r12, [%[a], #208]\n\t" + "LDR r9, [r1, #208]\n\t" + "LDR r12, [r0, #208]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #208]\n\t" + "STR r12, [r0, #208]\n\t" "ADC r7, r7, #0\n\t" /* a[i+53] += m[53] * mu */ - "LDR r9, [%[m], #212]\n\t" - "LDR r12, [%[a], #212]\n\t" + "LDR r9, [r1, #212]\n\t" + "LDR r12, [r0, #212]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #212]\n\t" + "STR r12, [r0, #212]\n\t" "ADC r6, r6, #0\n\t" /* a[i+54] += m[54] * mu */ - "LDR r9, [%[m], #216]\n\t" - "LDR r12, [%[a], #216]\n\t" + "LDR r9, [r1, #216]\n\t" + "LDR r12, [r0, #216]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #216]\n\t" + "STR r12, [r0, #216]\n\t" "ADC r7, r7, #0\n\t" /* a[i+55] += m[55] * mu */ - "LDR r9, [%[m], #220]\n\t" - "LDR r12, [%[a], #220]\n\t" + "LDR r9, [r1, #220]\n\t" + "LDR r12, [r0, #220]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #220]\n\t" + "STR r12, [r0, #220]\n\t" "ADC r6, r6, #0\n\t" /* a[i+56] += m[56] * mu */ - "LDR r9, [%[m], #224]\n\t" - "LDR r12, [%[a], #224]\n\t" + "LDR r9, [r1, #224]\n\t" + "LDR r12, [r0, #224]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #224]\n\t" + "STR r12, [r0, #224]\n\t" "ADC r7, r7, #0\n\t" /* a[i+57] += m[57] * mu */ - "LDR r9, [%[m], #228]\n\t" - "LDR r12, [%[a], #228]\n\t" + "LDR r9, [r1, #228]\n\t" + "LDR r12, [r0, #228]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #228]\n\t" + "STR r12, [r0, #228]\n\t" "ADC r6, r6, #0\n\t" /* a[i+58] += m[58] * mu */ - "LDR r9, [%[m], #232]\n\t" - "LDR r12, [%[a], #232]\n\t" + "LDR r9, [r1, #232]\n\t" + "LDR r12, [r0, #232]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #232]\n\t" + "STR r12, [r0, #232]\n\t" "ADC r7, r7, #0\n\t" /* a[i+59] += m[59] * mu */ - "LDR r9, [%[m], #236]\n\t" - "LDR r12, [%[a], #236]\n\t" + "LDR r9, [r1, #236]\n\t" + "LDR r12, [r0, #236]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #236]\n\t" + "STR r12, [r0, #236]\n\t" "ADC r6, r6, #0\n\t" /* a[i+60] += m[60] * mu */ - "LDR r9, [%[m], #240]\n\t" - "LDR r12, [%[a], #240]\n\t" + "LDR r9, [r1, #240]\n\t" + "LDR r12, [r0, #240]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #240]\n\t" + "STR r12, [r0, #240]\n\t" "ADC r7, r7, #0\n\t" /* a[i+61] += m[61] * mu */ - "LDR r9, [%[m], #244]\n\t" - "LDR r12, [%[a], #244]\n\t" + "LDR r9, [r1, #244]\n\t" + "LDR r12, [r0, #244]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #244]\n\t" + "STR r12, [r0, #244]\n\t" "ADC r6, r6, #0\n\t" /* a[i+62] += m[62] * mu */ - "LDR r9, [%[m], #248]\n\t" - "LDR r12, [%[a], #248]\n\t" + "LDR r9, [r1, #248]\n\t" + "LDR r12, [r0, #248]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #248]\n\t" + "STR r12, [r0, #248]\n\t" "ADC r7, r7, #0\n\t" /* a[i+63] += m[63] * mu */ - "LDR r9, [%[m], #252]\n\t" - "LDR r12, [%[a], #252]\n\t" + "LDR r9, [r1, #252]\n\t" + "LDR r12, [r0, #252]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #252]\n\t" + "STR r12, [r0, #252]\n\t" "ADC r6, r6, #0\n\t" /* a[i+64] += m[64] * mu */ - "LDR r9, [%[m], #256]\n\t" - "LDR r12, [%[a], #256]\n\t" + "LDR r9, [r1, #256]\n\t" + "LDR r12, [r0, #256]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #256]\n\t" + "STR r12, [r0, #256]\n\t" "ADC r7, r7, #0\n\t" /* a[i+65] += m[65] * mu */ - "LDR r9, [%[m], #260]\n\t" - "LDR r12, [%[a], #260]\n\t" + "LDR r9, [r1, #260]\n\t" + "LDR r12, [r0, #260]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #260]\n\t" + "STR r12, [r0, #260]\n\t" "ADC r6, r6, #0\n\t" /* a[i+66] += m[66] * mu */ - "LDR r9, [%[m], #264]\n\t" - "LDR r12, [%[a], #264]\n\t" + "LDR r9, [r1, #264]\n\t" + "LDR r12, [r0, #264]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #264]\n\t" + "STR r12, [r0, #264]\n\t" "ADC r7, r7, #0\n\t" /* a[i+67] += m[67] * mu */ - "LDR r9, [%[m], #268]\n\t" - "LDR r12, [%[a], #268]\n\t" + "LDR r9, [r1, #268]\n\t" + "LDR r12, [r0, #268]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #268]\n\t" + "STR r12, [r0, #268]\n\t" "ADC r6, r6, #0\n\t" /* a[i+68] += m[68] * mu */ - "LDR r9, [%[m], #272]\n\t" - "LDR r12, [%[a], #272]\n\t" + "LDR r9, [r1, #272]\n\t" + "LDR r12, [r0, #272]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #272]\n\t" + "STR r12, [r0, #272]\n\t" "ADC r7, r7, #0\n\t" /* a[i+69] += m[69] * mu */ - "LDR r9, [%[m], #276]\n\t" - "LDR r12, [%[a], #276]\n\t" + "LDR r9, [r1, #276]\n\t" + "LDR r12, [r0, #276]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #276]\n\t" + "STR r12, [r0, #276]\n\t" "ADC r6, r6, #0\n\t" /* a[i+70] += m[70] * mu */ - "LDR r9, [%[m], #280]\n\t" - "LDR r12, [%[a], #280]\n\t" + "LDR r9, [r1, #280]\n\t" + "LDR r12, [r0, #280]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #280]\n\t" + "STR r12, [r0, #280]\n\t" "ADC r7, r7, #0\n\t" /* a[i+71] += m[71] * mu */ - "LDR r9, [%[m], #284]\n\t" - "LDR r12, [%[a], #284]\n\t" + "LDR r9, [r1, #284]\n\t" + "LDR r12, [r0, #284]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #284]\n\t" + "STR r12, [r0, #284]\n\t" "ADC r6, r6, #0\n\t" /* a[i+72] += m[72] * mu */ - "LDR r9, [%[m], #288]\n\t" - "LDR r12, [%[a], #288]\n\t" + "LDR r9, [r1, #288]\n\t" + "LDR r12, [r0, #288]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #288]\n\t" + "STR r12, [r0, #288]\n\t" "ADC r7, r7, #0\n\t" /* a[i+73] += m[73] * mu */ - "LDR r9, [%[m], #292]\n\t" - "LDR r12, [%[a], #292]\n\t" + "LDR r9, [r1, #292]\n\t" + "LDR r12, [r0, #292]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #292]\n\t" + "STR r12, [r0, #292]\n\t" "ADC r6, r6, #0\n\t" /* a[i+74] += m[74] * mu */ - "LDR r9, [%[m], #296]\n\t" - "LDR r12, [%[a], #296]\n\t" + "LDR r9, [r1, #296]\n\t" + "LDR r12, [r0, #296]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #296]\n\t" + "STR r12, [r0, #296]\n\t" "ADC r7, r7, #0\n\t" /* a[i+75] += m[75] * mu */ - "LDR r9, [%[m], #300]\n\t" - "LDR r12, [%[a], #300]\n\t" + "LDR r9, [r1, #300]\n\t" + "LDR r12, [r0, #300]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #300]\n\t" + "STR r12, [r0, #300]\n\t" "ADC r6, r6, #0\n\t" /* a[i+76] += m[76] * mu */ - "LDR r9, [%[m], #304]\n\t" - "LDR r12, [%[a], #304]\n\t" + "LDR r9, [r1, #304]\n\t" + "LDR r12, [r0, #304]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #304]\n\t" + "STR r12, [r0, #304]\n\t" "ADC r7, r7, #0\n\t" /* a[i+77] += m[77] * mu */ - "LDR r9, [%[m], #308]\n\t" - "LDR r12, [%[a], #308]\n\t" + "LDR r9, [r1, #308]\n\t" + "LDR r12, [r0, #308]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #308]\n\t" + "STR r12, [r0, #308]\n\t" "ADC r6, r6, #0\n\t" /* a[i+78] += m[78] * mu */ - "LDR r9, [%[m], #312]\n\t" - "LDR r12, [%[a], #312]\n\t" + "LDR r9, [r1, #312]\n\t" + "LDR r12, [r0, #312]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #312]\n\t" + "STR r12, [r0, #312]\n\t" "ADC r7, r7, #0\n\t" /* a[i+79] += m[79] * mu */ - "LDR r9, [%[m], #316]\n\t" - "LDR r12, [%[a], #316]\n\t" + "LDR r9, [r1, #316]\n\t" + "LDR r12, [r0, #316]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #316]\n\t" + "STR r12, [r0, #316]\n\t" "ADC r6, r6, #0\n\t" /* a[i+80] += m[80] * mu */ - "LDR r9, [%[m], #320]\n\t" - "LDR r12, [%[a], #320]\n\t" + "LDR r9, [r1, #320]\n\t" + "LDR r12, [r0, #320]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #320]\n\t" + "STR r12, [r0, #320]\n\t" "ADC r7, r7, #0\n\t" /* a[i+81] += m[81] * mu */ - "LDR r9, [%[m], #324]\n\t" - "LDR r12, [%[a], #324]\n\t" + "LDR r9, [r1, #324]\n\t" + "LDR r12, [r0, #324]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #324]\n\t" + "STR r12, [r0, #324]\n\t" "ADC r6, r6, #0\n\t" /* a[i+82] += m[82] * mu */ - "LDR r9, [%[m], #328]\n\t" - "LDR r12, [%[a], #328]\n\t" + "LDR r9, [r1, #328]\n\t" + "LDR r12, [r0, #328]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #328]\n\t" + "STR r12, [r0, #328]\n\t" "ADC r7, r7, #0\n\t" /* a[i+83] += m[83] * mu */ - "LDR r9, [%[m], #332]\n\t" - "LDR r12, [%[a], #332]\n\t" + "LDR r9, [r1, #332]\n\t" + "LDR r12, [r0, #332]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #332]\n\t" + "STR r12, [r0, #332]\n\t" "ADC r6, r6, #0\n\t" /* a[i+84] += m[84] * mu */ - "LDR r9, [%[m], #336]\n\t" - "LDR r12, [%[a], #336]\n\t" + "LDR r9, [r1, #336]\n\t" + "LDR r12, [r0, #336]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #336]\n\t" + "STR r12, [r0, #336]\n\t" "ADC r7, r7, #0\n\t" /* a[i+85] += m[85] * mu */ - "LDR r9, [%[m], #340]\n\t" - "LDR r12, [%[a], #340]\n\t" + "LDR r9, [r1, #340]\n\t" + "LDR r12, [r0, #340]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #340]\n\t" + "STR r12, [r0, #340]\n\t" "ADC r6, r6, #0\n\t" /* a[i+86] += m[86] * mu */ - "LDR r9, [%[m], #344]\n\t" - "LDR r12, [%[a], #344]\n\t" + "LDR r9, [r1, #344]\n\t" + "LDR r12, [r0, #344]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #344]\n\t" + "STR r12, [r0, #344]\n\t" "ADC r7, r7, #0\n\t" /* a[i+87] += m[87] * mu */ - "LDR r9, [%[m], #348]\n\t" - "LDR r12, [%[a], #348]\n\t" + "LDR r9, [r1, #348]\n\t" + "LDR r12, [r0, #348]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #348]\n\t" + "STR r12, [r0, #348]\n\t" "ADC r6, r6, #0\n\t" /* a[i+88] += m[88] * mu */ - "LDR r9, [%[m], #352]\n\t" - "LDR r12, [%[a], #352]\n\t" + "LDR r9, [r1, #352]\n\t" + "LDR r12, [r0, #352]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #352]\n\t" + "STR r12, [r0, #352]\n\t" "ADC r7, r7, #0\n\t" /* a[i+89] += m[89] * mu */ - "LDR r9, [%[m], #356]\n\t" - "LDR r12, [%[a], #356]\n\t" + "LDR r9, [r1, #356]\n\t" + "LDR r12, [r0, #356]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #356]\n\t" + "STR r12, [r0, #356]\n\t" "ADC r6, r6, #0\n\t" /* a[i+90] += m[90] * mu */ - "LDR r9, [%[m], #360]\n\t" - "LDR r12, [%[a], #360]\n\t" + "LDR r9, [r1, #360]\n\t" + "LDR r12, [r0, #360]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #360]\n\t" + "STR r12, [r0, #360]\n\t" "ADC r7, r7, #0\n\t" /* a[i+91] += m[91] * mu */ - "LDR r9, [%[m], #364]\n\t" - "LDR r12, [%[a], #364]\n\t" + "LDR r9, [r1, #364]\n\t" + "LDR r12, [r0, #364]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #364]\n\t" + "STR r12, [r0, #364]\n\t" "ADC r6, r6, #0\n\t" /* a[i+92] += m[92] * mu */ - "LDR r9, [%[m], #368]\n\t" - "LDR r12, [%[a], #368]\n\t" + "LDR r9, [r1, #368]\n\t" + "LDR r12, [r0, #368]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #368]\n\t" + "STR r12, [r0, #368]\n\t" "ADC r7, r7, #0\n\t" /* a[i+93] += m[93] * mu */ - "LDR r9, [%[m], #372]\n\t" - "LDR r12, [%[a], #372]\n\t" + "LDR r9, [r1, #372]\n\t" + "LDR r12, [r0, #372]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #372]\n\t" + "STR r12, [r0, #372]\n\t" "ADC r6, r6, #0\n\t" /* a[i+94] += m[94] * mu */ - "LDR r9, [%[m], #376]\n\t" - "LDR r12, [%[a], #376]\n\t" + "LDR r9, [r1, #376]\n\t" + "LDR r12, [r0, #376]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #376]\n\t" + "STR r12, [r0, #376]\n\t" "ADC r7, r7, #0\n\t" /* a[i+95] += m[95] * mu */ - "LDR r9, [%[m], #380]\n\t" - "LDR r12, [%[a], #380]\n\t" + "LDR r9, [r1, #380]\n\t" + "LDR r12, [r0, #380]\n\t" "UMULL r8, r9, r10, r9\n\t" "ADDS r7, r7, r8\n\t" "ADCS r6, r9, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, r3\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #380]\n\t" - "LDR r12, [%[a], #384]\n\t" + "STR r12, [r0, #380]\n\t" + "LDR r12, [r0, #384]\n\t" "ADCS r12, r12, r6\n\t" - "STR r12, [%[a], #384]\n\t" + "STR r12, [r0, #384]\n\t" "ADC r3, r3, #0\n\t" /* i += 1 */ "ADD r11, r11, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r11, #0x180\n\t" #if defined(__GNUC__) "BLT L_sp_3072_mont_reduce_96_word_%=\n\t" @@ -19077,19 +20700,30 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( "BLT.W L_sp_3072_mont_reduce_96_word_%=\n\t" #endif /* Loop Done */ - "STR r4, [%[a]]\n\t" - "STR r5, [%[a], #4]\n\t" - "MOV %[mp], r3\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_3072_cond_sub_96(a - 96, a, m, (sp_digit)0 - mp); } @@ -19113,10 +20747,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r11, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r11, [r1]\n\t" /* i = 0 */ "MOV r9, #0\n\t" /* ca = 0 */ @@ -19128,8 +20771,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( "L_sp_3072_mont_reduce_96_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "LDR r10, [%[a]]\n\t" - "MUL r8, %[mp], r10\n\t" + "LDR r10, [r0]\n\t" + "MUL r8, r2, r10\n\t" /* j = 0 */ "MOV r12, #0\n\t" "MOV r4, #0\n\t" @@ -19140,42 +20783,42 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( "L_sp_3072_mont_reduce_96_mul_%=:\n\t" #endif /* a[i+j+0] += m[j+0] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+1] += m[j+1] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+2] += m[j+2] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+3] += m[j+3] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" @@ -19187,16 +20830,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( #else "BLT.N L_sp_3072_mont_reduce_96_mul_%=\n\t" #endif - "LDR r10, [%[a], #384]\n\t" + "LDR r10, [r0, #384]\n\t" "ADDS r4, r4, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" "ADDS r10, r10, r4\n\t" "ADC r3, r3, r3\n\t" - "STR r10, [%[a], #384]\n\t" + "STR r10, [r0, #384]\n\t" /* i += 1 */ "ADD r9, r9, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r9, #0x180\n\t" #if defined(__GNUC__) "BLT L_sp_3072_mont_reduce_96_word_%=\n\t" @@ -19206,17 +20849,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( "BLT.N L_sp_3072_mont_reduce_96_word_%=\n\t" #endif /* Loop Done */ - "MOV %[mp], r3\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_3072_cond_sub_96(a - 96, a, m, (sp_digit)0 - mp); } @@ -19242,17 +20896,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* i = 0 */ "MOV r4, #0\n\t" "MOV r5, #0\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r7, [%[a], #4]\n\t" - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[a], #12]\n\t" - "LDR r10, [%[a], #16]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" + "LDR r10, [r0, #16]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_3072_mont_reduce_96_word:\n\t" @@ -19260,490 +20923,490 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( "L_sp_3072_mont_reduce_96_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL lr, %[mp], r6\n\t" + "MUL lr, r2, r6\n\t" /* a[i+0] += m[0] * mu */ - "LDR r12, [%[m]]\n\t" + "LDR r12, [r1]\n\t" "MOV r3, #0\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+1] += m[1] * mu */ - "LDR r12, [%[m], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "MOV r6, r7\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+2] += m[2] * mu */ - "LDR r12, [%[m], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "MOV r7, r8\n\t" "UMAAL r7, r3, lr, r12\n\t" /* a[i+3] += m[3] * mu */ - "LDR r12, [%[m], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "MOV r8, r9\n\t" "UMAAL r8, r3, lr, r12\n\t" /* a[i+4] += m[4] * mu */ - "LDR r12, [%[m], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "MOV r9, r10\n\t" "UMAAL r9, r3, lr, r12\n\t" /* a[i+5] += m[5] * mu */ - "LDR r12, [%[m], #20]\n\t" - "LDR r10, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR r10, [r0, #20]\n\t" "UMAAL r10, r3, lr, r12\n\t" /* a[i+6] += m[6] * mu */ - "LDR r12, [%[m], #24]\n\t" - "LDR r11, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR r11, [r0, #24]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #24]\n\t" + "STR r11, [r0, #24]\n\t" /* a[i+7] += m[7] * mu */ - "LDR r12, [%[m], #28]\n\t" - "LDR r11, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR r11, [r0, #28]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #28]\n\t" + "STR r11, [r0, #28]\n\t" /* a[i+8] += m[8] * mu */ - "LDR r12, [%[m], #32]\n\t" - "LDR r11, [%[a], #32]\n\t" + "LDR r12, [r1, #32]\n\t" + "LDR r11, [r0, #32]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #32]\n\t" + "STR r11, [r0, #32]\n\t" /* a[i+9] += m[9] * mu */ - "LDR r12, [%[m], #36]\n\t" - "LDR r11, [%[a], #36]\n\t" + "LDR r12, [r1, #36]\n\t" + "LDR r11, [r0, #36]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #36]\n\t" + "STR r11, [r0, #36]\n\t" /* a[i+10] += m[10] * mu */ - "LDR r12, [%[m], #40]\n\t" - "LDR r11, [%[a], #40]\n\t" + "LDR r12, [r1, #40]\n\t" + "LDR r11, [r0, #40]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #40]\n\t" + "STR r11, [r0, #40]\n\t" /* a[i+11] += m[11] * mu */ - "LDR r12, [%[m], #44]\n\t" - "LDR r11, [%[a], #44]\n\t" + "LDR r12, [r1, #44]\n\t" + "LDR r11, [r0, #44]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #44]\n\t" + "STR r11, [r0, #44]\n\t" /* a[i+12] += m[12] * mu */ - "LDR r12, [%[m], #48]\n\t" - "LDR r11, [%[a], #48]\n\t" + "LDR r12, [r1, #48]\n\t" + "LDR r11, [r0, #48]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #48]\n\t" + "STR r11, [r0, #48]\n\t" /* a[i+13] += m[13] * mu */ - "LDR r12, [%[m], #52]\n\t" - "LDR r11, [%[a], #52]\n\t" + "LDR r12, [r1, #52]\n\t" + "LDR r11, [r0, #52]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #52]\n\t" + "STR r11, [r0, #52]\n\t" /* a[i+14] += m[14] * mu */ - "LDR r12, [%[m], #56]\n\t" - "LDR r11, [%[a], #56]\n\t" + "LDR r12, [r1, #56]\n\t" + "LDR r11, [r0, #56]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #56]\n\t" + "STR r11, [r0, #56]\n\t" /* a[i+15] += m[15] * mu */ - "LDR r12, [%[m], #60]\n\t" - "LDR r11, [%[a], #60]\n\t" + "LDR r12, [r1, #60]\n\t" + "LDR r11, [r0, #60]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #60]\n\t" + "STR r11, [r0, #60]\n\t" /* a[i+16] += m[16] * mu */ - "LDR r12, [%[m], #64]\n\t" - "LDR r11, [%[a], #64]\n\t" + "LDR r12, [r1, #64]\n\t" + "LDR r11, [r0, #64]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #64]\n\t" + "STR r11, [r0, #64]\n\t" /* a[i+17] += m[17] * mu */ - "LDR r12, [%[m], #68]\n\t" - "LDR r11, [%[a], #68]\n\t" + "LDR r12, [r1, #68]\n\t" + "LDR r11, [r0, #68]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #68]\n\t" + "STR r11, [r0, #68]\n\t" /* a[i+18] += m[18] * mu */ - "LDR r12, [%[m], #72]\n\t" - "LDR r11, [%[a], #72]\n\t" + "LDR r12, [r1, #72]\n\t" + "LDR r11, [r0, #72]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #72]\n\t" + "STR r11, [r0, #72]\n\t" /* a[i+19] += m[19] * mu */ - "LDR r12, [%[m], #76]\n\t" - "LDR r11, [%[a], #76]\n\t" + "LDR r12, [r1, #76]\n\t" + "LDR r11, [r0, #76]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #76]\n\t" + "STR r11, [r0, #76]\n\t" /* a[i+20] += m[20] * mu */ - "LDR r12, [%[m], #80]\n\t" - "LDR r11, [%[a], #80]\n\t" + "LDR r12, [r1, #80]\n\t" + "LDR r11, [r0, #80]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #80]\n\t" + "STR r11, [r0, #80]\n\t" /* a[i+21] += m[21] * mu */ - "LDR r12, [%[m], #84]\n\t" - "LDR r11, [%[a], #84]\n\t" + "LDR r12, [r1, #84]\n\t" + "LDR r11, [r0, #84]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #84]\n\t" + "STR r11, [r0, #84]\n\t" /* a[i+22] += m[22] * mu */ - "LDR r12, [%[m], #88]\n\t" - "LDR r11, [%[a], #88]\n\t" + "LDR r12, [r1, #88]\n\t" + "LDR r11, [r0, #88]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #88]\n\t" + "STR r11, [r0, #88]\n\t" /* a[i+23] += m[23] * mu */ - "LDR r12, [%[m], #92]\n\t" - "LDR r11, [%[a], #92]\n\t" + "LDR r12, [r1, #92]\n\t" + "LDR r11, [r0, #92]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #92]\n\t" + "STR r11, [r0, #92]\n\t" /* a[i+24] += m[24] * mu */ - "LDR r12, [%[m], #96]\n\t" - "LDR r11, [%[a], #96]\n\t" + "LDR r12, [r1, #96]\n\t" + "LDR r11, [r0, #96]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #96]\n\t" + "STR r11, [r0, #96]\n\t" /* a[i+25] += m[25] * mu */ - "LDR r12, [%[m], #100]\n\t" - "LDR r11, [%[a], #100]\n\t" + "LDR r12, [r1, #100]\n\t" + "LDR r11, [r0, #100]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #100]\n\t" + "STR r11, [r0, #100]\n\t" /* a[i+26] += m[26] * mu */ - "LDR r12, [%[m], #104]\n\t" - "LDR r11, [%[a], #104]\n\t" + "LDR r12, [r1, #104]\n\t" + "LDR r11, [r0, #104]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #104]\n\t" + "STR r11, [r0, #104]\n\t" /* a[i+27] += m[27] * mu */ - "LDR r12, [%[m], #108]\n\t" - "LDR r11, [%[a], #108]\n\t" + "LDR r12, [r1, #108]\n\t" + "LDR r11, [r0, #108]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #108]\n\t" + "STR r11, [r0, #108]\n\t" /* a[i+28] += m[28] * mu */ - "LDR r12, [%[m], #112]\n\t" - "LDR r11, [%[a], #112]\n\t" + "LDR r12, [r1, #112]\n\t" + "LDR r11, [r0, #112]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #112]\n\t" + "STR r11, [r0, #112]\n\t" /* a[i+29] += m[29] * mu */ - "LDR r12, [%[m], #116]\n\t" - "LDR r11, [%[a], #116]\n\t" + "LDR r12, [r1, #116]\n\t" + "LDR r11, [r0, #116]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #116]\n\t" + "STR r11, [r0, #116]\n\t" /* a[i+30] += m[30] * mu */ - "LDR r12, [%[m], #120]\n\t" - "LDR r11, [%[a], #120]\n\t" + "LDR r12, [r1, #120]\n\t" + "LDR r11, [r0, #120]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #120]\n\t" + "STR r11, [r0, #120]\n\t" /* a[i+31] += m[31] * mu */ - "LDR r12, [%[m], #124]\n\t" - "LDR r11, [%[a], #124]\n\t" + "LDR r12, [r1, #124]\n\t" + "LDR r11, [r0, #124]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #124]\n\t" + "STR r11, [r0, #124]\n\t" /* a[i+32] += m[32] * mu */ - "LDR r12, [%[m], #128]\n\t" - "LDR r11, [%[a], #128]\n\t" + "LDR r12, [r1, #128]\n\t" + "LDR r11, [r0, #128]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #128]\n\t" + "STR r11, [r0, #128]\n\t" /* a[i+33] += m[33] * mu */ - "LDR r12, [%[m], #132]\n\t" - "LDR r11, [%[a], #132]\n\t" + "LDR r12, [r1, #132]\n\t" + "LDR r11, [r0, #132]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #132]\n\t" + "STR r11, [r0, #132]\n\t" /* a[i+34] += m[34] * mu */ - "LDR r12, [%[m], #136]\n\t" - "LDR r11, [%[a], #136]\n\t" + "LDR r12, [r1, #136]\n\t" + "LDR r11, [r0, #136]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #136]\n\t" + "STR r11, [r0, #136]\n\t" /* a[i+35] += m[35] * mu */ - "LDR r12, [%[m], #140]\n\t" - "LDR r11, [%[a], #140]\n\t" + "LDR r12, [r1, #140]\n\t" + "LDR r11, [r0, #140]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #140]\n\t" + "STR r11, [r0, #140]\n\t" /* a[i+36] += m[36] * mu */ - "LDR r12, [%[m], #144]\n\t" - "LDR r11, [%[a], #144]\n\t" + "LDR r12, [r1, #144]\n\t" + "LDR r11, [r0, #144]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #144]\n\t" + "STR r11, [r0, #144]\n\t" /* a[i+37] += m[37] * mu */ - "LDR r12, [%[m], #148]\n\t" - "LDR r11, [%[a], #148]\n\t" + "LDR r12, [r1, #148]\n\t" + "LDR r11, [r0, #148]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #148]\n\t" + "STR r11, [r0, #148]\n\t" /* a[i+38] += m[38] * mu */ - "LDR r12, [%[m], #152]\n\t" - "LDR r11, [%[a], #152]\n\t" + "LDR r12, [r1, #152]\n\t" + "LDR r11, [r0, #152]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #152]\n\t" + "STR r11, [r0, #152]\n\t" /* a[i+39] += m[39] * mu */ - "LDR r12, [%[m], #156]\n\t" - "LDR r11, [%[a], #156]\n\t" + "LDR r12, [r1, #156]\n\t" + "LDR r11, [r0, #156]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #156]\n\t" + "STR r11, [r0, #156]\n\t" /* a[i+40] += m[40] * mu */ - "LDR r12, [%[m], #160]\n\t" - "LDR r11, [%[a], #160]\n\t" + "LDR r12, [r1, #160]\n\t" + "LDR r11, [r0, #160]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #160]\n\t" + "STR r11, [r0, #160]\n\t" /* a[i+41] += m[41] * mu */ - "LDR r12, [%[m], #164]\n\t" - "LDR r11, [%[a], #164]\n\t" + "LDR r12, [r1, #164]\n\t" + "LDR r11, [r0, #164]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #164]\n\t" + "STR r11, [r0, #164]\n\t" /* a[i+42] += m[42] * mu */ - "LDR r12, [%[m], #168]\n\t" - "LDR r11, [%[a], #168]\n\t" + "LDR r12, [r1, #168]\n\t" + "LDR r11, [r0, #168]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #168]\n\t" + "STR r11, [r0, #168]\n\t" /* a[i+43] += m[43] * mu */ - "LDR r12, [%[m], #172]\n\t" - "LDR r11, [%[a], #172]\n\t" + "LDR r12, [r1, #172]\n\t" + "LDR r11, [r0, #172]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #172]\n\t" + "STR r11, [r0, #172]\n\t" /* a[i+44] += m[44] * mu */ - "LDR r12, [%[m], #176]\n\t" - "LDR r11, [%[a], #176]\n\t" + "LDR r12, [r1, #176]\n\t" + "LDR r11, [r0, #176]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #176]\n\t" + "STR r11, [r0, #176]\n\t" /* a[i+45] += m[45] * mu */ - "LDR r12, [%[m], #180]\n\t" - "LDR r11, [%[a], #180]\n\t" + "LDR r12, [r1, #180]\n\t" + "LDR r11, [r0, #180]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #180]\n\t" + "STR r11, [r0, #180]\n\t" /* a[i+46] += m[46] * mu */ - "LDR r12, [%[m], #184]\n\t" - "LDR r11, [%[a], #184]\n\t" + "LDR r12, [r1, #184]\n\t" + "LDR r11, [r0, #184]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #184]\n\t" + "STR r11, [r0, #184]\n\t" /* a[i+47] += m[47] * mu */ - "LDR r12, [%[m], #188]\n\t" - "LDR r11, [%[a], #188]\n\t" + "LDR r12, [r1, #188]\n\t" + "LDR r11, [r0, #188]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #188]\n\t" + "STR r11, [r0, #188]\n\t" /* a[i+48] += m[48] * mu */ - "LDR r12, [%[m], #192]\n\t" - "LDR r11, [%[a], #192]\n\t" + "LDR r12, [r1, #192]\n\t" + "LDR r11, [r0, #192]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #192]\n\t" + "STR r11, [r0, #192]\n\t" /* a[i+49] += m[49] * mu */ - "LDR r12, [%[m], #196]\n\t" - "LDR r11, [%[a], #196]\n\t" + "LDR r12, [r1, #196]\n\t" + "LDR r11, [r0, #196]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #196]\n\t" + "STR r11, [r0, #196]\n\t" /* a[i+50] += m[50] * mu */ - "LDR r12, [%[m], #200]\n\t" - "LDR r11, [%[a], #200]\n\t" + "LDR r12, [r1, #200]\n\t" + "LDR r11, [r0, #200]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #200]\n\t" + "STR r11, [r0, #200]\n\t" /* a[i+51] += m[51] * mu */ - "LDR r12, [%[m], #204]\n\t" - "LDR r11, [%[a], #204]\n\t" + "LDR r12, [r1, #204]\n\t" + "LDR r11, [r0, #204]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #204]\n\t" + "STR r11, [r0, #204]\n\t" /* a[i+52] += m[52] * mu */ - "LDR r12, [%[m], #208]\n\t" - "LDR r11, [%[a], #208]\n\t" + "LDR r12, [r1, #208]\n\t" + "LDR r11, [r0, #208]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #208]\n\t" + "STR r11, [r0, #208]\n\t" /* a[i+53] += m[53] * mu */ - "LDR r12, [%[m], #212]\n\t" - "LDR r11, [%[a], #212]\n\t" + "LDR r12, [r1, #212]\n\t" + "LDR r11, [r0, #212]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #212]\n\t" + "STR r11, [r0, #212]\n\t" /* a[i+54] += m[54] * mu */ - "LDR r12, [%[m], #216]\n\t" - "LDR r11, [%[a], #216]\n\t" + "LDR r12, [r1, #216]\n\t" + "LDR r11, [r0, #216]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #216]\n\t" + "STR r11, [r0, #216]\n\t" /* a[i+55] += m[55] * mu */ - "LDR r12, [%[m], #220]\n\t" - "LDR r11, [%[a], #220]\n\t" + "LDR r12, [r1, #220]\n\t" + "LDR r11, [r0, #220]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #220]\n\t" + "STR r11, [r0, #220]\n\t" /* a[i+56] += m[56] * mu */ - "LDR r12, [%[m], #224]\n\t" - "LDR r11, [%[a], #224]\n\t" + "LDR r12, [r1, #224]\n\t" + "LDR r11, [r0, #224]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #224]\n\t" + "STR r11, [r0, #224]\n\t" /* a[i+57] += m[57] * mu */ - "LDR r12, [%[m], #228]\n\t" - "LDR r11, [%[a], #228]\n\t" + "LDR r12, [r1, #228]\n\t" + "LDR r11, [r0, #228]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #228]\n\t" + "STR r11, [r0, #228]\n\t" /* a[i+58] += m[58] * mu */ - "LDR r12, [%[m], #232]\n\t" - "LDR r11, [%[a], #232]\n\t" + "LDR r12, [r1, #232]\n\t" + "LDR r11, [r0, #232]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #232]\n\t" + "STR r11, [r0, #232]\n\t" /* a[i+59] += m[59] * mu */ - "LDR r12, [%[m], #236]\n\t" - "LDR r11, [%[a], #236]\n\t" + "LDR r12, [r1, #236]\n\t" + "LDR r11, [r0, #236]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #236]\n\t" + "STR r11, [r0, #236]\n\t" /* a[i+60] += m[60] * mu */ - "LDR r12, [%[m], #240]\n\t" - "LDR r11, [%[a], #240]\n\t" + "LDR r12, [r1, #240]\n\t" + "LDR r11, [r0, #240]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #240]\n\t" + "STR r11, [r0, #240]\n\t" /* a[i+61] += m[61] * mu */ - "LDR r12, [%[m], #244]\n\t" - "LDR r11, [%[a], #244]\n\t" + "LDR r12, [r1, #244]\n\t" + "LDR r11, [r0, #244]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #244]\n\t" + "STR r11, [r0, #244]\n\t" /* a[i+62] += m[62] * mu */ - "LDR r12, [%[m], #248]\n\t" - "LDR r11, [%[a], #248]\n\t" + "LDR r12, [r1, #248]\n\t" + "LDR r11, [r0, #248]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #248]\n\t" + "STR r11, [r0, #248]\n\t" /* a[i+63] += m[63] * mu */ - "LDR r12, [%[m], #252]\n\t" - "LDR r11, [%[a], #252]\n\t" + "LDR r12, [r1, #252]\n\t" + "LDR r11, [r0, #252]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #252]\n\t" + "STR r11, [r0, #252]\n\t" /* a[i+64] += m[64] * mu */ - "LDR r12, [%[m], #256]\n\t" - "LDR r11, [%[a], #256]\n\t" + "LDR r12, [r1, #256]\n\t" + "LDR r11, [r0, #256]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #256]\n\t" + "STR r11, [r0, #256]\n\t" /* a[i+65] += m[65] * mu */ - "LDR r12, [%[m], #260]\n\t" - "LDR r11, [%[a], #260]\n\t" + "LDR r12, [r1, #260]\n\t" + "LDR r11, [r0, #260]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #260]\n\t" + "STR r11, [r0, #260]\n\t" /* a[i+66] += m[66] * mu */ - "LDR r12, [%[m], #264]\n\t" - "LDR r11, [%[a], #264]\n\t" + "LDR r12, [r1, #264]\n\t" + "LDR r11, [r0, #264]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #264]\n\t" + "STR r11, [r0, #264]\n\t" /* a[i+67] += m[67] * mu */ - "LDR r12, [%[m], #268]\n\t" - "LDR r11, [%[a], #268]\n\t" + "LDR r12, [r1, #268]\n\t" + "LDR r11, [r0, #268]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #268]\n\t" + "STR r11, [r0, #268]\n\t" /* a[i+68] += m[68] * mu */ - "LDR r12, [%[m], #272]\n\t" - "LDR r11, [%[a], #272]\n\t" + "LDR r12, [r1, #272]\n\t" + "LDR r11, [r0, #272]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #272]\n\t" + "STR r11, [r0, #272]\n\t" /* a[i+69] += m[69] * mu */ - "LDR r12, [%[m], #276]\n\t" - "LDR r11, [%[a], #276]\n\t" + "LDR r12, [r1, #276]\n\t" + "LDR r11, [r0, #276]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #276]\n\t" + "STR r11, [r0, #276]\n\t" /* a[i+70] += m[70] * mu */ - "LDR r12, [%[m], #280]\n\t" - "LDR r11, [%[a], #280]\n\t" + "LDR r12, [r1, #280]\n\t" + "LDR r11, [r0, #280]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #280]\n\t" + "STR r11, [r0, #280]\n\t" /* a[i+71] += m[71] * mu */ - "LDR r12, [%[m], #284]\n\t" - "LDR r11, [%[a], #284]\n\t" + "LDR r12, [r1, #284]\n\t" + "LDR r11, [r0, #284]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #284]\n\t" + "STR r11, [r0, #284]\n\t" /* a[i+72] += m[72] * mu */ - "LDR r12, [%[m], #288]\n\t" - "LDR r11, [%[a], #288]\n\t" + "LDR r12, [r1, #288]\n\t" + "LDR r11, [r0, #288]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #288]\n\t" + "STR r11, [r0, #288]\n\t" /* a[i+73] += m[73] * mu */ - "LDR r12, [%[m], #292]\n\t" - "LDR r11, [%[a], #292]\n\t" + "LDR r12, [r1, #292]\n\t" + "LDR r11, [r0, #292]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #292]\n\t" + "STR r11, [r0, #292]\n\t" /* a[i+74] += m[74] * mu */ - "LDR r12, [%[m], #296]\n\t" - "LDR r11, [%[a], #296]\n\t" + "LDR r12, [r1, #296]\n\t" + "LDR r11, [r0, #296]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #296]\n\t" + "STR r11, [r0, #296]\n\t" /* a[i+75] += m[75] * mu */ - "LDR r12, [%[m], #300]\n\t" - "LDR r11, [%[a], #300]\n\t" + "LDR r12, [r1, #300]\n\t" + "LDR r11, [r0, #300]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #300]\n\t" + "STR r11, [r0, #300]\n\t" /* a[i+76] += m[76] * mu */ - "LDR r12, [%[m], #304]\n\t" - "LDR r11, [%[a], #304]\n\t" + "LDR r12, [r1, #304]\n\t" + "LDR r11, [r0, #304]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #304]\n\t" + "STR r11, [r0, #304]\n\t" /* a[i+77] += m[77] * mu */ - "LDR r12, [%[m], #308]\n\t" - "LDR r11, [%[a], #308]\n\t" + "LDR r12, [r1, #308]\n\t" + "LDR r11, [r0, #308]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #308]\n\t" + "STR r11, [r0, #308]\n\t" /* a[i+78] += m[78] * mu */ - "LDR r12, [%[m], #312]\n\t" - "LDR r11, [%[a], #312]\n\t" + "LDR r12, [r1, #312]\n\t" + "LDR r11, [r0, #312]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #312]\n\t" + "STR r11, [r0, #312]\n\t" /* a[i+79] += m[79] * mu */ - "LDR r12, [%[m], #316]\n\t" - "LDR r11, [%[a], #316]\n\t" + "LDR r12, [r1, #316]\n\t" + "LDR r11, [r0, #316]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #316]\n\t" + "STR r11, [r0, #316]\n\t" /* a[i+80] += m[80] * mu */ - "LDR r12, [%[m], #320]\n\t" - "LDR r11, [%[a], #320]\n\t" + "LDR r12, [r1, #320]\n\t" + "LDR r11, [r0, #320]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #320]\n\t" + "STR r11, [r0, #320]\n\t" /* a[i+81] += m[81] * mu */ - "LDR r12, [%[m], #324]\n\t" - "LDR r11, [%[a], #324]\n\t" + "LDR r12, [r1, #324]\n\t" + "LDR r11, [r0, #324]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #324]\n\t" + "STR r11, [r0, #324]\n\t" /* a[i+82] += m[82] * mu */ - "LDR r12, [%[m], #328]\n\t" - "LDR r11, [%[a], #328]\n\t" + "LDR r12, [r1, #328]\n\t" + "LDR r11, [r0, #328]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #328]\n\t" + "STR r11, [r0, #328]\n\t" /* a[i+83] += m[83] * mu */ - "LDR r12, [%[m], #332]\n\t" - "LDR r11, [%[a], #332]\n\t" + "LDR r12, [r1, #332]\n\t" + "LDR r11, [r0, #332]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #332]\n\t" + "STR r11, [r0, #332]\n\t" /* a[i+84] += m[84] * mu */ - "LDR r12, [%[m], #336]\n\t" - "LDR r11, [%[a], #336]\n\t" + "LDR r12, [r1, #336]\n\t" + "LDR r11, [r0, #336]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #336]\n\t" + "STR r11, [r0, #336]\n\t" /* a[i+85] += m[85] * mu */ - "LDR r12, [%[m], #340]\n\t" - "LDR r11, [%[a], #340]\n\t" + "LDR r12, [r1, #340]\n\t" + "LDR r11, [r0, #340]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #340]\n\t" + "STR r11, [r0, #340]\n\t" /* a[i+86] += m[86] * mu */ - "LDR r12, [%[m], #344]\n\t" - "LDR r11, [%[a], #344]\n\t" + "LDR r12, [r1, #344]\n\t" + "LDR r11, [r0, #344]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #344]\n\t" + "STR r11, [r0, #344]\n\t" /* a[i+87] += m[87] * mu */ - "LDR r12, [%[m], #348]\n\t" - "LDR r11, [%[a], #348]\n\t" + "LDR r12, [r1, #348]\n\t" + "LDR r11, [r0, #348]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #348]\n\t" + "STR r11, [r0, #348]\n\t" /* a[i+88] += m[88] * mu */ - "LDR r12, [%[m], #352]\n\t" - "LDR r11, [%[a], #352]\n\t" + "LDR r12, [r1, #352]\n\t" + "LDR r11, [r0, #352]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #352]\n\t" + "STR r11, [r0, #352]\n\t" /* a[i+89] += m[89] * mu */ - "LDR r12, [%[m], #356]\n\t" - "LDR r11, [%[a], #356]\n\t" + "LDR r12, [r1, #356]\n\t" + "LDR r11, [r0, #356]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #356]\n\t" + "STR r11, [r0, #356]\n\t" /* a[i+90] += m[90] * mu */ - "LDR r12, [%[m], #360]\n\t" - "LDR r11, [%[a], #360]\n\t" + "LDR r12, [r1, #360]\n\t" + "LDR r11, [r0, #360]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #360]\n\t" + "STR r11, [r0, #360]\n\t" /* a[i+91] += m[91] * mu */ - "LDR r12, [%[m], #364]\n\t" - "LDR r11, [%[a], #364]\n\t" + "LDR r12, [r1, #364]\n\t" + "LDR r11, [r0, #364]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #364]\n\t" + "STR r11, [r0, #364]\n\t" /* a[i+92] += m[92] * mu */ - "LDR r12, [%[m], #368]\n\t" - "LDR r11, [%[a], #368]\n\t" + "LDR r12, [r1, #368]\n\t" + "LDR r11, [r0, #368]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #368]\n\t" + "STR r11, [r0, #368]\n\t" /* a[i+93] += m[93] * mu */ - "LDR r12, [%[m], #372]\n\t" - "LDR r11, [%[a], #372]\n\t" + "LDR r12, [r1, #372]\n\t" + "LDR r11, [r0, #372]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #372]\n\t" + "STR r11, [r0, #372]\n\t" /* a[i+94] += m[94] * mu */ - "LDR r12, [%[m], #376]\n\t" - "LDR r11, [%[a], #376]\n\t" + "LDR r12, [r1, #376]\n\t" + "LDR r11, [r0, #376]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #376]\n\t" + "STR r11, [r0, #376]\n\t" /* a[i+95] += m[95] * mu */ - "LDR r12, [%[m], #380]\n\t" - "LDR r11, [%[a], #380]\n\t" + "LDR r12, [r1, #380]\n\t" + "LDR r11, [r0, #380]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "LDR lr, [%[a], #384]\n\t" + "LDR lr, [r0, #384]\n\t" "MOV r12, #0\n\t" "UMAAL r3, lr, r12, r12\n\t" - "STR r11, [%[a], #380]\n\t" + "STR r11, [r0, #380]\n\t" "ADDS r3, r3, r5\n\t" "ADC r5, lr, #0\n\t" - "STR r3, [%[a], #384]\n\t" + "STR r3, [r0, #384]\n\t" /* i += 1 */ "ADD r4, r4, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r4, #0x180\n\t" #if defined(__GNUC__) "BLT L_sp_3072_mont_reduce_96_word_%=\n\t" @@ -19753,22 +21416,33 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( "BLT.W L_sp_3072_mont_reduce_96_word_%=\n\t" #endif /* Loop Done */ - "STR r6, [%[a]]\n\t" - "STR r7, [%[a], #4]\n\t" - "STR r8, [%[a], #8]\n\t" - "STR r9, [%[a], #12]\n\t" - "STR r10, [%[a], #16]\n\t" - "MOV %[mp], r5\n\t" + "STR r6, [r0]\n\t" + "STR r7, [r0, #4]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #12]\n\t" + "STR r10, [r0, #16]\n\t" + "MOV r2, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_3072_cond_sub_96(a - 96, a, m, (sp_digit)0 - mp); } @@ -19792,10 +21466,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r11, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r11, [r1]\n\t" /* i = 0 */ "MOV r9, #0\n\t" /* ca = 0 */ @@ -19807,8 +21490,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( "L_sp_3072_mont_reduce_96_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "LDR r10, [%[a]]\n\t" - "MUL r8, %[mp], r10\n\t" + "LDR r10, [r0]\n\t" + "MUL r8, r2, r10\n\t" /* j = 0 */ "MOV r12, #0\n\t" "MOV r4, #0\n\t" @@ -19819,31 +21502,31 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( "L_sp_3072_mont_reduce_96_mul_%=:\n\t" #endif /* a[i+j+0] += m[j+0] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+1] += m[j+1] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+2] += m[j+2] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+3] += m[j+3] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" "CMP r12, #0x180\n\t" @@ -19854,16 +21537,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( #else "BLT.N L_sp_3072_mont_reduce_96_mul_%=\n\t" #endif - "LDR r10, [%[a], #384]\n\t" + "LDR r10, [r0, #384]\n\t" "ADDS r4, r4, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" "ADDS r10, r10, r4\n\t" "ADC r3, r3, r3\n\t" - "STR r10, [%[a], #384]\n\t" + "STR r10, [r0, #384]\n\t" /* i += 1 */ "ADD r9, r9, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r9, #0x180\n\t" #if defined(__GNUC__) "BLT L_sp_3072_mont_reduce_96_word_%=\n\t" @@ -19873,17 +21556,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_3072_mont_reduce_96( "BLT.N L_sp_3072_mont_reduce_96_word_%=\n\t" #endif /* Loop Done */ - "MOV %[mp], r3\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_3072_cond_sub_96(a - 96, a, m, (sp_digit)0 - mp); } @@ -19938,11 +21632,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_96(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r11, #0\n\t" - "ADD r12, %[a], #0x180\n\t" + "ADD r12, r1, #0x180\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_3072_sub_96_word:\n\t" @@ -19950,15 +21652,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_96(sp_digit* r, "L_sp_3072_sub_96_word_%=:\n\t" #endif "RSBS r11, r11, #0\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "SBC r11, r3, r3\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_3072_sub_96_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -19966,17 +21668,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_96(sp_digit* r, #else "BNE.N L_sp_3072_sub_96_word_%=\n\t" #endif - "MOV %[r], r11\n\t" + "MOV r0, r11\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -19999,187 +21712,206 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_sub_96(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -20207,53 +21939,73 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_3072_word_96(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r8, %[div], #16\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r8, r2, #16\n\t" "ADD r5, r8, #1\n\t" - "UDIV r6, %[d1], r5\n\t" - "LSL r7, %[div], #16\n\t" + "UDIV r6, r0, r5\n\t" + "LSL r7, r2, #16\n\t" "LSL r6, r6, #16\n\t" - "UMULL r3, r4, %[div], r6\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "SUBS r3, %[d1], r5\n\t" + "UMULL r3, r4, r2, r6\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "SUBS r3, r0, r5\n\t" "SBC r9, r9, r9\n\t" "ADD r9, r9, #1\n\t" "RSB r10, r9, #0\n\t" "LSL r9, r9, #16\n\t" "AND r7, r7, r10\n\t" "AND r8, r8, r10\n\t" - "SUBS %[d0], %[d0], r7\n\t" + "SUBS r1, r1, r7\n\t" "ADD r6, r6, r9\n\t" - "SBC %[d1], %[d1], r8\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "SBC r0, r0, r8\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "UMULL r3, r4, %[div], r3\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "UMULL r3, r4, r2, r3\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "MUL r3, %[div], r3\n\t" - "SUB %[d0], %[d0], r3\n\t" - "UDIV r3, %[d0], %[div]\n\t" - "ADD %[d1], r6, r3\n\t" + "MUL r3, r2, r3\n\t" + "SUB r1, r1, r3\n\t" + "UDIV r3, r1, r2\n\t" + "ADD r0, r6, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -20280,13 +22032,22 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_3072_word_96(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r5, %[div], #1\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r5, r2, #1\n\t" "ADD r5, r5, #1\n\t" - "MOV r6, %[d0]\n\t" - "MOV r7, %[d1]\n\t" + "MOV r6, r1\n\t" + "MOV r7, r0\n\t" /* Do top 32 */ "SUBS r8, r5, r7\n\t" "SBC r8, r8, r8\n\t" @@ -20320,29 +22081,40 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_3072_word_96(sp_digit d1, #endif "ADD r3, r3, r3\n\t" "ADD r3, r3, #1\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "SUBS r8, r9, %[div]\n\t" - "ADC %[d1], r3, #0\n\t" + "SUBS r8, r9, r2\n\t" + "ADC r0, r3, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -20471,9 +22243,17 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0xffffffff\n\t" "MOV r8, #1\n\t" "MOV r7, #0\n\t" @@ -20486,8 +22266,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, #else "L_sp_3072_cmp_96_words_%=:\n\t" #endif - "LDR r4, [%[a], r6]\n\t" - "LDR r5, [%[b], r6]\n\t" + "LDR r4, [r0, r6]\n\t" + "LDR r5, [r1, r6]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20505,8 +22285,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, #endif "EOR r2, r2, r3\n\t" #else - "LDR r4, [%[a], #380]\n\t" - "LDR r5, [%[b], #380]\n\t" + "LDR r4, [r0, #380]\n\t" + "LDR r5, [r1, #380]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20516,8 +22296,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #376]\n\t" - "LDR r5, [%[b], #376]\n\t" + "LDR r4, [r0, #376]\n\t" + "LDR r5, [r1, #376]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20527,8 +22307,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #372]\n\t" - "LDR r5, [%[b], #372]\n\t" + "LDR r4, [r0, #372]\n\t" + "LDR r5, [r1, #372]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20538,8 +22318,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #368]\n\t" - "LDR r5, [%[b], #368]\n\t" + "LDR r4, [r0, #368]\n\t" + "LDR r5, [r1, #368]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20549,8 +22329,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #364]\n\t" - "LDR r5, [%[b], #364]\n\t" + "LDR r4, [r0, #364]\n\t" + "LDR r5, [r1, #364]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20560,8 +22340,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #360]\n\t" - "LDR r5, [%[b], #360]\n\t" + "LDR r4, [r0, #360]\n\t" + "LDR r5, [r1, #360]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20571,8 +22351,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #356]\n\t" - "LDR r5, [%[b], #356]\n\t" + "LDR r4, [r0, #356]\n\t" + "LDR r5, [r1, #356]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20582,8 +22362,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #352]\n\t" - "LDR r5, [%[b], #352]\n\t" + "LDR r4, [r0, #352]\n\t" + "LDR r5, [r1, #352]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20593,8 +22373,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #348]\n\t" - "LDR r5, [%[b], #348]\n\t" + "LDR r4, [r0, #348]\n\t" + "LDR r5, [r1, #348]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20604,8 +22384,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #344]\n\t" - "LDR r5, [%[b], #344]\n\t" + "LDR r4, [r0, #344]\n\t" + "LDR r5, [r1, #344]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20615,8 +22395,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #340]\n\t" - "LDR r5, [%[b], #340]\n\t" + "LDR r4, [r0, #340]\n\t" + "LDR r5, [r1, #340]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20626,8 +22406,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #336]\n\t" - "LDR r5, [%[b], #336]\n\t" + "LDR r4, [r0, #336]\n\t" + "LDR r5, [r1, #336]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20637,8 +22417,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #332]\n\t" - "LDR r5, [%[b], #332]\n\t" + "LDR r4, [r0, #332]\n\t" + "LDR r5, [r1, #332]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20648,8 +22428,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #328]\n\t" - "LDR r5, [%[b], #328]\n\t" + "LDR r4, [r0, #328]\n\t" + "LDR r5, [r1, #328]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20659,8 +22439,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #324]\n\t" - "LDR r5, [%[b], #324]\n\t" + "LDR r4, [r0, #324]\n\t" + "LDR r5, [r1, #324]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20670,8 +22450,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #320]\n\t" - "LDR r5, [%[b], #320]\n\t" + "LDR r4, [r0, #320]\n\t" + "LDR r5, [r1, #320]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20681,8 +22461,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #316]\n\t" - "LDR r5, [%[b], #316]\n\t" + "LDR r4, [r0, #316]\n\t" + "LDR r5, [r1, #316]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20692,8 +22472,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #312]\n\t" - "LDR r5, [%[b], #312]\n\t" + "LDR r4, [r0, #312]\n\t" + "LDR r5, [r1, #312]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20703,8 +22483,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #308]\n\t" - "LDR r5, [%[b], #308]\n\t" + "LDR r4, [r0, #308]\n\t" + "LDR r5, [r1, #308]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20714,8 +22494,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #304]\n\t" - "LDR r5, [%[b], #304]\n\t" + "LDR r4, [r0, #304]\n\t" + "LDR r5, [r1, #304]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20725,8 +22505,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #300]\n\t" - "LDR r5, [%[b], #300]\n\t" + "LDR r4, [r0, #300]\n\t" + "LDR r5, [r1, #300]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20736,8 +22516,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #296]\n\t" - "LDR r5, [%[b], #296]\n\t" + "LDR r4, [r0, #296]\n\t" + "LDR r5, [r1, #296]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20747,8 +22527,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #292]\n\t" - "LDR r5, [%[b], #292]\n\t" + "LDR r4, [r0, #292]\n\t" + "LDR r5, [r1, #292]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20758,8 +22538,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #288]\n\t" - "LDR r5, [%[b], #288]\n\t" + "LDR r4, [r0, #288]\n\t" + "LDR r5, [r1, #288]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20769,8 +22549,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #284]\n\t" - "LDR r5, [%[b], #284]\n\t" + "LDR r4, [r0, #284]\n\t" + "LDR r5, [r1, #284]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20780,8 +22560,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #280]\n\t" - "LDR r5, [%[b], #280]\n\t" + "LDR r4, [r0, #280]\n\t" + "LDR r5, [r1, #280]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20791,8 +22571,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #276]\n\t" - "LDR r5, [%[b], #276]\n\t" + "LDR r4, [r0, #276]\n\t" + "LDR r5, [r1, #276]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20802,8 +22582,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #272]\n\t" - "LDR r5, [%[b], #272]\n\t" + "LDR r4, [r0, #272]\n\t" + "LDR r5, [r1, #272]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20813,8 +22593,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #268]\n\t" - "LDR r5, [%[b], #268]\n\t" + "LDR r4, [r0, #268]\n\t" + "LDR r5, [r1, #268]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20824,8 +22604,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #264]\n\t" - "LDR r5, [%[b], #264]\n\t" + "LDR r4, [r0, #264]\n\t" + "LDR r5, [r1, #264]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20835,8 +22615,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #260]\n\t" - "LDR r5, [%[b], #260]\n\t" + "LDR r4, [r0, #260]\n\t" + "LDR r5, [r1, #260]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20846,8 +22626,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #256]\n\t" - "LDR r5, [%[b], #256]\n\t" + "LDR r4, [r0, #256]\n\t" + "LDR r5, [r1, #256]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20857,8 +22637,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #252]\n\t" - "LDR r5, [%[b], #252]\n\t" + "LDR r4, [r0, #252]\n\t" + "LDR r5, [r1, #252]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20868,8 +22648,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #248]\n\t" - "LDR r5, [%[b], #248]\n\t" + "LDR r4, [r0, #248]\n\t" + "LDR r5, [r1, #248]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20879,8 +22659,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #244]\n\t" - "LDR r5, [%[b], #244]\n\t" + "LDR r4, [r0, #244]\n\t" + "LDR r5, [r1, #244]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20890,8 +22670,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #240]\n\t" - "LDR r5, [%[b], #240]\n\t" + "LDR r4, [r0, #240]\n\t" + "LDR r5, [r1, #240]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20901,8 +22681,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #236]\n\t" - "LDR r5, [%[b], #236]\n\t" + "LDR r4, [r0, #236]\n\t" + "LDR r5, [r1, #236]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20912,8 +22692,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #232]\n\t" - "LDR r5, [%[b], #232]\n\t" + "LDR r4, [r0, #232]\n\t" + "LDR r5, [r1, #232]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20923,8 +22703,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #228]\n\t" - "LDR r5, [%[b], #228]\n\t" + "LDR r4, [r0, #228]\n\t" + "LDR r5, [r1, #228]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20934,8 +22714,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #224]\n\t" - "LDR r5, [%[b], #224]\n\t" + "LDR r4, [r0, #224]\n\t" + "LDR r5, [r1, #224]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20945,8 +22725,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #220]\n\t" - "LDR r5, [%[b], #220]\n\t" + "LDR r4, [r0, #220]\n\t" + "LDR r5, [r1, #220]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20956,8 +22736,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #216]\n\t" - "LDR r5, [%[b], #216]\n\t" + "LDR r4, [r0, #216]\n\t" + "LDR r5, [r1, #216]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20967,8 +22747,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #212]\n\t" - "LDR r5, [%[b], #212]\n\t" + "LDR r4, [r0, #212]\n\t" + "LDR r5, [r1, #212]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20978,8 +22758,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #208]\n\t" - "LDR r5, [%[b], #208]\n\t" + "LDR r4, [r0, #208]\n\t" + "LDR r5, [r1, #208]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -20989,8 +22769,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #204]\n\t" - "LDR r5, [%[b], #204]\n\t" + "LDR r4, [r0, #204]\n\t" + "LDR r5, [r1, #204]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21000,8 +22780,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #200]\n\t" - "LDR r5, [%[b], #200]\n\t" + "LDR r4, [r0, #200]\n\t" + "LDR r5, [r1, #200]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21011,8 +22791,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #196]\n\t" - "LDR r5, [%[b], #196]\n\t" + "LDR r4, [r0, #196]\n\t" + "LDR r5, [r1, #196]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21022,8 +22802,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #192]\n\t" - "LDR r5, [%[b], #192]\n\t" + "LDR r4, [r0, #192]\n\t" + "LDR r5, [r1, #192]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21033,8 +22813,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #188]\n\t" - "LDR r5, [%[b], #188]\n\t" + "LDR r4, [r0, #188]\n\t" + "LDR r5, [r1, #188]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21044,8 +22824,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #184]\n\t" - "LDR r5, [%[b], #184]\n\t" + "LDR r4, [r0, #184]\n\t" + "LDR r5, [r1, #184]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21055,8 +22835,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #180]\n\t" - "LDR r5, [%[b], #180]\n\t" + "LDR r4, [r0, #180]\n\t" + "LDR r5, [r1, #180]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21066,8 +22846,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #176]\n\t" - "LDR r5, [%[b], #176]\n\t" + "LDR r4, [r0, #176]\n\t" + "LDR r5, [r1, #176]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21077,8 +22857,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #172]\n\t" - "LDR r5, [%[b], #172]\n\t" + "LDR r4, [r0, #172]\n\t" + "LDR r5, [r1, #172]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21088,8 +22868,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #168]\n\t" - "LDR r5, [%[b], #168]\n\t" + "LDR r4, [r0, #168]\n\t" + "LDR r5, [r1, #168]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21099,8 +22879,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #164]\n\t" - "LDR r5, [%[b], #164]\n\t" + "LDR r4, [r0, #164]\n\t" + "LDR r5, [r1, #164]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21110,8 +22890,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #160]\n\t" - "LDR r5, [%[b], #160]\n\t" + "LDR r4, [r0, #160]\n\t" + "LDR r5, [r1, #160]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21121,8 +22901,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #156]\n\t" - "LDR r5, [%[b], #156]\n\t" + "LDR r4, [r0, #156]\n\t" + "LDR r5, [r1, #156]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21132,8 +22912,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #152]\n\t" - "LDR r5, [%[b], #152]\n\t" + "LDR r4, [r0, #152]\n\t" + "LDR r5, [r1, #152]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21143,8 +22923,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #148]\n\t" - "LDR r5, [%[b], #148]\n\t" + "LDR r4, [r0, #148]\n\t" + "LDR r5, [r1, #148]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21154,8 +22934,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #144]\n\t" - "LDR r5, [%[b], #144]\n\t" + "LDR r4, [r0, #144]\n\t" + "LDR r5, [r1, #144]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21165,8 +22945,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #140]\n\t" - "LDR r5, [%[b], #140]\n\t" + "LDR r4, [r0, #140]\n\t" + "LDR r5, [r1, #140]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21176,8 +22956,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #136]\n\t" - "LDR r5, [%[b], #136]\n\t" + "LDR r4, [r0, #136]\n\t" + "LDR r5, [r1, #136]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21187,8 +22967,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #132]\n\t" - "LDR r5, [%[b], #132]\n\t" + "LDR r4, [r0, #132]\n\t" + "LDR r5, [r1, #132]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21198,8 +22978,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #128]\n\t" - "LDR r5, [%[b], #128]\n\t" + "LDR r4, [r0, #128]\n\t" + "LDR r5, [r1, #128]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21209,8 +22989,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #124]\n\t" - "LDR r5, [%[b], #124]\n\t" + "LDR r4, [r0, #124]\n\t" + "LDR r5, [r1, #124]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21220,8 +23000,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #120]\n\t" - "LDR r5, [%[b], #120]\n\t" + "LDR r4, [r0, #120]\n\t" + "LDR r5, [r1, #120]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21231,8 +23011,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #116]\n\t" - "LDR r5, [%[b], #116]\n\t" + "LDR r4, [r0, #116]\n\t" + "LDR r5, [r1, #116]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21242,8 +23022,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #112]\n\t" - "LDR r5, [%[b], #112]\n\t" + "LDR r4, [r0, #112]\n\t" + "LDR r5, [r1, #112]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21253,8 +23033,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #108]\n\t" - "LDR r5, [%[b], #108]\n\t" + "LDR r4, [r0, #108]\n\t" + "LDR r5, [r1, #108]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21264,8 +23044,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #104]\n\t" - "LDR r5, [%[b], #104]\n\t" + "LDR r4, [r0, #104]\n\t" + "LDR r5, [r1, #104]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21275,8 +23055,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #100]\n\t" - "LDR r5, [%[b], #100]\n\t" + "LDR r4, [r0, #100]\n\t" + "LDR r5, [r1, #100]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21286,8 +23066,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #96]\n\t" - "LDR r5, [%[b], #96]\n\t" + "LDR r4, [r0, #96]\n\t" + "LDR r5, [r1, #96]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21297,8 +23077,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #92]\n\t" - "LDR r5, [%[b], #92]\n\t" + "LDR r4, [r0, #92]\n\t" + "LDR r5, [r1, #92]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21308,8 +23088,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #88]\n\t" - "LDR r5, [%[b], #88]\n\t" + "LDR r4, [r0, #88]\n\t" + "LDR r5, [r1, #88]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21319,8 +23099,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #84]\n\t" - "LDR r5, [%[b], #84]\n\t" + "LDR r4, [r0, #84]\n\t" + "LDR r5, [r1, #84]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21330,8 +23110,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #80]\n\t" - "LDR r5, [%[b], #80]\n\t" + "LDR r4, [r0, #80]\n\t" + "LDR r5, [r1, #80]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21341,8 +23121,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #76]\n\t" - "LDR r5, [%[b], #76]\n\t" + "LDR r4, [r0, #76]\n\t" + "LDR r5, [r1, #76]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21352,8 +23132,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #72]\n\t" - "LDR r5, [%[b], #72]\n\t" + "LDR r4, [r0, #72]\n\t" + "LDR r5, [r1, #72]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21363,8 +23143,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #68]\n\t" - "LDR r5, [%[b], #68]\n\t" + "LDR r4, [r0, #68]\n\t" + "LDR r5, [r1, #68]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21374,8 +23154,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #64]\n\t" - "LDR r5, [%[b], #64]\n\t" + "LDR r4, [r0, #64]\n\t" + "LDR r5, [r1, #64]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21385,8 +23165,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #60]\n\t" - "LDR r5, [%[b], #60]\n\t" + "LDR r4, [r0, #60]\n\t" + "LDR r5, [r1, #60]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21396,8 +23176,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #56]\n\t" - "LDR r5, [%[b], #56]\n\t" + "LDR r4, [r0, #56]\n\t" + "LDR r5, [r1, #56]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21407,8 +23187,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #52]\n\t" - "LDR r5, [%[b], #52]\n\t" + "LDR r4, [r0, #52]\n\t" + "LDR r5, [r1, #52]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21418,8 +23198,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #48]\n\t" - "LDR r5, [%[b], #48]\n\t" + "LDR r4, [r0, #48]\n\t" + "LDR r5, [r1, #48]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21429,8 +23209,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #44]\n\t" - "LDR r5, [%[b], #44]\n\t" + "LDR r4, [r0, #44]\n\t" + "LDR r5, [r1, #44]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21440,8 +23220,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #40]\n\t" - "LDR r5, [%[b], #40]\n\t" + "LDR r4, [r0, #40]\n\t" + "LDR r5, [r1, #40]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21451,8 +23231,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #36]\n\t" - "LDR r5, [%[b], #36]\n\t" + "LDR r4, [r0, #36]\n\t" + "LDR r5, [r1, #36]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21462,8 +23242,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #32]\n\t" - "LDR r5, [%[b], #32]\n\t" + "LDR r4, [r0, #32]\n\t" + "LDR r5, [r1, #32]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21473,8 +23253,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #28]\n\t" - "LDR r5, [%[b], #28]\n\t" + "LDR r4, [r0, #28]\n\t" + "LDR r5, [r1, #28]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21484,8 +23264,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #24]\n\t" - "LDR r5, [%[b], #24]\n\t" + "LDR r4, [r0, #24]\n\t" + "LDR r5, [r1, #24]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21495,8 +23275,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #20]\n\t" - "LDR r5, [%[b], #20]\n\t" + "LDR r4, [r0, #20]\n\t" + "LDR r5, [r1, #20]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21506,8 +23286,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #16]\n\t" - "LDR r5, [%[b], #16]\n\t" + "LDR r4, [r0, #16]\n\t" + "LDR r5, [r1, #16]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21517,8 +23297,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #12]\n\t" - "LDR r5, [%[b], #12]\n\t" + "LDR r4, [r0, #12]\n\t" + "LDR r5, [r1, #12]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21528,8 +23308,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #8]\n\t" - "LDR r5, [%[b], #8]\n\t" + "LDR r4, [r0, #8]\n\t" + "LDR r5, [r1, #8]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21539,8 +23319,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #4]\n\t" - "LDR r5, [%[b], #4]\n\t" + "LDR r4, [r0, #4]\n\t" + "LDR r5, [r1, #4]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21550,8 +23330,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[b]]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r1]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -21563,16 +23343,26 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_3072_cmp_96(const sp_digit* a, "movne r3, r7\n\t" "EOR r2, r2, r3\n\t" #endif /*WOLFSSL_SP_SMALL */ - "MOV %[a], r2\n\t" + "MOV r0, r2\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -22086,9 +23876,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_add_48(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" "MOV r8, #0\n\t" "MOV r4, #0\n\t" @@ -22099,12 +23898,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_add_48(sp_digit* r, "L_sp_3072_cond_add_48_words_%=:\n\t" #endif "ADDS r5, r5, #0xffffffff\n\t" - "LDR r6, [%[a], r4]\n\t" - "LDR r7, [%[b], r4]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r4]\n\t" + "LDR r7, [r2, r4]\n\t" + "AND r7, r7, r3\n\t" "ADCS r6, r6, r7\n\t" "ADC r5, r8, r8\n\t" - "STR r6, [%[r], r4]\n\t" + "STR r6, [r0, r4]\n\t" "ADD r4, r4, #4\n\t" "CMP r4, #0xc0\n\t" #if defined(__GNUC__) @@ -22114,16 +23913,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_add_48(sp_digit* r, #else "BLT.N L_sp_3072_cond_add_48_words_%=\n\t" #endif - "MOV %[r], r5\n\t" + "MOV r0, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -22150,188 +23961,209 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_3072_cond_add_48(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADDS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "ADC %[r], r10, r10\n\t" + "STM r0!, {r6, r7}\n\t" + "ADC r0, r10, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -22633,595 +24465,614 @@ WC_OMIT_FRAME_POINTER static void sp_3072_lshift_96(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register byte n __asm__ ("r2") = (byte)n_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)n + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "RSB r7, %[n], #31\n\t" - "LDR r5, [%[a], #380]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "RSB r7, r2, #31\n\t" + "LDR r5, [r1, #380]\n\t" "LSR r6, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r6, r6, r7\n\t" - "LDR r4, [%[a], #376]\n\t" - "STR r6, [%[r], #384]\n\t" + "LDR r4, [r1, #376]\n\t" + "STR r6, [r0, #384]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #372]\n\t" - "STR r5, [%[r], #380]\n\t" + "LDR r6, [r1, #372]\n\t" + "STR r5, [r0, #380]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #368]\n\t" - "STR r4, [%[r], #376]\n\t" + "LDR r5, [r1, #368]\n\t" + "STR r4, [r0, #376]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #364]\n\t" - "STR r6, [%[r], #372]\n\t" + "LDR r4, [r1, #364]\n\t" + "STR r6, [r0, #372]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #360]\n\t" - "STR r5, [%[r], #368]\n\t" + "LDR r6, [r1, #360]\n\t" + "STR r5, [r0, #368]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #356]\n\t" - "STR r4, [%[r], #364]\n\t" + "LDR r5, [r1, #356]\n\t" + "STR r4, [r0, #364]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #352]\n\t" - "STR r6, [%[r], #360]\n\t" + "LDR r4, [r1, #352]\n\t" + "STR r6, [r0, #360]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #348]\n\t" - "STR r5, [%[r], #356]\n\t" + "LDR r6, [r1, #348]\n\t" + "STR r5, [r0, #356]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #344]\n\t" - "STR r4, [%[r], #352]\n\t" + "LDR r5, [r1, #344]\n\t" + "STR r4, [r0, #352]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #340]\n\t" - "STR r6, [%[r], #348]\n\t" + "LDR r4, [r1, #340]\n\t" + "STR r6, [r0, #348]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #336]\n\t" - "STR r5, [%[r], #344]\n\t" + "LDR r6, [r1, #336]\n\t" + "STR r5, [r0, #344]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #332]\n\t" - "STR r4, [%[r], #340]\n\t" + "LDR r5, [r1, #332]\n\t" + "STR r4, [r0, #340]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #328]\n\t" - "STR r6, [%[r], #336]\n\t" + "LDR r4, [r1, #328]\n\t" + "STR r6, [r0, #336]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #324]\n\t" - "STR r5, [%[r], #332]\n\t" + "LDR r6, [r1, #324]\n\t" + "STR r5, [r0, #332]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #320]\n\t" - "STR r4, [%[r], #328]\n\t" + "LDR r5, [r1, #320]\n\t" + "STR r4, [r0, #328]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #316]\n\t" - "STR r6, [%[r], #324]\n\t" + "LDR r4, [r1, #316]\n\t" + "STR r6, [r0, #324]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #312]\n\t" - "STR r5, [%[r], #320]\n\t" + "LDR r6, [r1, #312]\n\t" + "STR r5, [r0, #320]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #308]\n\t" - "STR r4, [%[r], #316]\n\t" + "LDR r5, [r1, #308]\n\t" + "STR r4, [r0, #316]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #304]\n\t" - "STR r6, [%[r], #312]\n\t" + "LDR r4, [r1, #304]\n\t" + "STR r6, [r0, #312]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #300]\n\t" - "STR r5, [%[r], #308]\n\t" + "LDR r6, [r1, #300]\n\t" + "STR r5, [r0, #308]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #296]\n\t" - "STR r4, [%[r], #304]\n\t" + "LDR r5, [r1, #296]\n\t" + "STR r4, [r0, #304]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #292]\n\t" - "STR r6, [%[r], #300]\n\t" + "LDR r4, [r1, #292]\n\t" + "STR r6, [r0, #300]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #288]\n\t" - "STR r5, [%[r], #296]\n\t" + "LDR r6, [r1, #288]\n\t" + "STR r5, [r0, #296]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #284]\n\t" - "STR r4, [%[r], #292]\n\t" + "LDR r5, [r1, #284]\n\t" + "STR r4, [r0, #292]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #280]\n\t" - "STR r6, [%[r], #288]\n\t" + "LDR r4, [r1, #280]\n\t" + "STR r6, [r0, #288]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #276]\n\t" - "STR r5, [%[r], #284]\n\t" + "LDR r6, [r1, #276]\n\t" + "STR r5, [r0, #284]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #272]\n\t" - "STR r4, [%[r], #280]\n\t" + "LDR r5, [r1, #272]\n\t" + "STR r4, [r0, #280]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #268]\n\t" - "STR r6, [%[r], #276]\n\t" + "LDR r4, [r1, #268]\n\t" + "STR r6, [r0, #276]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #264]\n\t" - "STR r5, [%[r], #272]\n\t" + "LDR r6, [r1, #264]\n\t" + "STR r5, [r0, #272]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #260]\n\t" - "STR r4, [%[r], #268]\n\t" + "LDR r5, [r1, #260]\n\t" + "STR r4, [r0, #268]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #256]\n\t" - "STR r6, [%[r], #264]\n\t" + "LDR r4, [r1, #256]\n\t" + "STR r6, [r0, #264]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #252]\n\t" - "STR r5, [%[r], #260]\n\t" + "LDR r6, [r1, #252]\n\t" + "STR r5, [r0, #260]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #248]\n\t" - "STR r4, [%[r], #256]\n\t" + "LDR r5, [r1, #248]\n\t" + "STR r4, [r0, #256]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #244]\n\t" - "STR r6, [%[r], #252]\n\t" + "LDR r4, [r1, #244]\n\t" + "STR r6, [r0, #252]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #240]\n\t" - "STR r5, [%[r], #248]\n\t" + "LDR r6, [r1, #240]\n\t" + "STR r5, [r0, #248]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #236]\n\t" - "STR r4, [%[r], #244]\n\t" + "LDR r5, [r1, #236]\n\t" + "STR r4, [r0, #244]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #232]\n\t" - "STR r6, [%[r], #240]\n\t" + "LDR r4, [r1, #232]\n\t" + "STR r6, [r0, #240]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #228]\n\t" - "STR r5, [%[r], #236]\n\t" + "LDR r6, [r1, #228]\n\t" + "STR r5, [r0, #236]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #224]\n\t" - "STR r4, [%[r], #232]\n\t" + "LDR r5, [r1, #224]\n\t" + "STR r4, [r0, #232]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #220]\n\t" - "STR r6, [%[r], #228]\n\t" + "LDR r4, [r1, #220]\n\t" + "STR r6, [r0, #228]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #216]\n\t" - "STR r5, [%[r], #224]\n\t" + "LDR r6, [r1, #216]\n\t" + "STR r5, [r0, #224]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #212]\n\t" - "STR r4, [%[r], #220]\n\t" + "LDR r5, [r1, #212]\n\t" + "STR r4, [r0, #220]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #208]\n\t" - "STR r6, [%[r], #216]\n\t" + "LDR r4, [r1, #208]\n\t" + "STR r6, [r0, #216]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #204]\n\t" - "STR r5, [%[r], #212]\n\t" + "LDR r6, [r1, #204]\n\t" + "STR r5, [r0, #212]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #200]\n\t" - "STR r4, [%[r], #208]\n\t" + "LDR r5, [r1, #200]\n\t" + "STR r4, [r0, #208]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #196]\n\t" - "STR r6, [%[r], #204]\n\t" + "LDR r4, [r1, #196]\n\t" + "STR r6, [r0, #204]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #192]\n\t" - "STR r5, [%[r], #200]\n\t" + "LDR r6, [r1, #192]\n\t" + "STR r5, [r0, #200]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #188]\n\t" - "STR r4, [%[r], #196]\n\t" + "LDR r5, [r1, #188]\n\t" + "STR r4, [r0, #196]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #184]\n\t" - "STR r6, [%[r], #192]\n\t" + "LDR r4, [r1, #184]\n\t" + "STR r6, [r0, #192]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #180]\n\t" - "STR r5, [%[r], #188]\n\t" + "LDR r6, [r1, #180]\n\t" + "STR r5, [r0, #188]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #176]\n\t" - "STR r4, [%[r], #184]\n\t" + "LDR r5, [r1, #176]\n\t" + "STR r4, [r0, #184]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #172]\n\t" - "STR r6, [%[r], #180]\n\t" + "LDR r4, [r1, #172]\n\t" + "STR r6, [r0, #180]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #168]\n\t" - "STR r5, [%[r], #176]\n\t" + "LDR r6, [r1, #168]\n\t" + "STR r5, [r0, #176]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #164]\n\t" - "STR r4, [%[r], #172]\n\t" + "LDR r5, [r1, #164]\n\t" + "STR r4, [r0, #172]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #160]\n\t" - "STR r6, [%[r], #168]\n\t" + "LDR r4, [r1, #160]\n\t" + "STR r6, [r0, #168]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #156]\n\t" - "STR r5, [%[r], #164]\n\t" + "LDR r6, [r1, #156]\n\t" + "STR r5, [r0, #164]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #152]\n\t" - "STR r4, [%[r], #160]\n\t" + "LDR r5, [r1, #152]\n\t" + "STR r4, [r0, #160]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #148]\n\t" - "STR r6, [%[r], #156]\n\t" + "LDR r4, [r1, #148]\n\t" + "STR r6, [r0, #156]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #144]\n\t" - "STR r5, [%[r], #152]\n\t" + "LDR r6, [r1, #144]\n\t" + "STR r5, [r0, #152]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #140]\n\t" - "STR r4, [%[r], #148]\n\t" + "LDR r5, [r1, #140]\n\t" + "STR r4, [r0, #148]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #136]\n\t" - "STR r6, [%[r], #144]\n\t" + "LDR r4, [r1, #136]\n\t" + "STR r6, [r0, #144]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #132]\n\t" - "STR r5, [%[r], #140]\n\t" + "LDR r6, [r1, #132]\n\t" + "STR r5, [r0, #140]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #128]\n\t" - "STR r4, [%[r], #136]\n\t" + "LDR r5, [r1, #128]\n\t" + "STR r4, [r0, #136]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #124]\n\t" - "STR r6, [%[r], #132]\n\t" + "LDR r4, [r1, #124]\n\t" + "STR r6, [r0, #132]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #120]\n\t" - "STR r5, [%[r], #128]\n\t" + "LDR r6, [r1, #120]\n\t" + "STR r5, [r0, #128]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #116]\n\t" - "STR r4, [%[r], #124]\n\t" + "LDR r5, [r1, #116]\n\t" + "STR r4, [r0, #124]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #112]\n\t" - "STR r6, [%[r], #120]\n\t" + "LDR r4, [r1, #112]\n\t" + "STR r6, [r0, #120]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #108]\n\t" - "STR r5, [%[r], #116]\n\t" + "LDR r6, [r1, #108]\n\t" + "STR r5, [r0, #116]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #104]\n\t" - "STR r4, [%[r], #112]\n\t" + "LDR r5, [r1, #104]\n\t" + "STR r4, [r0, #112]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #100]\n\t" - "STR r6, [%[r], #108]\n\t" + "LDR r4, [r1, #100]\n\t" + "STR r6, [r0, #108]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #96]\n\t" - "STR r5, [%[r], #104]\n\t" + "LDR r6, [r1, #96]\n\t" + "STR r5, [r0, #104]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #92]\n\t" - "STR r4, [%[r], #100]\n\t" + "LDR r5, [r1, #92]\n\t" + "STR r4, [r0, #100]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #88]\n\t" - "STR r6, [%[r], #96]\n\t" + "LDR r4, [r1, #88]\n\t" + "STR r6, [r0, #96]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #84]\n\t" - "STR r5, [%[r], #92]\n\t" + "LDR r6, [r1, #84]\n\t" + "STR r5, [r0, #92]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #80]\n\t" - "STR r4, [%[r], #88]\n\t" + "LDR r5, [r1, #80]\n\t" + "STR r4, [r0, #88]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #76]\n\t" - "STR r6, [%[r], #84]\n\t" + "LDR r4, [r1, #76]\n\t" + "STR r6, [r0, #84]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #72]\n\t" - "STR r5, [%[r], #80]\n\t" + "LDR r6, [r1, #72]\n\t" + "STR r5, [r0, #80]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #68]\n\t" - "STR r4, [%[r], #76]\n\t" + "LDR r5, [r1, #68]\n\t" + "STR r4, [r0, #76]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #64]\n\t" - "STR r6, [%[r], #72]\n\t" + "LDR r4, [r1, #64]\n\t" + "STR r6, [r0, #72]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #60]\n\t" - "STR r5, [%[r], #68]\n\t" + "LDR r6, [r1, #60]\n\t" + "STR r5, [r0, #68]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #56]\n\t" - "STR r4, [%[r], #64]\n\t" + "LDR r5, [r1, #56]\n\t" + "STR r4, [r0, #64]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #52]\n\t" - "STR r6, [%[r], #60]\n\t" + "LDR r4, [r1, #52]\n\t" + "STR r6, [r0, #60]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #48]\n\t" - "STR r5, [%[r], #56]\n\t" + "LDR r6, [r1, #48]\n\t" + "STR r5, [r0, #56]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #44]\n\t" - "STR r4, [%[r], #52]\n\t" + "LDR r5, [r1, #44]\n\t" + "STR r4, [r0, #52]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #40]\n\t" - "STR r6, [%[r], #48]\n\t" + "LDR r4, [r1, #40]\n\t" + "STR r6, [r0, #48]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #36]\n\t" - "STR r5, [%[r], #44]\n\t" + "LDR r6, [r1, #36]\n\t" + "STR r5, [r0, #44]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #32]\n\t" - "STR r4, [%[r], #40]\n\t" + "LDR r5, [r1, #32]\n\t" + "STR r4, [r0, #40]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #28]\n\t" - "STR r6, [%[r], #36]\n\t" + "LDR r4, [r1, #28]\n\t" + "STR r6, [r0, #36]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #24]\n\t" - "STR r5, [%[r], #32]\n\t" + "LDR r6, [r1, #24]\n\t" + "STR r5, [r0, #32]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #20]\n\t" - "STR r4, [%[r], #28]\n\t" + "LDR r5, [r1, #20]\n\t" + "STR r4, [r0, #28]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #16]\n\t" - "STR r6, [%[r], #24]\n\t" + "LDR r4, [r1, #16]\n\t" + "STR r6, [r0, #24]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #12]\n\t" - "STR r5, [%[r], #20]\n\t" + "LDR r6, [r1, #12]\n\t" + "STR r5, [r0, #20]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #8]\n\t" - "STR r4, [%[r], #16]\n\t" + "LDR r5, [r1, #8]\n\t" + "STR r4, [r0, #16]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #4]\n\t" - "STR r6, [%[r], #12]\n\t" + "LDR r4, [r1, #4]\n\t" + "STR r6, [r0, #12]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a]]\n\t" - "STR r5, [%[r], #8]\n\t" + "LDR r6, [r1]\n\t" + "STR r5, [r0, #8]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "STR r6, [%[r]]\n\t" - "STR r4, [%[r], #4]\n\t" + "STR r6, [r0]\n\t" + "STR r4, [r0, #4]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [n] "+r" (n) : + : "memory", "cc", "r4", "r5", "r6", "r3", "r7" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [n] "r" (n) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r3", "r7" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + n = (byte)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Modular exponentiate 2 to the e mod m. (r = 2^e mod m) @@ -23650,243 +25501,261 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_sub_in_place_128(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SUBS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "SBC %[a], r9, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "SBC r0, r9, r9\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -23908,244 +25777,263 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_add_128(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -24244,11 +26132,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_add_128(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r3, #0\n\t" - "ADD r12, %[a], #0x200\n\t" + "ADD r12, r1, #0x200\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_4096_add_128_word:\n\t" @@ -24256,16 +26152,16 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_add_128(sp_digit* r, "L_sp_4096_add_128_word_%=:\n\t" #endif "ADDS r3, r3, #0xffffffff\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "MOV r4, #0\n\t" "ADC r3, r4, #0\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_4096_add_128_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -24273,17 +26169,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_add_128(sp_digit* r, #else "BNE.N L_sp_4096_add_128_word_%=\n\t" #endif - "MOV %[r], r3\n\t" + "MOV r0, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -24305,11 +26212,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_sub_in_place_128(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "ADD r11, %[a], #0x200\n\t" + "ADD r11, r0, #0x200\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_4096_sub_in_place_128_word:\n\t" @@ -24317,15 +26232,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_sub_in_place_128(sp_digit* a, "L_sp_4096_sub_in_place_128_word_%=:\n\t" #endif "RSBS r10, r10, #0\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" "SBC r10, r10, r10\n\t" - "CMP %[a], r11\n\t" + "CMP r0, r11\n\t" #if defined(__GNUC__) "BNE L_sp_4096_sub_in_place_128_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -24333,17 +26248,27 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_sub_in_place_128(sp_digit* a, #else "BNE.N L_sp_4096_sub_in_place_128_word_%=\n\t" #endif - "MOV %[a], r10\n\t" + "MOV r0, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -24367,12 +26292,20 @@ WC_OMIT_FRAME_POINTER static void sp_4096_mul_128(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x400\n\t" - "LDR lr, [%[a]]\n\t" - "LDR r11, [%[b]]\n\t" + "LDR lr, [r1]\n\t" + "LDR r11, [r2]\n\t" "UMULL r8, r6, lr, r11\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -24394,14 +26327,14 @@ WC_OMIT_FRAME_POINTER static void sp_4096_mul_128(sp_digit* r, #else "L_sp_4096_mul_128_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" "ADC r8, r8, #0\n\t" - "LDR lr, [%[a], r4]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r4]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -24423,8 +26356,8 @@ WC_OMIT_FRAME_POINTER static void sp_4096_mul_128(sp_digit* r, #else "BLT.N L_sp_4096_mul_128_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -24448,8 +26381,8 @@ WC_OMIT_FRAME_POINTER static void sp_4096_mul_128(sp_digit* r, #else "BLE.N L_sp_4096_mul_128_outer_%=\n\t" #endif - "LDR lr, [%[a], #508]\n\t" - "LDR r11, [%[b], #508]\n\t" + "LDR lr, [r1, #508]\n\t" + "LDR r11, [r2, #508]\n\t" "UMLAL r6, r7, lr, r11\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -24461,7 +26394,7 @@ WC_OMIT_FRAME_POINTER static void sp_4096_mul_128(sp_digit* r, "L_sp_4096_mul_128_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_4096_mul_128_store_%=\n\t" @@ -24470,16 +26403,27 @@ WC_OMIT_FRAME_POINTER static void sp_4096_mul_128(sp_digit* r, #else "BGT.N L_sp_4096_mul_128_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Square a and put result in r. (r = a * a) @@ -24498,11 +26442,19 @@ WC_OMIT_FRAME_POINTER static void sp_4096_sqr_128(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x400\n\t" - "LDR lr, [%[a]]\n\t" + "LDR lr, [r1]\n\t" "UMULL r8, r6, lr, lr\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -24524,8 +26476,8 @@ WC_OMIT_FRAME_POINTER static void sp_4096_sqr_128(sp_digit* r, #else "L_sp_4096_sqr_128_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[a], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r1, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -24550,7 +26502,7 @@ WC_OMIT_FRAME_POINTER static void sp_4096_sqr_128(sp_digit* r, #else "BLT.N L_sp_4096_sqr_128_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" + "LDR lr, [r1, r3]\n\t" "UMULL r9, r10, lr, lr\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -24574,7 +26526,7 @@ WC_OMIT_FRAME_POINTER static void sp_4096_sqr_128(sp_digit* r, #else "BLE.N L_sp_4096_sqr_128_outer_%=\n\t" #endif - "LDR lr, [%[a], #508]\n\t" + "LDR lr, [r1, #508]\n\t" "UMLAL r6, r7, lr, lr\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -24586,7 +26538,7 @@ WC_OMIT_FRAME_POINTER static void sp_4096_sqr_128(sp_digit* r, "L_sp_4096_sqr_128_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_4096_sqr_128_store_%=\n\t" @@ -24595,16 +26547,26 @@ WC_OMIT_FRAME_POINTER static void sp_4096_sqr_128(sp_digit* r, #else "BGT.N L_sp_4096_sqr_128_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -24647,14 +26609,22 @@ WC_OMIT_FRAME_POINTER static void sp_4096_mul_d_128(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDR r8, [%[a]]\n\t" - "UMULL r5, r3, %[b], r8\n\t" + "LDR r8, [r1]\n\t" + "UMULL r5, r3, r2, r8\n\t" "MOV r4, #0\n\t" - "STR r5, [%[r]]\n\t" + "STR r5, [r0]\n\t" "MOV r5, #0\n\t" "MOV r9, #4\n\t" "\n" @@ -24664,12 +26634,12 @@ WC_OMIT_FRAME_POINTER static void sp_4096_mul_d_128(sp_digit* r, "L_sp_4096_mul_d_128_word_%=:\n\t" #endif /* A[i] * B */ - "LDR r8, [%[a], r9]\n\t" - "UMULL r6, r7, %[b], r8\n\t" + "LDR r8, [r1, r9]\n\t" + "UMULL r6, r7, r2, r8\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], r9]\n\t" + "STR r3, [r0, r9]\n\t" "MOV r3, r4\n\t" "MOV r4, r5\n\t" "MOV r5, #0\n\t" @@ -24682,16 +26652,27 @@ WC_OMIT_FRAME_POINTER static void sp_4096_mul_d_128(sp_digit* r, #else "BLT.N L_sp_4096_mul_d_128_word_%=\n\t" #endif - "STR r3, [%[r], #512]\n\t" + "STR r3, [r0, #512]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -24713,658 +26694,677 @@ WC_OMIT_FRAME_POINTER static void sp_4096_mul_d_128(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDM %[a]!, {r8}\n\t" - "UMULL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMULL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[1] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[2] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[3] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[4] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[5] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[6] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[7] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[8] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[9] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[10] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[11] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[12] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[13] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[14] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[15] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[16] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[17] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[18] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[19] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[20] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[21] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[22] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[23] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[24] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[25] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[26] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[27] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[28] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[29] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[30] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[31] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[32] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[33] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[34] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[35] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[36] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[37] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[38] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[39] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[40] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[41] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[42] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[43] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[44] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[45] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[46] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[47] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[48] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[49] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[50] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[51] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[52] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[53] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[54] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[55] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[56] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[57] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[58] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[59] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[60] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[61] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[62] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[63] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[64] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[65] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[66] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[67] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[68] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[69] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[70] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[71] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[72] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[73] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[74] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[75] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[76] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[77] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[78] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[79] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[80] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[81] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[82] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[83] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[84] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[85] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[86] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[87] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[88] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[89] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[90] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[91] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[92] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[93] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[94] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[95] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[96] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[97] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[98] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[99] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[100] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[101] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[102] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[103] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[104] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[105] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[106] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[107] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[108] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[109] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[110] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[111] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[112] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[113] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[114] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[115] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[116] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[117] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[118] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[119] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[120] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[121] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[122] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[123] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[124] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[125] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[126] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[127] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" - "STR r5, [%[r]]\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" + "STR r5, [r0]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -25407,9 +27407,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_cond_sub_128(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, #0\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -25420,12 +27429,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_cond_sub_128(sp_digit* r, "L_sp_4096_cond_sub_128_words_%=:\n\t" #endif "SUBS r4, r8, r4\n\t" - "LDR r6, [%[a], r5]\n\t" - "LDR r7, [%[b], r5]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r5]\n\t" + "LDR r7, [r2, r5]\n\t" + "AND r7, r7, r3\n\t" "SBCS r6, r6, r7\n\t" "SBC r4, r8, r8\n\t" - "STR r6, [%[r], r5]\n\t" + "STR r6, [r0, r5]\n\t" "ADD r5, r5, #4\n\t" "CMP r5, #0x200\n\t" #if defined(__GNUC__) @@ -25435,16 +27444,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_cond_sub_128(sp_digit* r, #else "BLT.N L_sp_4096_cond_sub_128_words_%=\n\t" #endif - "MOV %[r], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -25471,468 +27492,489 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_cond_sub_128(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SUBS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "SBC %[r], r5, r5\n\t" + "STM r0!, {r6, r7}\n\t" + "SBC r0, r5, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -25958,15 +28000,24 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR lr, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR lr, [r1]\n\t" /* i = 0 */ "MOV r11, #0\n\t" "MOV r3, #0\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[a], #4]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_4096_mont_reduce_128_word:\n\t" @@ -25974,1033 +28025,1033 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( "L_sp_4096_mont_reduce_128_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL r10, %[mp], r4\n\t" + "MUL r10, r2, r4\n\t" /* a[i+0] += m[0] * mu */ "MOV r7, #0\n\t" "UMLAL r4, r7, r10, lr\n\t" /* a[i+1] += m[1] * mu */ - "LDR r9, [%[m], #4]\n\t" + "LDR r9, [r1, #4]\n\t" "MOV r6, #0\n\t" "UMLAL r5, r6, r10, r9\n\t" "MOV r4, r5\n\t" "ADDS r4, r4, r7\n\t" "ADC r6, r6, #0\n\t" /* a[i+2] += m[2] * mu */ - "LDR r9, [%[m], #8]\n\t" - "LDR r5, [%[a], #8]\n\t" + "LDR r9, [r1, #8]\n\t" + "LDR r5, [r0, #8]\n\t" "MOV r7, #0\n\t" "UMLAL r5, r7, r10, r9\n\t" "ADDS r5, r5, r6\n\t" "ADC r7, r7, #0\n\t" /* a[i+3] += m[3] * mu */ - "LDR r9, [%[m], #12]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r9, [r1, #12]\n\t" + "LDR r12, [r0, #12]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #12]\n\t" + "STR r12, [r0, #12]\n\t" "ADC r6, r6, #0\n\t" /* a[i+4] += m[4] * mu */ - "LDR r9, [%[m], #16]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r9, [r1, #16]\n\t" + "LDR r12, [r0, #16]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #16]\n\t" + "STR r12, [r0, #16]\n\t" "ADC r7, r7, #0\n\t" /* a[i+5] += m[5] * mu */ - "LDR r9, [%[m], #20]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r12, [r0, #20]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #20]\n\t" + "STR r12, [r0, #20]\n\t" "ADC r6, r6, #0\n\t" /* a[i+6] += m[6] * mu */ - "LDR r9, [%[m], #24]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r9, [r1, #24]\n\t" + "LDR r12, [r0, #24]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #24]\n\t" + "STR r12, [r0, #24]\n\t" "ADC r7, r7, #0\n\t" /* a[i+7] += m[7] * mu */ - "LDR r9, [%[m], #28]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r9, [r1, #28]\n\t" + "LDR r12, [r0, #28]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #28]\n\t" + "STR r12, [r0, #28]\n\t" "ADC r6, r6, #0\n\t" /* a[i+8] += m[8] * mu */ - "LDR r9, [%[m], #32]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r9, [r1, #32]\n\t" + "LDR r12, [r0, #32]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #32]\n\t" + "STR r12, [r0, #32]\n\t" "ADC r7, r7, #0\n\t" /* a[i+9] += m[9] * mu */ - "LDR r9, [%[m], #36]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r9, [r1, #36]\n\t" + "LDR r12, [r0, #36]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #36]\n\t" + "STR r12, [r0, #36]\n\t" "ADC r6, r6, #0\n\t" /* a[i+10] += m[10] * mu */ - "LDR r9, [%[m], #40]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r9, [r1, #40]\n\t" + "LDR r12, [r0, #40]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #40]\n\t" + "STR r12, [r0, #40]\n\t" "ADC r7, r7, #0\n\t" /* a[i+11] += m[11] * mu */ - "LDR r9, [%[m], #44]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r9, [r1, #44]\n\t" + "LDR r12, [r0, #44]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #44]\n\t" + "STR r12, [r0, #44]\n\t" "ADC r6, r6, #0\n\t" /* a[i+12] += m[12] * mu */ - "LDR r9, [%[m], #48]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r9, [r1, #48]\n\t" + "LDR r12, [r0, #48]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #48]\n\t" + "STR r12, [r0, #48]\n\t" "ADC r7, r7, #0\n\t" /* a[i+13] += m[13] * mu */ - "LDR r9, [%[m], #52]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r9, [r1, #52]\n\t" + "LDR r12, [r0, #52]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #52]\n\t" + "STR r12, [r0, #52]\n\t" "ADC r6, r6, #0\n\t" /* a[i+14] += m[14] * mu */ - "LDR r9, [%[m], #56]\n\t" - "LDR r12, [%[a], #56]\n\t" + "LDR r9, [r1, #56]\n\t" + "LDR r12, [r0, #56]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #56]\n\t" + "STR r12, [r0, #56]\n\t" "ADC r7, r7, #0\n\t" /* a[i+15] += m[15] * mu */ - "LDR r9, [%[m], #60]\n\t" - "LDR r12, [%[a], #60]\n\t" + "LDR r9, [r1, #60]\n\t" + "LDR r12, [r0, #60]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #60]\n\t" + "STR r12, [r0, #60]\n\t" "ADC r6, r6, #0\n\t" /* a[i+16] += m[16] * mu */ - "LDR r9, [%[m], #64]\n\t" - "LDR r12, [%[a], #64]\n\t" + "LDR r9, [r1, #64]\n\t" + "LDR r12, [r0, #64]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #64]\n\t" + "STR r12, [r0, #64]\n\t" "ADC r7, r7, #0\n\t" /* a[i+17] += m[17] * mu */ - "LDR r9, [%[m], #68]\n\t" - "LDR r12, [%[a], #68]\n\t" + "LDR r9, [r1, #68]\n\t" + "LDR r12, [r0, #68]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #68]\n\t" + "STR r12, [r0, #68]\n\t" "ADC r6, r6, #0\n\t" /* a[i+18] += m[18] * mu */ - "LDR r9, [%[m], #72]\n\t" - "LDR r12, [%[a], #72]\n\t" + "LDR r9, [r1, #72]\n\t" + "LDR r12, [r0, #72]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #72]\n\t" + "STR r12, [r0, #72]\n\t" "ADC r7, r7, #0\n\t" /* a[i+19] += m[19] * mu */ - "LDR r9, [%[m], #76]\n\t" - "LDR r12, [%[a], #76]\n\t" + "LDR r9, [r1, #76]\n\t" + "LDR r12, [r0, #76]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #76]\n\t" + "STR r12, [r0, #76]\n\t" "ADC r6, r6, #0\n\t" /* a[i+20] += m[20] * mu */ - "LDR r9, [%[m], #80]\n\t" - "LDR r12, [%[a], #80]\n\t" + "LDR r9, [r1, #80]\n\t" + "LDR r12, [r0, #80]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #80]\n\t" + "STR r12, [r0, #80]\n\t" "ADC r7, r7, #0\n\t" /* a[i+21] += m[21] * mu */ - "LDR r9, [%[m], #84]\n\t" - "LDR r12, [%[a], #84]\n\t" + "LDR r9, [r1, #84]\n\t" + "LDR r12, [r0, #84]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #84]\n\t" + "STR r12, [r0, #84]\n\t" "ADC r6, r6, #0\n\t" /* a[i+22] += m[22] * mu */ - "LDR r9, [%[m], #88]\n\t" - "LDR r12, [%[a], #88]\n\t" + "LDR r9, [r1, #88]\n\t" + "LDR r12, [r0, #88]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #88]\n\t" + "STR r12, [r0, #88]\n\t" "ADC r7, r7, #0\n\t" /* a[i+23] += m[23] * mu */ - "LDR r9, [%[m], #92]\n\t" - "LDR r12, [%[a], #92]\n\t" + "LDR r9, [r1, #92]\n\t" + "LDR r12, [r0, #92]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #92]\n\t" + "STR r12, [r0, #92]\n\t" "ADC r6, r6, #0\n\t" /* a[i+24] += m[24] * mu */ - "LDR r9, [%[m], #96]\n\t" - "LDR r12, [%[a], #96]\n\t" + "LDR r9, [r1, #96]\n\t" + "LDR r12, [r0, #96]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #96]\n\t" + "STR r12, [r0, #96]\n\t" "ADC r7, r7, #0\n\t" /* a[i+25] += m[25] * mu */ - "LDR r9, [%[m], #100]\n\t" - "LDR r12, [%[a], #100]\n\t" + "LDR r9, [r1, #100]\n\t" + "LDR r12, [r0, #100]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #100]\n\t" + "STR r12, [r0, #100]\n\t" "ADC r6, r6, #0\n\t" /* a[i+26] += m[26] * mu */ - "LDR r9, [%[m], #104]\n\t" - "LDR r12, [%[a], #104]\n\t" + "LDR r9, [r1, #104]\n\t" + "LDR r12, [r0, #104]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #104]\n\t" + "STR r12, [r0, #104]\n\t" "ADC r7, r7, #0\n\t" /* a[i+27] += m[27] * mu */ - "LDR r9, [%[m], #108]\n\t" - "LDR r12, [%[a], #108]\n\t" + "LDR r9, [r1, #108]\n\t" + "LDR r12, [r0, #108]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #108]\n\t" + "STR r12, [r0, #108]\n\t" "ADC r6, r6, #0\n\t" /* a[i+28] += m[28] * mu */ - "LDR r9, [%[m], #112]\n\t" - "LDR r12, [%[a], #112]\n\t" + "LDR r9, [r1, #112]\n\t" + "LDR r12, [r0, #112]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #112]\n\t" + "STR r12, [r0, #112]\n\t" "ADC r7, r7, #0\n\t" /* a[i+29] += m[29] * mu */ - "LDR r9, [%[m], #116]\n\t" - "LDR r12, [%[a], #116]\n\t" + "LDR r9, [r1, #116]\n\t" + "LDR r12, [r0, #116]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #116]\n\t" + "STR r12, [r0, #116]\n\t" "ADC r6, r6, #0\n\t" /* a[i+30] += m[30] * mu */ - "LDR r9, [%[m], #120]\n\t" - "LDR r12, [%[a], #120]\n\t" + "LDR r9, [r1, #120]\n\t" + "LDR r12, [r0, #120]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #120]\n\t" + "STR r12, [r0, #120]\n\t" "ADC r7, r7, #0\n\t" /* a[i+31] += m[31] * mu */ - "LDR r9, [%[m], #124]\n\t" - "LDR r12, [%[a], #124]\n\t" + "LDR r9, [r1, #124]\n\t" + "LDR r12, [r0, #124]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #124]\n\t" + "STR r12, [r0, #124]\n\t" "ADC r6, r6, #0\n\t" /* a[i+32] += m[32] * mu */ - "LDR r9, [%[m], #128]\n\t" - "LDR r12, [%[a], #128]\n\t" + "LDR r9, [r1, #128]\n\t" + "LDR r12, [r0, #128]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #128]\n\t" + "STR r12, [r0, #128]\n\t" "ADC r7, r7, #0\n\t" /* a[i+33] += m[33] * mu */ - "LDR r9, [%[m], #132]\n\t" - "LDR r12, [%[a], #132]\n\t" + "LDR r9, [r1, #132]\n\t" + "LDR r12, [r0, #132]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #132]\n\t" + "STR r12, [r0, #132]\n\t" "ADC r6, r6, #0\n\t" /* a[i+34] += m[34] * mu */ - "LDR r9, [%[m], #136]\n\t" - "LDR r12, [%[a], #136]\n\t" + "LDR r9, [r1, #136]\n\t" + "LDR r12, [r0, #136]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #136]\n\t" + "STR r12, [r0, #136]\n\t" "ADC r7, r7, #0\n\t" /* a[i+35] += m[35] * mu */ - "LDR r9, [%[m], #140]\n\t" - "LDR r12, [%[a], #140]\n\t" + "LDR r9, [r1, #140]\n\t" + "LDR r12, [r0, #140]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #140]\n\t" + "STR r12, [r0, #140]\n\t" "ADC r6, r6, #0\n\t" /* a[i+36] += m[36] * mu */ - "LDR r9, [%[m], #144]\n\t" - "LDR r12, [%[a], #144]\n\t" + "LDR r9, [r1, #144]\n\t" + "LDR r12, [r0, #144]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #144]\n\t" + "STR r12, [r0, #144]\n\t" "ADC r7, r7, #0\n\t" /* a[i+37] += m[37] * mu */ - "LDR r9, [%[m], #148]\n\t" - "LDR r12, [%[a], #148]\n\t" + "LDR r9, [r1, #148]\n\t" + "LDR r12, [r0, #148]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #148]\n\t" + "STR r12, [r0, #148]\n\t" "ADC r6, r6, #0\n\t" /* a[i+38] += m[38] * mu */ - "LDR r9, [%[m], #152]\n\t" - "LDR r12, [%[a], #152]\n\t" + "LDR r9, [r1, #152]\n\t" + "LDR r12, [r0, #152]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #152]\n\t" + "STR r12, [r0, #152]\n\t" "ADC r7, r7, #0\n\t" /* a[i+39] += m[39] * mu */ - "LDR r9, [%[m], #156]\n\t" - "LDR r12, [%[a], #156]\n\t" + "LDR r9, [r1, #156]\n\t" + "LDR r12, [r0, #156]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #156]\n\t" + "STR r12, [r0, #156]\n\t" "ADC r6, r6, #0\n\t" /* a[i+40] += m[40] * mu */ - "LDR r9, [%[m], #160]\n\t" - "LDR r12, [%[a], #160]\n\t" + "LDR r9, [r1, #160]\n\t" + "LDR r12, [r0, #160]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #160]\n\t" + "STR r12, [r0, #160]\n\t" "ADC r7, r7, #0\n\t" /* a[i+41] += m[41] * mu */ - "LDR r9, [%[m], #164]\n\t" - "LDR r12, [%[a], #164]\n\t" + "LDR r9, [r1, #164]\n\t" + "LDR r12, [r0, #164]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #164]\n\t" + "STR r12, [r0, #164]\n\t" "ADC r6, r6, #0\n\t" /* a[i+42] += m[42] * mu */ - "LDR r9, [%[m], #168]\n\t" - "LDR r12, [%[a], #168]\n\t" + "LDR r9, [r1, #168]\n\t" + "LDR r12, [r0, #168]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #168]\n\t" + "STR r12, [r0, #168]\n\t" "ADC r7, r7, #0\n\t" /* a[i+43] += m[43] * mu */ - "LDR r9, [%[m], #172]\n\t" - "LDR r12, [%[a], #172]\n\t" + "LDR r9, [r1, #172]\n\t" + "LDR r12, [r0, #172]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #172]\n\t" + "STR r12, [r0, #172]\n\t" "ADC r6, r6, #0\n\t" /* a[i+44] += m[44] * mu */ - "LDR r9, [%[m], #176]\n\t" - "LDR r12, [%[a], #176]\n\t" + "LDR r9, [r1, #176]\n\t" + "LDR r12, [r0, #176]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #176]\n\t" + "STR r12, [r0, #176]\n\t" "ADC r7, r7, #0\n\t" /* a[i+45] += m[45] * mu */ - "LDR r9, [%[m], #180]\n\t" - "LDR r12, [%[a], #180]\n\t" + "LDR r9, [r1, #180]\n\t" + "LDR r12, [r0, #180]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #180]\n\t" + "STR r12, [r0, #180]\n\t" "ADC r6, r6, #0\n\t" /* a[i+46] += m[46] * mu */ - "LDR r9, [%[m], #184]\n\t" - "LDR r12, [%[a], #184]\n\t" + "LDR r9, [r1, #184]\n\t" + "LDR r12, [r0, #184]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #184]\n\t" + "STR r12, [r0, #184]\n\t" "ADC r7, r7, #0\n\t" /* a[i+47] += m[47] * mu */ - "LDR r9, [%[m], #188]\n\t" - "LDR r12, [%[a], #188]\n\t" + "LDR r9, [r1, #188]\n\t" + "LDR r12, [r0, #188]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #188]\n\t" + "STR r12, [r0, #188]\n\t" "ADC r6, r6, #0\n\t" /* a[i+48] += m[48] * mu */ - "LDR r9, [%[m], #192]\n\t" - "LDR r12, [%[a], #192]\n\t" + "LDR r9, [r1, #192]\n\t" + "LDR r12, [r0, #192]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #192]\n\t" + "STR r12, [r0, #192]\n\t" "ADC r7, r7, #0\n\t" /* a[i+49] += m[49] * mu */ - "LDR r9, [%[m], #196]\n\t" - "LDR r12, [%[a], #196]\n\t" + "LDR r9, [r1, #196]\n\t" + "LDR r12, [r0, #196]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #196]\n\t" + "STR r12, [r0, #196]\n\t" "ADC r6, r6, #0\n\t" /* a[i+50] += m[50] * mu */ - "LDR r9, [%[m], #200]\n\t" - "LDR r12, [%[a], #200]\n\t" + "LDR r9, [r1, #200]\n\t" + "LDR r12, [r0, #200]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #200]\n\t" + "STR r12, [r0, #200]\n\t" "ADC r7, r7, #0\n\t" /* a[i+51] += m[51] * mu */ - "LDR r9, [%[m], #204]\n\t" - "LDR r12, [%[a], #204]\n\t" + "LDR r9, [r1, #204]\n\t" + "LDR r12, [r0, #204]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #204]\n\t" + "STR r12, [r0, #204]\n\t" "ADC r6, r6, #0\n\t" /* a[i+52] += m[52] * mu */ - "LDR r9, [%[m], #208]\n\t" - "LDR r12, [%[a], #208]\n\t" + "LDR r9, [r1, #208]\n\t" + "LDR r12, [r0, #208]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #208]\n\t" + "STR r12, [r0, #208]\n\t" "ADC r7, r7, #0\n\t" /* a[i+53] += m[53] * mu */ - "LDR r9, [%[m], #212]\n\t" - "LDR r12, [%[a], #212]\n\t" + "LDR r9, [r1, #212]\n\t" + "LDR r12, [r0, #212]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #212]\n\t" + "STR r12, [r0, #212]\n\t" "ADC r6, r6, #0\n\t" /* a[i+54] += m[54] * mu */ - "LDR r9, [%[m], #216]\n\t" - "LDR r12, [%[a], #216]\n\t" + "LDR r9, [r1, #216]\n\t" + "LDR r12, [r0, #216]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #216]\n\t" + "STR r12, [r0, #216]\n\t" "ADC r7, r7, #0\n\t" /* a[i+55] += m[55] * mu */ - "LDR r9, [%[m], #220]\n\t" - "LDR r12, [%[a], #220]\n\t" + "LDR r9, [r1, #220]\n\t" + "LDR r12, [r0, #220]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #220]\n\t" + "STR r12, [r0, #220]\n\t" "ADC r6, r6, #0\n\t" /* a[i+56] += m[56] * mu */ - "LDR r9, [%[m], #224]\n\t" - "LDR r12, [%[a], #224]\n\t" + "LDR r9, [r1, #224]\n\t" + "LDR r12, [r0, #224]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #224]\n\t" + "STR r12, [r0, #224]\n\t" "ADC r7, r7, #0\n\t" /* a[i+57] += m[57] * mu */ - "LDR r9, [%[m], #228]\n\t" - "LDR r12, [%[a], #228]\n\t" + "LDR r9, [r1, #228]\n\t" + "LDR r12, [r0, #228]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #228]\n\t" + "STR r12, [r0, #228]\n\t" "ADC r6, r6, #0\n\t" /* a[i+58] += m[58] * mu */ - "LDR r9, [%[m], #232]\n\t" - "LDR r12, [%[a], #232]\n\t" + "LDR r9, [r1, #232]\n\t" + "LDR r12, [r0, #232]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #232]\n\t" + "STR r12, [r0, #232]\n\t" "ADC r7, r7, #0\n\t" /* a[i+59] += m[59] * mu */ - "LDR r9, [%[m], #236]\n\t" - "LDR r12, [%[a], #236]\n\t" + "LDR r9, [r1, #236]\n\t" + "LDR r12, [r0, #236]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #236]\n\t" + "STR r12, [r0, #236]\n\t" "ADC r6, r6, #0\n\t" /* a[i+60] += m[60] * mu */ - "LDR r9, [%[m], #240]\n\t" - "LDR r12, [%[a], #240]\n\t" + "LDR r9, [r1, #240]\n\t" + "LDR r12, [r0, #240]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #240]\n\t" + "STR r12, [r0, #240]\n\t" "ADC r7, r7, #0\n\t" /* a[i+61] += m[61] * mu */ - "LDR r9, [%[m], #244]\n\t" - "LDR r12, [%[a], #244]\n\t" + "LDR r9, [r1, #244]\n\t" + "LDR r12, [r0, #244]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #244]\n\t" + "STR r12, [r0, #244]\n\t" "ADC r6, r6, #0\n\t" /* a[i+62] += m[62] * mu */ - "LDR r9, [%[m], #248]\n\t" - "LDR r12, [%[a], #248]\n\t" + "LDR r9, [r1, #248]\n\t" + "LDR r12, [r0, #248]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #248]\n\t" + "STR r12, [r0, #248]\n\t" "ADC r7, r7, #0\n\t" /* a[i+63] += m[63] * mu */ - "LDR r9, [%[m], #252]\n\t" - "LDR r12, [%[a], #252]\n\t" + "LDR r9, [r1, #252]\n\t" + "LDR r12, [r0, #252]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #252]\n\t" + "STR r12, [r0, #252]\n\t" "ADC r6, r6, #0\n\t" /* a[i+64] += m[64] * mu */ - "LDR r9, [%[m], #256]\n\t" - "LDR r12, [%[a], #256]\n\t" + "LDR r9, [r1, #256]\n\t" + "LDR r12, [r0, #256]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #256]\n\t" + "STR r12, [r0, #256]\n\t" "ADC r7, r7, #0\n\t" /* a[i+65] += m[65] * mu */ - "LDR r9, [%[m], #260]\n\t" - "LDR r12, [%[a], #260]\n\t" + "LDR r9, [r1, #260]\n\t" + "LDR r12, [r0, #260]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #260]\n\t" + "STR r12, [r0, #260]\n\t" "ADC r6, r6, #0\n\t" /* a[i+66] += m[66] * mu */ - "LDR r9, [%[m], #264]\n\t" - "LDR r12, [%[a], #264]\n\t" + "LDR r9, [r1, #264]\n\t" + "LDR r12, [r0, #264]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #264]\n\t" + "STR r12, [r0, #264]\n\t" "ADC r7, r7, #0\n\t" /* a[i+67] += m[67] * mu */ - "LDR r9, [%[m], #268]\n\t" - "LDR r12, [%[a], #268]\n\t" + "LDR r9, [r1, #268]\n\t" + "LDR r12, [r0, #268]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #268]\n\t" + "STR r12, [r0, #268]\n\t" "ADC r6, r6, #0\n\t" /* a[i+68] += m[68] * mu */ - "LDR r9, [%[m], #272]\n\t" - "LDR r12, [%[a], #272]\n\t" + "LDR r9, [r1, #272]\n\t" + "LDR r12, [r0, #272]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #272]\n\t" + "STR r12, [r0, #272]\n\t" "ADC r7, r7, #0\n\t" /* a[i+69] += m[69] * mu */ - "LDR r9, [%[m], #276]\n\t" - "LDR r12, [%[a], #276]\n\t" + "LDR r9, [r1, #276]\n\t" + "LDR r12, [r0, #276]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #276]\n\t" + "STR r12, [r0, #276]\n\t" "ADC r6, r6, #0\n\t" /* a[i+70] += m[70] * mu */ - "LDR r9, [%[m], #280]\n\t" - "LDR r12, [%[a], #280]\n\t" + "LDR r9, [r1, #280]\n\t" + "LDR r12, [r0, #280]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #280]\n\t" + "STR r12, [r0, #280]\n\t" "ADC r7, r7, #0\n\t" /* a[i+71] += m[71] * mu */ - "LDR r9, [%[m], #284]\n\t" - "LDR r12, [%[a], #284]\n\t" + "LDR r9, [r1, #284]\n\t" + "LDR r12, [r0, #284]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #284]\n\t" + "STR r12, [r0, #284]\n\t" "ADC r6, r6, #0\n\t" /* a[i+72] += m[72] * mu */ - "LDR r9, [%[m], #288]\n\t" - "LDR r12, [%[a], #288]\n\t" + "LDR r9, [r1, #288]\n\t" + "LDR r12, [r0, #288]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #288]\n\t" + "STR r12, [r0, #288]\n\t" "ADC r7, r7, #0\n\t" /* a[i+73] += m[73] * mu */ - "LDR r9, [%[m], #292]\n\t" - "LDR r12, [%[a], #292]\n\t" + "LDR r9, [r1, #292]\n\t" + "LDR r12, [r0, #292]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #292]\n\t" + "STR r12, [r0, #292]\n\t" "ADC r6, r6, #0\n\t" /* a[i+74] += m[74] * mu */ - "LDR r9, [%[m], #296]\n\t" - "LDR r12, [%[a], #296]\n\t" + "LDR r9, [r1, #296]\n\t" + "LDR r12, [r0, #296]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #296]\n\t" + "STR r12, [r0, #296]\n\t" "ADC r7, r7, #0\n\t" /* a[i+75] += m[75] * mu */ - "LDR r9, [%[m], #300]\n\t" - "LDR r12, [%[a], #300]\n\t" + "LDR r9, [r1, #300]\n\t" + "LDR r12, [r0, #300]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #300]\n\t" + "STR r12, [r0, #300]\n\t" "ADC r6, r6, #0\n\t" /* a[i+76] += m[76] * mu */ - "LDR r9, [%[m], #304]\n\t" - "LDR r12, [%[a], #304]\n\t" + "LDR r9, [r1, #304]\n\t" + "LDR r12, [r0, #304]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #304]\n\t" + "STR r12, [r0, #304]\n\t" "ADC r7, r7, #0\n\t" /* a[i+77] += m[77] * mu */ - "LDR r9, [%[m], #308]\n\t" - "LDR r12, [%[a], #308]\n\t" + "LDR r9, [r1, #308]\n\t" + "LDR r12, [r0, #308]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #308]\n\t" + "STR r12, [r0, #308]\n\t" "ADC r6, r6, #0\n\t" /* a[i+78] += m[78] * mu */ - "LDR r9, [%[m], #312]\n\t" - "LDR r12, [%[a], #312]\n\t" + "LDR r9, [r1, #312]\n\t" + "LDR r12, [r0, #312]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #312]\n\t" + "STR r12, [r0, #312]\n\t" "ADC r7, r7, #0\n\t" /* a[i+79] += m[79] * mu */ - "LDR r9, [%[m], #316]\n\t" - "LDR r12, [%[a], #316]\n\t" + "LDR r9, [r1, #316]\n\t" + "LDR r12, [r0, #316]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #316]\n\t" + "STR r12, [r0, #316]\n\t" "ADC r6, r6, #0\n\t" /* a[i+80] += m[80] * mu */ - "LDR r9, [%[m], #320]\n\t" - "LDR r12, [%[a], #320]\n\t" + "LDR r9, [r1, #320]\n\t" + "LDR r12, [r0, #320]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #320]\n\t" + "STR r12, [r0, #320]\n\t" "ADC r7, r7, #0\n\t" /* a[i+81] += m[81] * mu */ - "LDR r9, [%[m], #324]\n\t" - "LDR r12, [%[a], #324]\n\t" + "LDR r9, [r1, #324]\n\t" + "LDR r12, [r0, #324]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #324]\n\t" + "STR r12, [r0, #324]\n\t" "ADC r6, r6, #0\n\t" /* a[i+82] += m[82] * mu */ - "LDR r9, [%[m], #328]\n\t" - "LDR r12, [%[a], #328]\n\t" + "LDR r9, [r1, #328]\n\t" + "LDR r12, [r0, #328]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #328]\n\t" + "STR r12, [r0, #328]\n\t" "ADC r7, r7, #0\n\t" /* a[i+83] += m[83] * mu */ - "LDR r9, [%[m], #332]\n\t" - "LDR r12, [%[a], #332]\n\t" + "LDR r9, [r1, #332]\n\t" + "LDR r12, [r0, #332]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #332]\n\t" + "STR r12, [r0, #332]\n\t" "ADC r6, r6, #0\n\t" /* a[i+84] += m[84] * mu */ - "LDR r9, [%[m], #336]\n\t" - "LDR r12, [%[a], #336]\n\t" + "LDR r9, [r1, #336]\n\t" + "LDR r12, [r0, #336]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #336]\n\t" + "STR r12, [r0, #336]\n\t" "ADC r7, r7, #0\n\t" /* a[i+85] += m[85] * mu */ - "LDR r9, [%[m], #340]\n\t" - "LDR r12, [%[a], #340]\n\t" + "LDR r9, [r1, #340]\n\t" + "LDR r12, [r0, #340]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #340]\n\t" + "STR r12, [r0, #340]\n\t" "ADC r6, r6, #0\n\t" /* a[i+86] += m[86] * mu */ - "LDR r9, [%[m], #344]\n\t" - "LDR r12, [%[a], #344]\n\t" + "LDR r9, [r1, #344]\n\t" + "LDR r12, [r0, #344]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #344]\n\t" + "STR r12, [r0, #344]\n\t" "ADC r7, r7, #0\n\t" /* a[i+87] += m[87] * mu */ - "LDR r9, [%[m], #348]\n\t" - "LDR r12, [%[a], #348]\n\t" + "LDR r9, [r1, #348]\n\t" + "LDR r12, [r0, #348]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #348]\n\t" + "STR r12, [r0, #348]\n\t" "ADC r6, r6, #0\n\t" /* a[i+88] += m[88] * mu */ - "LDR r9, [%[m], #352]\n\t" - "LDR r12, [%[a], #352]\n\t" + "LDR r9, [r1, #352]\n\t" + "LDR r12, [r0, #352]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #352]\n\t" + "STR r12, [r0, #352]\n\t" "ADC r7, r7, #0\n\t" /* a[i+89] += m[89] * mu */ - "LDR r9, [%[m], #356]\n\t" - "LDR r12, [%[a], #356]\n\t" + "LDR r9, [r1, #356]\n\t" + "LDR r12, [r0, #356]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #356]\n\t" + "STR r12, [r0, #356]\n\t" "ADC r6, r6, #0\n\t" /* a[i+90] += m[90] * mu */ - "LDR r9, [%[m], #360]\n\t" - "LDR r12, [%[a], #360]\n\t" + "LDR r9, [r1, #360]\n\t" + "LDR r12, [r0, #360]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #360]\n\t" + "STR r12, [r0, #360]\n\t" "ADC r7, r7, #0\n\t" /* a[i+91] += m[91] * mu */ - "LDR r9, [%[m], #364]\n\t" - "LDR r12, [%[a], #364]\n\t" + "LDR r9, [r1, #364]\n\t" + "LDR r12, [r0, #364]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #364]\n\t" + "STR r12, [r0, #364]\n\t" "ADC r6, r6, #0\n\t" /* a[i+92] += m[92] * mu */ - "LDR r9, [%[m], #368]\n\t" - "LDR r12, [%[a], #368]\n\t" + "LDR r9, [r1, #368]\n\t" + "LDR r12, [r0, #368]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #368]\n\t" + "STR r12, [r0, #368]\n\t" "ADC r7, r7, #0\n\t" /* a[i+93] += m[93] * mu */ - "LDR r9, [%[m], #372]\n\t" - "LDR r12, [%[a], #372]\n\t" + "LDR r9, [r1, #372]\n\t" + "LDR r12, [r0, #372]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #372]\n\t" + "STR r12, [r0, #372]\n\t" "ADC r6, r6, #0\n\t" /* a[i+94] += m[94] * mu */ - "LDR r9, [%[m], #376]\n\t" - "LDR r12, [%[a], #376]\n\t" + "LDR r9, [r1, #376]\n\t" + "LDR r12, [r0, #376]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #376]\n\t" + "STR r12, [r0, #376]\n\t" "ADC r7, r7, #0\n\t" /* a[i+95] += m[95] * mu */ - "LDR r9, [%[m], #380]\n\t" - "LDR r12, [%[a], #380]\n\t" + "LDR r9, [r1, #380]\n\t" + "LDR r12, [r0, #380]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #380]\n\t" + "STR r12, [r0, #380]\n\t" "ADC r6, r6, #0\n\t" /* a[i+96] += m[96] * mu */ - "LDR r9, [%[m], #384]\n\t" - "LDR r12, [%[a], #384]\n\t" + "LDR r9, [r1, #384]\n\t" + "LDR r12, [r0, #384]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #384]\n\t" + "STR r12, [r0, #384]\n\t" "ADC r7, r7, #0\n\t" /* a[i+97] += m[97] * mu */ - "LDR r9, [%[m], #388]\n\t" - "LDR r12, [%[a], #388]\n\t" + "LDR r9, [r1, #388]\n\t" + "LDR r12, [r0, #388]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #388]\n\t" + "STR r12, [r0, #388]\n\t" "ADC r6, r6, #0\n\t" /* a[i+98] += m[98] * mu */ - "LDR r9, [%[m], #392]\n\t" - "LDR r12, [%[a], #392]\n\t" + "LDR r9, [r1, #392]\n\t" + "LDR r12, [r0, #392]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #392]\n\t" + "STR r12, [r0, #392]\n\t" "ADC r7, r7, #0\n\t" /* a[i+99] += m[99] * mu */ - "LDR r9, [%[m], #396]\n\t" - "LDR r12, [%[a], #396]\n\t" + "LDR r9, [r1, #396]\n\t" + "LDR r12, [r0, #396]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #396]\n\t" + "STR r12, [r0, #396]\n\t" "ADC r6, r6, #0\n\t" /* a[i+100] += m[100] * mu */ - "LDR r9, [%[m], #400]\n\t" - "LDR r12, [%[a], #400]\n\t" + "LDR r9, [r1, #400]\n\t" + "LDR r12, [r0, #400]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #400]\n\t" + "STR r12, [r0, #400]\n\t" "ADC r7, r7, #0\n\t" /* a[i+101] += m[101] * mu */ - "LDR r9, [%[m], #404]\n\t" - "LDR r12, [%[a], #404]\n\t" + "LDR r9, [r1, #404]\n\t" + "LDR r12, [r0, #404]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #404]\n\t" + "STR r12, [r0, #404]\n\t" "ADC r6, r6, #0\n\t" /* a[i+102] += m[102] * mu */ - "LDR r9, [%[m], #408]\n\t" - "LDR r12, [%[a], #408]\n\t" + "LDR r9, [r1, #408]\n\t" + "LDR r12, [r0, #408]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #408]\n\t" + "STR r12, [r0, #408]\n\t" "ADC r7, r7, #0\n\t" /* a[i+103] += m[103] * mu */ - "LDR r9, [%[m], #412]\n\t" - "LDR r12, [%[a], #412]\n\t" + "LDR r9, [r1, #412]\n\t" + "LDR r12, [r0, #412]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #412]\n\t" + "STR r12, [r0, #412]\n\t" "ADC r6, r6, #0\n\t" /* a[i+104] += m[104] * mu */ - "LDR r9, [%[m], #416]\n\t" - "LDR r12, [%[a], #416]\n\t" + "LDR r9, [r1, #416]\n\t" + "LDR r12, [r0, #416]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #416]\n\t" + "STR r12, [r0, #416]\n\t" "ADC r7, r7, #0\n\t" /* a[i+105] += m[105] * mu */ - "LDR r9, [%[m], #420]\n\t" - "LDR r12, [%[a], #420]\n\t" + "LDR r9, [r1, #420]\n\t" + "LDR r12, [r0, #420]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #420]\n\t" + "STR r12, [r0, #420]\n\t" "ADC r6, r6, #0\n\t" /* a[i+106] += m[106] * mu */ - "LDR r9, [%[m], #424]\n\t" - "LDR r12, [%[a], #424]\n\t" + "LDR r9, [r1, #424]\n\t" + "LDR r12, [r0, #424]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #424]\n\t" + "STR r12, [r0, #424]\n\t" "ADC r7, r7, #0\n\t" /* a[i+107] += m[107] * mu */ - "LDR r9, [%[m], #428]\n\t" - "LDR r12, [%[a], #428]\n\t" + "LDR r9, [r1, #428]\n\t" + "LDR r12, [r0, #428]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #428]\n\t" + "STR r12, [r0, #428]\n\t" "ADC r6, r6, #0\n\t" /* a[i+108] += m[108] * mu */ - "LDR r9, [%[m], #432]\n\t" - "LDR r12, [%[a], #432]\n\t" + "LDR r9, [r1, #432]\n\t" + "LDR r12, [r0, #432]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #432]\n\t" + "STR r12, [r0, #432]\n\t" "ADC r7, r7, #0\n\t" /* a[i+109] += m[109] * mu */ - "LDR r9, [%[m], #436]\n\t" - "LDR r12, [%[a], #436]\n\t" + "LDR r9, [r1, #436]\n\t" + "LDR r12, [r0, #436]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #436]\n\t" + "STR r12, [r0, #436]\n\t" "ADC r6, r6, #0\n\t" /* a[i+110] += m[110] * mu */ - "LDR r9, [%[m], #440]\n\t" - "LDR r12, [%[a], #440]\n\t" + "LDR r9, [r1, #440]\n\t" + "LDR r12, [r0, #440]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #440]\n\t" + "STR r12, [r0, #440]\n\t" "ADC r7, r7, #0\n\t" /* a[i+111] += m[111] * mu */ - "LDR r9, [%[m], #444]\n\t" - "LDR r12, [%[a], #444]\n\t" + "LDR r9, [r1, #444]\n\t" + "LDR r12, [r0, #444]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #444]\n\t" + "STR r12, [r0, #444]\n\t" "ADC r6, r6, #0\n\t" /* a[i+112] += m[112] * mu */ - "LDR r9, [%[m], #448]\n\t" - "LDR r12, [%[a], #448]\n\t" + "LDR r9, [r1, #448]\n\t" + "LDR r12, [r0, #448]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #448]\n\t" + "STR r12, [r0, #448]\n\t" "ADC r7, r7, #0\n\t" /* a[i+113] += m[113] * mu */ - "LDR r9, [%[m], #452]\n\t" - "LDR r12, [%[a], #452]\n\t" + "LDR r9, [r1, #452]\n\t" + "LDR r12, [r0, #452]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #452]\n\t" + "STR r12, [r0, #452]\n\t" "ADC r6, r6, #0\n\t" /* a[i+114] += m[114] * mu */ - "LDR r9, [%[m], #456]\n\t" - "LDR r12, [%[a], #456]\n\t" + "LDR r9, [r1, #456]\n\t" + "LDR r12, [r0, #456]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #456]\n\t" + "STR r12, [r0, #456]\n\t" "ADC r7, r7, #0\n\t" /* a[i+115] += m[115] * mu */ - "LDR r9, [%[m], #460]\n\t" - "LDR r12, [%[a], #460]\n\t" + "LDR r9, [r1, #460]\n\t" + "LDR r12, [r0, #460]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #460]\n\t" + "STR r12, [r0, #460]\n\t" "ADC r6, r6, #0\n\t" /* a[i+116] += m[116] * mu */ - "LDR r9, [%[m], #464]\n\t" - "LDR r12, [%[a], #464]\n\t" + "LDR r9, [r1, #464]\n\t" + "LDR r12, [r0, #464]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #464]\n\t" + "STR r12, [r0, #464]\n\t" "ADC r7, r7, #0\n\t" /* a[i+117] += m[117] * mu */ - "LDR r9, [%[m], #468]\n\t" - "LDR r12, [%[a], #468]\n\t" + "LDR r9, [r1, #468]\n\t" + "LDR r12, [r0, #468]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #468]\n\t" + "STR r12, [r0, #468]\n\t" "ADC r6, r6, #0\n\t" /* a[i+118] += m[118] * mu */ - "LDR r9, [%[m], #472]\n\t" - "LDR r12, [%[a], #472]\n\t" + "LDR r9, [r1, #472]\n\t" + "LDR r12, [r0, #472]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #472]\n\t" + "STR r12, [r0, #472]\n\t" "ADC r7, r7, #0\n\t" /* a[i+119] += m[119] * mu */ - "LDR r9, [%[m], #476]\n\t" - "LDR r12, [%[a], #476]\n\t" + "LDR r9, [r1, #476]\n\t" + "LDR r12, [r0, #476]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #476]\n\t" + "STR r12, [r0, #476]\n\t" "ADC r6, r6, #0\n\t" /* a[i+120] += m[120] * mu */ - "LDR r9, [%[m], #480]\n\t" - "LDR r12, [%[a], #480]\n\t" + "LDR r9, [r1, #480]\n\t" + "LDR r12, [r0, #480]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #480]\n\t" + "STR r12, [r0, #480]\n\t" "ADC r7, r7, #0\n\t" /* a[i+121] += m[121] * mu */ - "LDR r9, [%[m], #484]\n\t" - "LDR r12, [%[a], #484]\n\t" + "LDR r9, [r1, #484]\n\t" + "LDR r12, [r0, #484]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #484]\n\t" + "STR r12, [r0, #484]\n\t" "ADC r6, r6, #0\n\t" /* a[i+122] += m[122] * mu */ - "LDR r9, [%[m], #488]\n\t" - "LDR r12, [%[a], #488]\n\t" + "LDR r9, [r1, #488]\n\t" + "LDR r12, [r0, #488]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #488]\n\t" + "STR r12, [r0, #488]\n\t" "ADC r7, r7, #0\n\t" /* a[i+123] += m[123] * mu */ - "LDR r9, [%[m], #492]\n\t" - "LDR r12, [%[a], #492]\n\t" + "LDR r9, [r1, #492]\n\t" + "LDR r12, [r0, #492]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #492]\n\t" + "STR r12, [r0, #492]\n\t" "ADC r6, r6, #0\n\t" /* a[i+124] += m[124] * mu */ - "LDR r9, [%[m], #496]\n\t" - "LDR r12, [%[a], #496]\n\t" + "LDR r9, [r1, #496]\n\t" + "LDR r12, [r0, #496]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #496]\n\t" + "STR r12, [r0, #496]\n\t" "ADC r7, r7, #0\n\t" /* a[i+125] += m[125] * mu */ - "LDR r9, [%[m], #500]\n\t" - "LDR r12, [%[a], #500]\n\t" + "LDR r9, [r1, #500]\n\t" + "LDR r12, [r0, #500]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #500]\n\t" + "STR r12, [r0, #500]\n\t" "ADC r6, r6, #0\n\t" /* a[i+126] += m[126] * mu */ - "LDR r9, [%[m], #504]\n\t" - "LDR r12, [%[a], #504]\n\t" + "LDR r9, [r1, #504]\n\t" + "LDR r12, [r0, #504]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #504]\n\t" + "STR r12, [r0, #504]\n\t" "ADC r7, r7, #0\n\t" /* a[i+127] += m[127] * mu */ - "LDR r9, [%[m], #508]\n\t" - "LDR r12, [%[a], #508]\n\t" + "LDR r9, [r1, #508]\n\t" + "LDR r12, [r0, #508]\n\t" "UMULL r8, r9, r10, r9\n\t" "ADDS r7, r7, r8\n\t" "ADCS r6, r9, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, r3\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #508]\n\t" - "LDR r12, [%[a], #512]\n\t" + "STR r12, [r0, #508]\n\t" + "LDR r12, [r0, #512]\n\t" "ADCS r12, r12, r6\n\t" - "STR r12, [%[a], #512]\n\t" + "STR r12, [r0, #512]\n\t" "ADC r3, r3, #0\n\t" /* i += 1 */ "ADD r11, r11, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r11, #0x200\n\t" #if defined(__GNUC__) "BLT L_sp_4096_mont_reduce_128_word_%=\n\t" @@ -27010,19 +29061,30 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( "BLT.W L_sp_4096_mont_reduce_128_word_%=\n\t" #endif /* Loop Done */ - "STR r4, [%[a]]\n\t" - "STR r5, [%[a], #4]\n\t" - "MOV %[mp], r3\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_4096_cond_sub_128(a - 128, a, m, (sp_digit)0 - mp); } @@ -27046,10 +29108,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r11, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r11, [r1]\n\t" /* i = 0 */ "MOV r9, #0\n\t" /* ca = 0 */ @@ -27061,8 +29132,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( "L_sp_4096_mont_reduce_128_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "LDR r10, [%[a]]\n\t" - "MUL r8, %[mp], r10\n\t" + "LDR r10, [r0]\n\t" + "MUL r8, r2, r10\n\t" /* j = 0 */ "MOV r12, #0\n\t" "MOV r4, #0\n\t" @@ -27073,42 +29144,42 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( "L_sp_4096_mont_reduce_128_mul_%=:\n\t" #endif /* a[i+j+0] += m[j+0] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+1] += m[j+1] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+2] += m[j+2] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+3] += m[j+3] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "MOV r5, #0\n\t" "UMLAL r10, r5, r8, r7\n\t" "ADDS r10, r10, r4\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" "ADC r4, r5, #0\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" @@ -27120,16 +29191,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( #else "BLT.N L_sp_4096_mont_reduce_128_mul_%=\n\t" #endif - "LDR r10, [%[a], #512]\n\t" + "LDR r10, [r0, #512]\n\t" "ADDS r4, r4, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" "ADDS r10, r10, r4\n\t" "ADC r3, r3, r3\n\t" - "STR r10, [%[a], #512]\n\t" + "STR r10, [r0, #512]\n\t" /* i += 1 */ "ADD r9, r9, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r9, #0x200\n\t" #if defined(__GNUC__) "BLT L_sp_4096_mont_reduce_128_word_%=\n\t" @@ -27139,17 +29210,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( "BLT.N L_sp_4096_mont_reduce_128_word_%=\n\t" #endif /* Loop Done */ - "MOV %[mp], r3\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_4096_cond_sub_128(a - 128, a, m, (sp_digit)0 - mp); } @@ -27175,17 +29257,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* i = 0 */ "MOV r4, #0\n\t" "MOV r5, #0\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r7, [%[a], #4]\n\t" - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[a], #12]\n\t" - "LDR r10, [%[a], #16]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" + "LDR r10, [r0, #16]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_4096_mont_reduce_128_word:\n\t" @@ -27193,650 +29284,650 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( "L_sp_4096_mont_reduce_128_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL lr, %[mp], r6\n\t" + "MUL lr, r2, r6\n\t" /* a[i+0] += m[0] * mu */ - "LDR r12, [%[m]]\n\t" + "LDR r12, [r1]\n\t" "MOV r3, #0\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+1] += m[1] * mu */ - "LDR r12, [%[m], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "MOV r6, r7\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+2] += m[2] * mu */ - "LDR r12, [%[m], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "MOV r7, r8\n\t" "UMAAL r7, r3, lr, r12\n\t" /* a[i+3] += m[3] * mu */ - "LDR r12, [%[m], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "MOV r8, r9\n\t" "UMAAL r8, r3, lr, r12\n\t" /* a[i+4] += m[4] * mu */ - "LDR r12, [%[m], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "MOV r9, r10\n\t" "UMAAL r9, r3, lr, r12\n\t" /* a[i+5] += m[5] * mu */ - "LDR r12, [%[m], #20]\n\t" - "LDR r10, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR r10, [r0, #20]\n\t" "UMAAL r10, r3, lr, r12\n\t" /* a[i+6] += m[6] * mu */ - "LDR r12, [%[m], #24]\n\t" - "LDR r11, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR r11, [r0, #24]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #24]\n\t" + "STR r11, [r0, #24]\n\t" /* a[i+7] += m[7] * mu */ - "LDR r12, [%[m], #28]\n\t" - "LDR r11, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR r11, [r0, #28]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #28]\n\t" + "STR r11, [r0, #28]\n\t" /* a[i+8] += m[8] * mu */ - "LDR r12, [%[m], #32]\n\t" - "LDR r11, [%[a], #32]\n\t" + "LDR r12, [r1, #32]\n\t" + "LDR r11, [r0, #32]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #32]\n\t" + "STR r11, [r0, #32]\n\t" /* a[i+9] += m[9] * mu */ - "LDR r12, [%[m], #36]\n\t" - "LDR r11, [%[a], #36]\n\t" + "LDR r12, [r1, #36]\n\t" + "LDR r11, [r0, #36]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #36]\n\t" + "STR r11, [r0, #36]\n\t" /* a[i+10] += m[10] * mu */ - "LDR r12, [%[m], #40]\n\t" - "LDR r11, [%[a], #40]\n\t" + "LDR r12, [r1, #40]\n\t" + "LDR r11, [r0, #40]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #40]\n\t" + "STR r11, [r0, #40]\n\t" /* a[i+11] += m[11] * mu */ - "LDR r12, [%[m], #44]\n\t" - "LDR r11, [%[a], #44]\n\t" + "LDR r12, [r1, #44]\n\t" + "LDR r11, [r0, #44]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #44]\n\t" + "STR r11, [r0, #44]\n\t" /* a[i+12] += m[12] * mu */ - "LDR r12, [%[m], #48]\n\t" - "LDR r11, [%[a], #48]\n\t" + "LDR r12, [r1, #48]\n\t" + "LDR r11, [r0, #48]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #48]\n\t" + "STR r11, [r0, #48]\n\t" /* a[i+13] += m[13] * mu */ - "LDR r12, [%[m], #52]\n\t" - "LDR r11, [%[a], #52]\n\t" + "LDR r12, [r1, #52]\n\t" + "LDR r11, [r0, #52]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #52]\n\t" + "STR r11, [r0, #52]\n\t" /* a[i+14] += m[14] * mu */ - "LDR r12, [%[m], #56]\n\t" - "LDR r11, [%[a], #56]\n\t" + "LDR r12, [r1, #56]\n\t" + "LDR r11, [r0, #56]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #56]\n\t" + "STR r11, [r0, #56]\n\t" /* a[i+15] += m[15] * mu */ - "LDR r12, [%[m], #60]\n\t" - "LDR r11, [%[a], #60]\n\t" + "LDR r12, [r1, #60]\n\t" + "LDR r11, [r0, #60]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #60]\n\t" + "STR r11, [r0, #60]\n\t" /* a[i+16] += m[16] * mu */ - "LDR r12, [%[m], #64]\n\t" - "LDR r11, [%[a], #64]\n\t" + "LDR r12, [r1, #64]\n\t" + "LDR r11, [r0, #64]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #64]\n\t" + "STR r11, [r0, #64]\n\t" /* a[i+17] += m[17] * mu */ - "LDR r12, [%[m], #68]\n\t" - "LDR r11, [%[a], #68]\n\t" + "LDR r12, [r1, #68]\n\t" + "LDR r11, [r0, #68]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #68]\n\t" + "STR r11, [r0, #68]\n\t" /* a[i+18] += m[18] * mu */ - "LDR r12, [%[m], #72]\n\t" - "LDR r11, [%[a], #72]\n\t" + "LDR r12, [r1, #72]\n\t" + "LDR r11, [r0, #72]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #72]\n\t" + "STR r11, [r0, #72]\n\t" /* a[i+19] += m[19] * mu */ - "LDR r12, [%[m], #76]\n\t" - "LDR r11, [%[a], #76]\n\t" + "LDR r12, [r1, #76]\n\t" + "LDR r11, [r0, #76]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #76]\n\t" + "STR r11, [r0, #76]\n\t" /* a[i+20] += m[20] * mu */ - "LDR r12, [%[m], #80]\n\t" - "LDR r11, [%[a], #80]\n\t" + "LDR r12, [r1, #80]\n\t" + "LDR r11, [r0, #80]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #80]\n\t" + "STR r11, [r0, #80]\n\t" /* a[i+21] += m[21] * mu */ - "LDR r12, [%[m], #84]\n\t" - "LDR r11, [%[a], #84]\n\t" + "LDR r12, [r1, #84]\n\t" + "LDR r11, [r0, #84]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #84]\n\t" + "STR r11, [r0, #84]\n\t" /* a[i+22] += m[22] * mu */ - "LDR r12, [%[m], #88]\n\t" - "LDR r11, [%[a], #88]\n\t" + "LDR r12, [r1, #88]\n\t" + "LDR r11, [r0, #88]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #88]\n\t" + "STR r11, [r0, #88]\n\t" /* a[i+23] += m[23] * mu */ - "LDR r12, [%[m], #92]\n\t" - "LDR r11, [%[a], #92]\n\t" + "LDR r12, [r1, #92]\n\t" + "LDR r11, [r0, #92]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #92]\n\t" + "STR r11, [r0, #92]\n\t" /* a[i+24] += m[24] * mu */ - "LDR r12, [%[m], #96]\n\t" - "LDR r11, [%[a], #96]\n\t" + "LDR r12, [r1, #96]\n\t" + "LDR r11, [r0, #96]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #96]\n\t" + "STR r11, [r0, #96]\n\t" /* a[i+25] += m[25] * mu */ - "LDR r12, [%[m], #100]\n\t" - "LDR r11, [%[a], #100]\n\t" + "LDR r12, [r1, #100]\n\t" + "LDR r11, [r0, #100]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #100]\n\t" + "STR r11, [r0, #100]\n\t" /* a[i+26] += m[26] * mu */ - "LDR r12, [%[m], #104]\n\t" - "LDR r11, [%[a], #104]\n\t" + "LDR r12, [r1, #104]\n\t" + "LDR r11, [r0, #104]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #104]\n\t" + "STR r11, [r0, #104]\n\t" /* a[i+27] += m[27] * mu */ - "LDR r12, [%[m], #108]\n\t" - "LDR r11, [%[a], #108]\n\t" + "LDR r12, [r1, #108]\n\t" + "LDR r11, [r0, #108]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #108]\n\t" + "STR r11, [r0, #108]\n\t" /* a[i+28] += m[28] * mu */ - "LDR r12, [%[m], #112]\n\t" - "LDR r11, [%[a], #112]\n\t" + "LDR r12, [r1, #112]\n\t" + "LDR r11, [r0, #112]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #112]\n\t" + "STR r11, [r0, #112]\n\t" /* a[i+29] += m[29] * mu */ - "LDR r12, [%[m], #116]\n\t" - "LDR r11, [%[a], #116]\n\t" + "LDR r12, [r1, #116]\n\t" + "LDR r11, [r0, #116]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #116]\n\t" + "STR r11, [r0, #116]\n\t" /* a[i+30] += m[30] * mu */ - "LDR r12, [%[m], #120]\n\t" - "LDR r11, [%[a], #120]\n\t" + "LDR r12, [r1, #120]\n\t" + "LDR r11, [r0, #120]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #120]\n\t" + "STR r11, [r0, #120]\n\t" /* a[i+31] += m[31] * mu */ - "LDR r12, [%[m], #124]\n\t" - "LDR r11, [%[a], #124]\n\t" + "LDR r12, [r1, #124]\n\t" + "LDR r11, [r0, #124]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #124]\n\t" + "STR r11, [r0, #124]\n\t" /* a[i+32] += m[32] * mu */ - "LDR r12, [%[m], #128]\n\t" - "LDR r11, [%[a], #128]\n\t" + "LDR r12, [r1, #128]\n\t" + "LDR r11, [r0, #128]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #128]\n\t" + "STR r11, [r0, #128]\n\t" /* a[i+33] += m[33] * mu */ - "LDR r12, [%[m], #132]\n\t" - "LDR r11, [%[a], #132]\n\t" + "LDR r12, [r1, #132]\n\t" + "LDR r11, [r0, #132]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #132]\n\t" + "STR r11, [r0, #132]\n\t" /* a[i+34] += m[34] * mu */ - "LDR r12, [%[m], #136]\n\t" - "LDR r11, [%[a], #136]\n\t" + "LDR r12, [r1, #136]\n\t" + "LDR r11, [r0, #136]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #136]\n\t" + "STR r11, [r0, #136]\n\t" /* a[i+35] += m[35] * mu */ - "LDR r12, [%[m], #140]\n\t" - "LDR r11, [%[a], #140]\n\t" + "LDR r12, [r1, #140]\n\t" + "LDR r11, [r0, #140]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #140]\n\t" + "STR r11, [r0, #140]\n\t" /* a[i+36] += m[36] * mu */ - "LDR r12, [%[m], #144]\n\t" - "LDR r11, [%[a], #144]\n\t" + "LDR r12, [r1, #144]\n\t" + "LDR r11, [r0, #144]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #144]\n\t" + "STR r11, [r0, #144]\n\t" /* a[i+37] += m[37] * mu */ - "LDR r12, [%[m], #148]\n\t" - "LDR r11, [%[a], #148]\n\t" + "LDR r12, [r1, #148]\n\t" + "LDR r11, [r0, #148]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #148]\n\t" + "STR r11, [r0, #148]\n\t" /* a[i+38] += m[38] * mu */ - "LDR r12, [%[m], #152]\n\t" - "LDR r11, [%[a], #152]\n\t" + "LDR r12, [r1, #152]\n\t" + "LDR r11, [r0, #152]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #152]\n\t" + "STR r11, [r0, #152]\n\t" /* a[i+39] += m[39] * mu */ - "LDR r12, [%[m], #156]\n\t" - "LDR r11, [%[a], #156]\n\t" + "LDR r12, [r1, #156]\n\t" + "LDR r11, [r0, #156]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #156]\n\t" + "STR r11, [r0, #156]\n\t" /* a[i+40] += m[40] * mu */ - "LDR r12, [%[m], #160]\n\t" - "LDR r11, [%[a], #160]\n\t" + "LDR r12, [r1, #160]\n\t" + "LDR r11, [r0, #160]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #160]\n\t" + "STR r11, [r0, #160]\n\t" /* a[i+41] += m[41] * mu */ - "LDR r12, [%[m], #164]\n\t" - "LDR r11, [%[a], #164]\n\t" + "LDR r12, [r1, #164]\n\t" + "LDR r11, [r0, #164]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #164]\n\t" + "STR r11, [r0, #164]\n\t" /* a[i+42] += m[42] * mu */ - "LDR r12, [%[m], #168]\n\t" - "LDR r11, [%[a], #168]\n\t" + "LDR r12, [r1, #168]\n\t" + "LDR r11, [r0, #168]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #168]\n\t" + "STR r11, [r0, #168]\n\t" /* a[i+43] += m[43] * mu */ - "LDR r12, [%[m], #172]\n\t" - "LDR r11, [%[a], #172]\n\t" + "LDR r12, [r1, #172]\n\t" + "LDR r11, [r0, #172]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #172]\n\t" + "STR r11, [r0, #172]\n\t" /* a[i+44] += m[44] * mu */ - "LDR r12, [%[m], #176]\n\t" - "LDR r11, [%[a], #176]\n\t" + "LDR r12, [r1, #176]\n\t" + "LDR r11, [r0, #176]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #176]\n\t" + "STR r11, [r0, #176]\n\t" /* a[i+45] += m[45] * mu */ - "LDR r12, [%[m], #180]\n\t" - "LDR r11, [%[a], #180]\n\t" + "LDR r12, [r1, #180]\n\t" + "LDR r11, [r0, #180]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #180]\n\t" + "STR r11, [r0, #180]\n\t" /* a[i+46] += m[46] * mu */ - "LDR r12, [%[m], #184]\n\t" - "LDR r11, [%[a], #184]\n\t" + "LDR r12, [r1, #184]\n\t" + "LDR r11, [r0, #184]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #184]\n\t" + "STR r11, [r0, #184]\n\t" /* a[i+47] += m[47] * mu */ - "LDR r12, [%[m], #188]\n\t" - "LDR r11, [%[a], #188]\n\t" + "LDR r12, [r1, #188]\n\t" + "LDR r11, [r0, #188]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #188]\n\t" + "STR r11, [r0, #188]\n\t" /* a[i+48] += m[48] * mu */ - "LDR r12, [%[m], #192]\n\t" - "LDR r11, [%[a], #192]\n\t" + "LDR r12, [r1, #192]\n\t" + "LDR r11, [r0, #192]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #192]\n\t" + "STR r11, [r0, #192]\n\t" /* a[i+49] += m[49] * mu */ - "LDR r12, [%[m], #196]\n\t" - "LDR r11, [%[a], #196]\n\t" + "LDR r12, [r1, #196]\n\t" + "LDR r11, [r0, #196]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #196]\n\t" + "STR r11, [r0, #196]\n\t" /* a[i+50] += m[50] * mu */ - "LDR r12, [%[m], #200]\n\t" - "LDR r11, [%[a], #200]\n\t" + "LDR r12, [r1, #200]\n\t" + "LDR r11, [r0, #200]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #200]\n\t" + "STR r11, [r0, #200]\n\t" /* a[i+51] += m[51] * mu */ - "LDR r12, [%[m], #204]\n\t" - "LDR r11, [%[a], #204]\n\t" + "LDR r12, [r1, #204]\n\t" + "LDR r11, [r0, #204]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #204]\n\t" + "STR r11, [r0, #204]\n\t" /* a[i+52] += m[52] * mu */ - "LDR r12, [%[m], #208]\n\t" - "LDR r11, [%[a], #208]\n\t" + "LDR r12, [r1, #208]\n\t" + "LDR r11, [r0, #208]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #208]\n\t" + "STR r11, [r0, #208]\n\t" /* a[i+53] += m[53] * mu */ - "LDR r12, [%[m], #212]\n\t" - "LDR r11, [%[a], #212]\n\t" + "LDR r12, [r1, #212]\n\t" + "LDR r11, [r0, #212]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #212]\n\t" + "STR r11, [r0, #212]\n\t" /* a[i+54] += m[54] * mu */ - "LDR r12, [%[m], #216]\n\t" - "LDR r11, [%[a], #216]\n\t" + "LDR r12, [r1, #216]\n\t" + "LDR r11, [r0, #216]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #216]\n\t" + "STR r11, [r0, #216]\n\t" /* a[i+55] += m[55] * mu */ - "LDR r12, [%[m], #220]\n\t" - "LDR r11, [%[a], #220]\n\t" + "LDR r12, [r1, #220]\n\t" + "LDR r11, [r0, #220]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #220]\n\t" + "STR r11, [r0, #220]\n\t" /* a[i+56] += m[56] * mu */ - "LDR r12, [%[m], #224]\n\t" - "LDR r11, [%[a], #224]\n\t" + "LDR r12, [r1, #224]\n\t" + "LDR r11, [r0, #224]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #224]\n\t" + "STR r11, [r0, #224]\n\t" /* a[i+57] += m[57] * mu */ - "LDR r12, [%[m], #228]\n\t" - "LDR r11, [%[a], #228]\n\t" + "LDR r12, [r1, #228]\n\t" + "LDR r11, [r0, #228]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #228]\n\t" + "STR r11, [r0, #228]\n\t" /* a[i+58] += m[58] * mu */ - "LDR r12, [%[m], #232]\n\t" - "LDR r11, [%[a], #232]\n\t" + "LDR r12, [r1, #232]\n\t" + "LDR r11, [r0, #232]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #232]\n\t" + "STR r11, [r0, #232]\n\t" /* a[i+59] += m[59] * mu */ - "LDR r12, [%[m], #236]\n\t" - "LDR r11, [%[a], #236]\n\t" + "LDR r12, [r1, #236]\n\t" + "LDR r11, [r0, #236]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #236]\n\t" + "STR r11, [r0, #236]\n\t" /* a[i+60] += m[60] * mu */ - "LDR r12, [%[m], #240]\n\t" - "LDR r11, [%[a], #240]\n\t" + "LDR r12, [r1, #240]\n\t" + "LDR r11, [r0, #240]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #240]\n\t" + "STR r11, [r0, #240]\n\t" /* a[i+61] += m[61] * mu */ - "LDR r12, [%[m], #244]\n\t" - "LDR r11, [%[a], #244]\n\t" + "LDR r12, [r1, #244]\n\t" + "LDR r11, [r0, #244]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #244]\n\t" + "STR r11, [r0, #244]\n\t" /* a[i+62] += m[62] * mu */ - "LDR r12, [%[m], #248]\n\t" - "LDR r11, [%[a], #248]\n\t" + "LDR r12, [r1, #248]\n\t" + "LDR r11, [r0, #248]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #248]\n\t" + "STR r11, [r0, #248]\n\t" /* a[i+63] += m[63] * mu */ - "LDR r12, [%[m], #252]\n\t" - "LDR r11, [%[a], #252]\n\t" + "LDR r12, [r1, #252]\n\t" + "LDR r11, [r0, #252]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #252]\n\t" + "STR r11, [r0, #252]\n\t" /* a[i+64] += m[64] * mu */ - "LDR r12, [%[m], #256]\n\t" - "LDR r11, [%[a], #256]\n\t" + "LDR r12, [r1, #256]\n\t" + "LDR r11, [r0, #256]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #256]\n\t" + "STR r11, [r0, #256]\n\t" /* a[i+65] += m[65] * mu */ - "LDR r12, [%[m], #260]\n\t" - "LDR r11, [%[a], #260]\n\t" + "LDR r12, [r1, #260]\n\t" + "LDR r11, [r0, #260]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #260]\n\t" + "STR r11, [r0, #260]\n\t" /* a[i+66] += m[66] * mu */ - "LDR r12, [%[m], #264]\n\t" - "LDR r11, [%[a], #264]\n\t" + "LDR r12, [r1, #264]\n\t" + "LDR r11, [r0, #264]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #264]\n\t" + "STR r11, [r0, #264]\n\t" /* a[i+67] += m[67] * mu */ - "LDR r12, [%[m], #268]\n\t" - "LDR r11, [%[a], #268]\n\t" + "LDR r12, [r1, #268]\n\t" + "LDR r11, [r0, #268]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #268]\n\t" + "STR r11, [r0, #268]\n\t" /* a[i+68] += m[68] * mu */ - "LDR r12, [%[m], #272]\n\t" - "LDR r11, [%[a], #272]\n\t" + "LDR r12, [r1, #272]\n\t" + "LDR r11, [r0, #272]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #272]\n\t" + "STR r11, [r0, #272]\n\t" /* a[i+69] += m[69] * mu */ - "LDR r12, [%[m], #276]\n\t" - "LDR r11, [%[a], #276]\n\t" + "LDR r12, [r1, #276]\n\t" + "LDR r11, [r0, #276]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #276]\n\t" + "STR r11, [r0, #276]\n\t" /* a[i+70] += m[70] * mu */ - "LDR r12, [%[m], #280]\n\t" - "LDR r11, [%[a], #280]\n\t" + "LDR r12, [r1, #280]\n\t" + "LDR r11, [r0, #280]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #280]\n\t" + "STR r11, [r0, #280]\n\t" /* a[i+71] += m[71] * mu */ - "LDR r12, [%[m], #284]\n\t" - "LDR r11, [%[a], #284]\n\t" + "LDR r12, [r1, #284]\n\t" + "LDR r11, [r0, #284]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #284]\n\t" + "STR r11, [r0, #284]\n\t" /* a[i+72] += m[72] * mu */ - "LDR r12, [%[m], #288]\n\t" - "LDR r11, [%[a], #288]\n\t" + "LDR r12, [r1, #288]\n\t" + "LDR r11, [r0, #288]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #288]\n\t" + "STR r11, [r0, #288]\n\t" /* a[i+73] += m[73] * mu */ - "LDR r12, [%[m], #292]\n\t" - "LDR r11, [%[a], #292]\n\t" + "LDR r12, [r1, #292]\n\t" + "LDR r11, [r0, #292]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #292]\n\t" + "STR r11, [r0, #292]\n\t" /* a[i+74] += m[74] * mu */ - "LDR r12, [%[m], #296]\n\t" - "LDR r11, [%[a], #296]\n\t" + "LDR r12, [r1, #296]\n\t" + "LDR r11, [r0, #296]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #296]\n\t" + "STR r11, [r0, #296]\n\t" /* a[i+75] += m[75] * mu */ - "LDR r12, [%[m], #300]\n\t" - "LDR r11, [%[a], #300]\n\t" + "LDR r12, [r1, #300]\n\t" + "LDR r11, [r0, #300]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #300]\n\t" + "STR r11, [r0, #300]\n\t" /* a[i+76] += m[76] * mu */ - "LDR r12, [%[m], #304]\n\t" - "LDR r11, [%[a], #304]\n\t" + "LDR r12, [r1, #304]\n\t" + "LDR r11, [r0, #304]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #304]\n\t" + "STR r11, [r0, #304]\n\t" /* a[i+77] += m[77] * mu */ - "LDR r12, [%[m], #308]\n\t" - "LDR r11, [%[a], #308]\n\t" + "LDR r12, [r1, #308]\n\t" + "LDR r11, [r0, #308]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #308]\n\t" + "STR r11, [r0, #308]\n\t" /* a[i+78] += m[78] * mu */ - "LDR r12, [%[m], #312]\n\t" - "LDR r11, [%[a], #312]\n\t" + "LDR r12, [r1, #312]\n\t" + "LDR r11, [r0, #312]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #312]\n\t" + "STR r11, [r0, #312]\n\t" /* a[i+79] += m[79] * mu */ - "LDR r12, [%[m], #316]\n\t" - "LDR r11, [%[a], #316]\n\t" + "LDR r12, [r1, #316]\n\t" + "LDR r11, [r0, #316]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #316]\n\t" + "STR r11, [r0, #316]\n\t" /* a[i+80] += m[80] * mu */ - "LDR r12, [%[m], #320]\n\t" - "LDR r11, [%[a], #320]\n\t" + "LDR r12, [r1, #320]\n\t" + "LDR r11, [r0, #320]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #320]\n\t" + "STR r11, [r0, #320]\n\t" /* a[i+81] += m[81] * mu */ - "LDR r12, [%[m], #324]\n\t" - "LDR r11, [%[a], #324]\n\t" + "LDR r12, [r1, #324]\n\t" + "LDR r11, [r0, #324]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #324]\n\t" + "STR r11, [r0, #324]\n\t" /* a[i+82] += m[82] * mu */ - "LDR r12, [%[m], #328]\n\t" - "LDR r11, [%[a], #328]\n\t" + "LDR r12, [r1, #328]\n\t" + "LDR r11, [r0, #328]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #328]\n\t" + "STR r11, [r0, #328]\n\t" /* a[i+83] += m[83] * mu */ - "LDR r12, [%[m], #332]\n\t" - "LDR r11, [%[a], #332]\n\t" + "LDR r12, [r1, #332]\n\t" + "LDR r11, [r0, #332]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #332]\n\t" + "STR r11, [r0, #332]\n\t" /* a[i+84] += m[84] * mu */ - "LDR r12, [%[m], #336]\n\t" - "LDR r11, [%[a], #336]\n\t" + "LDR r12, [r1, #336]\n\t" + "LDR r11, [r0, #336]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #336]\n\t" + "STR r11, [r0, #336]\n\t" /* a[i+85] += m[85] * mu */ - "LDR r12, [%[m], #340]\n\t" - "LDR r11, [%[a], #340]\n\t" + "LDR r12, [r1, #340]\n\t" + "LDR r11, [r0, #340]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #340]\n\t" + "STR r11, [r0, #340]\n\t" /* a[i+86] += m[86] * mu */ - "LDR r12, [%[m], #344]\n\t" - "LDR r11, [%[a], #344]\n\t" + "LDR r12, [r1, #344]\n\t" + "LDR r11, [r0, #344]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #344]\n\t" + "STR r11, [r0, #344]\n\t" /* a[i+87] += m[87] * mu */ - "LDR r12, [%[m], #348]\n\t" - "LDR r11, [%[a], #348]\n\t" + "LDR r12, [r1, #348]\n\t" + "LDR r11, [r0, #348]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #348]\n\t" + "STR r11, [r0, #348]\n\t" /* a[i+88] += m[88] * mu */ - "LDR r12, [%[m], #352]\n\t" - "LDR r11, [%[a], #352]\n\t" + "LDR r12, [r1, #352]\n\t" + "LDR r11, [r0, #352]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #352]\n\t" + "STR r11, [r0, #352]\n\t" /* a[i+89] += m[89] * mu */ - "LDR r12, [%[m], #356]\n\t" - "LDR r11, [%[a], #356]\n\t" + "LDR r12, [r1, #356]\n\t" + "LDR r11, [r0, #356]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #356]\n\t" + "STR r11, [r0, #356]\n\t" /* a[i+90] += m[90] * mu */ - "LDR r12, [%[m], #360]\n\t" - "LDR r11, [%[a], #360]\n\t" + "LDR r12, [r1, #360]\n\t" + "LDR r11, [r0, #360]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #360]\n\t" + "STR r11, [r0, #360]\n\t" /* a[i+91] += m[91] * mu */ - "LDR r12, [%[m], #364]\n\t" - "LDR r11, [%[a], #364]\n\t" + "LDR r12, [r1, #364]\n\t" + "LDR r11, [r0, #364]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #364]\n\t" + "STR r11, [r0, #364]\n\t" /* a[i+92] += m[92] * mu */ - "LDR r12, [%[m], #368]\n\t" - "LDR r11, [%[a], #368]\n\t" + "LDR r12, [r1, #368]\n\t" + "LDR r11, [r0, #368]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #368]\n\t" + "STR r11, [r0, #368]\n\t" /* a[i+93] += m[93] * mu */ - "LDR r12, [%[m], #372]\n\t" - "LDR r11, [%[a], #372]\n\t" + "LDR r12, [r1, #372]\n\t" + "LDR r11, [r0, #372]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #372]\n\t" + "STR r11, [r0, #372]\n\t" /* a[i+94] += m[94] * mu */ - "LDR r12, [%[m], #376]\n\t" - "LDR r11, [%[a], #376]\n\t" + "LDR r12, [r1, #376]\n\t" + "LDR r11, [r0, #376]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #376]\n\t" + "STR r11, [r0, #376]\n\t" /* a[i+95] += m[95] * mu */ - "LDR r12, [%[m], #380]\n\t" - "LDR r11, [%[a], #380]\n\t" + "LDR r12, [r1, #380]\n\t" + "LDR r11, [r0, #380]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #380]\n\t" + "STR r11, [r0, #380]\n\t" /* a[i+96] += m[96] * mu */ - "LDR r12, [%[m], #384]\n\t" - "LDR r11, [%[a], #384]\n\t" + "LDR r12, [r1, #384]\n\t" + "LDR r11, [r0, #384]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #384]\n\t" + "STR r11, [r0, #384]\n\t" /* a[i+97] += m[97] * mu */ - "LDR r12, [%[m], #388]\n\t" - "LDR r11, [%[a], #388]\n\t" + "LDR r12, [r1, #388]\n\t" + "LDR r11, [r0, #388]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #388]\n\t" + "STR r11, [r0, #388]\n\t" /* a[i+98] += m[98] * mu */ - "LDR r12, [%[m], #392]\n\t" - "LDR r11, [%[a], #392]\n\t" + "LDR r12, [r1, #392]\n\t" + "LDR r11, [r0, #392]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #392]\n\t" + "STR r11, [r0, #392]\n\t" /* a[i+99] += m[99] * mu */ - "LDR r12, [%[m], #396]\n\t" - "LDR r11, [%[a], #396]\n\t" + "LDR r12, [r1, #396]\n\t" + "LDR r11, [r0, #396]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #396]\n\t" + "STR r11, [r0, #396]\n\t" /* a[i+100] += m[100] * mu */ - "LDR r12, [%[m], #400]\n\t" - "LDR r11, [%[a], #400]\n\t" + "LDR r12, [r1, #400]\n\t" + "LDR r11, [r0, #400]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #400]\n\t" + "STR r11, [r0, #400]\n\t" /* a[i+101] += m[101] * mu */ - "LDR r12, [%[m], #404]\n\t" - "LDR r11, [%[a], #404]\n\t" + "LDR r12, [r1, #404]\n\t" + "LDR r11, [r0, #404]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #404]\n\t" + "STR r11, [r0, #404]\n\t" /* a[i+102] += m[102] * mu */ - "LDR r12, [%[m], #408]\n\t" - "LDR r11, [%[a], #408]\n\t" + "LDR r12, [r1, #408]\n\t" + "LDR r11, [r0, #408]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #408]\n\t" + "STR r11, [r0, #408]\n\t" /* a[i+103] += m[103] * mu */ - "LDR r12, [%[m], #412]\n\t" - "LDR r11, [%[a], #412]\n\t" + "LDR r12, [r1, #412]\n\t" + "LDR r11, [r0, #412]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #412]\n\t" + "STR r11, [r0, #412]\n\t" /* a[i+104] += m[104] * mu */ - "LDR r12, [%[m], #416]\n\t" - "LDR r11, [%[a], #416]\n\t" + "LDR r12, [r1, #416]\n\t" + "LDR r11, [r0, #416]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #416]\n\t" + "STR r11, [r0, #416]\n\t" /* a[i+105] += m[105] * mu */ - "LDR r12, [%[m], #420]\n\t" - "LDR r11, [%[a], #420]\n\t" + "LDR r12, [r1, #420]\n\t" + "LDR r11, [r0, #420]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #420]\n\t" + "STR r11, [r0, #420]\n\t" /* a[i+106] += m[106] * mu */ - "LDR r12, [%[m], #424]\n\t" - "LDR r11, [%[a], #424]\n\t" + "LDR r12, [r1, #424]\n\t" + "LDR r11, [r0, #424]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #424]\n\t" + "STR r11, [r0, #424]\n\t" /* a[i+107] += m[107] * mu */ - "LDR r12, [%[m], #428]\n\t" - "LDR r11, [%[a], #428]\n\t" + "LDR r12, [r1, #428]\n\t" + "LDR r11, [r0, #428]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #428]\n\t" + "STR r11, [r0, #428]\n\t" /* a[i+108] += m[108] * mu */ - "LDR r12, [%[m], #432]\n\t" - "LDR r11, [%[a], #432]\n\t" + "LDR r12, [r1, #432]\n\t" + "LDR r11, [r0, #432]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #432]\n\t" + "STR r11, [r0, #432]\n\t" /* a[i+109] += m[109] * mu */ - "LDR r12, [%[m], #436]\n\t" - "LDR r11, [%[a], #436]\n\t" + "LDR r12, [r1, #436]\n\t" + "LDR r11, [r0, #436]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #436]\n\t" + "STR r11, [r0, #436]\n\t" /* a[i+110] += m[110] * mu */ - "LDR r12, [%[m], #440]\n\t" - "LDR r11, [%[a], #440]\n\t" + "LDR r12, [r1, #440]\n\t" + "LDR r11, [r0, #440]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #440]\n\t" + "STR r11, [r0, #440]\n\t" /* a[i+111] += m[111] * mu */ - "LDR r12, [%[m], #444]\n\t" - "LDR r11, [%[a], #444]\n\t" + "LDR r12, [r1, #444]\n\t" + "LDR r11, [r0, #444]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #444]\n\t" + "STR r11, [r0, #444]\n\t" /* a[i+112] += m[112] * mu */ - "LDR r12, [%[m], #448]\n\t" - "LDR r11, [%[a], #448]\n\t" + "LDR r12, [r1, #448]\n\t" + "LDR r11, [r0, #448]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #448]\n\t" + "STR r11, [r0, #448]\n\t" /* a[i+113] += m[113] * mu */ - "LDR r12, [%[m], #452]\n\t" - "LDR r11, [%[a], #452]\n\t" + "LDR r12, [r1, #452]\n\t" + "LDR r11, [r0, #452]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #452]\n\t" + "STR r11, [r0, #452]\n\t" /* a[i+114] += m[114] * mu */ - "LDR r12, [%[m], #456]\n\t" - "LDR r11, [%[a], #456]\n\t" + "LDR r12, [r1, #456]\n\t" + "LDR r11, [r0, #456]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #456]\n\t" + "STR r11, [r0, #456]\n\t" /* a[i+115] += m[115] * mu */ - "LDR r12, [%[m], #460]\n\t" - "LDR r11, [%[a], #460]\n\t" + "LDR r12, [r1, #460]\n\t" + "LDR r11, [r0, #460]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #460]\n\t" + "STR r11, [r0, #460]\n\t" /* a[i+116] += m[116] * mu */ - "LDR r12, [%[m], #464]\n\t" - "LDR r11, [%[a], #464]\n\t" + "LDR r12, [r1, #464]\n\t" + "LDR r11, [r0, #464]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #464]\n\t" + "STR r11, [r0, #464]\n\t" /* a[i+117] += m[117] * mu */ - "LDR r12, [%[m], #468]\n\t" - "LDR r11, [%[a], #468]\n\t" + "LDR r12, [r1, #468]\n\t" + "LDR r11, [r0, #468]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #468]\n\t" + "STR r11, [r0, #468]\n\t" /* a[i+118] += m[118] * mu */ - "LDR r12, [%[m], #472]\n\t" - "LDR r11, [%[a], #472]\n\t" + "LDR r12, [r1, #472]\n\t" + "LDR r11, [r0, #472]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #472]\n\t" + "STR r11, [r0, #472]\n\t" /* a[i+119] += m[119] * mu */ - "LDR r12, [%[m], #476]\n\t" - "LDR r11, [%[a], #476]\n\t" + "LDR r12, [r1, #476]\n\t" + "LDR r11, [r0, #476]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #476]\n\t" + "STR r11, [r0, #476]\n\t" /* a[i+120] += m[120] * mu */ - "LDR r12, [%[m], #480]\n\t" - "LDR r11, [%[a], #480]\n\t" + "LDR r12, [r1, #480]\n\t" + "LDR r11, [r0, #480]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #480]\n\t" + "STR r11, [r0, #480]\n\t" /* a[i+121] += m[121] * mu */ - "LDR r12, [%[m], #484]\n\t" - "LDR r11, [%[a], #484]\n\t" + "LDR r12, [r1, #484]\n\t" + "LDR r11, [r0, #484]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #484]\n\t" + "STR r11, [r0, #484]\n\t" /* a[i+122] += m[122] * mu */ - "LDR r12, [%[m], #488]\n\t" - "LDR r11, [%[a], #488]\n\t" + "LDR r12, [r1, #488]\n\t" + "LDR r11, [r0, #488]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #488]\n\t" + "STR r11, [r0, #488]\n\t" /* a[i+123] += m[123] * mu */ - "LDR r12, [%[m], #492]\n\t" - "LDR r11, [%[a], #492]\n\t" + "LDR r12, [r1, #492]\n\t" + "LDR r11, [r0, #492]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #492]\n\t" + "STR r11, [r0, #492]\n\t" /* a[i+124] += m[124] * mu */ - "LDR r12, [%[m], #496]\n\t" - "LDR r11, [%[a], #496]\n\t" + "LDR r12, [r1, #496]\n\t" + "LDR r11, [r0, #496]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #496]\n\t" + "STR r11, [r0, #496]\n\t" /* a[i+125] += m[125] * mu */ - "LDR r12, [%[m], #500]\n\t" - "LDR r11, [%[a], #500]\n\t" + "LDR r12, [r1, #500]\n\t" + "LDR r11, [r0, #500]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #500]\n\t" + "STR r11, [r0, #500]\n\t" /* a[i+126] += m[126] * mu */ - "LDR r12, [%[m], #504]\n\t" - "LDR r11, [%[a], #504]\n\t" + "LDR r12, [r1, #504]\n\t" + "LDR r11, [r0, #504]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #504]\n\t" + "STR r11, [r0, #504]\n\t" /* a[i+127] += m[127] * mu */ - "LDR r12, [%[m], #508]\n\t" - "LDR r11, [%[a], #508]\n\t" + "LDR r12, [r1, #508]\n\t" + "LDR r11, [r0, #508]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "LDR lr, [%[a], #512]\n\t" + "LDR lr, [r0, #512]\n\t" "MOV r12, #0\n\t" "UMAAL r3, lr, r12, r12\n\t" - "STR r11, [%[a], #508]\n\t" + "STR r11, [r0, #508]\n\t" "ADDS r3, r3, r5\n\t" "ADC r5, lr, #0\n\t" - "STR r3, [%[a], #512]\n\t" + "STR r3, [r0, #512]\n\t" /* i += 1 */ "ADD r4, r4, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r4, #0x200\n\t" #if defined(__GNUC__) "BLT L_sp_4096_mont_reduce_128_word_%=\n\t" @@ -27846,22 +29937,33 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( "BLT.W L_sp_4096_mont_reduce_128_word_%=\n\t" #endif /* Loop Done */ - "STR r6, [%[a]]\n\t" - "STR r7, [%[a], #4]\n\t" - "STR r8, [%[a], #8]\n\t" - "STR r9, [%[a], #12]\n\t" - "STR r10, [%[a], #16]\n\t" - "MOV %[mp], r5\n\t" + "STR r6, [r0]\n\t" + "STR r7, [r0, #4]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #12]\n\t" + "STR r10, [r0, #16]\n\t" + "MOV r2, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_4096_cond_sub_128(a - 128, a, m, (sp_digit)0 - mp); } @@ -27885,10 +29987,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r11, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r11, [r1]\n\t" /* i = 0 */ "MOV r9, #0\n\t" /* ca = 0 */ @@ -27900,8 +30011,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( "L_sp_4096_mont_reduce_128_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "LDR r10, [%[a]]\n\t" - "MUL r8, %[mp], r10\n\t" + "LDR r10, [r0]\n\t" + "MUL r8, r2, r10\n\t" /* j = 0 */ "MOV r12, #0\n\t" "MOV r4, #0\n\t" @@ -27912,31 +30023,31 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( "L_sp_4096_mont_reduce_128_mul_%=:\n\t" #endif /* a[i+j+0] += m[j+0] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+1] += m[j+1] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+2] += m[j+2] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" /* a[i+j+3] += m[j+3] * mu */ - "LDR r7, [%[m], r12]\n\t" - "LDR r10, [%[a], r12]\n\t" + "LDR r7, [r1, r12]\n\t" + "LDR r10, [r0, r12]\n\t" "UMAAL r10, r4, r8, r7\n\t" - "STR r10, [%[a], r12]\n\t" + "STR r10, [r0, r12]\n\t" /* j += 1 */ "ADD r12, r12, #4\n\t" "CMP r12, #0x200\n\t" @@ -27947,16 +30058,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( #else "BLT.N L_sp_4096_mont_reduce_128_mul_%=\n\t" #endif - "LDR r10, [%[a], #512]\n\t" + "LDR r10, [r0, #512]\n\t" "ADDS r4, r4, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" "ADDS r10, r10, r4\n\t" "ADC r3, r3, r3\n\t" - "STR r10, [%[a], #512]\n\t" + "STR r10, [r0, #512]\n\t" /* i += 1 */ "ADD r9, r9, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r9, #0x200\n\t" #if defined(__GNUC__) "BLT L_sp_4096_mont_reduce_128_word_%=\n\t" @@ -27966,17 +30077,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_4096_mont_reduce_128( "BLT.N L_sp_4096_mont_reduce_128_word_%=\n\t" #endif /* Loop Done */ - "MOV %[mp], r3\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_4096_cond_sub_128(a - 128, a, m, (sp_digit)0 - mp); } @@ -28031,11 +30153,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_sub_128(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r11, #0\n\t" - "ADD r12, %[a], #0x200\n\t" + "ADD r12, r1, #0x200\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_4096_sub_128_word:\n\t" @@ -28043,15 +30173,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_sub_128(sp_digit* r, "L_sp_4096_sub_128_word_%=:\n\t" #endif "RSBS r11, r11, #0\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "SBC r11, r3, r3\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_4096_sub_128_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -28059,17 +30189,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_sub_128(sp_digit* r, #else "BNE.N L_sp_4096_sub_128_word_%=\n\t" #endif - "MOV %[r], r11\n\t" + "MOV r0, r11\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -28092,243 +30233,262 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_sub_128(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -28356,53 +30516,73 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_4096_word_128(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r8, %[div], #16\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r8, r2, #16\n\t" "ADD r5, r8, #1\n\t" - "UDIV r6, %[d1], r5\n\t" - "LSL r7, %[div], #16\n\t" + "UDIV r6, r0, r5\n\t" + "LSL r7, r2, #16\n\t" "LSL r6, r6, #16\n\t" - "UMULL r3, r4, %[div], r6\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "SUBS r3, %[d1], r5\n\t" + "UMULL r3, r4, r2, r6\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "SUBS r3, r0, r5\n\t" "SBC r9, r9, r9\n\t" "ADD r9, r9, #1\n\t" "RSB r10, r9, #0\n\t" "LSL r9, r9, #16\n\t" "AND r7, r7, r10\n\t" "AND r8, r8, r10\n\t" - "SUBS %[d0], %[d0], r7\n\t" + "SUBS r1, r1, r7\n\t" "ADD r6, r6, r9\n\t" - "SBC %[d1], %[d1], r8\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "SBC r0, r0, r8\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "UMULL r3, r4, %[div], r3\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "UMULL r3, r4, r2, r3\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "MUL r3, %[div], r3\n\t" - "SUB %[d0], %[d0], r3\n\t" - "UDIV r3, %[d0], %[div]\n\t" - "ADD %[d1], r6, r3\n\t" + "MUL r3, r2, r3\n\t" + "SUB r1, r1, r3\n\t" + "UDIV r3, r1, r2\n\t" + "ADD r0, r6, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -28429,13 +30609,22 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_4096_word_128(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r5, %[div], #1\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r5, r2, #1\n\t" "ADD r5, r5, #1\n\t" - "MOV r6, %[d0]\n\t" - "MOV r7, %[d1]\n\t" + "MOV r6, r1\n\t" + "MOV r7, r0\n\t" /* Do top 32 */ "SUBS r8, r5, r7\n\t" "SBC r8, r8, r8\n\t" @@ -28469,29 +30658,40 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_4096_word_128(sp_digit d1, #endif "ADD r3, r3, r3\n\t" "ADD r3, r3, #1\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "SUBS r8, r9, %[div]\n\t" - "ADC %[d1], r3, #0\n\t" + "SUBS r8, r9, r2\n\t" + "ADC r0, r3, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -28620,9 +30820,17 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0xffffffff\n\t" "MOV r8, #1\n\t" "MOV r7, #0\n\t" @@ -28635,8 +30843,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, #else "L_sp_4096_cmp_128_words_%=:\n\t" #endif - "LDR r4, [%[a], r6]\n\t" - "LDR r5, [%[b], r6]\n\t" + "LDR r4, [r0, r6]\n\t" + "LDR r5, [r1, r6]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28654,8 +30862,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, #endif "EOR r2, r2, r3\n\t" #else - "LDR r4, [%[a], #508]\n\t" - "LDR r5, [%[b], #508]\n\t" + "LDR r4, [r0, #508]\n\t" + "LDR r5, [r1, #508]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28665,8 +30873,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #504]\n\t" - "LDR r5, [%[b], #504]\n\t" + "LDR r4, [r0, #504]\n\t" + "LDR r5, [r1, #504]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28676,8 +30884,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #500]\n\t" - "LDR r5, [%[b], #500]\n\t" + "LDR r4, [r0, #500]\n\t" + "LDR r5, [r1, #500]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28687,8 +30895,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #496]\n\t" - "LDR r5, [%[b], #496]\n\t" + "LDR r4, [r0, #496]\n\t" + "LDR r5, [r1, #496]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28698,8 +30906,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #492]\n\t" - "LDR r5, [%[b], #492]\n\t" + "LDR r4, [r0, #492]\n\t" + "LDR r5, [r1, #492]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28709,8 +30917,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #488]\n\t" - "LDR r5, [%[b], #488]\n\t" + "LDR r4, [r0, #488]\n\t" + "LDR r5, [r1, #488]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28720,8 +30928,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #484]\n\t" - "LDR r5, [%[b], #484]\n\t" + "LDR r4, [r0, #484]\n\t" + "LDR r5, [r1, #484]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28731,8 +30939,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #480]\n\t" - "LDR r5, [%[b], #480]\n\t" + "LDR r4, [r0, #480]\n\t" + "LDR r5, [r1, #480]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28742,8 +30950,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #476]\n\t" - "LDR r5, [%[b], #476]\n\t" + "LDR r4, [r0, #476]\n\t" + "LDR r5, [r1, #476]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28753,8 +30961,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #472]\n\t" - "LDR r5, [%[b], #472]\n\t" + "LDR r4, [r0, #472]\n\t" + "LDR r5, [r1, #472]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28764,8 +30972,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #468]\n\t" - "LDR r5, [%[b], #468]\n\t" + "LDR r4, [r0, #468]\n\t" + "LDR r5, [r1, #468]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28775,8 +30983,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #464]\n\t" - "LDR r5, [%[b], #464]\n\t" + "LDR r4, [r0, #464]\n\t" + "LDR r5, [r1, #464]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28786,8 +30994,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #460]\n\t" - "LDR r5, [%[b], #460]\n\t" + "LDR r4, [r0, #460]\n\t" + "LDR r5, [r1, #460]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28797,8 +31005,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #456]\n\t" - "LDR r5, [%[b], #456]\n\t" + "LDR r4, [r0, #456]\n\t" + "LDR r5, [r1, #456]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28808,8 +31016,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #452]\n\t" - "LDR r5, [%[b], #452]\n\t" + "LDR r4, [r0, #452]\n\t" + "LDR r5, [r1, #452]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28819,8 +31027,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #448]\n\t" - "LDR r5, [%[b], #448]\n\t" + "LDR r4, [r0, #448]\n\t" + "LDR r5, [r1, #448]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28830,8 +31038,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #444]\n\t" - "LDR r5, [%[b], #444]\n\t" + "LDR r4, [r0, #444]\n\t" + "LDR r5, [r1, #444]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28841,8 +31049,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #440]\n\t" - "LDR r5, [%[b], #440]\n\t" + "LDR r4, [r0, #440]\n\t" + "LDR r5, [r1, #440]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28852,8 +31060,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #436]\n\t" - "LDR r5, [%[b], #436]\n\t" + "LDR r4, [r0, #436]\n\t" + "LDR r5, [r1, #436]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28863,8 +31071,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #432]\n\t" - "LDR r5, [%[b], #432]\n\t" + "LDR r4, [r0, #432]\n\t" + "LDR r5, [r1, #432]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28874,8 +31082,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #428]\n\t" - "LDR r5, [%[b], #428]\n\t" + "LDR r4, [r0, #428]\n\t" + "LDR r5, [r1, #428]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28885,8 +31093,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #424]\n\t" - "LDR r5, [%[b], #424]\n\t" + "LDR r4, [r0, #424]\n\t" + "LDR r5, [r1, #424]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28896,8 +31104,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #420]\n\t" - "LDR r5, [%[b], #420]\n\t" + "LDR r4, [r0, #420]\n\t" + "LDR r5, [r1, #420]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28907,8 +31115,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #416]\n\t" - "LDR r5, [%[b], #416]\n\t" + "LDR r4, [r0, #416]\n\t" + "LDR r5, [r1, #416]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28918,8 +31126,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #412]\n\t" - "LDR r5, [%[b], #412]\n\t" + "LDR r4, [r0, #412]\n\t" + "LDR r5, [r1, #412]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28929,8 +31137,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #408]\n\t" - "LDR r5, [%[b], #408]\n\t" + "LDR r4, [r0, #408]\n\t" + "LDR r5, [r1, #408]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28940,8 +31148,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #404]\n\t" - "LDR r5, [%[b], #404]\n\t" + "LDR r4, [r0, #404]\n\t" + "LDR r5, [r1, #404]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28951,8 +31159,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #400]\n\t" - "LDR r5, [%[b], #400]\n\t" + "LDR r4, [r0, #400]\n\t" + "LDR r5, [r1, #400]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28962,8 +31170,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #396]\n\t" - "LDR r5, [%[b], #396]\n\t" + "LDR r4, [r0, #396]\n\t" + "LDR r5, [r1, #396]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28973,8 +31181,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #392]\n\t" - "LDR r5, [%[b], #392]\n\t" + "LDR r4, [r0, #392]\n\t" + "LDR r5, [r1, #392]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28984,8 +31192,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #388]\n\t" - "LDR r5, [%[b], #388]\n\t" + "LDR r4, [r0, #388]\n\t" + "LDR r5, [r1, #388]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -28995,8 +31203,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #384]\n\t" - "LDR r5, [%[b], #384]\n\t" + "LDR r4, [r0, #384]\n\t" + "LDR r5, [r1, #384]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29006,8 +31214,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #380]\n\t" - "LDR r5, [%[b], #380]\n\t" + "LDR r4, [r0, #380]\n\t" + "LDR r5, [r1, #380]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29017,8 +31225,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #376]\n\t" - "LDR r5, [%[b], #376]\n\t" + "LDR r4, [r0, #376]\n\t" + "LDR r5, [r1, #376]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29028,8 +31236,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #372]\n\t" - "LDR r5, [%[b], #372]\n\t" + "LDR r4, [r0, #372]\n\t" + "LDR r5, [r1, #372]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29039,8 +31247,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #368]\n\t" - "LDR r5, [%[b], #368]\n\t" + "LDR r4, [r0, #368]\n\t" + "LDR r5, [r1, #368]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29050,8 +31258,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #364]\n\t" - "LDR r5, [%[b], #364]\n\t" + "LDR r4, [r0, #364]\n\t" + "LDR r5, [r1, #364]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29061,8 +31269,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #360]\n\t" - "LDR r5, [%[b], #360]\n\t" + "LDR r4, [r0, #360]\n\t" + "LDR r5, [r1, #360]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29072,8 +31280,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #356]\n\t" - "LDR r5, [%[b], #356]\n\t" + "LDR r4, [r0, #356]\n\t" + "LDR r5, [r1, #356]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29083,8 +31291,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #352]\n\t" - "LDR r5, [%[b], #352]\n\t" + "LDR r4, [r0, #352]\n\t" + "LDR r5, [r1, #352]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29094,8 +31302,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #348]\n\t" - "LDR r5, [%[b], #348]\n\t" + "LDR r4, [r0, #348]\n\t" + "LDR r5, [r1, #348]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29105,8 +31313,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #344]\n\t" - "LDR r5, [%[b], #344]\n\t" + "LDR r4, [r0, #344]\n\t" + "LDR r5, [r1, #344]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29116,8 +31324,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #340]\n\t" - "LDR r5, [%[b], #340]\n\t" + "LDR r4, [r0, #340]\n\t" + "LDR r5, [r1, #340]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29127,8 +31335,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #336]\n\t" - "LDR r5, [%[b], #336]\n\t" + "LDR r4, [r0, #336]\n\t" + "LDR r5, [r1, #336]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29138,8 +31346,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #332]\n\t" - "LDR r5, [%[b], #332]\n\t" + "LDR r4, [r0, #332]\n\t" + "LDR r5, [r1, #332]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29149,8 +31357,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #328]\n\t" - "LDR r5, [%[b], #328]\n\t" + "LDR r4, [r0, #328]\n\t" + "LDR r5, [r1, #328]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29160,8 +31368,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #324]\n\t" - "LDR r5, [%[b], #324]\n\t" + "LDR r4, [r0, #324]\n\t" + "LDR r5, [r1, #324]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29171,8 +31379,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #320]\n\t" - "LDR r5, [%[b], #320]\n\t" + "LDR r4, [r0, #320]\n\t" + "LDR r5, [r1, #320]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29182,8 +31390,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #316]\n\t" - "LDR r5, [%[b], #316]\n\t" + "LDR r4, [r0, #316]\n\t" + "LDR r5, [r1, #316]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29193,8 +31401,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #312]\n\t" - "LDR r5, [%[b], #312]\n\t" + "LDR r4, [r0, #312]\n\t" + "LDR r5, [r1, #312]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29204,8 +31412,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #308]\n\t" - "LDR r5, [%[b], #308]\n\t" + "LDR r4, [r0, #308]\n\t" + "LDR r5, [r1, #308]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29215,8 +31423,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #304]\n\t" - "LDR r5, [%[b], #304]\n\t" + "LDR r4, [r0, #304]\n\t" + "LDR r5, [r1, #304]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29226,8 +31434,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #300]\n\t" - "LDR r5, [%[b], #300]\n\t" + "LDR r4, [r0, #300]\n\t" + "LDR r5, [r1, #300]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29237,8 +31445,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #296]\n\t" - "LDR r5, [%[b], #296]\n\t" + "LDR r4, [r0, #296]\n\t" + "LDR r5, [r1, #296]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29248,8 +31456,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #292]\n\t" - "LDR r5, [%[b], #292]\n\t" + "LDR r4, [r0, #292]\n\t" + "LDR r5, [r1, #292]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29259,8 +31467,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #288]\n\t" - "LDR r5, [%[b], #288]\n\t" + "LDR r4, [r0, #288]\n\t" + "LDR r5, [r1, #288]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29270,8 +31478,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #284]\n\t" - "LDR r5, [%[b], #284]\n\t" + "LDR r4, [r0, #284]\n\t" + "LDR r5, [r1, #284]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29281,8 +31489,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #280]\n\t" - "LDR r5, [%[b], #280]\n\t" + "LDR r4, [r0, #280]\n\t" + "LDR r5, [r1, #280]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29292,8 +31500,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #276]\n\t" - "LDR r5, [%[b], #276]\n\t" + "LDR r4, [r0, #276]\n\t" + "LDR r5, [r1, #276]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29303,8 +31511,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #272]\n\t" - "LDR r5, [%[b], #272]\n\t" + "LDR r4, [r0, #272]\n\t" + "LDR r5, [r1, #272]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29314,8 +31522,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #268]\n\t" - "LDR r5, [%[b], #268]\n\t" + "LDR r4, [r0, #268]\n\t" + "LDR r5, [r1, #268]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29325,8 +31533,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #264]\n\t" - "LDR r5, [%[b], #264]\n\t" + "LDR r4, [r0, #264]\n\t" + "LDR r5, [r1, #264]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29336,8 +31544,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #260]\n\t" - "LDR r5, [%[b], #260]\n\t" + "LDR r4, [r0, #260]\n\t" + "LDR r5, [r1, #260]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29347,8 +31555,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #256]\n\t" - "LDR r5, [%[b], #256]\n\t" + "LDR r4, [r0, #256]\n\t" + "LDR r5, [r1, #256]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29358,8 +31566,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #252]\n\t" - "LDR r5, [%[b], #252]\n\t" + "LDR r4, [r0, #252]\n\t" + "LDR r5, [r1, #252]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29369,8 +31577,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #248]\n\t" - "LDR r5, [%[b], #248]\n\t" + "LDR r4, [r0, #248]\n\t" + "LDR r5, [r1, #248]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29380,8 +31588,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #244]\n\t" - "LDR r5, [%[b], #244]\n\t" + "LDR r4, [r0, #244]\n\t" + "LDR r5, [r1, #244]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29391,8 +31599,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #240]\n\t" - "LDR r5, [%[b], #240]\n\t" + "LDR r4, [r0, #240]\n\t" + "LDR r5, [r1, #240]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29402,8 +31610,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #236]\n\t" - "LDR r5, [%[b], #236]\n\t" + "LDR r4, [r0, #236]\n\t" + "LDR r5, [r1, #236]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29413,8 +31621,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #232]\n\t" - "LDR r5, [%[b], #232]\n\t" + "LDR r4, [r0, #232]\n\t" + "LDR r5, [r1, #232]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29424,8 +31632,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #228]\n\t" - "LDR r5, [%[b], #228]\n\t" + "LDR r4, [r0, #228]\n\t" + "LDR r5, [r1, #228]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29435,8 +31643,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #224]\n\t" - "LDR r5, [%[b], #224]\n\t" + "LDR r4, [r0, #224]\n\t" + "LDR r5, [r1, #224]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29446,8 +31654,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #220]\n\t" - "LDR r5, [%[b], #220]\n\t" + "LDR r4, [r0, #220]\n\t" + "LDR r5, [r1, #220]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29457,8 +31665,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #216]\n\t" - "LDR r5, [%[b], #216]\n\t" + "LDR r4, [r0, #216]\n\t" + "LDR r5, [r1, #216]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29468,8 +31676,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #212]\n\t" - "LDR r5, [%[b], #212]\n\t" + "LDR r4, [r0, #212]\n\t" + "LDR r5, [r1, #212]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29479,8 +31687,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #208]\n\t" - "LDR r5, [%[b], #208]\n\t" + "LDR r4, [r0, #208]\n\t" + "LDR r5, [r1, #208]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29490,8 +31698,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #204]\n\t" - "LDR r5, [%[b], #204]\n\t" + "LDR r4, [r0, #204]\n\t" + "LDR r5, [r1, #204]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29501,8 +31709,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #200]\n\t" - "LDR r5, [%[b], #200]\n\t" + "LDR r4, [r0, #200]\n\t" + "LDR r5, [r1, #200]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29512,8 +31720,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #196]\n\t" - "LDR r5, [%[b], #196]\n\t" + "LDR r4, [r0, #196]\n\t" + "LDR r5, [r1, #196]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29523,8 +31731,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #192]\n\t" - "LDR r5, [%[b], #192]\n\t" + "LDR r4, [r0, #192]\n\t" + "LDR r5, [r1, #192]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29534,8 +31742,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #188]\n\t" - "LDR r5, [%[b], #188]\n\t" + "LDR r4, [r0, #188]\n\t" + "LDR r5, [r1, #188]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29545,8 +31753,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #184]\n\t" - "LDR r5, [%[b], #184]\n\t" + "LDR r4, [r0, #184]\n\t" + "LDR r5, [r1, #184]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29556,8 +31764,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #180]\n\t" - "LDR r5, [%[b], #180]\n\t" + "LDR r4, [r0, #180]\n\t" + "LDR r5, [r1, #180]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29567,8 +31775,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #176]\n\t" - "LDR r5, [%[b], #176]\n\t" + "LDR r4, [r0, #176]\n\t" + "LDR r5, [r1, #176]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29578,8 +31786,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #172]\n\t" - "LDR r5, [%[b], #172]\n\t" + "LDR r4, [r0, #172]\n\t" + "LDR r5, [r1, #172]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29589,8 +31797,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #168]\n\t" - "LDR r5, [%[b], #168]\n\t" + "LDR r4, [r0, #168]\n\t" + "LDR r5, [r1, #168]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29600,8 +31808,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #164]\n\t" - "LDR r5, [%[b], #164]\n\t" + "LDR r4, [r0, #164]\n\t" + "LDR r5, [r1, #164]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29611,8 +31819,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #160]\n\t" - "LDR r5, [%[b], #160]\n\t" + "LDR r4, [r0, #160]\n\t" + "LDR r5, [r1, #160]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29622,8 +31830,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #156]\n\t" - "LDR r5, [%[b], #156]\n\t" + "LDR r4, [r0, #156]\n\t" + "LDR r5, [r1, #156]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29633,8 +31841,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #152]\n\t" - "LDR r5, [%[b], #152]\n\t" + "LDR r4, [r0, #152]\n\t" + "LDR r5, [r1, #152]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29644,8 +31852,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #148]\n\t" - "LDR r5, [%[b], #148]\n\t" + "LDR r4, [r0, #148]\n\t" + "LDR r5, [r1, #148]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29655,8 +31863,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #144]\n\t" - "LDR r5, [%[b], #144]\n\t" + "LDR r4, [r0, #144]\n\t" + "LDR r5, [r1, #144]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29666,8 +31874,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #140]\n\t" - "LDR r5, [%[b], #140]\n\t" + "LDR r4, [r0, #140]\n\t" + "LDR r5, [r1, #140]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29677,8 +31885,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #136]\n\t" - "LDR r5, [%[b], #136]\n\t" + "LDR r4, [r0, #136]\n\t" + "LDR r5, [r1, #136]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29688,8 +31896,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #132]\n\t" - "LDR r5, [%[b], #132]\n\t" + "LDR r4, [r0, #132]\n\t" + "LDR r5, [r1, #132]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29699,8 +31907,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #128]\n\t" - "LDR r5, [%[b], #128]\n\t" + "LDR r4, [r0, #128]\n\t" + "LDR r5, [r1, #128]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29710,8 +31918,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #124]\n\t" - "LDR r5, [%[b], #124]\n\t" + "LDR r4, [r0, #124]\n\t" + "LDR r5, [r1, #124]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29721,8 +31929,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #120]\n\t" - "LDR r5, [%[b], #120]\n\t" + "LDR r4, [r0, #120]\n\t" + "LDR r5, [r1, #120]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29732,8 +31940,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #116]\n\t" - "LDR r5, [%[b], #116]\n\t" + "LDR r4, [r0, #116]\n\t" + "LDR r5, [r1, #116]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29743,8 +31951,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #112]\n\t" - "LDR r5, [%[b], #112]\n\t" + "LDR r4, [r0, #112]\n\t" + "LDR r5, [r1, #112]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29754,8 +31962,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #108]\n\t" - "LDR r5, [%[b], #108]\n\t" + "LDR r4, [r0, #108]\n\t" + "LDR r5, [r1, #108]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29765,8 +31973,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #104]\n\t" - "LDR r5, [%[b], #104]\n\t" + "LDR r4, [r0, #104]\n\t" + "LDR r5, [r1, #104]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29776,8 +31984,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #100]\n\t" - "LDR r5, [%[b], #100]\n\t" + "LDR r4, [r0, #100]\n\t" + "LDR r5, [r1, #100]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29787,8 +31995,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #96]\n\t" - "LDR r5, [%[b], #96]\n\t" + "LDR r4, [r0, #96]\n\t" + "LDR r5, [r1, #96]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29798,8 +32006,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #92]\n\t" - "LDR r5, [%[b], #92]\n\t" + "LDR r4, [r0, #92]\n\t" + "LDR r5, [r1, #92]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29809,8 +32017,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #88]\n\t" - "LDR r5, [%[b], #88]\n\t" + "LDR r4, [r0, #88]\n\t" + "LDR r5, [r1, #88]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29820,8 +32028,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #84]\n\t" - "LDR r5, [%[b], #84]\n\t" + "LDR r4, [r0, #84]\n\t" + "LDR r5, [r1, #84]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29831,8 +32039,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #80]\n\t" - "LDR r5, [%[b], #80]\n\t" + "LDR r4, [r0, #80]\n\t" + "LDR r5, [r1, #80]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29842,8 +32050,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #76]\n\t" - "LDR r5, [%[b], #76]\n\t" + "LDR r4, [r0, #76]\n\t" + "LDR r5, [r1, #76]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29853,8 +32061,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #72]\n\t" - "LDR r5, [%[b], #72]\n\t" + "LDR r4, [r0, #72]\n\t" + "LDR r5, [r1, #72]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29864,8 +32072,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #68]\n\t" - "LDR r5, [%[b], #68]\n\t" + "LDR r4, [r0, #68]\n\t" + "LDR r5, [r1, #68]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29875,8 +32083,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #64]\n\t" - "LDR r5, [%[b], #64]\n\t" + "LDR r4, [r0, #64]\n\t" + "LDR r5, [r1, #64]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29886,8 +32094,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #60]\n\t" - "LDR r5, [%[b], #60]\n\t" + "LDR r4, [r0, #60]\n\t" + "LDR r5, [r1, #60]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29897,8 +32105,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #56]\n\t" - "LDR r5, [%[b], #56]\n\t" + "LDR r4, [r0, #56]\n\t" + "LDR r5, [r1, #56]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29908,8 +32116,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #52]\n\t" - "LDR r5, [%[b], #52]\n\t" + "LDR r4, [r0, #52]\n\t" + "LDR r5, [r1, #52]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29919,8 +32127,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #48]\n\t" - "LDR r5, [%[b], #48]\n\t" + "LDR r4, [r0, #48]\n\t" + "LDR r5, [r1, #48]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29930,8 +32138,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #44]\n\t" - "LDR r5, [%[b], #44]\n\t" + "LDR r4, [r0, #44]\n\t" + "LDR r5, [r1, #44]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29941,8 +32149,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #40]\n\t" - "LDR r5, [%[b], #40]\n\t" + "LDR r4, [r0, #40]\n\t" + "LDR r5, [r1, #40]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29952,8 +32160,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #36]\n\t" - "LDR r5, [%[b], #36]\n\t" + "LDR r4, [r0, #36]\n\t" + "LDR r5, [r1, #36]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29963,8 +32171,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #32]\n\t" - "LDR r5, [%[b], #32]\n\t" + "LDR r4, [r0, #32]\n\t" + "LDR r5, [r1, #32]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29974,8 +32182,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #28]\n\t" - "LDR r5, [%[b], #28]\n\t" + "LDR r4, [r0, #28]\n\t" + "LDR r5, [r1, #28]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29985,8 +32193,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #24]\n\t" - "LDR r5, [%[b], #24]\n\t" + "LDR r4, [r0, #24]\n\t" + "LDR r5, [r1, #24]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -29996,8 +32204,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #20]\n\t" - "LDR r5, [%[b], #20]\n\t" + "LDR r4, [r0, #20]\n\t" + "LDR r5, [r1, #20]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -30007,8 +32215,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #16]\n\t" - "LDR r5, [%[b], #16]\n\t" + "LDR r4, [r0, #16]\n\t" + "LDR r5, [r1, #16]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -30018,8 +32226,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #12]\n\t" - "LDR r5, [%[b], #12]\n\t" + "LDR r4, [r0, #12]\n\t" + "LDR r5, [r1, #12]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -30029,8 +32237,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #8]\n\t" - "LDR r5, [%[b], #8]\n\t" + "LDR r4, [r0, #8]\n\t" + "LDR r5, [r1, #8]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -30040,8 +32248,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #4]\n\t" - "LDR r5, [%[b], #4]\n\t" + "LDR r4, [r0, #4]\n\t" + "LDR r5, [r1, #4]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -30051,8 +32259,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[b]]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r1]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -30064,16 +32272,26 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_4096_cmp_128(const sp_digit* a, "movne r3, r7\n\t" "EOR r2, r2, r3\n\t" #endif /*WOLFSSL_SP_SMALL */ - "MOV %[a], r2\n\t" + "MOV r0, r2\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -30587,9 +32805,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_cond_add_64(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" "MOV r8, #0\n\t" "MOV r4, #0\n\t" @@ -30600,12 +32827,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_cond_add_64(sp_digit* r, "L_sp_4096_cond_add_64_words_%=:\n\t" #endif "ADDS r5, r5, #0xffffffff\n\t" - "LDR r6, [%[a], r4]\n\t" - "LDR r7, [%[b], r4]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r4]\n\t" + "LDR r7, [r2, r4]\n\t" + "AND r7, r7, r3\n\t" "ADCS r6, r6, r7\n\t" "ADC r5, r8, r8\n\t" - "STR r6, [%[r], r4]\n\t" + "STR r6, [r0, r4]\n\t" "ADD r4, r4, #4\n\t" "CMP r4, #0x100\n\t" #if defined(__GNUC__) @@ -30615,16 +32842,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_cond_add_64(sp_digit* r, #else "BLT.N L_sp_4096_cond_add_64_words_%=\n\t" #endif - "MOV %[r], r5\n\t" + "MOV r0, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -30651,244 +32890,265 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_4096_cond_add_64(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADDS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "ADC %[r], r10, r10\n\t" + "STM r0!, {r6, r7}\n\t" + "ADC r0, r10, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -31190,787 +33450,806 @@ WC_OMIT_FRAME_POINTER static void sp_4096_lshift_128(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register byte n __asm__ ("r2") = (byte)n_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)n + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "RSB r7, %[n], #31\n\t" - "LDR r5, [%[a], #508]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "RSB r7, r2, #31\n\t" + "LDR r5, [r1, #508]\n\t" "LSR r6, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r6, r6, r7\n\t" - "LDR r4, [%[a], #504]\n\t" - "STR r6, [%[r], #512]\n\t" + "LDR r4, [r1, #504]\n\t" + "STR r6, [r0, #512]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #500]\n\t" - "STR r5, [%[r], #508]\n\t" + "LDR r6, [r1, #500]\n\t" + "STR r5, [r0, #508]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #496]\n\t" - "STR r4, [%[r], #504]\n\t" + "LDR r5, [r1, #496]\n\t" + "STR r4, [r0, #504]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #492]\n\t" - "STR r6, [%[r], #500]\n\t" + "LDR r4, [r1, #492]\n\t" + "STR r6, [r0, #500]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #488]\n\t" - "STR r5, [%[r], #496]\n\t" + "LDR r6, [r1, #488]\n\t" + "STR r5, [r0, #496]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #484]\n\t" - "STR r4, [%[r], #492]\n\t" + "LDR r5, [r1, #484]\n\t" + "STR r4, [r0, #492]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #480]\n\t" - "STR r6, [%[r], #488]\n\t" + "LDR r4, [r1, #480]\n\t" + "STR r6, [r0, #488]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #476]\n\t" - "STR r5, [%[r], #484]\n\t" + "LDR r6, [r1, #476]\n\t" + "STR r5, [r0, #484]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #472]\n\t" - "STR r4, [%[r], #480]\n\t" + "LDR r5, [r1, #472]\n\t" + "STR r4, [r0, #480]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #468]\n\t" - "STR r6, [%[r], #476]\n\t" + "LDR r4, [r1, #468]\n\t" + "STR r6, [r0, #476]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #464]\n\t" - "STR r5, [%[r], #472]\n\t" + "LDR r6, [r1, #464]\n\t" + "STR r5, [r0, #472]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #460]\n\t" - "STR r4, [%[r], #468]\n\t" + "LDR r5, [r1, #460]\n\t" + "STR r4, [r0, #468]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #456]\n\t" - "STR r6, [%[r], #464]\n\t" + "LDR r4, [r1, #456]\n\t" + "STR r6, [r0, #464]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #452]\n\t" - "STR r5, [%[r], #460]\n\t" + "LDR r6, [r1, #452]\n\t" + "STR r5, [r0, #460]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #448]\n\t" - "STR r4, [%[r], #456]\n\t" + "LDR r5, [r1, #448]\n\t" + "STR r4, [r0, #456]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #444]\n\t" - "STR r6, [%[r], #452]\n\t" + "LDR r4, [r1, #444]\n\t" + "STR r6, [r0, #452]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #440]\n\t" - "STR r5, [%[r], #448]\n\t" + "LDR r6, [r1, #440]\n\t" + "STR r5, [r0, #448]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #436]\n\t" - "STR r4, [%[r], #444]\n\t" + "LDR r5, [r1, #436]\n\t" + "STR r4, [r0, #444]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #432]\n\t" - "STR r6, [%[r], #440]\n\t" + "LDR r4, [r1, #432]\n\t" + "STR r6, [r0, #440]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #428]\n\t" - "STR r5, [%[r], #436]\n\t" + "LDR r6, [r1, #428]\n\t" + "STR r5, [r0, #436]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #424]\n\t" - "STR r4, [%[r], #432]\n\t" + "LDR r5, [r1, #424]\n\t" + "STR r4, [r0, #432]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #420]\n\t" - "STR r6, [%[r], #428]\n\t" + "LDR r4, [r1, #420]\n\t" + "STR r6, [r0, #428]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #416]\n\t" - "STR r5, [%[r], #424]\n\t" + "LDR r6, [r1, #416]\n\t" + "STR r5, [r0, #424]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #412]\n\t" - "STR r4, [%[r], #420]\n\t" + "LDR r5, [r1, #412]\n\t" + "STR r4, [r0, #420]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #408]\n\t" - "STR r6, [%[r], #416]\n\t" + "LDR r4, [r1, #408]\n\t" + "STR r6, [r0, #416]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #404]\n\t" - "STR r5, [%[r], #412]\n\t" + "LDR r6, [r1, #404]\n\t" + "STR r5, [r0, #412]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #400]\n\t" - "STR r4, [%[r], #408]\n\t" + "LDR r5, [r1, #400]\n\t" + "STR r4, [r0, #408]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #396]\n\t" - "STR r6, [%[r], #404]\n\t" + "LDR r4, [r1, #396]\n\t" + "STR r6, [r0, #404]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #392]\n\t" - "STR r5, [%[r], #400]\n\t" + "LDR r6, [r1, #392]\n\t" + "STR r5, [r0, #400]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #388]\n\t" - "STR r4, [%[r], #396]\n\t" + "LDR r5, [r1, #388]\n\t" + "STR r4, [r0, #396]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #384]\n\t" - "STR r6, [%[r], #392]\n\t" + "LDR r4, [r1, #384]\n\t" + "STR r6, [r0, #392]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #380]\n\t" - "STR r5, [%[r], #388]\n\t" + "LDR r6, [r1, #380]\n\t" + "STR r5, [r0, #388]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #376]\n\t" - "STR r4, [%[r], #384]\n\t" + "LDR r5, [r1, #376]\n\t" + "STR r4, [r0, #384]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #372]\n\t" - "STR r6, [%[r], #380]\n\t" + "LDR r4, [r1, #372]\n\t" + "STR r6, [r0, #380]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #368]\n\t" - "STR r5, [%[r], #376]\n\t" + "LDR r6, [r1, #368]\n\t" + "STR r5, [r0, #376]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #364]\n\t" - "STR r4, [%[r], #372]\n\t" + "LDR r5, [r1, #364]\n\t" + "STR r4, [r0, #372]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #360]\n\t" - "STR r6, [%[r], #368]\n\t" + "LDR r4, [r1, #360]\n\t" + "STR r6, [r0, #368]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #356]\n\t" - "STR r5, [%[r], #364]\n\t" + "LDR r6, [r1, #356]\n\t" + "STR r5, [r0, #364]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #352]\n\t" - "STR r4, [%[r], #360]\n\t" + "LDR r5, [r1, #352]\n\t" + "STR r4, [r0, #360]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #348]\n\t" - "STR r6, [%[r], #356]\n\t" + "LDR r4, [r1, #348]\n\t" + "STR r6, [r0, #356]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #344]\n\t" - "STR r5, [%[r], #352]\n\t" + "LDR r6, [r1, #344]\n\t" + "STR r5, [r0, #352]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #340]\n\t" - "STR r4, [%[r], #348]\n\t" + "LDR r5, [r1, #340]\n\t" + "STR r4, [r0, #348]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #336]\n\t" - "STR r6, [%[r], #344]\n\t" + "LDR r4, [r1, #336]\n\t" + "STR r6, [r0, #344]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #332]\n\t" - "STR r5, [%[r], #340]\n\t" + "LDR r6, [r1, #332]\n\t" + "STR r5, [r0, #340]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #328]\n\t" - "STR r4, [%[r], #336]\n\t" + "LDR r5, [r1, #328]\n\t" + "STR r4, [r0, #336]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #324]\n\t" - "STR r6, [%[r], #332]\n\t" + "LDR r4, [r1, #324]\n\t" + "STR r6, [r0, #332]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #320]\n\t" - "STR r5, [%[r], #328]\n\t" + "LDR r6, [r1, #320]\n\t" + "STR r5, [r0, #328]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #316]\n\t" - "STR r4, [%[r], #324]\n\t" + "LDR r5, [r1, #316]\n\t" + "STR r4, [r0, #324]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #312]\n\t" - "STR r6, [%[r], #320]\n\t" + "LDR r4, [r1, #312]\n\t" + "STR r6, [r0, #320]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #308]\n\t" - "STR r5, [%[r], #316]\n\t" + "LDR r6, [r1, #308]\n\t" + "STR r5, [r0, #316]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #304]\n\t" - "STR r4, [%[r], #312]\n\t" + "LDR r5, [r1, #304]\n\t" + "STR r4, [r0, #312]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #300]\n\t" - "STR r6, [%[r], #308]\n\t" + "LDR r4, [r1, #300]\n\t" + "STR r6, [r0, #308]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #296]\n\t" - "STR r5, [%[r], #304]\n\t" + "LDR r6, [r1, #296]\n\t" + "STR r5, [r0, #304]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #292]\n\t" - "STR r4, [%[r], #300]\n\t" + "LDR r5, [r1, #292]\n\t" + "STR r4, [r0, #300]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #288]\n\t" - "STR r6, [%[r], #296]\n\t" + "LDR r4, [r1, #288]\n\t" + "STR r6, [r0, #296]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #284]\n\t" - "STR r5, [%[r], #292]\n\t" + "LDR r6, [r1, #284]\n\t" + "STR r5, [r0, #292]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #280]\n\t" - "STR r4, [%[r], #288]\n\t" + "LDR r5, [r1, #280]\n\t" + "STR r4, [r0, #288]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #276]\n\t" - "STR r6, [%[r], #284]\n\t" + "LDR r4, [r1, #276]\n\t" + "STR r6, [r0, #284]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #272]\n\t" - "STR r5, [%[r], #280]\n\t" + "LDR r6, [r1, #272]\n\t" + "STR r5, [r0, #280]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #268]\n\t" - "STR r4, [%[r], #276]\n\t" + "LDR r5, [r1, #268]\n\t" + "STR r4, [r0, #276]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #264]\n\t" - "STR r6, [%[r], #272]\n\t" + "LDR r4, [r1, #264]\n\t" + "STR r6, [r0, #272]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #260]\n\t" - "STR r5, [%[r], #268]\n\t" + "LDR r6, [r1, #260]\n\t" + "STR r5, [r0, #268]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #256]\n\t" - "STR r4, [%[r], #264]\n\t" + "LDR r5, [r1, #256]\n\t" + "STR r4, [r0, #264]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #252]\n\t" - "STR r6, [%[r], #260]\n\t" + "LDR r4, [r1, #252]\n\t" + "STR r6, [r0, #260]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #248]\n\t" - "STR r5, [%[r], #256]\n\t" + "LDR r6, [r1, #248]\n\t" + "STR r5, [r0, #256]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #244]\n\t" - "STR r4, [%[r], #252]\n\t" + "LDR r5, [r1, #244]\n\t" + "STR r4, [r0, #252]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #240]\n\t" - "STR r6, [%[r], #248]\n\t" + "LDR r4, [r1, #240]\n\t" + "STR r6, [r0, #248]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #236]\n\t" - "STR r5, [%[r], #244]\n\t" + "LDR r6, [r1, #236]\n\t" + "STR r5, [r0, #244]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #232]\n\t" - "STR r4, [%[r], #240]\n\t" + "LDR r5, [r1, #232]\n\t" + "STR r4, [r0, #240]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #228]\n\t" - "STR r6, [%[r], #236]\n\t" + "LDR r4, [r1, #228]\n\t" + "STR r6, [r0, #236]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #224]\n\t" - "STR r5, [%[r], #232]\n\t" + "LDR r6, [r1, #224]\n\t" + "STR r5, [r0, #232]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #220]\n\t" - "STR r4, [%[r], #228]\n\t" + "LDR r5, [r1, #220]\n\t" + "STR r4, [r0, #228]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #216]\n\t" - "STR r6, [%[r], #224]\n\t" + "LDR r4, [r1, #216]\n\t" + "STR r6, [r0, #224]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #212]\n\t" - "STR r5, [%[r], #220]\n\t" + "LDR r6, [r1, #212]\n\t" + "STR r5, [r0, #220]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #208]\n\t" - "STR r4, [%[r], #216]\n\t" + "LDR r5, [r1, #208]\n\t" + "STR r4, [r0, #216]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #204]\n\t" - "STR r6, [%[r], #212]\n\t" + "LDR r4, [r1, #204]\n\t" + "STR r6, [r0, #212]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #200]\n\t" - "STR r5, [%[r], #208]\n\t" + "LDR r6, [r1, #200]\n\t" + "STR r5, [r0, #208]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #196]\n\t" - "STR r4, [%[r], #204]\n\t" + "LDR r5, [r1, #196]\n\t" + "STR r4, [r0, #204]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #192]\n\t" - "STR r6, [%[r], #200]\n\t" + "LDR r4, [r1, #192]\n\t" + "STR r6, [r0, #200]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #188]\n\t" - "STR r5, [%[r], #196]\n\t" + "LDR r6, [r1, #188]\n\t" + "STR r5, [r0, #196]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #184]\n\t" - "STR r4, [%[r], #192]\n\t" + "LDR r5, [r1, #184]\n\t" + "STR r4, [r0, #192]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #180]\n\t" - "STR r6, [%[r], #188]\n\t" + "LDR r4, [r1, #180]\n\t" + "STR r6, [r0, #188]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #176]\n\t" - "STR r5, [%[r], #184]\n\t" + "LDR r6, [r1, #176]\n\t" + "STR r5, [r0, #184]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #172]\n\t" - "STR r4, [%[r], #180]\n\t" + "LDR r5, [r1, #172]\n\t" + "STR r4, [r0, #180]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #168]\n\t" - "STR r6, [%[r], #176]\n\t" + "LDR r4, [r1, #168]\n\t" + "STR r6, [r0, #176]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #164]\n\t" - "STR r5, [%[r], #172]\n\t" + "LDR r6, [r1, #164]\n\t" + "STR r5, [r0, #172]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #160]\n\t" - "STR r4, [%[r], #168]\n\t" + "LDR r5, [r1, #160]\n\t" + "STR r4, [r0, #168]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #156]\n\t" - "STR r6, [%[r], #164]\n\t" + "LDR r4, [r1, #156]\n\t" + "STR r6, [r0, #164]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #152]\n\t" - "STR r5, [%[r], #160]\n\t" + "LDR r6, [r1, #152]\n\t" + "STR r5, [r0, #160]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #148]\n\t" - "STR r4, [%[r], #156]\n\t" + "LDR r5, [r1, #148]\n\t" + "STR r4, [r0, #156]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #144]\n\t" - "STR r6, [%[r], #152]\n\t" + "LDR r4, [r1, #144]\n\t" + "STR r6, [r0, #152]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #140]\n\t" - "STR r5, [%[r], #148]\n\t" + "LDR r6, [r1, #140]\n\t" + "STR r5, [r0, #148]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #136]\n\t" - "STR r4, [%[r], #144]\n\t" + "LDR r5, [r1, #136]\n\t" + "STR r4, [r0, #144]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #132]\n\t" - "STR r6, [%[r], #140]\n\t" + "LDR r4, [r1, #132]\n\t" + "STR r6, [r0, #140]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #128]\n\t" - "STR r5, [%[r], #136]\n\t" + "LDR r6, [r1, #128]\n\t" + "STR r5, [r0, #136]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #124]\n\t" - "STR r4, [%[r], #132]\n\t" + "LDR r5, [r1, #124]\n\t" + "STR r4, [r0, #132]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #120]\n\t" - "STR r6, [%[r], #128]\n\t" + "LDR r4, [r1, #120]\n\t" + "STR r6, [r0, #128]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #116]\n\t" - "STR r5, [%[r], #124]\n\t" + "LDR r6, [r1, #116]\n\t" + "STR r5, [r0, #124]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #112]\n\t" - "STR r4, [%[r], #120]\n\t" + "LDR r5, [r1, #112]\n\t" + "STR r4, [r0, #120]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #108]\n\t" - "STR r6, [%[r], #116]\n\t" + "LDR r4, [r1, #108]\n\t" + "STR r6, [r0, #116]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #104]\n\t" - "STR r5, [%[r], #112]\n\t" + "LDR r6, [r1, #104]\n\t" + "STR r5, [r0, #112]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #100]\n\t" - "STR r4, [%[r], #108]\n\t" + "LDR r5, [r1, #100]\n\t" + "STR r4, [r0, #108]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #96]\n\t" - "STR r6, [%[r], #104]\n\t" + "LDR r4, [r1, #96]\n\t" + "STR r6, [r0, #104]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #92]\n\t" - "STR r5, [%[r], #100]\n\t" + "LDR r6, [r1, #92]\n\t" + "STR r5, [r0, #100]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #88]\n\t" - "STR r4, [%[r], #96]\n\t" + "LDR r5, [r1, #88]\n\t" + "STR r4, [r0, #96]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #84]\n\t" - "STR r6, [%[r], #92]\n\t" + "LDR r4, [r1, #84]\n\t" + "STR r6, [r0, #92]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #80]\n\t" - "STR r5, [%[r], #88]\n\t" + "LDR r6, [r1, #80]\n\t" + "STR r5, [r0, #88]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #76]\n\t" - "STR r4, [%[r], #84]\n\t" + "LDR r5, [r1, #76]\n\t" + "STR r4, [r0, #84]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #72]\n\t" - "STR r6, [%[r], #80]\n\t" + "LDR r4, [r1, #72]\n\t" + "STR r6, [r0, #80]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #68]\n\t" - "STR r5, [%[r], #76]\n\t" + "LDR r6, [r1, #68]\n\t" + "STR r5, [r0, #76]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #64]\n\t" - "STR r4, [%[r], #72]\n\t" + "LDR r5, [r1, #64]\n\t" + "STR r4, [r0, #72]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #60]\n\t" - "STR r6, [%[r], #68]\n\t" + "LDR r4, [r1, #60]\n\t" + "STR r6, [r0, #68]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #56]\n\t" - "STR r5, [%[r], #64]\n\t" + "LDR r6, [r1, #56]\n\t" + "STR r5, [r0, #64]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #52]\n\t" - "STR r4, [%[r], #60]\n\t" + "LDR r5, [r1, #52]\n\t" + "STR r4, [r0, #60]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #48]\n\t" - "STR r6, [%[r], #56]\n\t" + "LDR r4, [r1, #48]\n\t" + "STR r6, [r0, #56]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #44]\n\t" - "STR r5, [%[r], #52]\n\t" + "LDR r6, [r1, #44]\n\t" + "STR r5, [r0, #52]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #40]\n\t" - "STR r4, [%[r], #48]\n\t" + "LDR r5, [r1, #40]\n\t" + "STR r4, [r0, #48]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #36]\n\t" - "STR r6, [%[r], #44]\n\t" + "LDR r4, [r1, #36]\n\t" + "STR r6, [r0, #44]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #32]\n\t" - "STR r5, [%[r], #40]\n\t" + "LDR r6, [r1, #32]\n\t" + "STR r5, [r0, #40]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #28]\n\t" - "STR r4, [%[r], #36]\n\t" + "LDR r5, [r1, #28]\n\t" + "STR r4, [r0, #36]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #24]\n\t" - "STR r6, [%[r], #32]\n\t" + "LDR r4, [r1, #24]\n\t" + "STR r6, [r0, #32]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #20]\n\t" - "STR r5, [%[r], #28]\n\t" + "LDR r6, [r1, #20]\n\t" + "STR r5, [r0, #28]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #16]\n\t" - "STR r4, [%[r], #24]\n\t" + "LDR r5, [r1, #16]\n\t" + "STR r4, [r0, #24]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #12]\n\t" - "STR r6, [%[r], #20]\n\t" + "LDR r4, [r1, #12]\n\t" + "STR r6, [r0, #20]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #8]\n\t" - "STR r5, [%[r], #16]\n\t" + "LDR r6, [r1, #8]\n\t" + "STR r5, [r0, #16]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #4]\n\t" - "STR r4, [%[r], #12]\n\t" + "LDR r5, [r1, #4]\n\t" + "STR r4, [r0, #12]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a]]\n\t" - "STR r6, [%[r], #8]\n\t" + "LDR r4, [r1]\n\t" + "STR r6, [r0, #8]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "STR r4, [%[r]]\n\t" - "STR r5, [%[r], #4]\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [n] "+r" (n) : + : "memory", "cc", "r4", "r5", "r6", "r3", "r7" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [n] "r" (n) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r3", "r7" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + n = (byte)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Modular exponentiate 2 to the e mod m. (r = 2^e mod m) @@ -32263,12 +34542,20 @@ WC_OMIT_FRAME_POINTER static void sp_256_mul_8(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x40\n\t" - "LDR lr, [%[a]]\n\t" - "LDR r11, [%[b]]\n\t" + "LDR lr, [r1]\n\t" + "LDR r11, [r2]\n\t" "UMULL r8, r6, lr, r11\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -32290,14 +34577,14 @@ WC_OMIT_FRAME_POINTER static void sp_256_mul_8(sp_digit* r, const sp_digit* a, #else "L_sp_256_mul_8_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" "ADC r8, r8, #0\n\t" - "LDR lr, [%[a], r4]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r4]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -32319,8 +34606,8 @@ WC_OMIT_FRAME_POINTER static void sp_256_mul_8(sp_digit* r, const sp_digit* a, #else "BLT.N L_sp_256_mul_8_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -32344,8 +34631,8 @@ WC_OMIT_FRAME_POINTER static void sp_256_mul_8(sp_digit* r, const sp_digit* a, #else "BLE.N L_sp_256_mul_8_outer_%=\n\t" #endif - "LDR lr, [%[a], #28]\n\t" - "LDR r11, [%[b], #28]\n\t" + "LDR lr, [r1, #28]\n\t" + "LDR r11, [r2, #28]\n\t" "UMLAL r6, r7, lr, r11\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -32357,7 +34644,7 @@ WC_OMIT_FRAME_POINTER static void sp_256_mul_8(sp_digit* r, const sp_digit* a, "L_sp_256_mul_8_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_256_mul_8_store_%=\n\t" @@ -32366,16 +34653,27 @@ WC_OMIT_FRAME_POINTER static void sp_256_mul_8(sp_digit* r, const sp_digit* a, #else "BGT.N L_sp_256_mul_8_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -32398,352 +34696,371 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mul_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #36\n\t" - "STR %[r], [sp, #32]\n\t" - "MOV %[r], #0\n\t" - "LDR r12, [%[a]]\n\t" + "STR r0, [sp, #32]\n\t" + "MOV r0, #0\n\t" + "LDR r12, [r1]\n\t" /* A[0] * B[0] */ - "LDR lr, [%[b]]\n\t" + "LDR lr, [r2]\n\t" "UMULL r3, r4, r12, lr\n\t" /* A[0] * B[2] */ - "LDR lr, [%[b], #8]\n\t" + "LDR lr, [r2, #8]\n\t" "UMULL r5, r6, r12, lr\n\t" /* A[0] * B[4] */ - "LDR lr, [%[b], #16]\n\t" + "LDR lr, [r2, #16]\n\t" "UMULL r7, r8, r12, lr\n\t" /* A[0] * B[6] */ - "LDR lr, [%[b], #24]\n\t" + "LDR lr, [r2, #24]\n\t" "UMULL r9, r10, r12, lr\n\t" "STR r3, [sp]\n\t" /* A[0] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "MOV r11, %[r]\n\t" + "LDR lr, [r2, #4]\n\t" + "MOV r11, r0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[0] * B[3] */ - "LDR lr, [%[b], #12]\n\t" + "LDR lr, [r2, #12]\n\t" "ADCS r6, r6, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[0] * B[5] */ - "LDR lr, [%[b], #20]\n\t" + "LDR lr, [r2, #20]\n\t" "ADCS r8, r8, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[0] * B[7] */ - "LDR lr, [%[b], #28]\n\t" + "LDR lr, [r2, #28]\n\t" "ADCS r10, r10, #0\n\t" - "ADC r3, %[r], #0\n\t" + "ADC r3, r0, #0\n\t" "UMLAL r10, r3, r12, lr\n\t" /* A[1] * B[0] */ - "LDR r12, [%[a], #4]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #4]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "STR r4, [sp, #4]\n\t" "ADDS r5, r5, r11\n\t" /* A[1] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[1] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[1] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[1] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[1] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[1] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[1] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r4, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r4, r0, #0\n\t" "UMLAL r3, r4, r12, lr\n\t" /* A[2] * B[0] */ - "LDR r12, [%[a], #8]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #8]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "STR r5, [sp, #8]\n\t" "ADDS r6, r6, r11\n\t" /* A[2] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[2] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[2] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[2] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[2] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[2] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[2] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r5, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r5, r0, #0\n\t" "UMLAL r4, r5, r12, lr\n\t" /* A[3] * B[0] */ - "LDR r12, [%[a], #12]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #12]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "STR r6, [sp, #12]\n\t" "ADDS r7, r7, r11\n\t" /* A[3] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[3] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[3] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[3] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[3] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[3] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[3] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r6, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r6, r0, #0\n\t" "UMLAL r5, r6, r12, lr\n\t" /* A[4] * B[0] */ - "LDR r12, [%[a], #16]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #16]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "STR r7, [sp, #16]\n\t" "ADDS r8, r8, r11\n\t" /* A[4] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[4] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[4] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[4] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[4] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[4] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[4] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r7, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r7, r0, #0\n\t" "UMLAL r6, r7, r12, lr\n\t" /* A[5] * B[0] */ - "LDR r12, [%[a], #20]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "STR r8, [sp, #20]\n\t" "ADDS r9, r9, r11\n\t" /* A[5] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[5] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[5] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[5] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[5] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[5] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[5] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r8, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r8, r0, #0\n\t" "UMLAL r7, r8, r12, lr\n\t" /* A[6] * B[0] */ - "LDR r12, [%[a], #24]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "STR r9, [sp, #24]\n\t" "ADDS r10, r10, r11\n\t" /* A[6] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[6] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[6] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[6] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[6] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[6] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[6] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r9, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r9, r0, #0\n\t" "UMLAL r8, r9, r12, lr\n\t" /* A[7] * B[0] */ - "LDR r12, [%[a], #28]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "STR r10, [sp, #28]\n\t" "ADDS r3, r3, r11\n\t" /* A[7] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[7] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[7] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[7] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[7] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[7] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[7] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r10, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r10, r0, #0\n\t" "UMLAL r9, r10, r12, lr\n\t" - "LDR %[r], [sp, #32]\n\t" - "ADD %[r], %[r], #32\n\t" - "STM %[r], {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" + "LDR r0, [sp, #32]\n\t" + "ADD r0, r0, #32\n\t" + "STM r0, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "LDM sp, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" - "SUB %[r], %[r], #32\n\t" - "STM %[r], {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" + "SUB r0, r0, #32\n\t" + "STM r0, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "ADD sp, sp, #36\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -32765,18 +35082,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mul_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #44\n\t" #ifndef WOLFSSL_NO_VAR_ASSIGN_REG - "STRD %[r], %[a], [sp, #36]\n\t" + "STRD r0, r1, [sp, #36]\n\t" #else - "STR %[r], [sp, #36]\n\t" - "STR %[a], [sp, #40]\n\t" + "STR r0, [sp, #36]\n\t" + "STR r1, [sp, #40]\n\t" #endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ - "MOV lr, %[b]\n\t" - "LDM %[a], {r0, r1, r2, r3}\n\t" + "MOV lr, r2\n\t" + "LDM r1, {r0, r1, r2, r3}\n\t" "LDM lr!, {r4, r5, r6}\n\t" "UMULL r10, r11, r0, r4\n\t" "UMULL r12, r7, r1, r4\n\t" @@ -32879,16 +35204,27 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mul_8(sp_digit* r, "LDM sp, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "STM lr, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "ADD sp, sp, #44\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r10", "r11", "r12", "r7", + "r8", "r9", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r10", "r11", "r12", "r7", - "r8", "r9", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_ARM_ARCH_7M */ @@ -32909,11 +35245,19 @@ WC_OMIT_FRAME_POINTER static void sp_256_sqr_8(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x40\n\t" - "LDR lr, [%[a]]\n\t" + "LDR lr, [r1]\n\t" "UMULL r8, r6, lr, lr\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -32935,8 +35279,8 @@ WC_OMIT_FRAME_POINTER static void sp_256_sqr_8(sp_digit* r, const sp_digit* a) #else "L_sp_256_sqr_8_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[a], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r1, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -32961,7 +35305,7 @@ WC_OMIT_FRAME_POINTER static void sp_256_sqr_8(sp_digit* r, const sp_digit* a) #else "BLT.N L_sp_256_sqr_8_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" + "LDR lr, [r1, r3]\n\t" "UMULL r9, r10, lr, lr\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -32985,7 +35329,7 @@ WC_OMIT_FRAME_POINTER static void sp_256_sqr_8(sp_digit* r, const sp_digit* a) #else "BLE.N L_sp_256_sqr_8_outer_%=\n\t" #endif - "LDR lr, [%[a], #28]\n\t" + "LDR lr, [r1, #28]\n\t" "UMLAL r6, r7, lr, lr\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -32997,7 +35341,7 @@ WC_OMIT_FRAME_POINTER static void sp_256_sqr_8(sp_digit* r, const sp_digit* a) "L_sp_256_sqr_8_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_256_sqr_8_store_%=\n\t" @@ -33006,16 +35350,26 @@ WC_OMIT_FRAME_POINTER static void sp_256_sqr_8(sp_digit* r, const sp_digit* a) #else "BGT.N L_sp_256_sqr_8_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -33036,153 +35390,161 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_sqr_8(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x44\n\t" - "STR %[r], [sp, #64]\n\t" - "MOV %[r], #0\n\t" - "LDR r12, [%[a]]\n\t" + "STR r0, [sp, #64]\n\t" + "MOV r0, #0\n\t" + "LDR r12, [r1]\n\t" /* A[0] * A[1] */ - "LDR lr, [%[a], #4]\n\t" + "LDR lr, [r1, #4]\n\t" "UMULL r4, r5, r12, lr\n\t" /* A[0] * A[3] */ - "LDR lr, [%[a], #12]\n\t" + "LDR lr, [r1, #12]\n\t" "UMULL r6, r7, r12, lr\n\t" /* A[0] * A[5] */ - "LDR lr, [%[a], #20]\n\t" + "LDR lr, [r1, #20]\n\t" "UMULL r8, r9, r12, lr\n\t" /* A[0] * A[7] */ - "LDR lr, [%[a], #28]\n\t" + "LDR lr, [r1, #28]\n\t" "UMULL r10, r3, r12, lr\n\t" /* A[0] * A[2] */ - "LDR lr, [%[a], #8]\n\t" + "LDR lr, [r1, #8]\n\t" "MOV r11, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[0] * A[4] */ - "LDR lr, [%[a], #16]\n\t" + "LDR lr, [r1, #16]\n\t" "ADCS r7, r7, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[0] * A[6] */ - "LDR lr, [%[a], #24]\n\t" + "LDR lr, [r1, #24]\n\t" "ADCS r9, r9, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" "ADCS r3, r3, #0\n\t" "STR r4, [sp, #4]\n\t" "STR r5, [sp, #8]\n\t" /* A[1] * A[2] */ - "LDR r12, [%[a], #4]\n\t" - "LDR lr, [%[a], #8]\n\t" + "LDR r12, [r1, #4]\n\t" + "LDR lr, [r1, #8]\n\t" "MOV r11, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "STR r6, [sp, #12]\n\t" "ADDS r7, r7, r11\n\t" /* A[1] * A[3] */ - "LDR lr, [%[a], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "STR r7, [sp, #16]\n\t" "ADDS r8, r8, r11\n\t" /* A[1] * A[4] */ - "LDR lr, [%[a], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[1] * A[5] */ - "LDR lr, [%[a], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[1] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[1] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r4, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r4, r0, #0\n\t" "UMLAL r3, r4, r12, lr\n\t" /* A[2] * A[3] */ - "LDR r12, [%[a], #8]\n\t" - "LDR lr, [%[a], #12]\n\t" + "LDR r12, [r1, #8]\n\t" + "LDR lr, [r1, #12]\n\t" "MOV r11, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "STR r8, [sp, #20]\n\t" "ADDS r9, r9, r11\n\t" /* A[2] * A[4] */ - "LDR lr, [%[a], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "STR r9, [sp, #24]\n\t" "ADDS r10, r10, r11\n\t" /* A[2] * A[5] */ - "LDR lr, [%[a], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[2] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[2] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r5, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r5, r0, #0\n\t" "UMLAL r4, r5, r12, lr\n\t" /* A[3] * A[4] */ - "LDR r12, [%[a], #12]\n\t" - "LDR lr, [%[a], #16]\n\t" + "LDR r12, [r1, #12]\n\t" + "LDR lr, [r1, #16]\n\t" "MOV r11, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "STR r10, [sp, #28]\n\t" "ADDS r3, r3, r11\n\t" /* A[3] * A[5] */ - "LDR lr, [%[a], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[3] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[3] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r6, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r6, r0, #0\n\t" "UMLAL r5, r6, r12, lr\n\t" /* A[4] * A[5] */ - "LDR r12, [%[a], #16]\n\t" - "LDR lr, [%[a], #20]\n\t" + "LDR r12, [r1, #16]\n\t" + "LDR lr, [r1, #20]\n\t" "MOV r11, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[4] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[4] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r7, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r7, r0, #0\n\t" "UMLAL r6, r7, r12, lr\n\t" /* A[5] * A[6] */ - "LDR r12, [%[a], #20]\n\t" - "LDR lr, [%[a], #24]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR lr, [r1, #24]\n\t" "MOV r11, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[5] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r8, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r8, r0, #0\n\t" "UMLAL r7, r8, r12, lr\n\t" /* A[6] * A[7] */ - "LDR r12, [%[a], #24]\n\t" - "LDR lr, [%[a], #28]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR lr, [r1, #28]\n\t" "MOV r9, #0\n\t" "UMLAL r8, r9, r12, lr\n\t" "ADD lr, sp, #32\n\t" @@ -33205,75 +35567,85 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_sqr_8(sp_digit* r, "ADCS r7, r7, r7\n\t" "ADCS r8, r8, r8\n\t" "ADCS r9, r9, r9\n\t" - "ADC r10, %[r], #0\n\t" + "ADC r10, r0, #0\n\t" "STM lr, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "ADD lr, sp, #4\n\t" "LDM lr, {r4, r5, r6, r7, r8, r9, r10}\n\t" "MOV lr, sp\n\t" /* A[0] * A[0] */ - "LDR r12, [%[a]]\n\t" + "LDR r12, [r1]\n\t" "UMULL r3, r11, r12, r12\n\t" "ADDS r4, r4, r11\n\t" /* A[1] * A[1] */ - "LDR r12, [%[a], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "ADCS r5, r5, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, r12\n\t" "ADDS r6, r6, r11\n\t" /* A[2] * A[2] */ - "LDR r12, [%[a], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "ADCS r7, r7, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, r12\n\t" "ADDS r8, r8, r11\n\t" /* A[3] * A[3] */ - "LDR r12, [%[a], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "ADCS r9, r9, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, r12\n\t" "ADDS r10, r10, r11\n\t" "STM lr!, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "LDM lr, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" /* A[4] * A[4] */ - "LDR r12, [%[a], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "ADCS r3, r3, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, r12\n\t" "ADDS r4, r4, r11\n\t" /* A[5] * A[5] */ - "LDR r12, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" "ADCS r5, r5, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, r12\n\t" "ADDS r6, r6, r11\n\t" /* A[6] * A[6] */ - "LDR r12, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" "ADCS r7, r7, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, r12\n\t" "ADDS r8, r8, r11\n\t" /* A[7] * A[7] */ - "LDR r12, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" "ADCS r9, r9, #0\n\t" "ADC r10, r10, #0\n\t" "UMLAL r9, r10, r12, r12\n\t" - "LDR %[r], [sp, #64]\n\t" - "ADD %[r], %[r], #32\n\t" - "STM %[r], {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" + "LDR r0, [sp, #64]\n\t" + "ADD r0, r0, #32\n\t" + "STM r0, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "LDM sp, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" - "SUB %[r], %[r], #32\n\t" - "STM %[r], {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" + "SUB r0, r0, #32\n\t" + "STM r0, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "ADD sp, sp, #0x44\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -33293,12 +35665,20 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_sqr_8(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #32\n\t" - "STR %[r], [sp, #28]\n\t" - "LDM %[a], {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" + "STR r0, [sp, #28]\n\t" + "LDM r1, {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" "UMULL r9, r10, r0, r0\n\t" "UMULL r11, r12, r0, r1\n\t" "ADDS r11, r11, r11\n\t" @@ -33389,16 +35769,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_sqr_8(sp_digit* r, "LDM sp, {r0, r1, r2, r3, r4, r5, r6}\n\t" "STM lr, {r0, r1, r2, r3, r4, r5, r6}\n\t" "ADD sp, sp, #32\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_ARM_ARCH_7M */ @@ -33422,11 +35812,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_add_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r3, #0\n\t" - "ADD r12, %[a], #32\n\t" + "ADD r12, r1, #32\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_256_add_8_word:\n\t" @@ -33434,16 +35832,16 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_add_8(sp_digit* r, "L_sp_256_add_8_word_%=:\n\t" #endif "ADDS r3, r3, #0xffffffff\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "MOV r4, #0\n\t" "ADC r3, r4, #0\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_256_add_8_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -33451,17 +35849,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_add_8(sp_digit* r, #else "BNE.N L_sp_256_add_8_word_%=\n\t" #endif - "MOV %[r], r3\n\t" + "MOV r0, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -33484,34 +35893,53 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_add_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -33533,11 +35961,19 @@ WC_OMIT_FRAME_POINTER static int sp_256_mod_mul_norm_8(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #24\n\t" - "LDM %[a], {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "LDM r1, {r2, r3, r4, r5, r6, r7, r8, r9}\n\t" /* Clear overflow and underflow */ "MOV r11, #0\n\t" "MOV r12, #0\n\t" @@ -33749,23 +36185,32 @@ WC_OMIT_FRAME_POINTER static int sp_256_mod_mul_norm_8(sp_digit* r, "SBCS r8, r8, r9\n\t" "SBC r11, r11, r12\n\t" /* Store result */ - "STM %[r], {r2, r3, r4, r5, r6, r7, r8, r11}\n\t" - "MOV %[r], #0\n\t" + "STM r0, {r2, r3, r4, r5, r6, r7, r8, r11}\n\t" + "MOV r0, #0\n\t" "ADD sp, sp, #24\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -33989,334 +36434,343 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_mul_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[5] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m, (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x44\n\t" - "STR %[r], [sp, #64]\n\t" - "MOV %[r], #0\n\t" - "LDR r12, [%[a]]\n\t" + "STR r0, [sp, #64]\n\t" + "MOV r0, #0\n\t" + "LDR r12, [r1]\n\t" /* A[0] * B[0] */ - "LDR lr, [%[b]]\n\t" + "LDR lr, [r2]\n\t" "UMULL r3, r4, r12, lr\n\t" /* A[0] * B[2] */ - "LDR lr, [%[b], #8]\n\t" + "LDR lr, [r2, #8]\n\t" "UMULL r5, r6, r12, lr\n\t" /* A[0] * B[4] */ - "LDR lr, [%[b], #16]\n\t" + "LDR lr, [r2, #16]\n\t" "UMULL r7, r8, r12, lr\n\t" /* A[0] * B[6] */ - "LDR lr, [%[b], #24]\n\t" + "LDR lr, [r2, #24]\n\t" "UMULL r9, r10, r12, lr\n\t" "STR r3, [sp]\n\t" /* A[0] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "MOV r11, %[r]\n\t" + "LDR lr, [r2, #4]\n\t" + "MOV r11, r0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[0] * B[3] */ - "LDR lr, [%[b], #12]\n\t" + "LDR lr, [r2, #12]\n\t" "ADCS r6, r6, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[0] * B[5] */ - "LDR lr, [%[b], #20]\n\t" + "LDR lr, [r2, #20]\n\t" "ADCS r8, r8, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[0] * B[7] */ - "LDR lr, [%[b], #28]\n\t" + "LDR lr, [r2, #28]\n\t" "ADCS r10, r10, #0\n\t" - "ADC r3, %[r], #0\n\t" + "ADC r3, r0, #0\n\t" "UMLAL r10, r3, r12, lr\n\t" /* A[1] * B[0] */ - "LDR r12, [%[a], #4]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #4]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "STR r4, [sp, #4]\n\t" "ADDS r5, r5, r11\n\t" /* A[1] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[1] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[1] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[1] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[1] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[1] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[1] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r4, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r4, r0, #0\n\t" "UMLAL r3, r4, r12, lr\n\t" /* A[2] * B[0] */ - "LDR r12, [%[a], #8]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #8]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "STR r5, [sp, #8]\n\t" "ADDS r6, r6, r11\n\t" /* A[2] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[2] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[2] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[2] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[2] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[2] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[2] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r5, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r5, r0, #0\n\t" "UMLAL r4, r5, r12, lr\n\t" /* A[3] * B[0] */ - "LDR r12, [%[a], #12]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #12]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "STR r6, [sp, #12]\n\t" "ADDS r7, r7, r11\n\t" /* A[3] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[3] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[3] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[3] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[3] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[3] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[3] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r6, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r6, r0, #0\n\t" "UMLAL r5, r6, r12, lr\n\t" /* A[4] * B[0] */ - "LDR r12, [%[a], #16]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #16]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "STR r7, [sp, #16]\n\t" "ADDS r8, r8, r11\n\t" /* A[4] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[4] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[4] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[4] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[4] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[4] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[4] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r7, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r7, r0, #0\n\t" "UMLAL r6, r7, r12, lr\n\t" /* A[5] * B[0] */ - "LDR r12, [%[a], #20]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "STR r8, [sp, #20]\n\t" "ADDS r9, r9, r11\n\t" /* A[5] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[5] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[5] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[5] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[5] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[5] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[5] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r8, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r8, r0, #0\n\t" "UMLAL r7, r8, r12, lr\n\t" /* A[6] * B[0] */ - "LDR r12, [%[a], #24]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "STR r9, [sp, #24]\n\t" "ADDS r10, r10, r11\n\t" /* A[6] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[6] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[6] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[6] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[6] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[6] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[6] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r9, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r9, r0, #0\n\t" "UMLAL r8, r9, r12, lr\n\t" /* A[7] * B[0] */ - "LDR r12, [%[a], #28]\n\t" - "LDR lr, [%[b]]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR lr, [r2]\n\t" "MOV r11, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "STR r10, [sp, #28]\n\t" "ADDS r3, r3, r11\n\t" /* A[7] * B[1] */ - "LDR lr, [%[b], #4]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #4]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[7] * B[2] */ - "LDR lr, [%[b], #8]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #8]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[7] * B[3] */ - "LDR lr, [%[b], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[7] * B[4] */ - "LDR lr, [%[b], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[7] * B[5] */ - "LDR lr, [%[b], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[7] * B[6] */ - "LDR lr, [%[b], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r2, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[7] * B[7] */ - "LDR lr, [%[b], #28]\n\t" - "ADC r10, %[r], #0\n\t" + "LDR lr, [r2, #28]\n\t" + "ADC r10, r0, #0\n\t" "UMLAL r9, r10, r12, lr\n\t" "ADD lr, sp, #32\n\t" "STM lr, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" @@ -34441,28 +36895,37 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_mul_8(sp_digit* r, "SBCS r6, r6, #0\n\t" "SBCS r7, r7, lr, LSR #31\n\t" "SBC r8, r8, lr\n\t" - "LDR %[r], [sp, #64]\n\t" - "STM %[r], {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" + "LDR r0, [sp, #64]\n\t" + "STM r0, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" "ADD sp, sp, #0x44\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (const sp_digit*)(size_t)L_asm_args[3]; + mp = (sp_digit)(size_t)L_asm_args[4]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)mp_p; -#else - (void)mp; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -34489,18 +36952,27 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_mul_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[5] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m, (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3, r4}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x4c\n\t" #ifndef WOLFSSL_NO_VAR_ASSIGN_REG - "STRD %[r], %[a], [sp, #68]\n\t" + "STRD r0, r1, [sp, #68]\n\t" #else - "STR %[r], [sp, #68]\n\t" - "STR %[a], [sp, #72]\n\t" + "STR r0, [sp, #68]\n\t" + "STR r1, [sp, #72]\n\t" #endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ - "MOV lr, %[b]\n\t" - "LDM %[a], {r0, r1, r2, r3}\n\t" + "MOV lr, r2\n\t" + "LDM r1, {r0, r1, r2, r3}\n\t" "LDM lr!, {r4, r5, r6}\n\t" "UMULL r10, r11, r0, r4\n\t" "UMULL r12, r7, r1, r4\n\t" @@ -34719,28 +37191,37 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_mul_8(sp_digit* r, "SBCS r6, r6, #0\n\t" "SBCS r7, r7, lr, LSR #31\n\t" "SBC r8, r8, lr\n\t" - "LDR %[r], [sp, #68]\n\t" - "STM %[r], {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" + "LDR r0, [sp, #68]\n\t" + "STM r0, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" "ADD sp, sp, #0x4c\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3, r4}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r10", "r11", "r12", "r7", + "r8", "r9", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r10", "r11", "r12", "r7", - "r8", "r9", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (const sp_digit*)(size_t)L_asm_args[3]; + mp = (sp_digit)(size_t)L_asm_args[4]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)mp_p; -#else - (void)mp; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -34764,153 +37245,162 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_sqr_8(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x44\n\t" - "STR %[r], [sp, #64]\n\t" - "MOV %[r], #0\n\t" - "LDR r12, [%[a]]\n\t" + "STR r0, [sp, #64]\n\t" + "MOV r0, #0\n\t" + "LDR r12, [r1]\n\t" /* A[0] * A[1] */ - "LDR lr, [%[a], #4]\n\t" + "LDR lr, [r1, #4]\n\t" "UMULL r4, r5, r12, lr\n\t" /* A[0] * A[3] */ - "LDR lr, [%[a], #12]\n\t" + "LDR lr, [r1, #12]\n\t" "UMULL r6, r7, r12, lr\n\t" /* A[0] * A[5] */ - "LDR lr, [%[a], #20]\n\t" + "LDR lr, [r1, #20]\n\t" "UMULL r8, r9, r12, lr\n\t" /* A[0] * A[7] */ - "LDR lr, [%[a], #28]\n\t" + "LDR lr, [r1, #28]\n\t" "UMULL r10, r3, r12, lr\n\t" /* A[0] * A[2] */ - "LDR lr, [%[a], #8]\n\t" + "LDR lr, [r1, #8]\n\t" "MOV r11, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[0] * A[4] */ - "LDR lr, [%[a], #16]\n\t" + "LDR lr, [r1, #16]\n\t" "ADCS r7, r7, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "ADDS r8, r8, r11\n\t" /* A[0] * A[6] */ - "LDR lr, [%[a], #24]\n\t" + "LDR lr, [r1, #24]\n\t" "ADCS r9, r9, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" "ADCS r3, r3, #0\n\t" "STR r4, [sp, #4]\n\t" "STR r5, [sp, #8]\n\t" /* A[1] * A[2] */ - "LDR r12, [%[a], #4]\n\t" - "LDR lr, [%[a], #8]\n\t" + "LDR r12, [r1, #4]\n\t" + "LDR lr, [r1, #8]\n\t" "MOV r11, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "STR r6, [sp, #12]\n\t" "ADDS r7, r7, r11\n\t" /* A[1] * A[3] */ - "LDR lr, [%[a], #12]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #12]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, lr\n\t" "STR r7, [sp, #16]\n\t" "ADDS r8, r8, r11\n\t" /* A[1] * A[4] */ - "LDR lr, [%[a], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "ADDS r9, r9, r11\n\t" /* A[1] * A[5] */ - "LDR lr, [%[a], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "ADDS r10, r10, r11\n\t" /* A[1] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[1] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r4, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r4, r0, #0\n\t" "UMLAL r3, r4, r12, lr\n\t" /* A[2] * A[3] */ - "LDR r12, [%[a], #8]\n\t" - "LDR lr, [%[a], #12]\n\t" + "LDR r12, [r1, #8]\n\t" + "LDR lr, [r1, #12]\n\t" "MOV r11, #0\n\t" "UMLAL r8, r11, r12, lr\n\t" "STR r8, [sp, #20]\n\t" "ADDS r9, r9, r11\n\t" /* A[2] * A[4] */ - "LDR lr, [%[a], #16]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #16]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, lr\n\t" "STR r9, [sp, #24]\n\t" "ADDS r10, r10, r11\n\t" /* A[2] * A[5] */ - "LDR lr, [%[a], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "ADDS r3, r3, r11\n\t" /* A[2] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[2] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r5, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r5, r0, #0\n\t" "UMLAL r4, r5, r12, lr\n\t" /* A[3] * A[4] */ - "LDR r12, [%[a], #12]\n\t" - "LDR lr, [%[a], #16]\n\t" + "LDR r12, [r1, #12]\n\t" + "LDR lr, [r1, #16]\n\t" "MOV r11, #0\n\t" "UMLAL r10, r11, r12, lr\n\t" "STR r10, [sp, #28]\n\t" "ADDS r3, r3, r11\n\t" /* A[3] * A[5] */ - "LDR lr, [%[a], #20]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #20]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, lr\n\t" "ADDS r4, r4, r11\n\t" /* A[3] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[3] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r6, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r6, r0, #0\n\t" "UMLAL r5, r6, r12, lr\n\t" /* A[4] * A[5] */ - "LDR r12, [%[a], #16]\n\t" - "LDR lr, [%[a], #20]\n\t" + "LDR r12, [r1, #16]\n\t" + "LDR lr, [r1, #20]\n\t" "MOV r11, #0\n\t" "UMLAL r4, r11, r12, lr\n\t" "ADDS r5, r5, r11\n\t" /* A[4] * A[6] */ - "LDR lr, [%[a], #24]\n\t" - "ADC r11, %[r], #0\n\t" + "LDR lr, [r1, #24]\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, lr\n\t" "ADDS r6, r6, r11\n\t" /* A[4] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r7, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r7, r0, #0\n\t" "UMLAL r6, r7, r12, lr\n\t" /* A[5] * A[6] */ - "LDR r12, [%[a], #20]\n\t" - "LDR lr, [%[a], #24]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR lr, [r1, #24]\n\t" "MOV r11, #0\n\t" "UMLAL r6, r11, r12, lr\n\t" "ADDS r7, r7, r11\n\t" /* A[5] * A[7] */ - "LDR lr, [%[a], #28]\n\t" - "ADC r8, %[r], #0\n\t" + "LDR lr, [r1, #28]\n\t" + "ADC r8, r0, #0\n\t" "UMLAL r7, r8, r12, lr\n\t" /* A[6] * A[7] */ - "LDR r12, [%[a], #24]\n\t" - "LDR lr, [%[a], #28]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR lr, [r1, #28]\n\t" "MOV r9, #0\n\t" "UMLAL r8, r9, r12, lr\n\t" "ADD lr, sp, #32\n\t" @@ -34933,55 +37423,55 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_sqr_8(sp_digit* r, "ADCS r7, r7, r7\n\t" "ADCS r8, r8, r8\n\t" "ADCS r9, r9, r9\n\t" - "ADC r10, %[r], #0\n\t" + "ADC r10, r0, #0\n\t" "STM lr, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "ADD lr, sp, #4\n\t" "LDM lr, {r4, r5, r6, r7, r8, r9, r10}\n\t" "MOV lr, sp\n\t" /* A[0] * A[0] */ - "LDR r12, [%[a]]\n\t" + "LDR r12, [r1]\n\t" "UMULL r3, r11, r12, r12\n\t" "ADDS r4, r4, r11\n\t" /* A[1] * A[1] */ - "LDR r12, [%[a], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "ADCS r5, r5, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, r12\n\t" "ADDS r6, r6, r11\n\t" /* A[2] * A[2] */ - "LDR r12, [%[a], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "ADCS r7, r7, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, r12\n\t" "ADDS r8, r8, r11\n\t" /* A[3] * A[3] */ - "LDR r12, [%[a], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "ADCS r9, r9, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r9, r11, r12, r12\n\t" "ADDS r10, r10, r11\n\t" "STM lr!, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" "LDM lr, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" /* A[4] * A[4] */ - "LDR r12, [%[a], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "ADCS r3, r3, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r3, r11, r12, r12\n\t" "ADDS r4, r4, r11\n\t" /* A[5] * A[5] */ - "LDR r12, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" "ADCS r5, r5, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r5, r11, r12, r12\n\t" "ADDS r6, r6, r11\n\t" /* A[6] * A[6] */ - "LDR r12, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" "ADCS r7, r7, #0\n\t" - "ADC r11, %[r], #0\n\t" + "ADC r11, r0, #0\n\t" "UMLAL r7, r11, r12, r12\n\t" "ADDS r8, r8, r11\n\t" /* A[7] * A[7] */ - "LDR r12, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" "ADCS r9, r9, #0\n\t" "ADC r10, r10, #0\n\t" "UMLAL r9, r10, r12, r12\n\t" @@ -35108,28 +37598,36 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_sqr_8(sp_digit* r, "SBCS r6, r6, #0\n\t" "SBCS r7, r7, lr, LSR #31\n\t" "SBC r8, r8, lr\n\t" - "LDR %[r], [sp, #64]\n\t" - "STM %[r], {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" + "LDR r0, [sp, #64]\n\t" + "STM r0, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" "ADD sp, sp, #0x44\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; + mp = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)mp_p; -#else - (void)mp; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -35152,12 +37650,21 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_sqr_8(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x44\n\t" - "STR %[r], [sp, #64]\n\t" - "LDM %[a], {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" + "STR r0, [sp, #64]\n\t" + "LDM r1, {r0, r1, r2, r3, r4, r5, r6, r7}\n\t" "UMULL r9, r10, r0, r0\n\t" "UMULL r11, r12, r0, r1\n\t" "ADDS r11, r11, r11\n\t" @@ -35365,28 +37872,36 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_sqr_8(sp_digit* r, "SBCS r6, r6, #0\n\t" "SBCS r7, r7, lr, LSR #31\n\t" "SBC r8, r8, lr\n\t" - "LDR %[r], [sp, #64]\n\t" - "STM %[r], {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" + "LDR r0, [sp, #64]\n\t" + "STM r0, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" "ADD sp, sp, #0x44\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; + mp = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)mp_p; -#else - (void)mp; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -35506,9 +38021,17 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_256_cmp_8(const sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0xffffffff\n\t" "MOV r8, #1\n\t" "MOV r7, #0\n\t" @@ -35521,8 +38044,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_256_cmp_8(const sp_digit* a, #else "L_sp_256_cmp_8_words_%=:\n\t" #endif - "LDR r4, [%[a], r6]\n\t" - "LDR r5, [%[b], r6]\n\t" + "LDR r4, [r0, r6]\n\t" + "LDR r5, [r1, r6]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -35540,8 +38063,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_256_cmp_8(const sp_digit* a, #endif "EOR r2, r2, r3\n\t" #else - "LDR r4, [%[a], #28]\n\t" - "LDR r5, [%[b], #28]\n\t" + "LDR r4, [r0, #28]\n\t" + "LDR r5, [r1, #28]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -35551,8 +38074,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_256_cmp_8(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #24]\n\t" - "LDR r5, [%[b], #24]\n\t" + "LDR r4, [r0, #24]\n\t" + "LDR r5, [r1, #24]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -35562,8 +38085,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_256_cmp_8(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #20]\n\t" - "LDR r5, [%[b], #20]\n\t" + "LDR r4, [r0, #20]\n\t" + "LDR r5, [r1, #20]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -35573,8 +38096,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_256_cmp_8(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #16]\n\t" - "LDR r5, [%[b], #16]\n\t" + "LDR r4, [r0, #16]\n\t" + "LDR r5, [r1, #16]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -35584,8 +38107,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_256_cmp_8(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #12]\n\t" - "LDR r5, [%[b], #12]\n\t" + "LDR r4, [r0, #12]\n\t" + "LDR r5, [r1, #12]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -35595,8 +38118,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_256_cmp_8(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #8]\n\t" - "LDR r5, [%[b], #8]\n\t" + "LDR r4, [r0, #8]\n\t" + "LDR r5, [r1, #8]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -35606,8 +38129,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_256_cmp_8(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #4]\n\t" - "LDR r5, [%[b], #4]\n\t" + "LDR r4, [r0, #4]\n\t" + "LDR r5, [r1, #4]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -35617,8 +38140,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_256_cmp_8(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[b]]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r1]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -35630,16 +38153,26 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_256_cmp_8(const sp_digit* a, "movne r3, r7\n\t" "EOR r2, r2, r3\n\t" #endif /*WOLFSSL_SP_SMALL */ - "MOV %[a], r2\n\t" + "MOV r0, r2\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -35672,9 +38205,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_cond_sub_8(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, #0\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -35685,12 +38227,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_cond_sub_8(sp_digit* r, "L_sp_256_cond_sub_8_words_%=:\n\t" #endif "SUBS r4, r8, r4\n\t" - "LDR r6, [%[a], r5]\n\t" - "LDR r7, [%[b], r5]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r5]\n\t" + "LDR r7, [r2, r5]\n\t" + "AND r7, r7, r3\n\t" "SBCS r6, r6, r7\n\t" "SBC r4, r8, r8\n\t" - "STR r6, [%[r], r5]\n\t" + "STR r6, [r0, r5]\n\t" "ADD r5, r5, #4\n\t" "CMP r5, #32\n\t" #if defined(__GNUC__) @@ -35700,16 +38242,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_cond_sub_8(sp_digit* r, #else "BLT.N L_sp_256_cond_sub_8_words_%=\n\t" #endif - "MOV %[r], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -35736,48 +38290,69 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_cond_sub_8(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SUBS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "SBC %[r], r5, r5\n\t" + "STM r0!, {r6, r7}\n\t" + "SBC r0, r5, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -35805,15 +38380,24 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_8(sp_digit* a, register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR lr, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR lr, [r1]\n\t" /* i = 0 */ "MOV r11, #0\n\t" "MOV r3, #0\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[a], #4]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_256_mont_reduce_8_word:\n\t" @@ -35821,73 +38405,73 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_8(sp_digit* a, "L_sp_256_mont_reduce_8_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL r10, %[mp], r4\n\t" + "MUL r10, r2, r4\n\t" /* a[i+0] += m[0] * mu */ "MOV r7, #0\n\t" "UMLAL r4, r7, r10, lr\n\t" /* a[i+1] += m[1] * mu */ - "LDR r9, [%[m], #4]\n\t" + "LDR r9, [r1, #4]\n\t" "MOV r6, #0\n\t" "UMLAL r5, r6, r10, r9\n\t" "MOV r4, r5\n\t" "ADDS r4, r4, r7\n\t" "ADC r6, r6, #0\n\t" /* a[i+2] += m[2] * mu */ - "LDR r9, [%[m], #8]\n\t" - "LDR r5, [%[a], #8]\n\t" + "LDR r9, [r1, #8]\n\t" + "LDR r5, [r0, #8]\n\t" "MOV r7, #0\n\t" "UMLAL r5, r7, r10, r9\n\t" "ADDS r5, r5, r6\n\t" "ADC r7, r7, #0\n\t" /* a[i+3] += m[3] * mu */ - "LDR r9, [%[m], #12]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r9, [r1, #12]\n\t" + "LDR r12, [r0, #12]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #12]\n\t" + "STR r12, [r0, #12]\n\t" "ADC r6, r6, #0\n\t" /* a[i+4] += m[4] * mu */ - "LDR r9, [%[m], #16]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r9, [r1, #16]\n\t" + "LDR r12, [r0, #16]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #16]\n\t" + "STR r12, [r0, #16]\n\t" "ADC r7, r7, #0\n\t" /* a[i+5] += m[5] * mu */ - "LDR r9, [%[m], #20]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r12, [r0, #20]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #20]\n\t" + "STR r12, [r0, #20]\n\t" "ADC r6, r6, #0\n\t" /* a[i+6] += m[6] * mu */ - "LDR r9, [%[m], #24]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r9, [r1, #24]\n\t" + "LDR r12, [r0, #24]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #24]\n\t" + "STR r12, [r0, #24]\n\t" "ADC r7, r7, #0\n\t" /* a[i+7] += m[7] * mu */ - "LDR r9, [%[m], #28]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r9, [r1, #28]\n\t" + "LDR r12, [r0, #28]\n\t" "UMULL r8, r9, r10, r9\n\t" "ADDS r7, r7, r8\n\t" "ADCS r6, r9, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, r3\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #28]\n\t" - "LDR r12, [%[a], #32]\n\t" + "STR r12, [r0, #28]\n\t" + "LDR r12, [r0, #32]\n\t" "ADCS r12, r12, r6\n\t" - "STR r12, [%[a], #32]\n\t" + "STR r12, [r0, #32]\n\t" "ADC r3, r3, #0\n\t" /* i += 1 */ "ADD r11, r11, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r11, #32\n\t" #if defined(__GNUC__) "BLT L_sp_256_mont_reduce_8_word_%=\n\t" @@ -35897,19 +38481,30 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_8(sp_digit* a, "BLT.W L_sp_256_mont_reduce_8_word_%=\n\t" #endif /* Loop Done */ - "STR r4, [%[a]]\n\t" - "STR r5, [%[a], #4]\n\t" - "MOV %[mp], r3\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_256_cond_sub_8(a - 8, a, m, (sp_digit)0 - mp); } @@ -35933,17 +38528,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_8(sp_digit* a, register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* i = 0 */ "MOV r4, #0\n\t" "MOV r5, #0\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r7, [%[a], #4]\n\t" - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[a], #12]\n\t" - "LDR r10, [%[a], #16]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" + "LDR r10, [r0, #16]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_256_mont_reduce_8_word:\n\t" @@ -35951,50 +38555,50 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_8(sp_digit* a, "L_sp_256_mont_reduce_8_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL lr, %[mp], r6\n\t" + "MUL lr, r2, r6\n\t" /* a[i+0] += m[0] * mu */ - "LDR r12, [%[m]]\n\t" + "LDR r12, [r1]\n\t" "MOV r3, #0\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+1] += m[1] * mu */ - "LDR r12, [%[m], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "MOV r6, r7\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+2] += m[2] * mu */ - "LDR r12, [%[m], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "MOV r7, r8\n\t" "UMAAL r7, r3, lr, r12\n\t" /* a[i+3] += m[3] * mu */ - "LDR r12, [%[m], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "MOV r8, r9\n\t" "UMAAL r8, r3, lr, r12\n\t" /* a[i+4] += m[4] * mu */ - "LDR r12, [%[m], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "MOV r9, r10\n\t" "UMAAL r9, r3, lr, r12\n\t" /* a[i+5] += m[5] * mu */ - "LDR r12, [%[m], #20]\n\t" - "LDR r10, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR r10, [r0, #20]\n\t" "UMAAL r10, r3, lr, r12\n\t" /* a[i+6] += m[6] * mu */ - "LDR r12, [%[m], #24]\n\t" - "LDR r11, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR r11, [r0, #24]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #24]\n\t" + "STR r11, [r0, #24]\n\t" /* a[i+7] += m[7] * mu */ - "LDR r12, [%[m], #28]\n\t" - "LDR r11, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR r11, [r0, #28]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "LDR lr, [%[a], #32]\n\t" + "LDR lr, [r0, #32]\n\t" "MOV r12, #0\n\t" "UMAAL r3, lr, r12, r12\n\t" - "STR r11, [%[a], #28]\n\t" + "STR r11, [r0, #28]\n\t" "ADDS r3, r3, r5\n\t" "ADC r5, lr, #0\n\t" - "STR r3, [%[a], #32]\n\t" + "STR r3, [r0, #32]\n\t" /* i += 1 */ "ADD r4, r4, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r4, #32\n\t" #if defined(__GNUC__) "BLT L_sp_256_mont_reduce_8_word_%=\n\t" @@ -36004,22 +38608,33 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_8(sp_digit* a, "BLT.W L_sp_256_mont_reduce_8_word_%=\n\t" #endif /* Loop Done */ - "STR r6, [%[a]]\n\t" - "STR r7, [%[a], #4]\n\t" - "STR r8, [%[a], #8]\n\t" - "STR r9, [%[a], #12]\n\t" - "STR r10, [%[a], #16]\n\t" - "MOV %[mp], r5\n\t" + "STR r6, [r0]\n\t" + "STR r7, [r0, #4]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #12]\n\t" + "STR r10, [r0, #16]\n\t" + "MOV r2, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_256_cond_sub_8(a - 8, a, m, (sp_digit)0 - mp); } @@ -36042,15 +38657,24 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_8(sp_digit* a, { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x44\n\t" - "STR %[a], [sp, #64]\n\t" + "STR r0, [sp, #64]\n\t" "MOV lr, sp\n\t" - "LDM %[a]!, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" + "LDM r0!, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" "STM lr!, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" - "LDM %[a], {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" + "LDM r0, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" "STM lr, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" /* Start Reduction */ "LDM sp, {r5, r6, r7, r8, r9, r10, r11, r12}\n\t" @@ -36173,28 +38797,35 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_8(sp_digit* a, "SBCS r6, r6, #0\n\t" "SBCS r7, r7, lr, LSR #31\n\t" "SBC r8, r8, lr\n\t" - "LDR %[a], [sp, #64]\n\t" - "STM %[a], {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" + "LDR r0, [sp, #64]\n\t" + "STM r0, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" "ADD sp, sp, #0x44\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a) : + : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + "r10", "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", - "r10", "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)mp_p; -#else - (void)mp; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -36218,15 +38849,24 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_order_8( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR lr, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR lr, [r1]\n\t" /* i = 0 */ "MOV r11, #0\n\t" "MOV r3, #0\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[a], #4]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_256_mont_reduce_order_8_word:\n\t" @@ -36234,73 +38874,73 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_order_8( "L_sp_256_mont_reduce_order_8_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL r10, %[mp], r4\n\t" + "MUL r10, r2, r4\n\t" /* a[i+0] += m[0] * mu */ "MOV r7, #0\n\t" "UMLAL r4, r7, r10, lr\n\t" /* a[i+1] += m[1] * mu */ - "LDR r9, [%[m], #4]\n\t" + "LDR r9, [r1, #4]\n\t" "MOV r6, #0\n\t" "UMLAL r5, r6, r10, r9\n\t" "MOV r4, r5\n\t" "ADDS r4, r4, r7\n\t" "ADC r6, r6, #0\n\t" /* a[i+2] += m[2] * mu */ - "LDR r9, [%[m], #8]\n\t" - "LDR r5, [%[a], #8]\n\t" + "LDR r9, [r1, #8]\n\t" + "LDR r5, [r0, #8]\n\t" "MOV r7, #0\n\t" "UMLAL r5, r7, r10, r9\n\t" "ADDS r5, r5, r6\n\t" "ADC r7, r7, #0\n\t" /* a[i+3] += m[3] * mu */ - "LDR r9, [%[m], #12]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r9, [r1, #12]\n\t" + "LDR r12, [r0, #12]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #12]\n\t" + "STR r12, [r0, #12]\n\t" "ADC r6, r6, #0\n\t" /* a[i+4] += m[4] * mu */ - "LDR r9, [%[m], #16]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r9, [r1, #16]\n\t" + "LDR r12, [r0, #16]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #16]\n\t" + "STR r12, [r0, #16]\n\t" "ADC r7, r7, #0\n\t" /* a[i+5] += m[5] * mu */ - "LDR r9, [%[m], #20]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r12, [r0, #20]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #20]\n\t" + "STR r12, [r0, #20]\n\t" "ADC r6, r6, #0\n\t" /* a[i+6] += m[6] * mu */ - "LDR r9, [%[m], #24]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r9, [r1, #24]\n\t" + "LDR r12, [r0, #24]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #24]\n\t" + "STR r12, [r0, #24]\n\t" "ADC r7, r7, #0\n\t" /* a[i+7] += m[7] * mu */ - "LDR r9, [%[m], #28]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r9, [r1, #28]\n\t" + "LDR r12, [r0, #28]\n\t" "UMULL r8, r9, r10, r9\n\t" "ADDS r7, r7, r8\n\t" "ADCS r6, r9, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, r3\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #28]\n\t" - "LDR r12, [%[a], #32]\n\t" + "STR r12, [r0, #28]\n\t" + "LDR r12, [r0, #32]\n\t" "ADCS r12, r12, r6\n\t" - "STR r12, [%[a], #32]\n\t" + "STR r12, [r0, #32]\n\t" "ADC r3, r3, #0\n\t" /* i += 1 */ "ADD r11, r11, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r11, #32\n\t" #if defined(__GNUC__) "BLT L_sp_256_mont_reduce_order_8_word_%=\n\t" @@ -36310,19 +38950,30 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_order_8( "BLT.W L_sp_256_mont_reduce_order_8_word_%=\n\t" #endif /* Loop Done */ - "STR r4, [%[a]]\n\t" - "STR r5, [%[a], #4]\n\t" - "MOV %[mp], r3\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_256_cond_sub_8(a - 8, a, m, (sp_digit)0 - mp); } @@ -36346,17 +38997,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_order_8( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* i = 0 */ "MOV r4, #0\n\t" "MOV r5, #0\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r7, [%[a], #4]\n\t" - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[a], #12]\n\t" - "LDR r10, [%[a], #16]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" + "LDR r10, [r0, #16]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_256_mont_reduce_order_8_word:\n\t" @@ -36364,50 +39024,50 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_order_8( "L_sp_256_mont_reduce_order_8_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL lr, %[mp], r6\n\t" + "MUL lr, r2, r6\n\t" /* a[i+0] += m[0] * mu */ - "LDR r12, [%[m]]\n\t" + "LDR r12, [r1]\n\t" "MOV r3, #0\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+1] += m[1] * mu */ - "LDR r12, [%[m], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "MOV r6, r7\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+2] += m[2] * mu */ - "LDR r12, [%[m], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "MOV r7, r8\n\t" "UMAAL r7, r3, lr, r12\n\t" /* a[i+3] += m[3] * mu */ - "LDR r12, [%[m], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "MOV r8, r9\n\t" "UMAAL r8, r3, lr, r12\n\t" /* a[i+4] += m[4] * mu */ - "LDR r12, [%[m], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "MOV r9, r10\n\t" "UMAAL r9, r3, lr, r12\n\t" /* a[i+5] += m[5] * mu */ - "LDR r12, [%[m], #20]\n\t" - "LDR r10, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR r10, [r0, #20]\n\t" "UMAAL r10, r3, lr, r12\n\t" /* a[i+6] += m[6] * mu */ - "LDR r12, [%[m], #24]\n\t" - "LDR r11, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR r11, [r0, #24]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #24]\n\t" + "STR r11, [r0, #24]\n\t" /* a[i+7] += m[7] * mu */ - "LDR r12, [%[m], #28]\n\t" - "LDR r11, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR r11, [r0, #28]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "LDR lr, [%[a], #32]\n\t" + "LDR lr, [r0, #32]\n\t" "MOV r12, #0\n\t" "UMAAL r3, lr, r12, r12\n\t" - "STR r11, [%[a], #28]\n\t" + "STR r11, [r0, #28]\n\t" "ADDS r3, r3, r5\n\t" "ADC r5, lr, #0\n\t" - "STR r3, [%[a], #32]\n\t" + "STR r3, [r0, #32]\n\t" /* i += 1 */ "ADD r4, r4, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r4, #32\n\t" #if defined(__GNUC__) "BLT L_sp_256_mont_reduce_order_8_word_%=\n\t" @@ -36417,22 +39077,33 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_reduce_order_8( "BLT.W L_sp_256_mont_reduce_order_8_word_%=\n\t" #endif /* Loop Done */ - "STR r6, [%[a]]\n\t" - "STR r7, [%[a], #4]\n\t" - "STR r8, [%[a], #8]\n\t" - "STR r9, [%[a], #12]\n\t" - "STR r10, [%[a], #16]\n\t" - "MOV %[mp], r5\n\t" + "STR r6, [r0]\n\t" + "STR r7, [r0, #4]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #12]\n\t" + "STR r10, [r0, #16]\n\t" + "MOV r2, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_256_cond_sub_8(a - 8, a, m, (sp_digit)0 - mp); } @@ -36497,21 +39168,30 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_add_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV lr, #0\n\t" - "LDM %[a], {r5, r6, r7, r8, r9, r10, r11, r12}\n\t" - "LDM %[b]!, {r3, r4}\n\t" + "LDM r1, {r5, r6, r7, r8, r9, r10, r11, r12}\n\t" + "LDM r2!, {r3, r4}\n\t" "ADDS r5, r5, r3\n\t" "ADCS r6, r6, r4\n\t" - "LDM %[b]!, {r3, r4}\n\t" + "LDM r2!, {r3, r4}\n\t" "ADCS r7, r7, r3\n\t" "ADCS r8, r8, r4\n\t" - "LDM %[b]!, {r3, r4}\n\t" + "LDM r2!, {r3, r4}\n\t" "ADCS r9, r9, r3\n\t" "ADCS r10, r10, r4\n\t" - "LDM %[b]!, {r3, r4}\n\t" + "LDM r2!, {r3, r4}\n\t" "ADCS r11, r11, r3\n\t" "ADCS r12, r12, r4\n\t" "ADC lr, lr, #0\n\t" @@ -36524,8 +39204,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_add_8(sp_digit* r, "SBCS r10, r10, #0\n\t" "SBCS r11, r11, lr, LSR #31\n\t" "SBCS r12, r12, lr\n\t" - "SBC %[b], %[b], %[b]\n\t" - "SUB lr, lr, %[b]\n\t" + "SBC r2, r2, r2\n\t" + "SUB lr, lr, r2\n\t" "SUBS r5, r5, lr\n\t" "SBCS r6, r6, lr\n\t" "SBCS r7, r7, lr\n\t" @@ -36534,21 +39214,31 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_add_8(sp_digit* r, "SBCS r10, r10, #0\n\t" "SBCS r11, r11, lr, LSR #31\n\t" "SBC r12, r12, lr\n\t" - "STM %[r], {r5, r6, r7, r8, r9, r10, r11, r12}\n\t" + "STM r0, {r5, r6, r7, r8, r9, r10, r11, r12}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (const sp_digit*)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -36569,11 +39259,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_dbl_8(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0\n\t" - "LDM %[a], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADDS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -36592,8 +39290,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_dbl_8(sp_digit* r, "SBCS r9, r9, #0\n\t" "SBCS r10, r10, r2, LSR #31\n\t" "SBCS r11, r11, r2\n\t" - "SBC %[a], %[a], %[a]\n\t" - "SUB r2, r2, %[a]\n\t" + "SBC r1, r1, r1\n\t" + "SUB r2, r2, r1\n\t" "SUBS r4, r4, r2\n\t" "SBCS r5, r5, r2\n\t" "SBCS r6, r6, r2\n\t" @@ -36602,21 +39300,30 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_dbl_8(sp_digit* r, "SBCS r9, r9, #0\n\t" "SBCS r10, r10, r2, LSR #31\n\t" "SBC r11, r11, r2\n\t" - "STM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r2" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r2" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -36637,11 +39344,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_tpl_8(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r12, #0\n\t" - "LDM %[a], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADDS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -36670,16 +39385,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_tpl_8(sp_digit* r, "SBCS r9, r9, #0\n\t" "SBCS r10, r10, r12, LSR #31\n\t" "SBC r11, r11, r12\n\t" - "LDM %[a]!, {r2, r3}\n\t" + "LDM r1!, {r2, r3}\n\t" "ADDS r4, r4, r2\n\t" "ADCS r5, r5, r3\n\t" - "LDM %[a]!, {r2, r3}\n\t" + "LDM r1!, {r2, r3}\n\t" "ADCS r6, r6, r2\n\t" "ADCS r7, r7, r3\n\t" - "LDM %[a]!, {r2, r3}\n\t" + "LDM r1!, {r2, r3}\n\t" "ADCS r8, r8, r2\n\t" "ADCS r9, r9, r3\n\t" - "LDM %[a]!, {r2, r3}\n\t" + "LDM r1!, {r2, r3}\n\t" "ADCS r10, r10, r2\n\t" "ADCS r11, r11, r3\n\t" "ADC r12, r12, #0\n\t" @@ -36702,21 +39417,30 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_tpl_8(sp_digit* r, "SBCS r9, r9, #0\n\t" "SBCS r10, r10, r12, LSR #31\n\t" "SBC r11, r11, r12\n\t" - "STM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r2", "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r2", "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -36740,22 +39464,31 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_sub_8(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register const sp_digit* m __asm__ ("r3") = (const sp_digit*)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV lr, #0\n\t" - "LDM %[a], {r5, r6, r7, r8, r9, r10, r11, r12}\n\t" - "LDM %[b]!, {r3, r4}\n\t" - "SUBS r5, r5, %[m]\n\t" + "LDM r1, {r5, r6, r7, r8, r9, r10, r11, r12}\n\t" + "LDM r2!, {r3, r4}\n\t" + "SUBS r5, r5, r3\n\t" "SBCS r6, r6, r4\n\t" - "LDM %[b]!, {r3, r4}\n\t" - "SBCS r7, r7, %[m]\n\t" + "LDM r2!, {r3, r4}\n\t" + "SBCS r7, r7, r3\n\t" "SBCS r8, r8, r4\n\t" - "LDM %[b]!, {r3, r4}\n\t" - "SBCS r9, r9, %[m]\n\t" + "LDM r2!, {r3, r4}\n\t" + "SBCS r9, r9, r3\n\t" "SBCS r10, r10, r4\n\t" - "LDM %[b]!, {r3, r4}\n\t" - "SBCS r11, r11, %[m]\n\t" + "LDM r2!, {r3, r4}\n\t" + "SBCS r11, r11, r3\n\t" "SBCS r12, r12, r4\n\t" "SBC lr, lr, #0\n\t" "ADDS r5, r5, lr\n\t" @@ -36775,17 +39508,29 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_sub_8(sp_digit* r, "ADCS r10, r10, #0\n\t" "ADCS r11, r11, lr, LSR #31\n\t" "ADC r12, r12, lr\n\t" - "STM %[r], {r5, r6, r7, r8, r9, r10, r11, r12}\n\t" + "STM r0, {r5, r6, r7, r8, r9, r10, r11, r12}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (const sp_digit*)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Divide the number by 2 mod the modulus (prime). (r = a / 2 % m) @@ -36806,19 +39551,27 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_div2_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* m __asm__ ("r2") = (const sp_digit*)m_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r4, r5, r6, r7}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1, {r4, r5, r6, r7}\n\t" "AND r3, r4, #1\n\t" "RSB r8, r3, #0\n\t" "ADDS r4, r4, r8\n\t" "ADCS r5, r5, r8\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, #0\n\t" - "STM %[r], {r4, r5, r6, r7}\n\t" - "LDRD r4, r5, [%[a], #16]\n\t" - "LDRD r6, r7, [%[a], #24]\n\t" + "STM r0, {r4, r5, r6, r7}\n\t" + "LDRD r4, r5, [r1, #16]\n\t" + "LDRD r6, r7, [r1, #24]\n\t" "ADCS r4, r4, #0\n\t" "ADCS r5, r5, #0\n\t" "ADCS r6, r6, r8, LSR #31\n\t" @@ -36834,9 +39587,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_div2_8(sp_digit* r, "ORR r10, r10, r7, LSL #31\n\t" "ORR r11, r11, r3, LSL #31\n\t" "MOV r3, r4\n\t" - "STRD r8, r9, [%[r], #16]\n\t" - "STRD r10, r11, [%[r], #24]\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" + "STRD r8, r9, [r0, #16]\n\t" + "STRD r10, r11, [r0, #24]\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" "LSR r8, r4, #1\n\t" "LSR r9, r5, #1\n\t" "LSR r10, r6, #1\n\t" @@ -36845,17 +39598,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_256_mont_div2_8(sp_digit* r, "ORR r9, r9, r6, LSL #31\n\t" "ORR r10, r10, r7, LSL #31\n\t" "ORR r11, r11, r3, LSL #31\n\t" - "STM %[r], {r8, r9, r10, r11}\n\t" + "STM r0, {r8, r9, r10, r11}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Double the Montgomery form projective point p. @@ -40250,30 +43014,47 @@ WC_OMIT_FRAME_POINTER static void sp_256_add_one_8(sp_digit* a) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; +#else + void* L_asm_args[1] = {(void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r1, r2, r3, r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r1, r2, r3, r4}\n\t" "ADDS r1, r1, #1\n\t" "ADCS r2, r2, #0\n\t" "ADCS r3, r3, #0\n\t" "ADCS r4, r4, #0\n\t" - "STM %[a]!, {r1, r2, r3, r4}\n\t" - "LDM %[a], {r1, r2, r3, r4}\n\t" + "STM r0!, {r1, r2, r3, r4}\n\t" + "LDM r0, {r1, r2, r3, r4}\n\t" "ADCS r1, r1, #0\n\t" "ADCS r2, r2, #0\n\t" "ADCS r3, r3, #0\n\t" "ADCS r4, r4, #0\n\t" - "STM %[a]!, {r1, r2, r3, r4}\n\t" + "STM r0!, {r1, r2, r3, r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a) : + : "memory", "cc", "r1", "r2", "r3", "r4" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif @@ -40679,11 +43460,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_sub_in_place_8(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "ADD r11, %[a], #32\n\t" + "ADD r11, r0, #32\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_256_sub_in_place_8_word:\n\t" @@ -40691,15 +43480,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_sub_in_place_8(sp_digit* a, "L_sp_256_sub_in_place_8_word_%=:\n\t" #endif "RSBS r10, r10, #0\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" "SBC r10, r10, r10\n\t" - "CMP %[a], r11\n\t" + "CMP r0, r11\n\t" #if defined(__GNUC__) "BNE L_sp_256_sub_in_place_8_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -40707,17 +43496,27 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_sub_in_place_8(sp_digit* a, #else "BNE.N L_sp_256_sub_in_place_8_word_%=\n\t" #endif - "MOV %[a], r10\n\t" + "MOV r0, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -40738,33 +43537,51 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_sub_in_place_8(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SUBS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "SBC %[a], r9, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "SBC r0, r9, r9\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -40788,14 +43605,22 @@ WC_OMIT_FRAME_POINTER static void sp_256_mul_d_8(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDR r8, [%[a]]\n\t" - "UMULL r5, r3, %[b], r8\n\t" + "LDR r8, [r1]\n\t" + "UMULL r5, r3, r2, r8\n\t" "MOV r4, #0\n\t" - "STR r5, [%[r]]\n\t" + "STR r5, [r0]\n\t" "MOV r5, #0\n\t" "MOV r9, #4\n\t" "\n" @@ -40805,12 +43630,12 @@ WC_OMIT_FRAME_POINTER static void sp_256_mul_d_8(sp_digit* r, const sp_digit* a, "L_sp_256_mul_d_8_word_%=:\n\t" #endif /* A[i] * B */ - "LDR r8, [%[a], r9]\n\t" - "UMULL r6, r7, %[b], r8\n\t" + "LDR r8, [r1, r9]\n\t" + "UMULL r6, r7, r2, r8\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], r9]\n\t" + "STR r3, [r0, r9]\n\t" "MOV r3, r4\n\t" "MOV r4, r5\n\t" "MOV r5, #0\n\t" @@ -40823,16 +43648,27 @@ WC_OMIT_FRAME_POINTER static void sp_256_mul_d_8(sp_digit* r, const sp_digit* a, #else "BLT.N L_sp_256_mul_d_8_word_%=\n\t" #endif - "STR r3, [%[r], #32]\n\t" + "STR r3, [r0, #32]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -40854,58 +43690,77 @@ WC_OMIT_FRAME_POINTER static void sp_256_mul_d_8(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDM %[a]!, {r8}\n\t" - "UMULL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMULL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[1] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[2] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[3] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[4] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[5] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[6] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[7] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" - "STR r5, [%[r]]\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" + "STR r5, [r0]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -40932,53 +43787,73 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_256_word_8(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r8, %[div], #16\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r8, r2, #16\n\t" "ADD r5, r8, #1\n\t" - "UDIV r6, %[d1], r5\n\t" - "LSL r7, %[div], #16\n\t" + "UDIV r6, r0, r5\n\t" + "LSL r7, r2, #16\n\t" "LSL r6, r6, #16\n\t" - "UMULL r3, r4, %[div], r6\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "SUBS r3, %[d1], r5\n\t" + "UMULL r3, r4, r2, r6\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "SUBS r3, r0, r5\n\t" "SBC r9, r9, r9\n\t" "ADD r9, r9, #1\n\t" "RSB r10, r9, #0\n\t" "LSL r9, r9, #16\n\t" "AND r7, r7, r10\n\t" "AND r8, r8, r10\n\t" - "SUBS %[d0], %[d0], r7\n\t" + "SUBS r1, r1, r7\n\t" "ADD r6, r6, r9\n\t" - "SBC %[d1], %[d1], r8\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "SBC r0, r0, r8\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "UMULL r3, r4, %[div], r3\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "UMULL r3, r4, r2, r3\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "MUL r3, %[div], r3\n\t" - "SUB %[d0], %[d0], r3\n\t" - "UDIV r3, %[d0], %[div]\n\t" - "ADD %[d1], r6, r3\n\t" + "MUL r3, r2, r3\n\t" + "SUB r1, r1, r3\n\t" + "UDIV r3, r1, r2\n\t" + "ADD r0, r6, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -41005,13 +43880,22 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_256_word_8(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r5, %[div], #1\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r5, r2, #1\n\t" "ADD r5, r5, #1\n\t" - "MOV r6, %[d0]\n\t" - "MOV r7, %[d1]\n\t" + "MOV r6, r1\n\t" + "MOV r7, r0\n\t" /* Do top 32 */ "SUBS r8, r5, r7\n\t" "SBC r8, r8, r8\n\t" @@ -41045,29 +43929,40 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_256_word_8(sp_digit d1, #endif "ADD r3, r3, r3\n\t" "ADD r3, r3, #1\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "SUBS r8, r9, %[div]\n\t" - "ADC %[d1], r3, #0\n\t" + "SUBS r8, r9, r2\n\t" + "ADC r0, r3, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -41746,11 +44641,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_sub_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r11, #0\n\t" - "ADD r12, %[a], #32\n\t" + "ADD r12, r1, #32\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_256_sub_8_word:\n\t" @@ -41758,15 +44661,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_sub_8(sp_digit* r, "L_sp_256_sub_8_word_%=:\n\t" #endif "RSBS r11, r11, #0\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "SBC r11, r3, r3\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_256_sub_8_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -41774,17 +44677,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_sub_8(sp_digit* r, #else "BNE.N L_sp_256_sub_8_word_%=\n\t" #endif - "MOV %[r], r11\n\t" + "MOV r0, r11\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -41807,33 +44721,52 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_256_sub_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -41855,12 +44788,20 @@ WC_OMIT_FRAME_POINTER static void sp_256_rshift1_8(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "LDRD r2, r3, [%[a], #16]\n\t" - "LDRD r4, r5, [%[a], #24]\n\t" + "LDRD r2, r3, [r1, #16]\n\t" + "LDRD r4, r5, [r1, #24]\n\t" "LSR r6, r2, #1\n\t" "LSR r7, r3, #1\n\t" "LSR r8, r4, #1\n\t" @@ -41870,10 +44811,10 @@ WC_OMIT_FRAME_POINTER static void sp_256_rshift1_8(sp_digit* r, "ORR r8, r8, r5, LSL #31\n\t" "ORR r9, r9, r10, LSL #31\n\t" "MOV r10, r2\n\t" - "STRD r6, r7, [%[r], #16]\n\t" - "STRD r8, r9, [%[r], #24]\n\t" - "LDRD r2, r3, [%[a]]\n\t" - "LDRD r4, r5, [%[a], #8]\n\t" + "STRD r6, r7, [r0, #16]\n\t" + "STRD r8, r9, [r0, #24]\n\t" + "LDRD r2, r3, [r1]\n\t" + "LDRD r4, r5, [r1, #8]\n\t" "LSR r6, r2, #1\n\t" "LSR r7, r3, #1\n\t" "LSR r8, r4, #1\n\t" @@ -41882,18 +44823,28 @@ WC_OMIT_FRAME_POINTER static void sp_256_rshift1_8(sp_digit* r, "ORR r7, r7, r4, LSL #31\n\t" "ORR r8, r8, r5, LSL #31\n\t" "ORR r9, r9, r10, LSL #31\n\t" - "STRD r6, r7, [%[r]]\n\t" - "STRD r8, r9, [%[r], #8]\n\t" + "STRD r6, r7, [r0]\n\t" + "STRD r8, r9, [r0, #8]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Divide the number by 2 mod the modulus. (r = a / 2 % m) @@ -41914,11 +44865,19 @@ WC_OMIT_FRAME_POINTER static void sp_256_div2_mod_8(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* m __asm__ ("r2") = (const sp_digit*)m_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r12, #0\n\t" - "LDM %[a]!, {r4}\n\t" + "LDM r1!, {r4}\n\t" "ANDS r3, r4, #1\n\t" #if defined(__GNUC__) "BEQ L_sp_256_div2_mod_8_even_%=\n\t" @@ -41927,15 +44886,15 @@ WC_OMIT_FRAME_POINTER static void sp_256_div2_mod_8(sp_digit* r, #else "BEQ.N L_sp_256_div2_mod_8_even_%=\n\t" #endif - "LDM %[a]!, {r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADDS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" @@ -41954,8 +44913,8 @@ WC_OMIT_FRAME_POINTER static void sp_256_div2_mod_8(sp_digit* r, #else "L_sp_256_div2_mod_8_even_%=:\n\t" #endif - "LDRD r4, r5, [%[a], #12]\n\t" - "LDRD r6, r7, [%[a], #20]\n\t" + "LDRD r4, r5, [r1, #12]\n\t" + "LDRD r6, r7, [r1, #20]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_256_div2_mod_8_div2:\n\t" @@ -41972,9 +44931,9 @@ WC_OMIT_FRAME_POINTER static void sp_256_div2_mod_8(sp_digit* r, "ORR r10, r10, r7, LSL #31\n\t" "ORR r11, r11, r3, LSL #31\n\t" "MOV r3, r4\n\t" - "STRD r8, r9, [%[r], #16]\n\t" - "STRD r10, r11, [%[r], #24]\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" + "STRD r8, r9, [r0, #16]\n\t" + "STRD r10, r11, [r0, #24]\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" "LSR r8, r4, #1\n\t" "LSR r9, r5, #1\n\t" "LSR r10, r6, #1\n\t" @@ -41983,17 +44942,28 @@ WC_OMIT_FRAME_POINTER static void sp_256_div2_mod_8(sp_digit* r, "ORR r9, r9, r6, LSL #31\n\t" "ORR r10, r10, r7, LSL #31\n\t" "ORR r11, r11, r3, LSL #31\n\t" - "STM %[r], {r8, r9, r10, r11}\n\t" + "STM r0, {r8, r9, r10, r11}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Get the number of bits in the number. @@ -42010,10 +44980,18 @@ WC_OMIT_FRAME_POINTER static int sp_256_num_bits_8(const sp_digit* a) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; +#else + void* L_asm_args[1] = {(void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r1, [%[a], #28]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r1, [r0, #28]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_256_num_bits_8_7_%=\n\t" @@ -42038,7 +45016,7 @@ WC_OMIT_FRAME_POINTER static int sp_256_num_bits_8(const sp_digit* a) #else "L_sp_256_num_bits_8_7_%=:\n\t" #endif - "LDR r1, [%[a], #24]\n\t" + "LDR r1, [r0, #24]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_256_num_bits_8_6_%=\n\t" @@ -42063,7 +45041,7 @@ WC_OMIT_FRAME_POINTER static int sp_256_num_bits_8(const sp_digit* a) #else "L_sp_256_num_bits_8_6_%=:\n\t" #endif - "LDR r1, [%[a], #20]\n\t" + "LDR r1, [r0, #20]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_256_num_bits_8_5_%=\n\t" @@ -42088,7 +45066,7 @@ WC_OMIT_FRAME_POINTER static int sp_256_num_bits_8(const sp_digit* a) #else "L_sp_256_num_bits_8_5_%=:\n\t" #endif - "LDR r1, [%[a], #16]\n\t" + "LDR r1, [r0, #16]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_256_num_bits_8_4_%=\n\t" @@ -42113,7 +45091,7 @@ WC_OMIT_FRAME_POINTER static int sp_256_num_bits_8(const sp_digit* a) #else "L_sp_256_num_bits_8_4_%=:\n\t" #endif - "LDR r1, [%[a], #12]\n\t" + "LDR r1, [r0, #12]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_256_num_bits_8_3_%=\n\t" @@ -42138,7 +45116,7 @@ WC_OMIT_FRAME_POINTER static int sp_256_num_bits_8(const sp_digit* a) #else "L_sp_256_num_bits_8_3_%=:\n\t" #endif - "LDR r1, [%[a], #8]\n\t" + "LDR r1, [r0, #8]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_256_num_bits_8_2_%=\n\t" @@ -42163,7 +45141,7 @@ WC_OMIT_FRAME_POINTER static int sp_256_num_bits_8(const sp_digit* a) #else "L_sp_256_num_bits_8_2_%=:\n\t" #endif - "LDR r1, [%[a], #4]\n\t" + "LDR r1, [r0, #4]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_256_num_bits_8_1_%=\n\t" @@ -42188,7 +45166,7 @@ WC_OMIT_FRAME_POINTER static int sp_256_num_bits_8(const sp_digit* a) #else "L_sp_256_num_bits_8_1_%=:\n\t" #endif - "LDR r1, [%[a]]\n\t" + "LDR r1, [r0]\n\t" "MOV r2, #32\n\t" "CLZ r4, r1\n\t" "SUB r4, r2, r4\n\t" @@ -42198,16 +45176,25 @@ WC_OMIT_FRAME_POINTER static int sp_256_num_bits_8(const sp_digit* a) #else "L_sp_256_num_bits_8_9_%=:\n\t" #endif - "MOV %[a], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a) : + : "memory", "cc", "r1", "r2", "r3", "r4", "r5" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4", "r5" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -43207,12 +46194,20 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_12(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x60\n\t" - "LDR lr, [%[a]]\n\t" - "LDR r11, [%[b]]\n\t" + "LDR lr, [r1]\n\t" + "LDR r11, [r2]\n\t" "UMULL r8, r6, lr, r11\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -43234,14 +46229,14 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_12(sp_digit* r, const sp_digit* a, #else "L_sp_384_mul_12_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" "ADC r8, r8, #0\n\t" - "LDR lr, [%[a], r4]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r4]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -43263,8 +46258,8 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_12(sp_digit* r, const sp_digit* a, #else "BLT.N L_sp_384_mul_12_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -43288,8 +46283,8 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_12(sp_digit* r, const sp_digit* a, #else "BLE.N L_sp_384_mul_12_outer_%=\n\t" #endif - "LDR lr, [%[a], #44]\n\t" - "LDR r11, [%[b], #44]\n\t" + "LDR lr, [r1, #44]\n\t" + "LDR r11, [r2, #44]\n\t" "UMLAL r6, r7, lr, r11\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -43301,7 +46296,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_12(sp_digit* r, const sp_digit* a, "L_sp_384_mul_12_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_384_mul_12_store_%=\n\t" @@ -43310,16 +46305,27 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_12(sp_digit* r, const sp_digit* a, #else "BGT.N L_sp_384_mul_12_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -43341,967 +46347,975 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_12(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #48\n\t" /* A[0] * B[0] */ - "LDR r11, [%[a]]\n\t" - "LDR r12, [%[b]]\n\t" + "LDR r11, [r1]\n\t" + "LDR r12, [r2]\n\t" "UMULL r3, r4, r11, r12\n\t" "MOV r5, #0\n\t" "STR r3, [sp]\n\t" /* A[0] * B[1] */ - "LDR r9, [%[b], #4]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[0] */ - "LDR r8, [%[a], #4]\n\t" + "LDR r8, [r1, #4]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #4]\n\t" /* A[2] * B[0] */ - "LDR r8, [%[a], #8]\n\t" + "LDR r8, [r1, #8]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[1] */ - "LDR r11, [%[a], #4]\n\t" - "LDR r12, [%[b], #4]\n\t" + "LDR r11, [r1, #4]\n\t" + "LDR r12, [r2, #4]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[0] * B[2] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #8]\n\t" /* A[0] * B[3] */ - "LDR r9, [%[b], #12]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[2] */ - "LDR r9, [%[b], #8]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[1] */ - "LDR r8, [%[a], #8]\n\t" + "LDR r8, [r1, #8]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[0] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #12]\n\t" /* A[4] * B[0] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[1] */ - "LDR r8, [%[a], #12]\n\t" + "LDR r8, [r1, #12]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[2] */ - "LDR r11, [%[a], #8]\n\t" - "LDR r12, [%[b], #8]\n\t" + "LDR r11, [r1, #8]\n\t" + "LDR r12, [r2, #8]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[3] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[0] * B[4] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #16]\n\t" /* A[0] * B[5] */ - "LDR r9, [%[b], #20]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[4] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[3] */ - "LDR r9, [%[b], #12]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[2] */ - "LDR r8, [%[a], #12]\n\t" + "LDR r8, [r1, #12]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[1] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[0] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #20]\n\t" /* A[6] * B[0] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[1] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[2] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[3] */ - "LDR r11, [%[a], #12]\n\t" - "LDR r12, [%[b], #12]\n\t" + "LDR r11, [r1, #12]\n\t" + "LDR r12, [r2, #12]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[4] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[5] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[0] * B[6] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #24]\n\t" /* A[0] * B[7] */ - "LDR r9, [%[b], #28]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[6] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[5] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[4] */ - "LDR r9, [%[b], #16]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[3] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[2] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[1] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[0] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #28]\n\t" /* A[8] * B[0] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[1] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[2] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[3] */ - "LDR r8, [%[a], #20]\n\t" + "LDR r8, [r1, #20]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[4] */ - "LDR r11, [%[a], #16]\n\t" - "LDR r12, [%[b], #16]\n\t" + "LDR r11, [r1, #16]\n\t" + "LDR r12, [r2, #16]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[5] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[6] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[7] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[0] * B[8] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #32]\n\t" /* A[0] * B[9] */ - "LDR r9, [%[b], #36]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[8] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[7] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[6] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[5] */ - "LDR r9, [%[b], #20]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[4] */ - "LDR r8, [%[a], #20]\n\t" + "LDR r8, [r1, #20]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[3] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[2] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[1] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[0] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #36]\n\t" /* A[10] * B[0] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[1] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[2] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[3] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[4] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[5] */ - "LDR r11, [%[a], #20]\n\t" - "LDR r12, [%[b], #20]\n\t" + "LDR r11, [r1, #20]\n\t" + "LDR r12, [r2, #20]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[6] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[7] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[8] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[9] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[0] * B[10] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #40]\n\t" /* A[0] * B[11] */ - "LDR r9, [%[b], #44]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[10] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[9] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[8] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[7] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[6] */ - "LDR r9, [%[b], #24]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[5] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[4] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[3] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[2] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[1] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[0] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #44]\n\t" /* A[11] * B[1] */ - "LDR r9, [%[b], #4]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[2] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[3] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[4] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[5] */ - "LDR r8, [%[a], #28]\n\t" + "LDR r8, [r1, #28]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[6] */ - "LDR r11, [%[a], #24]\n\t" - "LDR r12, [%[b], #24]\n\t" + "LDR r11, [r1, #24]\n\t" + "LDR r12, [r2, #24]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[7] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[8] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[9] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[10] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[11] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #48]\n\t" + "STR r3, [r0, #48]\n\t" /* A[2] * B[11] */ - "LDR r8, [%[a], #8]\n\t" + "LDR r8, [r1, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[10] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[9] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[8] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[7] */ - "LDR r9, [%[b], #28]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[6] */ - "LDR r8, [%[a], #28]\n\t" + "LDR r8, [r1, #28]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[5] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[4] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[3] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[2] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #52]\n\t" + "STR r4, [r0, #52]\n\t" /* A[11] * B[3] */ - "LDR r9, [%[b], #12]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[4] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[5] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[6] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[7] */ - "LDR r11, [%[a], #28]\n\t" - "LDR r12, [%[b], #28]\n\t" + "LDR r11, [r1, #28]\n\t" + "LDR r12, [r2, #28]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[8] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[9] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[10] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[11] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #56]\n\t" + "STR r5, [r0, #56]\n\t" /* A[4] * B[11] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[10] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[9] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[8] */ - "LDR r9, [%[b], #32]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[7] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[6] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[5] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[4] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #60]\n\t" + "STR r3, [r0, #60]\n\t" /* A[11] * B[5] */ - "LDR r9, [%[b], #20]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[6] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[7] */ - "LDR r8, [%[a], #36]\n\t" + "LDR r8, [r1, #36]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[8] */ - "LDR r11, [%[a], #32]\n\t" - "LDR r12, [%[b], #32]\n\t" + "LDR r11, [r1, #32]\n\t" + "LDR r12, [r2, #32]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[9] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[10] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[11] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #64]\n\t" + "STR r4, [r0, #64]\n\t" /* A[6] * B[11] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[10] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[9] */ - "LDR r9, [%[b], #36]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[8] */ - "LDR r8, [%[a], #36]\n\t" + "LDR r8, [r1, #36]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[7] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[6] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #68]\n\t" + "STR r5, [r0, #68]\n\t" /* A[11] * B[7] */ - "LDR r9, [%[b], #28]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[8] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[9] */ - "LDR r11, [%[a], #36]\n\t" - "LDR r12, [%[b], #36]\n\t" + "LDR r11, [r1, #36]\n\t" + "LDR r12, [r2, #36]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[10] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[11] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #72]\n\t" + "STR r3, [r0, #72]\n\t" /* A[8] * B[11] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[10] */ - "LDR r9, [%[b], #40]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[9] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[8] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #76]\n\t" + "STR r4, [r0, #76]\n\t" /* A[11] * B[9] */ "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" @@ -44309,20 +47323,20 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_12(sp_digit* r, const sp_digit* a, "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[10] */ - "LDR r11, [%[a], #40]\n\t" - "LDR r12, [%[b], #40]\n\t" + "LDR r11, [r1, #40]\n\t" + "LDR r12, [r2, #40]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[11] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #80]\n\t" + "STR r5, [r0, #80]\n\t" /* A[10] * B[11] */ "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" @@ -44330,32 +47344,43 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_12(sp_digit* r, const sp_digit* a, "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[10] */ - "LDR r8, [%[a], #44]\n\t" + "LDR r8, [r1, #44]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #84]\n\t" + "STR r3, [r0, #84]\n\t" /* A[11] * B[11] */ "UMLAL r4, r5, r8, r9\n\t" - "STR r4, [%[r], #88]\n\t" - "STR r5, [%[r], #92]\n\t" + "STR r4, [r0, #88]\n\t" + "STR r5, [r0, #92]\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r11", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r11", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -44375,11 +47400,19 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x60\n\t" - "LDR lr, [%[a]]\n\t" + "LDR lr, [r1]\n\t" "UMULL r8, r6, lr, lr\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -44401,8 +47434,8 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) #else "L_sp_384_sqr_12_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[a], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r1, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -44427,7 +47460,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) #else "BLT.N L_sp_384_sqr_12_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" + "LDR lr, [r1, r3]\n\t" "UMULL r9, r10, lr, lr\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -44451,7 +47484,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) #else "BLE.N L_sp_384_sqr_12_outer_%=\n\t" #endif - "LDR lr, [%[a], #44]\n\t" + "LDR lr, [r1, #44]\n\t" "UMLAL r6, r7, lr, lr\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -44463,7 +47496,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "L_sp_384_sqr_12_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_384_sqr_12_store_%=\n\t" @@ -44472,16 +47505,26 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) #else "BGT.N L_sp_384_sqr_12_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -44500,18 +47543,26 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #48\n\t" /* A[0] * A[0] */ - "LDR r10, [%[a]]\n\t" + "LDR r10, [r1]\n\t" "UMULL r8, r3, r10, r10\n\t" "MOV r4, #0\n\t" "STR r8, [sp]\n\t" /* A[0] * A[1] */ - "LDR r10, [%[a], #4]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #4]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -44523,8 +47574,8 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADC r2, r2, #0\n\t" "STR r3, [sp, #4]\n\t" /* A[0] * A[2] */ - "LDR r10, [%[a], #8]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #8]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" @@ -44535,15 +47586,15 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * A[1] */ - "LDR r10, [%[a], #4]\n\t" + "LDR r10, [r1, #4]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #8]\n\t" /* A[0] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -44554,8 +47605,8 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * A[2] */ - "LDR r10, [%[a], #8]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #8]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -44565,8 +47616,8 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADC r4, r4, #0\n\t" "STR r2, [sp, #12]\n\t" /* A[0] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -44577,8 +47628,8 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "MOV r2, #0\n\t" "ADC r2, r2, #0\n\t" /* A[1] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -44587,28 +47638,28 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" /* A[2] * A[2] */ - "LDR r10, [%[a], #8]\n\t" + "LDR r10, [r1, #8]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" "STR r3, [sp, #16]\n\t" /* A[0] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -44621,27 +47672,27 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #20]\n\t" /* A[0] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[3] */ - "LDR r10, [%[a], #12]\n\t" + "LDR r10, [r1, #12]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -44654,28 +47705,28 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #24]\n\t" /* A[0] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -44688,34 +47739,34 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADC r2, r2, r7\n\t" "STR r3, [sp, #28]\n\t" /* A[0] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[4] */ - "LDR r10, [%[a], #16]\n\t" + "LDR r10, [r1, #16]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -44728,35 +47779,35 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #32]\n\t" /* A[0] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -44769,41 +47820,41 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #36]\n\t" /* A[0] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[5] */ - "LDR r10, [%[a], #20]\n\t" + "LDR r10, [r1, #20]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -44816,42 +47867,42 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADC r2, r2, r7\n\t" "STR r3, [sp, #40]\n\t" /* A[0] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -44864,41 +47915,41 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #44]\n\t" /* A[1] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[2] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[6] */ - "LDR r10, [%[a], #24]\n\t" + "LDR r10, [r1, #24]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -44909,37 +47960,37 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r5\n\t" "ADCS r3, r3, r6\n\t" "ADC r4, r4, r7\n\t" - "STR r2, [%[r], #48]\n\t" + "STR r2, [r0, #48]\n\t" /* A[2] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[3] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -44950,36 +48001,36 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r5\n\t" "ADCS r4, r4, r6\n\t" "ADC r2, r2, r7\n\t" - "STR r3, [%[r], #52]\n\t" + "STR r3, [r0, #52]\n\t" /* A[3] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[4] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[7] */ - "LDR r10, [%[a], #28]\n\t" + "LDR r10, [r1, #28]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -44990,30 +48041,30 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r5\n\t" "ADCS r2, r2, r6\n\t" "ADC r3, r3, r7\n\t" - "STR r4, [%[r], #56]\n\t" + "STR r4, [r0, #56]\n\t" /* A[4] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[5] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -45024,29 +48075,29 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r5\n\t" "ADCS r3, r3, r6\n\t" "ADC r4, r4, r7\n\t" - "STR r2, [%[r], #60]\n\t" + "STR r2, [r0, #60]\n\t" /* A[5] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[6] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[8] */ - "LDR r10, [%[a], #32]\n\t" + "LDR r10, [r1, #32]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -45057,23 +48108,23 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r5\n\t" "ADCS r4, r4, r6\n\t" "ADC r2, r2, r7\n\t" - "STR r3, [%[r], #64]\n\t" + "STR r3, [r0, #64]\n\t" /* A[6] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[7] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -45084,10 +48135,10 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r5\n\t" "ADCS r2, r2, r6\n\t" "ADC r3, r3, r7\n\t" - "STR r4, [%[r], #68]\n\t" + "STR r4, [r0, #68]\n\t" /* A[7] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -45098,8 +48149,8 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[8] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -45108,15 +48159,15 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADCS r3, r3, r9\n\t" "ADC r4, r4, #0\n\t" /* A[9] * A[9] */ - "LDR r10, [%[a], #36]\n\t" + "LDR r10, [r1, #36]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" "ADC r4, r4, #0\n\t" - "STR r2, [%[r], #72]\n\t" + "STR r2, [r0, #72]\n\t" /* A[8] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -45127,8 +48178,8 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "MOV r2, #0\n\t" "ADC r2, r2, #0\n\t" /* A[9] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -45136,10 +48187,10 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" - "STR r3, [%[r], #76]\n\t" + "STR r3, [r0, #76]\n\t" /* A[9] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" @@ -45150,15 +48201,15 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[10] * A[10] */ - "LDR r10, [%[a], #40]\n\t" + "LDR r10, [r1, #40]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #80]\n\t" + "STR r4, [r0, #80]\n\t" /* A[10] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -45168,28 +48219,38 @@ WC_OMIT_FRAME_POINTER static void sp_384_sqr_12(sp_digit* r, const sp_digit* a) "ADCS r3, r3, r9\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" - "STR r2, [%[r], #84]\n\t" + "STR r2, [r0, #84]\n\t" /* A[11] * A[11] */ - "LDR r10, [%[a], #44]\n\t" + "LDR r10, [r1, #44]\n\t" "UMLAL r3, r4, r10, r10\n\t" - "STR r3, [%[r], #88]\n\t" - "STR r4, [%[r], #92]\n\t" + "STR r3, [r0, #88]\n\t" + "STR r4, [r0, #92]\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -45212,11 +48273,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_add_12(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r3, #0\n\t" - "ADD r12, %[a], #48\n\t" + "ADD r12, r1, #48\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_384_add_12_word:\n\t" @@ -45224,16 +48293,16 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_add_12(sp_digit* r, "L_sp_384_add_12_word_%=:\n\t" #endif "ADDS r3, r3, #0xffffffff\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "MOV r4, #0\n\t" "ADC r3, r4, #0\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_384_add_12_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -45241,17 +48310,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_add_12(sp_digit* r, #else "BNE.N L_sp_384_add_12_word_%=\n\t" #endif - "MOV %[r], r3\n\t" + "MOV r0, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -45274,41 +48354,60 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_add_12(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -45623,9 +48722,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_cond_sub_12(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, #0\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -45636,12 +48744,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_cond_sub_12(sp_digit* r, "L_sp_384_cond_sub_12_words_%=:\n\t" #endif "SUBS r4, r8, r4\n\t" - "LDR r6, [%[a], r5]\n\t" - "LDR r7, [%[b], r5]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r5]\n\t" + "LDR r7, [r2, r5]\n\t" + "AND r7, r7, r3\n\t" "SBCS r6, r6, r7\n\t" "SBC r4, r8, r8\n\t" - "STR r6, [%[r], r5]\n\t" + "STR r6, [r0, r5]\n\t" "ADD r5, r5, #4\n\t" "CMP r5, #48\n\t" #if defined(__GNUC__) @@ -45651,16 +48759,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_cond_sub_12(sp_digit* r, #else "BLT.N L_sp_384_cond_sub_12_words_%=\n\t" #endif - "MOV %[r], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -45687,62 +48807,83 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_cond_sub_12(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SUBS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "SBC %[r], r5, r5\n\t" + "STM r0!, {r6, r7}\n\t" + "SBC r0, r5, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -45769,15 +48910,24 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_384_mont_reduce_12(sp_digit* a, register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR lr, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR lr, [r1]\n\t" /* i = 0 */ "MOV r11, #0\n\t" "MOV r3, #0\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[a], #4]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_384_mont_reduce_12_word:\n\t" @@ -45785,105 +48935,105 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_384_mont_reduce_12(sp_digit* a, "L_sp_384_mont_reduce_12_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL r10, %[mp], r4\n\t" + "MUL r10, r2, r4\n\t" /* a[i+0] += m[0] * mu */ "MOV r7, #0\n\t" "UMLAL r4, r7, r10, lr\n\t" /* a[i+1] += m[1] * mu */ - "LDR r9, [%[m], #4]\n\t" + "LDR r9, [r1, #4]\n\t" "MOV r6, #0\n\t" "UMLAL r5, r6, r10, r9\n\t" "MOV r4, r5\n\t" "ADDS r4, r4, r7\n\t" "ADC r6, r6, #0\n\t" /* a[i+2] += m[2] * mu */ - "LDR r9, [%[m], #8]\n\t" - "LDR r5, [%[a], #8]\n\t" + "LDR r9, [r1, #8]\n\t" + "LDR r5, [r0, #8]\n\t" "MOV r7, #0\n\t" "UMLAL r5, r7, r10, r9\n\t" "ADDS r5, r5, r6\n\t" "ADC r7, r7, #0\n\t" /* a[i+3] += m[3] * mu */ - "LDR r9, [%[m], #12]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r9, [r1, #12]\n\t" + "LDR r12, [r0, #12]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #12]\n\t" + "STR r12, [r0, #12]\n\t" "ADC r6, r6, #0\n\t" /* a[i+4] += m[4] * mu */ - "LDR r9, [%[m], #16]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r9, [r1, #16]\n\t" + "LDR r12, [r0, #16]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #16]\n\t" + "STR r12, [r0, #16]\n\t" "ADC r7, r7, #0\n\t" /* a[i+5] += m[5] * mu */ - "LDR r9, [%[m], #20]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r12, [r0, #20]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #20]\n\t" + "STR r12, [r0, #20]\n\t" "ADC r6, r6, #0\n\t" /* a[i+6] += m[6] * mu */ - "LDR r9, [%[m], #24]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r9, [r1, #24]\n\t" + "LDR r12, [r0, #24]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #24]\n\t" + "STR r12, [r0, #24]\n\t" "ADC r7, r7, #0\n\t" /* a[i+7] += m[7] * mu */ - "LDR r9, [%[m], #28]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r9, [r1, #28]\n\t" + "LDR r12, [r0, #28]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #28]\n\t" + "STR r12, [r0, #28]\n\t" "ADC r6, r6, #0\n\t" /* a[i+8] += m[8] * mu */ - "LDR r9, [%[m], #32]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r9, [r1, #32]\n\t" + "LDR r12, [r0, #32]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #32]\n\t" + "STR r12, [r0, #32]\n\t" "ADC r7, r7, #0\n\t" /* a[i+9] += m[9] * mu */ - "LDR r9, [%[m], #36]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r9, [r1, #36]\n\t" + "LDR r12, [r0, #36]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #36]\n\t" + "STR r12, [r0, #36]\n\t" "ADC r6, r6, #0\n\t" /* a[i+10] += m[10] * mu */ - "LDR r9, [%[m], #40]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r9, [r1, #40]\n\t" + "LDR r12, [r0, #40]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #40]\n\t" + "STR r12, [r0, #40]\n\t" "ADC r7, r7, #0\n\t" /* a[i+11] += m[11] * mu */ - "LDR r9, [%[m], #44]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r9, [r1, #44]\n\t" + "LDR r12, [r0, #44]\n\t" "UMULL r8, r9, r10, r9\n\t" "ADDS r7, r7, r8\n\t" "ADCS r6, r9, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, r3\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #44]\n\t" - "LDR r12, [%[a], #48]\n\t" + "STR r12, [r0, #44]\n\t" + "LDR r12, [r0, #48]\n\t" "ADCS r12, r12, r6\n\t" - "STR r12, [%[a], #48]\n\t" + "STR r12, [r0, #48]\n\t" "ADC r3, r3, #0\n\t" /* i += 1 */ "ADD r11, r11, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r11, #48\n\t" #if defined(__GNUC__) "BLT L_sp_384_mont_reduce_12_word_%=\n\t" @@ -45893,19 +49043,30 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_384_mont_reduce_12(sp_digit* a, "BLT.W L_sp_384_mont_reduce_12_word_%=\n\t" #endif /* Loop Done */ - "STR r4, [%[a]]\n\t" - "STR r5, [%[a], #4]\n\t" - "MOV %[mp], r3\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_384_cond_sub_12(a - 12, a, m, (sp_digit)0 - mp); } @@ -45929,17 +49090,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_384_mont_reduce_12(sp_digit* a, register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* i = 0 */ "MOV r4, #0\n\t" "MOV r5, #0\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r7, [%[a], #4]\n\t" - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[a], #12]\n\t" - "LDR r10, [%[a], #16]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" + "LDR r10, [r0, #16]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_384_mont_reduce_12_word:\n\t" @@ -45947,70 +49117,70 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_384_mont_reduce_12(sp_digit* a, "L_sp_384_mont_reduce_12_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL lr, %[mp], r6\n\t" + "MUL lr, r2, r6\n\t" /* a[i+0] += m[0] * mu */ - "LDR r12, [%[m]]\n\t" + "LDR r12, [r1]\n\t" "MOV r3, #0\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+1] += m[1] * mu */ - "LDR r12, [%[m], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "MOV r6, r7\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+2] += m[2] * mu */ - "LDR r12, [%[m], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "MOV r7, r8\n\t" "UMAAL r7, r3, lr, r12\n\t" /* a[i+3] += m[3] * mu */ - "LDR r12, [%[m], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "MOV r8, r9\n\t" "UMAAL r8, r3, lr, r12\n\t" /* a[i+4] += m[4] * mu */ - "LDR r12, [%[m], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "MOV r9, r10\n\t" "UMAAL r9, r3, lr, r12\n\t" /* a[i+5] += m[5] * mu */ - "LDR r12, [%[m], #20]\n\t" - "LDR r10, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR r10, [r0, #20]\n\t" "UMAAL r10, r3, lr, r12\n\t" /* a[i+6] += m[6] * mu */ - "LDR r12, [%[m], #24]\n\t" - "LDR r11, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR r11, [r0, #24]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #24]\n\t" + "STR r11, [r0, #24]\n\t" /* a[i+7] += m[7] * mu */ - "LDR r12, [%[m], #28]\n\t" - "LDR r11, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR r11, [r0, #28]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #28]\n\t" + "STR r11, [r0, #28]\n\t" /* a[i+8] += m[8] * mu */ - "LDR r12, [%[m], #32]\n\t" - "LDR r11, [%[a], #32]\n\t" + "LDR r12, [r1, #32]\n\t" + "LDR r11, [r0, #32]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #32]\n\t" + "STR r11, [r0, #32]\n\t" /* a[i+9] += m[9] * mu */ - "LDR r12, [%[m], #36]\n\t" - "LDR r11, [%[a], #36]\n\t" + "LDR r12, [r1, #36]\n\t" + "LDR r11, [r0, #36]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #36]\n\t" + "STR r11, [r0, #36]\n\t" /* a[i+10] += m[10] * mu */ - "LDR r12, [%[m], #40]\n\t" - "LDR r11, [%[a], #40]\n\t" + "LDR r12, [r1, #40]\n\t" + "LDR r11, [r0, #40]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #40]\n\t" + "STR r11, [r0, #40]\n\t" /* a[i+11] += m[11] * mu */ - "LDR r12, [%[m], #44]\n\t" - "LDR r11, [%[a], #44]\n\t" + "LDR r12, [r1, #44]\n\t" + "LDR r11, [r0, #44]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "LDR lr, [%[a], #48]\n\t" + "LDR lr, [r0, #48]\n\t" "MOV r12, #0\n\t" "UMAAL r3, lr, r12, r12\n\t" - "STR r11, [%[a], #44]\n\t" + "STR r11, [r0, #44]\n\t" "ADDS r3, r3, r5\n\t" "ADC r5, lr, #0\n\t" - "STR r3, [%[a], #48]\n\t" + "STR r3, [r0, #48]\n\t" /* i += 1 */ "ADD r4, r4, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r4, #48\n\t" #if defined(__GNUC__) "BLT L_sp_384_mont_reduce_12_word_%=\n\t" @@ -46020,22 +49190,33 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_384_mont_reduce_12(sp_digit* a, "BLT.W L_sp_384_mont_reduce_12_word_%=\n\t" #endif /* Loop Done */ - "STR r6, [%[a]]\n\t" - "STR r7, [%[a], #4]\n\t" - "STR r8, [%[a], #8]\n\t" - "STR r9, [%[a], #12]\n\t" - "STR r10, [%[a], #16]\n\t" - "MOV %[mp], r5\n\t" + "STR r6, [r0]\n\t" + "STR r7, [r0, #4]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #12]\n\t" + "STR r10, [r0, #16]\n\t" + "MOV r2, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_384_cond_sub_12(a - 12, a, m, (sp_digit)0 - mp); } @@ -46201,9 +49382,17 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0xffffffff\n\t" "MOV r8, #1\n\t" "MOV r7, #0\n\t" @@ -46216,8 +49405,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, #else "L_sp_384_cmp_12_words_%=:\n\t" #endif - "LDR r4, [%[a], r6]\n\t" - "LDR r5, [%[b], r6]\n\t" + "LDR r4, [r0, r6]\n\t" + "LDR r5, [r1, r6]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46235,8 +49424,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, #endif "EOR r2, r2, r3\n\t" #else - "LDR r4, [%[a], #44]\n\t" - "LDR r5, [%[b], #44]\n\t" + "LDR r4, [r0, #44]\n\t" + "LDR r5, [r1, #44]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46246,8 +49435,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #40]\n\t" - "LDR r5, [%[b], #40]\n\t" + "LDR r4, [r0, #40]\n\t" + "LDR r5, [r1, #40]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46257,8 +49446,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #36]\n\t" - "LDR r5, [%[b], #36]\n\t" + "LDR r4, [r0, #36]\n\t" + "LDR r5, [r1, #36]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46268,8 +49457,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #32]\n\t" - "LDR r5, [%[b], #32]\n\t" + "LDR r4, [r0, #32]\n\t" + "LDR r5, [r1, #32]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46279,8 +49468,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #28]\n\t" - "LDR r5, [%[b], #28]\n\t" + "LDR r4, [r0, #28]\n\t" + "LDR r5, [r1, #28]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46290,8 +49479,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #24]\n\t" - "LDR r5, [%[b], #24]\n\t" + "LDR r4, [r0, #24]\n\t" + "LDR r5, [r1, #24]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46301,8 +49490,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #20]\n\t" - "LDR r5, [%[b], #20]\n\t" + "LDR r4, [r0, #20]\n\t" + "LDR r5, [r1, #20]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46312,8 +49501,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #16]\n\t" - "LDR r5, [%[b], #16]\n\t" + "LDR r4, [r0, #16]\n\t" + "LDR r5, [r1, #16]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46323,8 +49512,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #12]\n\t" - "LDR r5, [%[b], #12]\n\t" + "LDR r4, [r0, #12]\n\t" + "LDR r5, [r1, #12]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46334,8 +49523,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #8]\n\t" - "LDR r5, [%[b], #8]\n\t" + "LDR r4, [r0, #8]\n\t" + "LDR r5, [r1, #8]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46345,8 +49534,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #4]\n\t" - "LDR r5, [%[b], #4]\n\t" + "LDR r4, [r0, #4]\n\t" + "LDR r5, [r1, #4]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46356,8 +49545,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[b]]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r1]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -46369,16 +49558,26 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_384_cmp_12(const sp_digit* a, "movne r3, r7\n\t" "EOR r2, r2, r3\n\t" #endif /*WOLFSSL_SP_SMALL */ - "MOV %[a], r2\n\t" + "MOV r0, r2\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -46448,85 +49647,106 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_384_mont_add_12(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register const sp_digit* m __asm__ ("r3") = (const sp_digit*)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r3, #0\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "ADDS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" "ADC r3, r3, #0\n\t" - "SUB %[r], %[r], #48\n\t" + "SUB r0, r0, #48\n\t" "RSB r3, r3, #0\n\t" "LSR r12, r3, #1\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "SUBS r8, r8, r3\n\t" "SBCS r9, r9, #0\n\t" "SBCS r10, r10, #0\n\t" "SBCS r11, r11, r3\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "SBCS r8, r8, r12, LSL #1\n\t" "SBCS r9, r9, r3\n\t" "SBCS r10, r10, r3\n\t" "SBCS r11, r11, r3\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "SBCS r8, r8, r3\n\t" "SBCS r9, r9, r3\n\t" "SBCS r10, r10, r3\n\t" "SBCS r11, r11, r3\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "SBC %[b], %[b], %[b]\n\t" - "SUB %[r], %[r], #48\n\t" - "SUB r3, r3, %[b]\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "SBC r2, r2, r2\n\t" + "SUB r0, r0, #48\n\t" + "SUB r3, r3, r2\n\t" "LSR r12, r3, #1\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "SUBS r8, r8, r3\n\t" "SBCS r9, r9, #0\n\t" "SBCS r10, r10, #0\n\t" "SBCS r11, r11, r3\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "SBCS r8, r8, r12, LSL #1\n\t" "SBCS r9, r9, r3\n\t" "SBCS r10, r10, r3\n\t" "SBCS r11, r11, r3\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "SBCS r8, r8, r3\n\t" "SBCS r9, r9, r3\n\t" "SBCS r10, r10, r3\n\t" "SBC r11, r11, r3\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (const sp_digit*)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Double a Montgomery form number (r = a + a % m). @@ -46547,75 +49767,94 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_384_mont_dbl_12(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* m __asm__ ("r2") = (const sp_digit*)m_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9}\n\t" "ADDS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" "ADCS r7, r7, r7\n\t" "ADCS r8, r8, r8\n\t" "ADCS r9, r9, r9\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9}\n\t" "ADCS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" "ADCS r7, r7, r7\n\t" "ADCS r8, r8, r8\n\t" "ADCS r9, r9, r9\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" "ADC r2, r2, #0\n\t" - "SUB %[r], %[r], #48\n\t" + "SUB r0, r0, #48\n\t" "RSB r2, r2, #0\n\t" "LSR r3, r2, #1\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SUBS r4, r4, r2\n\t" "SBCS r5, r5, #0\n\t" "SBCS r6, r6, #0\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r3, LSL #1\n\t" "SBCS r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SBCS r4, r4, r2\n\t" "SBCS r5, r5, r2\n\t" "SBCS r6, r6, r2\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r2\n\t" "SBCS r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" - "SBC %[a], %[a], %[a]\n\t" - "SUB %[r], %[r], #48\n\t" - "SUB r2, r2, %[a]\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" + "SBC r1, r1, r1\n\t" + "SUB r0, r0, #48\n\t" + "SUB r2, r2, r1\n\t" "LSR r3, r2, #1\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SUBS r4, r4, r2\n\t" "SBCS r5, r5, #0\n\t" "SBCS r6, r6, #0\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r3, LSL #1\n\t" "SBCS r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SBCS r4, r4, r2\n\t" "SBCS r5, r5, r2\n\t" "SBCS r6, r6, r2\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r2\n\t" "SBC r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r3" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r3" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Triple a Montgomery form number (r = a + a + a % m). @@ -46636,140 +49875,159 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_384_mont_tpl_12(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* m __asm__ ("r2") = (const sp_digit*)m_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9}\n\t" "ADDS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" "ADCS r7, r7, r7\n\t" "ADCS r8, r8, r8\n\t" "ADCS r9, r9, r9\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9}\n\t" "ADCS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" "ADCS r7, r7, r7\n\t" "ADCS r8, r8, r8\n\t" "ADCS r9, r9, r9\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" "ADC r2, r2, #0\n\t" - "SUB %[r], %[r], #48\n\t" + "SUB r0, r0, #48\n\t" "RSB r2, r2, #0\n\t" "LSR r3, r2, #1\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SUBS r4, r4, r2\n\t" "SBCS r5, r5, #0\n\t" "SBCS r6, r6, #0\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r3, LSL #1\n\t" "SBCS r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SBCS r4, r4, r2\n\t" "SBCS r5, r5, r2\n\t" "SBCS r6, r6, r2\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r2\n\t" "SBCS r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" "SBC r12, r12, r12\n\t" - "SUB %[r], %[r], #48\n\t" + "SUB r0, r0, #48\n\t" "SUB r2, r2, r12\n\t" "LSR r3, r2, #1\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SUBS r4, r4, r2\n\t" "SBCS r5, r5, #0\n\t" "SBCS r6, r6, #0\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r3, LSL #1\n\t" "SBCS r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SBCS r4, r4, r2\n\t" "SBCS r5, r5, r2\n\t" "SBCS r6, r6, r2\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r2\n\t" "SBC r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" - "SUB %[r], %[r], #48\n\t" - "SUB %[a], %[a], #48\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" + "SUB r0, r0, #48\n\t" + "SUB r1, r1, #48\n\t" "MOV r2, #0\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADDS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" "ADC r2, r2, #0\n\t" - "SUB %[r], %[r], #48\n\t" + "SUB r0, r0, #48\n\t" "RSB r2, r2, #0\n\t" "LSR r3, r2, #1\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SUBS r4, r4, r2\n\t" "SBCS r5, r5, #0\n\t" "SBCS r6, r6, #0\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r3, LSL #1\n\t" "SBCS r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SBCS r4, r4, r2\n\t" "SBCS r5, r5, r2\n\t" "SBCS r6, r6, r2\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r2\n\t" "SBCS r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" "SBC r12, r12, r12\n\t" - "SUB %[r], %[r], #48\n\t" + "SUB r0, r0, #48\n\t" "SUB r2, r2, r12\n\t" "LSR r3, r2, #1\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SUBS r4, r4, r2\n\t" "SBCS r5, r5, #0\n\t" "SBCS r6, r6, #0\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r3, LSL #1\n\t" "SBCS r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9}\n\t" "SBCS r4, r4, r2\n\t" "SBCS r5, r5, r2\n\t" "SBCS r6, r6, r2\n\t" "SBCS r7, r7, r2\n\t" "SBCS r8, r8, r2\n\t" "SBC r9, r9, r2\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifndef WOLFSSL_SP_SMALL @@ -46791,40 +50049,59 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_sub_12(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -46852,9 +50129,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_cond_add_12(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" "MOV r8, #0\n\t" "MOV r4, #0\n\t" @@ -46865,12 +50151,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_cond_add_12(sp_digit* r, "L_sp_384_cond_add_12_words_%=:\n\t" #endif "ADDS r5, r5, #0xffffffff\n\t" - "LDR r6, [%[a], r4]\n\t" - "LDR r7, [%[b], r4]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r4]\n\t" + "LDR r7, [r2, r4]\n\t" + "AND r7, r7, r3\n\t" "ADCS r6, r6, r7\n\t" "ADC r5, r8, r8\n\t" - "STR r6, [%[r], r4]\n\t" + "STR r6, [r0, r4]\n\t" "ADD r4, r4, #4\n\t" "CMP r4, #48\n\t" #if defined(__GNUC__) @@ -46880,16 +50166,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_cond_add_12(sp_digit* r, #else "BLT.N L_sp_384_cond_add_12_words_%=\n\t" #endif - "MOV %[r], r5\n\t" + "MOV r0, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -46916,62 +50214,83 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_cond_add_12(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADDS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "ADC %[r], r10, r10\n\t" + "STM r0!, {r6, r7}\n\t" + "ADC r0, r10, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -46996,83 +50315,104 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_384_mont_sub_12(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register const sp_digit* m __asm__ ("r3") = (const sp_digit*)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "MOV %[m], #0\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "MOV r3, #0\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "SUBS r8, r8, r4\n\t" "SBCS r9, r9, r5\n\t" "SBCS r10, r10, r6\n\t" "SBCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "SBCS r8, r8, r4\n\t" "SBCS r9, r9, r5\n\t" "SBCS r10, r10, r6\n\t" "SBCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "SBCS r8, r8, r4\n\t" "SBCS r9, r9, r5\n\t" "SBCS r10, r10, r6\n\t" "SBCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "SBC %[m], %[m], #0\n\t" - "SUB %[r], %[r], #48\n\t" - "LSR r12, %[m], #1\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" - "ADDS r8, r8, %[m]\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "SBC r3, r3, #0\n\t" + "SUB r0, r0, #48\n\t" + "LSR r12, r3, #1\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" + "ADDS r8, r8, r3\n\t" "ADCS r9, r9, #0\n\t" "ADCS r10, r10, #0\n\t" - "ADCS r11, r11, %[m]\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "ADCS r11, r11, r3\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADCS r8, r8, r12, LSL #1\n\t" - "ADCS r9, r9, %[m]\n\t" - "ADCS r10, r10, %[m]\n\t" - "ADCS r11, r11, %[m]\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" - "ADCS r8, r8, %[m]\n\t" - "ADCS r9, r9, %[m]\n\t" - "ADCS r10, r10, %[m]\n\t" - "ADCS r11, r11, %[m]\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "ADC %[m], %[m], #0\n\t" - "SUB %[r], %[r], #48\n\t" - "LSR r12, %[m], #1\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" - "ADDS r8, r8, %[m]\n\t" + "ADCS r9, r9, r3\n\t" + "ADCS r10, r10, r3\n\t" + "ADCS r11, r11, r3\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" + "ADCS r8, r8, r3\n\t" + "ADCS r9, r9, r3\n\t" + "ADCS r10, r10, r3\n\t" + "ADCS r11, r11, r3\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "ADC r3, r3, #0\n\t" + "SUB r0, r0, #48\n\t" + "LSR r12, r3, #1\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" + "ADDS r8, r8, r3\n\t" "ADCS r9, r9, #0\n\t" "ADCS r10, r10, #0\n\t" - "ADCS r11, r11, %[m]\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "ADCS r11, r11, r3\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADCS r8, r8, r12, LSL #1\n\t" - "ADCS r9, r9, %[m]\n\t" - "ADCS r10, r10, %[m]\n\t" - "ADCS r11, r11, %[m]\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" - "ADCS r8, r8, %[m]\n\t" - "ADCS r9, r9, %[m]\n\t" - "ADCS r10, r10, %[m]\n\t" - "ADC r11, r11, %[m]\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" + "ADCS r9, r9, r3\n\t" + "ADCS r10, r10, r3\n\t" + "ADCS r11, r11, r3\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" + "ADCS r8, r8, r3\n\t" + "ADCS r9, r9, r3\n\t" + "ADCS r10, r10, r3\n\t" + "ADC r11, r11, r3\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (const sp_digit*)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifdef WOLFSSL_SP_SMALL @@ -47095,64 +50435,82 @@ WC_OMIT_FRAME_POINTER static void sp_384_rshift1_12(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1, {r2, r3}\n\t" "LSR r2, r2, #1\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #8]\n\t" - "STR r2, [%[r]]\n\t" + "LDR r4, [r1, #8]\n\t" + "STR r2, [r0]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #12]\n\t" - "STR r3, [%[r], #4]\n\t" + "LDR r2, [r1, #12]\n\t" + "STR r3, [r0, #4]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #16]\n\t" - "STR r4, [%[r], #8]\n\t" + "LDR r3, [r1, #16]\n\t" + "STR r4, [r0, #8]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #20]\n\t" - "STR r2, [%[r], #12]\n\t" + "LDR r4, [r1, #20]\n\t" + "STR r2, [r0, #12]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #24]\n\t" - "STR r3, [%[r], #16]\n\t" + "LDR r2, [r1, #24]\n\t" + "STR r3, [r0, #16]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #28]\n\t" - "STR r4, [%[r], #20]\n\t" + "LDR r3, [r1, #28]\n\t" + "STR r4, [r0, #20]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #32]\n\t" - "STR r2, [%[r], #24]\n\t" + "LDR r4, [r1, #32]\n\t" + "STR r2, [r0, #24]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #36]\n\t" - "STR r3, [%[r], #28]\n\t" + "LDR r2, [r1, #36]\n\t" + "STR r3, [r0, #28]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #40]\n\t" - "STR r4, [%[r], #32]\n\t" + "LDR r3, [r1, #40]\n\t" + "STR r4, [r0, #32]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #44]\n\t" - "STR r2, [%[r], #36]\n\t" + "LDR r4, [r1, #44]\n\t" + "STR r2, [r0, #36]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "STR r3, [%[r], #40]\n\t" - "STR r4, [%[r], #44]\n\t" + "STR r3, [r0, #40]\n\t" + "STR r4, [r0, #44]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Divide the number by 2 mod the modulus (prime). (r = a / 2 % m) @@ -50620,36 +53978,53 @@ WC_OMIT_FRAME_POINTER static void sp_384_add_one_12(sp_digit* a) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; +#else + void* L_asm_args[1] = {(void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r1, r2, r3, r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r1, r2, r3, r4}\n\t" "ADDS r1, r1, #1\n\t" "ADCS r2, r2, #0\n\t" "ADCS r3, r3, #0\n\t" "ADCS r4, r4, #0\n\t" - "STM %[a]!, {r1, r2, r3, r4}\n\t" - "LDM %[a], {r1, r2, r3, r4}\n\t" + "STM r0!, {r1, r2, r3, r4}\n\t" + "LDM r0, {r1, r2, r3, r4}\n\t" "ADCS r1, r1, #0\n\t" "ADCS r2, r2, #0\n\t" "ADCS r3, r3, #0\n\t" "ADCS r4, r4, #0\n\t" - "STM %[a]!, {r1, r2, r3, r4}\n\t" - "LDM %[a], {r1, r2, r3, r4}\n\t" + "STM r0!, {r1, r2, r3, r4}\n\t" + "LDM r0, {r1, r2, r3, r4}\n\t" "ADCS r1, r1, #0\n\t" "ADCS r2, r2, #0\n\t" "ADCS r3, r3, #0\n\t" "ADCS r4, r4, #0\n\t" - "STM %[a]!, {r1, r2, r3, r4}\n\t" + "STM r0!, {r1, r2, r3, r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a) : + : "memory", "cc", "r1", "r2", "r3", "r4" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif @@ -51055,11 +54430,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_sub_in_place_12(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "ADD r11, %[a], #48\n\t" + "ADD r11, r0, #48\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_384_sub_in_place_12_word:\n\t" @@ -51067,15 +54450,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_sub_in_place_12(sp_digit* a, "L_sp_384_sub_in_place_12_word_%=:\n\t" #endif "RSBS r10, r10, #0\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" "SBC r10, r10, r10\n\t" - "CMP %[a], r11\n\t" + "CMP r0, r11\n\t" #if defined(__GNUC__) "BNE L_sp_384_sub_in_place_12_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -51083,17 +54466,27 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_sub_in_place_12(sp_digit* a, #else "BNE.N L_sp_384_sub_in_place_12_word_%=\n\t" #endif - "MOV %[a], r10\n\t" + "MOV r0, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -51114,40 +54507,58 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_384_sub_in_place_12(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SUBS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "SBC %[a], r9, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "SBC r0, r9, r9\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -51171,14 +54582,22 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_d_12(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDR r8, [%[a]]\n\t" - "UMULL r5, r3, %[b], r8\n\t" + "LDR r8, [r1]\n\t" + "UMULL r5, r3, r2, r8\n\t" "MOV r4, #0\n\t" - "STR r5, [%[r]]\n\t" + "STR r5, [r0]\n\t" "MOV r5, #0\n\t" "MOV r9, #4\n\t" "\n" @@ -51188,12 +54607,12 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_d_12(sp_digit* r, "L_sp_384_mul_d_12_word_%=:\n\t" #endif /* A[i] * B */ - "LDR r8, [%[a], r9]\n\t" - "UMULL r6, r7, %[b], r8\n\t" + "LDR r8, [r1, r9]\n\t" + "UMULL r6, r7, r2, r8\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], r9]\n\t" + "STR r3, [r0, r9]\n\t" "MOV r3, r4\n\t" "MOV r4, r5\n\t" "MOV r5, #0\n\t" @@ -51206,16 +54625,27 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_d_12(sp_digit* r, #else "BLT.N L_sp_384_mul_d_12_word_%=\n\t" #endif - "STR r3, [%[r], #48]\n\t" + "STR r3, [r0, #48]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -51237,78 +54667,97 @@ WC_OMIT_FRAME_POINTER static void sp_384_mul_d_12(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDM %[a]!, {r8}\n\t" - "UMULL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMULL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[1] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[2] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[3] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[4] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[5] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[6] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[7] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[8] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[9] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[10] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[11] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" - "STR r3, [%[r]]\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" + "STR r3, [r0]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -51335,53 +54784,73 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_384_word_12(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r8, %[div], #16\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r8, r2, #16\n\t" "ADD r5, r8, #1\n\t" - "UDIV r6, %[d1], r5\n\t" - "LSL r7, %[div], #16\n\t" + "UDIV r6, r0, r5\n\t" + "LSL r7, r2, #16\n\t" "LSL r6, r6, #16\n\t" - "UMULL r3, r4, %[div], r6\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "SUBS r3, %[d1], r5\n\t" + "UMULL r3, r4, r2, r6\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "SUBS r3, r0, r5\n\t" "SBC r9, r9, r9\n\t" "ADD r9, r9, #1\n\t" "RSB r10, r9, #0\n\t" "LSL r9, r9, #16\n\t" "AND r7, r7, r10\n\t" "AND r8, r8, r10\n\t" - "SUBS %[d0], %[d0], r7\n\t" + "SUBS r1, r1, r7\n\t" "ADD r6, r6, r9\n\t" - "SBC %[d1], %[d1], r8\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "SBC r0, r0, r8\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "UMULL r3, r4, %[div], r3\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "UMULL r3, r4, r2, r3\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "MUL r3, %[div], r3\n\t" - "SUB %[d0], %[d0], r3\n\t" - "UDIV r3, %[d0], %[div]\n\t" - "ADD %[d1], r6, r3\n\t" + "MUL r3, r2, r3\n\t" + "SUB r1, r1, r3\n\t" + "UDIV r3, r1, r2\n\t" + "ADD r0, r6, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -51408,13 +54877,22 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_384_word_12(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r5, %[div], #1\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r5, r2, #1\n\t" "ADD r5, r5, #1\n\t" - "MOV r6, %[d0]\n\t" - "MOV r7, %[d1]\n\t" + "MOV r6, r1\n\t" + "MOV r7, r0\n\t" /* Do top 32 */ "SUBS r8, r5, r7\n\t" "SBC r8, r8, r8\n\t" @@ -51448,29 +54926,40 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_384_word_12(sp_digit d1, #endif "ADD r3, r3, r3\n\t" "ADD r3, r3, #1\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "SUBS r8, r9, %[div]\n\t" - "ADC %[d1], r3, #0\n\t" + "SUBS r8, r9, r2\n\t" + "ADC r0, r3, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -52119,10 +55608,18 @@ WC_OMIT_FRAME_POINTER static void sp_384_div2_mod_12(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* m __asm__ ("r2") = (const sp_digit*)m_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r4}\n\t" "ANDS r3, r4, #1\n\t" #if defined(__GNUC__) "BEQ L_sp_384_div2_mod_12_even_%=\n\t" @@ -52132,27 +55629,27 @@ WC_OMIT_FRAME_POINTER static void sp_384_div2_mod_12(sp_digit* r, "BEQ.N L_sp_384_div2_mod_12_even_%=\n\t" #endif "MOV r12, #0\n\t" - "LDM %[a]!, {r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADDS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "ADC r3, r12, r12\n\t" #if defined(__GNUC__) "B L_sp_384_div2_mod_12_div2_%=\n\t" @@ -52167,76 +55664,87 @@ WC_OMIT_FRAME_POINTER static void sp_384_div2_mod_12(sp_digit* r, #else "L_sp_384_div2_mod_12_even_%=:\n\t" #endif - "LDM %[a]!, {r5, r6, r7}\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_384_div2_mod_12_div2:\n\t" #else "L_sp_384_div2_mod_12_div2_%=:\n\t" #endif - "SUB %[r], %[r], #48\n\t" - "LDRD r8, r9, [%[r]]\n\t" + "SUB r0, r0, #48\n\t" + "LDRD r8, r9, [r0]\n\t" "LSR r8, r8, #1\n\t" "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" - "LDR r10, [%[r], #8]\n\t" - "STR r8, [%[r]]\n\t" + "LDR r10, [r0, #8]\n\t" + "STR r8, [r0]\n\t" "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" - "LDR r8, [%[r], #12]\n\t" - "STR r9, [%[r], #4]\n\t" + "LDR r8, [r0, #12]\n\t" + "STR r9, [r0, #4]\n\t" "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" - "LDR r9, [%[r], #16]\n\t" - "STR r10, [%[r], #8]\n\t" + "LDR r9, [r0, #16]\n\t" + "STR r10, [r0, #8]\n\t" "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" - "LDR r10, [%[r], #20]\n\t" - "STR r8, [%[r], #12]\n\t" + "LDR r10, [r0, #20]\n\t" + "STR r8, [r0, #12]\n\t" "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" - "LDR r8, [%[r], #24]\n\t" - "STR r9, [%[r], #16]\n\t" + "LDR r8, [r0, #24]\n\t" + "STR r9, [r0, #16]\n\t" "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" - "LDR r9, [%[r], #28]\n\t" - "STR r10, [%[r], #20]\n\t" + "LDR r9, [r0, #28]\n\t" + "STR r10, [r0, #20]\n\t" "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" - "LDR r10, [%[r], #32]\n\t" - "STR r8, [%[r], #24]\n\t" + "LDR r10, [r0, #32]\n\t" + "STR r8, [r0, #24]\n\t" "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" - "LDR r8, [%[r], #36]\n\t" - "STR r9, [%[r], #28]\n\t" + "LDR r8, [r0, #36]\n\t" + "STR r9, [r0, #28]\n\t" "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" - "LDR r9, [%[r], #40]\n\t" - "STR r10, [%[r], #32]\n\t" + "LDR r9, [r0, #40]\n\t" + "STR r10, [r0, #32]\n\t" "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" - "LDR r10, [%[r], #44]\n\t" - "STR r8, [%[r], #36]\n\t" + "LDR r10, [r0, #44]\n\t" + "STR r8, [r0, #36]\n\t" "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" "ORR r10, r10, r3, LSL #31\n\t" - "STR r9, [%[r], #40]\n\t" - "STR r10, [%[r], #44]\n\t" + "STR r9, [r0, #40]\n\t" + "STR r10, [r0, #44]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Get the number of bits in the number. @@ -52253,10 +55761,18 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; +#else + void* L_asm_args[1] = {(void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r1, [%[a], #44]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r1, [r0, #44]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_384_num_bits_12_11_%=\n\t" @@ -52281,7 +55797,7 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_11_%=:\n\t" #endif - "LDR r1, [%[a], #40]\n\t" + "LDR r1, [r0, #40]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_384_num_bits_12_10_%=\n\t" @@ -52306,7 +55822,7 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_10_%=:\n\t" #endif - "LDR r1, [%[a], #36]\n\t" + "LDR r1, [r0, #36]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_384_num_bits_12_9_%=\n\t" @@ -52331,7 +55847,7 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_9_%=:\n\t" #endif - "LDR r1, [%[a], #32]\n\t" + "LDR r1, [r0, #32]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_384_num_bits_12_8_%=\n\t" @@ -52356,7 +55872,7 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_8_%=:\n\t" #endif - "LDR r1, [%[a], #28]\n\t" + "LDR r1, [r0, #28]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_384_num_bits_12_7_%=\n\t" @@ -52381,7 +55897,7 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_7_%=:\n\t" #endif - "LDR r1, [%[a], #24]\n\t" + "LDR r1, [r0, #24]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_384_num_bits_12_6_%=\n\t" @@ -52406,7 +55922,7 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_6_%=:\n\t" #endif - "LDR r1, [%[a], #20]\n\t" + "LDR r1, [r0, #20]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_384_num_bits_12_5_%=\n\t" @@ -52431,7 +55947,7 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_5_%=:\n\t" #endif - "LDR r1, [%[a], #16]\n\t" + "LDR r1, [r0, #16]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_384_num_bits_12_4_%=\n\t" @@ -52456,7 +55972,7 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_4_%=:\n\t" #endif - "LDR r1, [%[a], #12]\n\t" + "LDR r1, [r0, #12]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_384_num_bits_12_3_%=\n\t" @@ -52481,7 +55997,7 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_3_%=:\n\t" #endif - "LDR r1, [%[a], #8]\n\t" + "LDR r1, [r0, #8]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_384_num_bits_12_2_%=\n\t" @@ -52506,7 +56022,7 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_2_%=:\n\t" #endif - "LDR r1, [%[a], #4]\n\t" + "LDR r1, [r0, #4]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_384_num_bits_12_1_%=\n\t" @@ -52531,7 +56047,7 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_1_%=:\n\t" #endif - "LDR r1, [%[a]]\n\t" + "LDR r1, [r0]\n\t" "MOV r2, #32\n\t" "CLZ r4, r1\n\t" "SUB r4, r2, r4\n\t" @@ -52541,16 +56057,25 @@ WC_OMIT_FRAME_POINTER static int sp_384_num_bits_12(const sp_digit* a) #else "L_sp_384_num_bits_12_13_%=:\n\t" #endif - "MOV %[a], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a) : + : "memory", "cc", "r1", "r2", "r3", "r4", "r5" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4", "r5" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -53597,12 +57122,20 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_17(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x88\n\t" - "LDR lr, [%[a]]\n\t" - "LDR r11, [%[b]]\n\t" + "LDR lr, [r1]\n\t" + "LDR r11, [r2]\n\t" "UMULL r8, r6, lr, r11\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -53624,14 +57157,14 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_17(sp_digit* r, const sp_digit* a, #else "L_sp_521_mul_17_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" "ADC r8, r8, #0\n\t" - "LDR lr, [%[a], r4]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r4]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -53653,8 +57186,8 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_17(sp_digit* r, const sp_digit* a, #else "BLT.N L_sp_521_mul_17_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -53678,14 +57211,14 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_17(sp_digit* r, const sp_digit* a, #else "BLE.N L_sp_521_mul_17_outer_%=\n\t" #endif - "LDR lr, [%[a], #64]\n\t" - "LDR r11, [%[b], #64]\n\t" + "LDR lr, [r1, #64]\n\t" + "LDR r11, [r2, #64]\n\t" "UMLAL r6, r7, lr, r11\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" "STR r7, [sp, r5]\n\t" "LDM sp!, {r6, r7}\n\t" - "STM %[r]!, {r6, r7}\n\t" + "STM r0!, {r6, r7}\n\t" "SUB r5, r5, #8\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -53694,7 +57227,7 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_17(sp_digit* r, const sp_digit* a, "L_sp_521_mul_17_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_521_mul_17_store_%=\n\t" @@ -53703,16 +57236,27 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_17(sp_digit* r, const sp_digit* a, #else "BGT.N L_sp_521_mul_17_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -53734,1977 +57278,1985 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_17(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x44\n\t" /* A[0] * B[0] */ - "LDR r11, [%[a]]\n\t" - "LDR r12, [%[b]]\n\t" + "LDR r11, [r1]\n\t" + "LDR r12, [r2]\n\t" "UMULL r3, r4, r11, r12\n\t" "MOV r5, #0\n\t" "STR r3, [sp]\n\t" /* A[0] * B[1] */ - "LDR r9, [%[b], #4]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[0] */ - "LDR r8, [%[a], #4]\n\t" + "LDR r8, [r1, #4]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #4]\n\t" /* A[2] * B[0] */ - "LDR r8, [%[a], #8]\n\t" + "LDR r8, [r1, #8]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[1] */ - "LDR r11, [%[a], #4]\n\t" - "LDR r12, [%[b], #4]\n\t" + "LDR r11, [r1, #4]\n\t" + "LDR r12, [r2, #4]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[0] * B[2] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #8]\n\t" /* A[0] * B[3] */ - "LDR r9, [%[b], #12]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[2] */ - "LDR r9, [%[b], #8]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[1] */ - "LDR r8, [%[a], #8]\n\t" + "LDR r8, [r1, #8]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[0] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #12]\n\t" /* A[4] * B[0] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[1] */ - "LDR r8, [%[a], #12]\n\t" + "LDR r8, [r1, #12]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[2] */ - "LDR r11, [%[a], #8]\n\t" - "LDR r12, [%[b], #8]\n\t" + "LDR r11, [r1, #8]\n\t" + "LDR r12, [r2, #8]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[3] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[0] * B[4] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #16]\n\t" /* A[0] * B[5] */ - "LDR r9, [%[b], #20]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[4] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[3] */ - "LDR r9, [%[b], #12]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[2] */ - "LDR r8, [%[a], #12]\n\t" + "LDR r8, [r1, #12]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[1] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[0] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #20]\n\t" /* A[6] * B[0] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[1] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[2] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[3] */ - "LDR r11, [%[a], #12]\n\t" - "LDR r12, [%[b], #12]\n\t" + "LDR r11, [r1, #12]\n\t" + "LDR r12, [r2, #12]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[4] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[5] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[0] * B[6] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #24]\n\t" /* A[0] * B[7] */ - "LDR r9, [%[b], #28]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[6] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[5] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[4] */ - "LDR r9, [%[b], #16]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[3] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[2] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[1] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[0] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #28]\n\t" /* A[8] * B[0] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[1] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[2] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[3] */ - "LDR r8, [%[a], #20]\n\t" + "LDR r8, [r1, #20]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[4] */ - "LDR r11, [%[a], #16]\n\t" - "LDR r12, [%[b], #16]\n\t" + "LDR r11, [r1, #16]\n\t" + "LDR r12, [r2, #16]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[5] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[6] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[7] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[0] * B[8] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #32]\n\t" /* A[0] * B[9] */ - "LDR r9, [%[b], #36]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[8] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[7] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[6] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[5] */ - "LDR r9, [%[b], #20]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[4] */ - "LDR r8, [%[a], #20]\n\t" + "LDR r8, [r1, #20]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[3] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[2] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[1] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[0] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #36]\n\t" /* A[10] * B[0] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[1] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[2] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[3] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[4] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[5] */ - "LDR r11, [%[a], #20]\n\t" - "LDR r12, [%[b], #20]\n\t" + "LDR r11, [r1, #20]\n\t" + "LDR r12, [r2, #20]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[6] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[7] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[8] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[9] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[0] * B[10] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #40]\n\t" /* A[0] * B[11] */ - "LDR r9, [%[b], #44]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[10] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[9] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[8] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[7] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[6] */ - "LDR r9, [%[b], #24]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[5] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[4] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[3] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[2] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[1] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[0] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #44]\n\t" /* A[12] * B[0] */ - "LDR r8, [%[a], #48]\n\t" + "LDR r8, [r1, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[1] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[2] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[3] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[4] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[5] */ - "LDR r8, [%[a], #28]\n\t" + "LDR r8, [r1, #28]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[6] */ - "LDR r11, [%[a], #24]\n\t" - "LDR r12, [%[b], #24]\n\t" + "LDR r11, [r1, #24]\n\t" + "LDR r12, [r2, #24]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[7] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[8] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[9] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[10] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[11] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[0] * B[12] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #48]\n\t" /* A[0] * B[13] */ - "LDR r9, [%[b], #52]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[12] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[11] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[10] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[9] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[8] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[7] */ - "LDR r9, [%[b], #28]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[6] */ - "LDR r8, [%[a], #28]\n\t" + "LDR r8, [r1, #28]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[5] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[4] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[3] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[2] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[12] * B[1] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[0] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #52]\n\t" /* A[14] * B[0] */ - "LDR r8, [%[a], #56]\n\t" + "LDR r8, [r1, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[13] * B[1] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[12] * B[2] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[3] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[4] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[5] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[6] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[7] */ - "LDR r11, [%[a], #28]\n\t" - "LDR r12, [%[b], #28]\n\t" + "LDR r11, [r1, #28]\n\t" + "LDR r12, [r2, #28]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[8] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[9] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[10] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[11] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[12] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[13] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[0] * B[14] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #56]\n\t" /* A[0] * B[15] */ - "LDR r9, [%[b], #60]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[14] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[13] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[12] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[11] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[10] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[9] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[8] */ - "LDR r9, [%[b], #32]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[7] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[6] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[5] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[4] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[12] * B[3] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[13] * B[2] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[14] * B[1] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[15] * B[0] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #60]\n\t" /* A[16] * B[0] */ - "LDR r8, [%[a], #64]\n\t" + "LDR r8, [r1, #64]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[15] * B[1] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[14] * B[2] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[3] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[12] * B[4] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[5] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[6] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[7] */ - "LDR r8, [%[a], #36]\n\t" + "LDR r8, [r1, #36]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[8] */ - "LDR r11, [%[a], #32]\n\t" - "LDR r12, [%[b], #32]\n\t" + "LDR r11, [r1, #32]\n\t" + "LDR r12, [r2, #32]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[9] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[10] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[11] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[12] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[13] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[14] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[15] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[0] * B[16] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #64]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #64]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #64]\n\t" /* A[1] * B[16] */ - "LDR r8, [%[a], #4]\n\t" + "LDR r8, [r1, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[15] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[14] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[13] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[12] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[11] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[10] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[9] */ - "LDR r9, [%[b], #36]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[8] */ - "LDR r8, [%[a], #36]\n\t" + "LDR r8, [r1, #36]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[7] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[6] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[12] * B[5] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[13] * B[4] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[14] * B[3] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[15] * B[2] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[16] * B[1] */ - "LDR r8, [%[a], #64]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #64]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #68]\n\t" + "STR r5, [r0, #68]\n\t" /* A[16] * B[2] */ - "LDR r9, [%[b], #8]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[15] * B[3] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[14] * B[4] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[13] * B[5] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[12] * B[6] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[7] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[8] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[9] */ - "LDR r11, [%[a], #36]\n\t" - "LDR r12, [%[b], #36]\n\t" + "LDR r11, [r1, #36]\n\t" + "LDR r12, [r2, #36]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[10] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[11] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[12] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[13] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[14] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[15] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[16] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #64]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #64]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #72]\n\t" + "STR r3, [r0, #72]\n\t" /* A[3] * B[16] */ - "LDR r8, [%[a], #12]\n\t" + "LDR r8, [r1, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[15] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[14] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[13] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[12] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[11] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[10] */ - "LDR r9, [%[b], #40]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[9] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[8] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[12] * B[7] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[6] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[14] * B[5] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[15] * B[4] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[16] * B[3] */ - "LDR r8, [%[a], #64]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #64]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #76]\n\t" + "STR r4, [r0, #76]\n\t" /* A[16] * B[4] */ - "LDR r9, [%[b], #16]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[15] * B[5] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[14] * B[6] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[13] * B[7] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[12] * B[8] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[9] */ - "LDR r8, [%[a], #44]\n\t" + "LDR r8, [r1, #44]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[10] */ - "LDR r11, [%[a], #40]\n\t" - "LDR r12, [%[b], #40]\n\t" + "LDR r11, [r1, #40]\n\t" + "LDR r12, [r2, #40]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[11] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[12] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[13] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[14] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[15] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[16] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #64]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #64]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #80]\n\t" + "STR r5, [r0, #80]\n\t" /* A[5] * B[16] */ - "LDR r8, [%[a], #20]\n\t" + "LDR r8, [r1, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[15] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[14] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[13] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[12] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[11] */ - "LDR r9, [%[b], #44]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[10] */ - "LDR r8, [%[a], #44]\n\t" + "LDR r8, [r1, #44]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[12] * B[9] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[13] * B[8] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[14] * B[7] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[15] * B[6] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[16] * B[5] */ - "LDR r8, [%[a], #64]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #64]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #84]\n\t" + "STR r3, [r0, #84]\n\t" /* A[16] * B[6] */ - "LDR r9, [%[b], #24]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[15] * B[7] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[14] * B[8] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[9] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[12] * B[10] */ - "LDR r8, [%[a], #48]\n\t" + "LDR r8, [r1, #48]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[11] */ - "LDR r11, [%[a], #44]\n\t" - "LDR r12, [%[b], #44]\n\t" + "LDR r11, [r1, #44]\n\t" + "LDR r12, [r2, #44]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[12] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[13] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[14] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[15] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[16] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #64]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #64]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #88]\n\t" + "STR r4, [r0, #88]\n\t" /* A[7] * B[16] */ - "LDR r8, [%[a], #28]\n\t" + "LDR r8, [r1, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[15] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[14] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[13] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[12] */ - "LDR r9, [%[b], #48]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[12] * B[11] */ - "LDR r8, [%[a], #48]\n\t" + "LDR r8, [r1, #48]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[13] * B[10] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[14] * B[9] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[15] * B[8] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[16] * B[7] */ - "LDR r8, [%[a], #64]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #64]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #92]\n\t" + "STR r5, [r0, #92]\n\t" /* A[16] * B[8] */ - "LDR r9, [%[b], #32]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[15] * B[9] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[14] * B[10] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[13] * B[11] */ - "LDR r8, [%[a], #52]\n\t" + "LDR r8, [r1, #52]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[12] * B[12] */ - "LDR r11, [%[a], #48]\n\t" - "LDR r12, [%[b], #48]\n\t" + "LDR r11, [r1, #48]\n\t" + "LDR r12, [r2, #48]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[13] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[14] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[15] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[16] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #64]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #64]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #96]\n\t" + "STR r3, [r0, #96]\n\t" /* A[9] * B[16] */ - "LDR r8, [%[a], #36]\n\t" + "LDR r8, [r1, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[15] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[14] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[12] * B[13] */ - "LDR r9, [%[b], #52]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[12] */ - "LDR r8, [%[a], #52]\n\t" + "LDR r8, [r1, #52]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[14] * B[11] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[15] * B[10] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[16] * B[9] */ - "LDR r8, [%[a], #64]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #64]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #100]\n\t" + "STR r4, [r0, #100]\n\t" /* A[16] * B[10] */ - "LDR r9, [%[b], #40]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[15] * B[11] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[14] * B[12] */ - "LDR r8, [%[a], #56]\n\t" + "LDR r8, [r1, #56]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[13] * B[13] */ - "LDR r11, [%[a], #52]\n\t" - "LDR r12, [%[b], #52]\n\t" + "LDR r11, [r1, #52]\n\t" + "LDR r12, [r2, #52]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[12] * B[14] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[15] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[16] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #64]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #64]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #104]\n\t" + "STR r5, [r0, #104]\n\t" /* A[11] * B[16] */ - "LDR r8, [%[a], #44]\n\t" + "LDR r8, [r1, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[12] * B[15] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[13] * B[14] */ - "LDR r9, [%[b], #56]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[14] * B[13] */ - "LDR r8, [%[a], #56]\n\t" + "LDR r8, [r1, #56]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[15] * B[12] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[16] * B[11] */ - "LDR r8, [%[a], #64]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #64]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #108]\n\t" + "STR r3, [r0, #108]\n\t" /* A[16] * B[12] */ - "LDR r9, [%[b], #48]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[15] * B[13] */ - "LDR r8, [%[a], #60]\n\t" + "LDR r8, [r1, #60]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[14] * B[14] */ - "LDR r11, [%[a], #56]\n\t" - "LDR r12, [%[b], #56]\n\t" + "LDR r11, [r1, #56]\n\t" + "LDR r12, [r2, #56]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[15] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[12] * B[16] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #64]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #64]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #112]\n\t" + "STR r4, [r0, #112]\n\t" /* A[13] * B[16] */ - "LDR r8, [%[a], #52]\n\t" + "LDR r8, [r1, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[14] * B[15] */ - "LDR r9, [%[b], #60]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[15] * B[14] */ - "LDR r8, [%[a], #60]\n\t" + "LDR r8, [r1, #60]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[16] * B[13] */ - "LDR r8, [%[a], #64]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #64]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #116]\n\t" + "STR r5, [r0, #116]\n\t" /* A[16] * B[14] */ "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" @@ -55712,20 +59264,20 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_17(sp_digit* r, const sp_digit* a, "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[15] * B[15] */ - "LDR r11, [%[a], #60]\n\t" - "LDR r12, [%[b], #60]\n\t" + "LDR r11, [r1, #60]\n\t" + "LDR r12, [r2, #60]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[14] * B[16] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #64]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #64]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #120]\n\t" + "STR r3, [r0, #120]\n\t" /* A[15] * B[16] */ "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" @@ -55733,36 +59285,47 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_17(sp_digit* r, const sp_digit* a, "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[16] * B[15] */ - "LDR r8, [%[a], #64]\n\t" + "LDR r8, [r1, #64]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #124]\n\t" + "STR r4, [r0, #124]\n\t" /* A[16] * B[16] */ "UMLAL r5, r3, r8, r9\n\t" - "STR r5, [%[r], #128]\n\t" - "STR r3, [%[r], #132]\n\t" + "STR r5, [r0, #128]\n\t" + "STR r3, [r0, #132]\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "LDM sp!, {r3}\n\t" - "STM %[r]!, {r3}\n\t" + "STM r0!, {r3}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r11", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r11", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -55782,11 +59345,19 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x88\n\t" - "LDR lr, [%[a]]\n\t" + "LDR lr, [r1]\n\t" "UMULL r8, r6, lr, lr\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -55808,8 +59379,8 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) #else "L_sp_521_sqr_17_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[a], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r1, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -55834,7 +59405,7 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) #else "BLT.N L_sp_521_sqr_17_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" + "LDR lr, [r1, r3]\n\t" "UMULL r9, r10, lr, lr\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -55858,13 +59429,13 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) #else "BLE.N L_sp_521_sqr_17_outer_%=\n\t" #endif - "LDR lr, [%[a], #64]\n\t" + "LDR lr, [r1, #64]\n\t" "UMLAL r6, r7, lr, lr\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" "STR r7, [sp, r5]\n\t" "LDM sp!, {r6, r7}\n\t" - "STM %[r]!, {r6, r7}\n\t" + "STM r0!, {r6, r7}\n\t" "SUB r5, r5, #8\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -55873,7 +59444,7 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "L_sp_521_sqr_17_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_521_sqr_17_store_%=\n\t" @@ -55882,16 +59453,26 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) #else "BGT.N L_sp_521_sqr_17_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -55910,18 +59491,26 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x44\n\t" /* A[0] * A[0] */ - "LDR r10, [%[a]]\n\t" + "LDR r10, [r1]\n\t" "UMULL r8, r3, r10, r10\n\t" "MOV r4, #0\n\t" "STR r8, [sp]\n\t" /* A[0] * A[1] */ - "LDR r10, [%[a], #4]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #4]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -55933,8 +59522,8 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r2, r2, #0\n\t" "STR r3, [sp, #4]\n\t" /* A[0] * A[2] */ - "LDR r10, [%[a], #8]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #8]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" @@ -55945,15 +59534,15 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * A[1] */ - "LDR r10, [%[a], #4]\n\t" + "LDR r10, [r1, #4]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #8]\n\t" /* A[0] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -55964,8 +59553,8 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * A[2] */ - "LDR r10, [%[a], #8]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #8]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -55975,8 +59564,8 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r4, r4, #0\n\t" "STR r2, [sp, #12]\n\t" /* A[0] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -55987,8 +59576,8 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "MOV r2, #0\n\t" "ADC r2, r2, #0\n\t" /* A[1] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -55997,28 +59586,28 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" /* A[2] * A[2] */ - "LDR r10, [%[a], #8]\n\t" + "LDR r10, [r1, #8]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" "STR r3, [sp, #16]\n\t" /* A[0] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -56031,27 +59620,27 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #20]\n\t" /* A[0] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[3] */ - "LDR r10, [%[a], #12]\n\t" + "LDR r10, [r1, #12]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -56064,28 +59653,28 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #24]\n\t" /* A[0] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -56098,34 +59687,34 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r2, r2, r7\n\t" "STR r3, [sp, #28]\n\t" /* A[0] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[4] */ - "LDR r10, [%[a], #16]\n\t" + "LDR r10, [r1, #16]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -56138,35 +59727,35 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #32]\n\t" /* A[0] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -56179,41 +59768,41 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #36]\n\t" /* A[0] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[5] */ - "LDR r10, [%[a], #20]\n\t" + "LDR r10, [r1, #20]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -56226,42 +59815,42 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r2, r2, r7\n\t" "STR r3, [sp, #40]\n\t" /* A[0] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -56274,48 +59863,48 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #44]\n\t" /* A[0] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[6] */ - "LDR r10, [%[a], #24]\n\t" + "LDR r10, [r1, #24]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -56328,49 +59917,49 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #48]\n\t" /* A[0] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -56383,55 +59972,55 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r2, r2, r7\n\t" "STR r3, [sp, #52]\n\t" /* A[0] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[7] */ - "LDR r10, [%[a], #28]\n\t" + "LDR r10, [r1, #28]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -56444,56 +60033,56 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #56]\n\t" /* A[0] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -56506,62 +60095,62 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #60]\n\t" /* A[0] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[8] */ - "LDR r10, [%[a], #32]\n\t" + "LDR r10, [r1, #32]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -56574,56 +60163,56 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADC r2, r2, r7\n\t" "STR r3, [sp, #64]\n\t" /* A[1] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[2] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -56634,57 +60223,57 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r5\n\t" "ADCS r2, r2, r6\n\t" "ADC r3, r3, r7\n\t" - "STR r4, [%[r], #68]\n\t" + "STR r4, [r0, #68]\n\t" /* A[2] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[3] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[9] * A[9] */ - "LDR r10, [%[a], #36]\n\t" + "LDR r10, [r1, #36]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -56695,51 +60284,51 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r5\n\t" "ADCS r3, r3, r6\n\t" "ADC r4, r4, r7\n\t" - "STR r2, [%[r], #72]\n\t" + "STR r2, [r0, #72]\n\t" /* A[3] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[4] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[9] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -56750,50 +60339,50 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r5\n\t" "ADCS r4, r4, r6\n\t" "ADC r2, r2, r7\n\t" - "STR r3, [%[r], #76]\n\t" + "STR r3, [r0, #76]\n\t" /* A[4] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[5] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[9] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[10] * A[10] */ - "LDR r10, [%[a], #40]\n\t" + "LDR r10, [r1, #40]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -56804,44 +60393,44 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r5\n\t" "ADCS r2, r2, r6\n\t" "ADC r3, r3, r7\n\t" - "STR r4, [%[r], #80]\n\t" + "STR r4, [r0, #80]\n\t" /* A[5] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[6] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[9] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[10] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -56852,43 +60441,43 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r5\n\t" "ADCS r3, r3, r6\n\t" "ADC r4, r4, r7\n\t" - "STR r2, [%[r], #84]\n\t" + "STR r2, [r0, #84]\n\t" /* A[6] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[7] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[9] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[10] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[11] * A[11] */ - "LDR r10, [%[a], #44]\n\t" + "LDR r10, [r1, #44]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -56899,37 +60488,37 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r5\n\t" "ADCS r4, r4, r6\n\t" "ADC r2, r2, r7\n\t" - "STR r3, [%[r], #88]\n\t" + "STR r3, [r0, #88]\n\t" /* A[7] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[8] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[9] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[10] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[11] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #44]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -56940,36 +60529,36 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r5\n\t" "ADCS r2, r2, r6\n\t" "ADC r3, r3, r7\n\t" - "STR r4, [%[r], #92]\n\t" + "STR r4, [r0, #92]\n\t" /* A[8] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[9] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[10] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[11] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #44]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[12] * A[12] */ - "LDR r10, [%[a], #48]\n\t" + "LDR r10, [r1, #48]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -56980,30 +60569,30 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r5\n\t" "ADCS r3, r3, r6\n\t" "ADC r4, r4, r7\n\t" - "STR r2, [%[r], #96]\n\t" + "STR r2, [r0, #96]\n\t" /* A[9] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[10] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[11] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #44]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[12] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #48]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -57014,29 +60603,29 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r5\n\t" "ADCS r4, r4, r6\n\t" "ADC r2, r2, r7\n\t" - "STR r3, [%[r], #100]\n\t" + "STR r3, [r0, #100]\n\t" /* A[10] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[11] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #44]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[12] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #48]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[13] * A[13] */ - "LDR r10, [%[a], #52]\n\t" + "LDR r10, [r1, #52]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -57047,23 +60636,23 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r5\n\t" "ADCS r2, r2, r6\n\t" "ADC r3, r3, r7\n\t" - "STR r4, [%[r], #104]\n\t" + "STR r4, [r0, #104]\n\t" /* A[11] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #44]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[12] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #48]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[13] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #52]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -57074,10 +60663,10 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r5\n\t" "ADCS r3, r3, r6\n\t" "ADC r4, r4, r7\n\t" - "STR r2, [%[r], #108]\n\t" + "STR r2, [r0, #108]\n\t" /* A[12] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #48]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -57088,8 +60677,8 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "MOV r2, #0\n\t" "ADC r2, r2, #0\n\t" /* A[13] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #52]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -57098,15 +60687,15 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" /* A[14] * A[14] */ - "LDR r10, [%[a], #56]\n\t" + "LDR r10, [r1, #56]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" - "STR r3, [%[r], #112]\n\t" + "STR r3, [r0, #112]\n\t" /* A[13] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #52]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" @@ -57117,8 +60706,8 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[14] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #56]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #56]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" @@ -57126,10 +60715,10 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #116]\n\t" + "STR r4, [r0, #116]\n\t" /* A[14] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #56]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #56]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -57140,15 +60729,15 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[15] * A[15] */ - "LDR r10, [%[a], #60]\n\t" + "LDR r10, [r1, #60]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" "ADC r4, r4, #0\n\t" - "STR r2, [%[r], #120]\n\t" + "STR r2, [r0, #120]\n\t" /* A[15] * A[16] */ - "LDR r10, [%[a], #64]\n\t" - "LDR r12, [%[a], #60]\n\t" + "LDR r10, [r1, #64]\n\t" + "LDR r12, [r1, #60]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -57158,32 +60747,42 @@ WC_OMIT_FRAME_POINTER static void sp_521_sqr_17(sp_digit* r, const sp_digit* a) "ADCS r4, r4, r9\n\t" "MOV r2, #0\n\t" "ADC r2, r2, #0\n\t" - "STR r3, [%[r], #124]\n\t" + "STR r3, [r0, #124]\n\t" /* A[16] * A[16] */ - "LDR r10, [%[a], #64]\n\t" + "LDR r10, [r1, #64]\n\t" "UMLAL r4, r2, r10, r10\n\t" - "STR r4, [%[r], #128]\n\t" - "STR r2, [%[r], #132]\n\t" + "STR r4, [r0, #128]\n\t" + "STR r2, [r0, #132]\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" "LDM sp!, {r2}\n\t" - "STM %[r]!, {r2}\n\t" + "STM r0!, {r2}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -57206,11 +60805,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_add_17(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r3, #0\n\t" - "ADD r12, %[a], #0x40\n\t" + "ADD r12, r1, #0x40\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_521_add_17_word:\n\t" @@ -57218,16 +60825,16 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_add_17(sp_digit* r, "L_sp_521_add_17_word_%=:\n\t" #endif "ADDS r3, r3, #0xffffffff\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "MOV r4, #0\n\t" "ADC r3, r4, #0\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_521_add_17_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -57236,22 +60843,33 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_add_17(sp_digit* r, "BNE.N L_sp_521_add_17_word_%=\n\t" #endif "ADDS r3, r3, #0xffffffff\n\t" - "LDM %[a], {r4}\n\t" - "LDM %[b], {r8}\n\t" + "LDM r1, {r4}\n\t" + "LDM r2, {r8}\n\t" "ADCS r4, r4, r8\n\t" - "STM %[r]!, {r4}\n\t" + "STM r0!, {r4}\n\t" "MOV r4, #0\n\t" - "ADC %[r], r4, #0\n\t" + "ADC r0, r4, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -57274,52 +60892,71 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_add_17(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3}\n\t" - "LDM %[b]!, {r7}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3}\n\t" + "LDM r2!, {r7}\n\t" "ADCS r3, r3, r7\n\t" - "STM %[r]!, {r3}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -57563,9 +61200,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_cond_sub_17(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, #0\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -57576,12 +61222,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_cond_sub_17(sp_digit* r, "L_sp_521_cond_sub_17_words_%=:\n\t" #endif "SUBS r4, r8, r4\n\t" - "LDR r6, [%[a], r5]\n\t" - "LDR r7, [%[b], r5]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r5]\n\t" + "LDR r7, [r2, r5]\n\t" + "AND r7, r7, r3\n\t" "SBCS r6, r6, r7\n\t" "SBC r4, r8, r8\n\t" - "STR r6, [%[r], r5]\n\t" + "STR r6, [r0, r5]\n\t" "ADD r5, r5, #4\n\t" "CMP r5, #0x44\n\t" #if defined(__GNUC__) @@ -57591,16 +61237,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_cond_sub_17(sp_digit* r, #else "BLT.N L_sp_521_cond_sub_17_words_%=\n\t" #endif - "MOV %[r], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -57627,81 +61285,102 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_cond_sub_17(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SUBS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r8, [%[b]]\n\t" - "AND r8, r8, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDR r6, [r1]\n\t" + "LDR r8, [r2]\n\t" + "AND r8, r8, r3\n\t" "SBCS r6, r6, r8\n\t" - "STR r6, [%[r]]\n\t" - "SBC %[r], r5, r5\n\t" + "STR r6, [r0]\n\t" + "SBC r0, r5, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -57723,13 +61402,22 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_17(sp_digit* a, { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x44\n\t" "MOV r12, sp\n\t" /* Shift top down by 9 bits */ - "ADD lr, %[a], #0x40\n\t" + "ADD lr, r0, #0x40\n\t" /* 0-7 */ "LDM lr!, {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "LSR r1, r1, #9\n\t" @@ -57772,7 +61460,7 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_17(sp_digit* a, "STM r12!, {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" /* Add top to bottom */ /* 0-5 */ - "LDM %[a], {r1, r2, r3, r4, r5, r6}\n\t" + "LDM r0, {r1, r2, r3, r4, r5, r6}\n\t" "LDM sp!, {r7, r8, r9, r10, r11, r12}\n\t" "ADDS r1, r1, r7\n\t" "ADCS r2, r2, r8\n\t" @@ -57780,9 +61468,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_17(sp_digit* a, "ADCS r4, r4, r10\n\t" "ADCS r5, r5, r11\n\t" "ADCS r6, r6, r12\n\t" - "STM %[a]!, {r1, r2, r3, r4, r5, r6}\n\t" + "STM r0!, {r1, r2, r3, r4, r5, r6}\n\t" /* 6-11 */ - "LDM %[a], {r1, r2, r3, r4, r5, r6}\n\t" + "LDM r0, {r1, r2, r3, r4, r5, r6}\n\t" "LDM sp!, {r7, r8, r9, r10, r11, r12}\n\t" "ADCS r1, r1, r7\n\t" "ADCS r2, r2, r8\n\t" @@ -57790,9 +61478,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_17(sp_digit* a, "ADCS r4, r4, r10\n\t" "ADCS r5, r5, r11\n\t" "ADCS r6, r6, r12\n\t" - "STM %[a]!, {r1, r2, r3, r4, r5, r6}\n\t" + "STM r0!, {r1, r2, r3, r4, r5, r6}\n\t" /* 12-16 */ - "LDM %[a], {r1, r2, r3, r4, r5}\n\t" + "LDM r0, {r1, r2, r3, r4, r5}\n\t" "LDM sp!, {r7, r8, r9, r10, r11}\n\t" "MOV lr, #0x1ff\n\t" "AND r5, r5, lr\n\t" @@ -57803,11 +61491,11 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_17(sp_digit* a, "ADCS r5, r5, r11\n\t" "LSR r12, r5, #9\n\t" "AND r5, r5, lr\n\t" - "STM %[a]!, {r1, r2, r3, r4, r5}\n\t" - "SUB %[a], %[a], #0x44\n\t" + "STM r0!, {r1, r2, r3, r4, r5}\n\t" + "SUB r0, r0, #0x44\n\t" /* Add overflow */ /* 0-8 */ - "LDM %[a], {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "LDM r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "ADDS r1, r1, r12\n\t" "ADCS r2, r2, #0\n\t" "ADCS r3, r3, #0\n\t" @@ -57817,9 +61505,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_17(sp_digit* a, "ADCS r7, r7, #0\n\t" "ADCS r8, r8, #0\n\t" "ADCS r9, r9, #0\n\t" - "STM %[a]!, {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" + "STM r0!, {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" /* 9-16 */ - "LDM %[a], {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" + "LDM r0, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" "ADCS r1, r1, #0\n\t" "ADCS r2, r2, #0\n\t" "ADCS r3, r3, #0\n\t" @@ -57828,26 +61516,33 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_17(sp_digit* a, "ADCS r6, r6, #0\n\t" "ADCS r7, r7, #0\n\t" "ADCS r8, r8, #0\n\t" - "STM %[a]!, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" + "STM r0!, {r1, r2, r3, r4, r5, r6, r7, r8}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a) : + : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + "r10", "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", - "r10", "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)mp_p; -#else - (void)mp; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -57871,15 +61566,24 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_order_17( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR lr, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR lr, [r1]\n\t" /* i = 0 */ "MOV r11, #0\n\t" "MOV r3, #0\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[a], #4]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_521_mont_reduce_order_17_word:\n\t" @@ -57887,7 +61591,7 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_order_17( "L_sp_521_mont_reduce_order_17_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL r10, %[mp], r4\n\t" + "MUL r10, r2, r4\n\t" "CMP r11, #0x40\n\t" #if defined(__GNUC__) "BNE L_sp_521_mont_reduce_order_17_nomask_%=\n\t" @@ -57907,142 +61611,142 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_order_17( /* a[i+0] += m[0] * mu */ "MOV r7, #0\n\t" "UMLAL r4, r7, r10, lr\n\t" - "STR r4, [%[a]]\n\t" + "STR r4, [r0]\n\t" /* a[i+1] += m[1] * mu */ - "LDR r9, [%[m], #4]\n\t" + "LDR r9, [r1, #4]\n\t" "MOV r6, #0\n\t" "UMLAL r5, r6, r10, r9\n\t" "MOV r4, r5\n\t" "ADDS r4, r4, r7\n\t" "ADC r6, r6, #0\n\t" /* a[i+2] += m[2] * mu */ - "LDR r9, [%[m], #8]\n\t" - "LDR r5, [%[a], #8]\n\t" + "LDR r9, [r1, #8]\n\t" + "LDR r5, [r0, #8]\n\t" "MOV r7, #0\n\t" "UMLAL r5, r7, r10, r9\n\t" "ADDS r5, r5, r6\n\t" "ADC r7, r7, #0\n\t" /* a[i+3] += m[3] * mu */ - "LDR r9, [%[m], #12]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r9, [r1, #12]\n\t" + "LDR r12, [r0, #12]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #12]\n\t" + "STR r12, [r0, #12]\n\t" "ADC r6, r6, #0\n\t" /* a[i+4] += m[4] * mu */ - "LDR r9, [%[m], #16]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r9, [r1, #16]\n\t" + "LDR r12, [r0, #16]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #16]\n\t" + "STR r12, [r0, #16]\n\t" "ADC r7, r7, #0\n\t" /* a[i+5] += m[5] * mu */ - "LDR r9, [%[m], #20]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r12, [r0, #20]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #20]\n\t" + "STR r12, [r0, #20]\n\t" "ADC r6, r6, #0\n\t" /* a[i+6] += m[6] * mu */ - "LDR r9, [%[m], #24]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r9, [r1, #24]\n\t" + "LDR r12, [r0, #24]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #24]\n\t" + "STR r12, [r0, #24]\n\t" "ADC r7, r7, #0\n\t" /* a[i+7] += m[7] * mu */ - "LDR r9, [%[m], #28]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r9, [r1, #28]\n\t" + "LDR r12, [r0, #28]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #28]\n\t" + "STR r12, [r0, #28]\n\t" "ADC r6, r6, #0\n\t" /* a[i+8] += m[8] * mu */ - "LDR r9, [%[m], #32]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r9, [r1, #32]\n\t" + "LDR r12, [r0, #32]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #32]\n\t" + "STR r12, [r0, #32]\n\t" "ADC r7, r7, #0\n\t" /* a[i+9] += m[9] * mu */ - "LDR r9, [%[m], #36]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r9, [r1, #36]\n\t" + "LDR r12, [r0, #36]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #36]\n\t" + "STR r12, [r0, #36]\n\t" "ADC r6, r6, #0\n\t" /* a[i+10] += m[10] * mu */ - "LDR r9, [%[m], #40]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r9, [r1, #40]\n\t" + "LDR r12, [r0, #40]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #40]\n\t" + "STR r12, [r0, #40]\n\t" "ADC r7, r7, #0\n\t" /* a[i+11] += m[11] * mu */ - "LDR r9, [%[m], #44]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r9, [r1, #44]\n\t" + "LDR r12, [r0, #44]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #44]\n\t" + "STR r12, [r0, #44]\n\t" "ADC r6, r6, #0\n\t" /* a[i+12] += m[12] * mu */ - "LDR r9, [%[m], #48]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r9, [r1, #48]\n\t" + "LDR r12, [r0, #48]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #48]\n\t" + "STR r12, [r0, #48]\n\t" "ADC r7, r7, #0\n\t" /* a[i+13] += m[13] * mu */ - "LDR r9, [%[m], #52]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r9, [r1, #52]\n\t" + "LDR r12, [r0, #52]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #52]\n\t" + "STR r12, [r0, #52]\n\t" "ADC r6, r6, #0\n\t" /* a[i+14] += m[14] * mu */ - "LDR r9, [%[m], #56]\n\t" - "LDR r12, [%[a], #56]\n\t" + "LDR r9, [r1, #56]\n\t" + "LDR r12, [r0, #56]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #56]\n\t" + "STR r12, [r0, #56]\n\t" "ADC r7, r7, #0\n\t" /* a[i+15] += m[15] * mu */ - "LDR r9, [%[m], #60]\n\t" - "LDR r12, [%[a], #60]\n\t" + "LDR r9, [r1, #60]\n\t" + "LDR r12, [r0, #60]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #60]\n\t" + "STR r12, [r0, #60]\n\t" "ADC r6, r6, #0\n\t" /* a[i+16] += m[16] * mu */ - "LDR r9, [%[m], #64]\n\t" - "LDR r12, [%[a], #64]\n\t" + "LDR r9, [r1, #64]\n\t" + "LDR r12, [r0, #64]\n\t" "UMULL r8, r9, r10, r9\n\t" "ADDS r6, r6, r8\n\t" "ADCS r7, r9, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, r3\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #64]\n\t" - "LDR r12, [%[a], #68]\n\t" + "STR r12, [r0, #64]\n\t" + "LDR r12, [r0, #68]\n\t" "ADCS r12, r12, r7\n\t" - "STR r12, [%[a], #68]\n\t" + "STR r12, [r0, #68]\n\t" "ADC r3, r3, #0\n\t" /* i += 1 */ "ADD r11, r11, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r11, #0x44\n\t" #if defined(__GNUC__) "BLT L_sp_521_mont_reduce_order_17_word_%=\n\t" @@ -58052,89 +61756,100 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_order_17( "BLT.W L_sp_521_mont_reduce_order_17_word_%=\n\t" #endif /* Loop Done */ - "STR r4, [%[a]]\n\t" - "STR r5, [%[a], #4]\n\t" - "SUB %[a], %[a], #4\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r7, [%[a], #4]\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" + "SUB r0, r0, #4\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" "LSR r6, r6, #9\n\t" "ORR r6, r6, r7, LSL #23\n\t" - "STR r6, [%[a], #4]\n\t" - "LDR r6, [%[a], #8]\n\t" + "STR r6, [r0, #4]\n\t" + "LDR r6, [r0, #8]\n\t" "LSR r7, r7, #9\n\t" "ORR r7, r7, r6, LSL #23\n\t" - "STR r7, [%[a], #8]\n\t" - "LDR r7, [%[a], #12]\n\t" + "STR r7, [r0, #8]\n\t" + "LDR r7, [r0, #12]\n\t" "LSR r6, r6, #9\n\t" "ORR r6, r6, r7, LSL #23\n\t" - "STR r6, [%[a], #12]\n\t" - "LDR r6, [%[a], #16]\n\t" + "STR r6, [r0, #12]\n\t" + "LDR r6, [r0, #16]\n\t" "LSR r7, r7, #9\n\t" "ORR r7, r7, r6, LSL #23\n\t" - "STR r7, [%[a], #16]\n\t" - "LDR r7, [%[a], #20]\n\t" + "STR r7, [r0, #16]\n\t" + "LDR r7, [r0, #20]\n\t" "LSR r6, r6, #9\n\t" "ORR r6, r6, r7, LSL #23\n\t" - "STR r6, [%[a], #20]\n\t" - "LDR r6, [%[a], #24]\n\t" + "STR r6, [r0, #20]\n\t" + "LDR r6, [r0, #24]\n\t" "LSR r7, r7, #9\n\t" "ORR r7, r7, r6, LSL #23\n\t" - "STR r7, [%[a], #24]\n\t" - "LDR r7, [%[a], #28]\n\t" + "STR r7, [r0, #24]\n\t" + "LDR r7, [r0, #28]\n\t" "LSR r6, r6, #9\n\t" "ORR r6, r6, r7, LSL #23\n\t" - "STR r6, [%[a], #28]\n\t" - "LDR r6, [%[a], #32]\n\t" + "STR r6, [r0, #28]\n\t" + "LDR r6, [r0, #32]\n\t" "LSR r7, r7, #9\n\t" "ORR r7, r7, r6, LSL #23\n\t" - "STR r7, [%[a], #32]\n\t" - "LDR r7, [%[a], #36]\n\t" + "STR r7, [r0, #32]\n\t" + "LDR r7, [r0, #36]\n\t" "LSR r6, r6, #9\n\t" "ORR r6, r6, r7, LSL #23\n\t" - "STR r6, [%[a], #36]\n\t" - "LDR r6, [%[a], #40]\n\t" + "STR r6, [r0, #36]\n\t" + "LDR r6, [r0, #40]\n\t" "LSR r7, r7, #9\n\t" "ORR r7, r7, r6, LSL #23\n\t" - "STR r7, [%[a], #40]\n\t" - "LDR r7, [%[a], #44]\n\t" + "STR r7, [r0, #40]\n\t" + "LDR r7, [r0, #44]\n\t" "LSR r6, r6, #9\n\t" "ORR r6, r6, r7, LSL #23\n\t" - "STR r6, [%[a], #44]\n\t" - "LDR r6, [%[a], #48]\n\t" + "STR r6, [r0, #44]\n\t" + "LDR r6, [r0, #48]\n\t" "LSR r7, r7, #9\n\t" "ORR r7, r7, r6, LSL #23\n\t" - "STR r7, [%[a], #48]\n\t" - "LDR r7, [%[a], #52]\n\t" + "STR r7, [r0, #48]\n\t" + "LDR r7, [r0, #52]\n\t" "LSR r6, r6, #9\n\t" "ORR r6, r6, r7, LSL #23\n\t" - "STR r6, [%[a], #52]\n\t" - "LDR r6, [%[a], #56]\n\t" + "STR r6, [r0, #52]\n\t" + "LDR r6, [r0, #56]\n\t" "LSR r7, r7, #9\n\t" "ORR r7, r7, r6, LSL #23\n\t" - "STR r7, [%[a], #56]\n\t" - "LDR r7, [%[a], #60]\n\t" + "STR r7, [r0, #56]\n\t" + "LDR r7, [r0, #60]\n\t" "LSR r6, r6, #9\n\t" "ORR r6, r6, r7, LSL #23\n\t" - "STR r6, [%[a], #60]\n\t" - "LDR r6, [%[a], #64]\n\t" + "STR r6, [r0, #60]\n\t" + "LDR r6, [r0, #64]\n\t" "LSR r7, r7, #9\n\t" "ORR r7, r7, r6, LSL #23\n\t" - "STR r7, [%[a], #64]\n\t" + "STR r7, [r0, #64]\n\t" "LSR r6, r6, #9\n\t" - "STR r6, [%[a], #68]\n\t" + "STR r6, [r0, #68]\n\t" "LSR r3, r6, #9\n\t" - "ADD %[a], %[a], #4\n\t" - "MOV %[mp], r3\n\t" + "ADD r0, r0, #4\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_521_cond_sub_17(a - 17, a, m, (sp_digit)0 - mp); } @@ -58158,17 +61873,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_order_17( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* i = 0 */ "MOV r4, #0\n\t" "MOV r5, #0\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r7, [%[a], #4]\n\t" - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[a], #12]\n\t" - "LDR r10, [%[a], #16]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" + "LDR r10, [r0, #16]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_521_mont_reduce_order_17_word:\n\t" @@ -58176,7 +61900,7 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_order_17( "L_sp_521_mont_reduce_order_17_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL lr, %[mp], r6\n\t" + "MUL lr, r2, r6\n\t" "CMP r4, #0x40\n\t" #if defined(__GNUC__) "BNE L_sp_521_mont_reduce_order_17_nomask_%=\n\t" @@ -58194,94 +61918,94 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_order_17( "L_sp_521_mont_reduce_order_17_nomask_%=:\n\t" #endif /* a[i+0] += m[0] * mu */ - "LDR r12, [%[m]]\n\t" + "LDR r12, [r1]\n\t" "MOV r3, #0\n\t" "UMAAL r6, r3, lr, r12\n\t" - "STR r6, [%[a]]\n\t" + "STR r6, [r0]\n\t" /* a[i+1] += m[1] * mu */ - "LDR r12, [%[m], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "MOV r6, r7\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+2] += m[2] * mu */ - "LDR r12, [%[m], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "MOV r7, r8\n\t" "UMAAL r7, r3, lr, r12\n\t" /* a[i+3] += m[3] * mu */ - "LDR r12, [%[m], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "MOV r8, r9\n\t" "UMAAL r8, r3, lr, r12\n\t" /* a[i+4] += m[4] * mu */ - "LDR r12, [%[m], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "MOV r9, r10\n\t" "UMAAL r9, r3, lr, r12\n\t" /* a[i+5] += m[5] * mu */ - "LDR r12, [%[m], #20]\n\t" - "LDR r10, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR r10, [r0, #20]\n\t" "UMAAL r10, r3, lr, r12\n\t" /* a[i+6] += m[6] * mu */ - "LDR r12, [%[m], #24]\n\t" - "LDR r11, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR r11, [r0, #24]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #24]\n\t" + "STR r11, [r0, #24]\n\t" /* a[i+7] += m[7] * mu */ - "LDR r12, [%[m], #28]\n\t" - "LDR r11, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR r11, [r0, #28]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #28]\n\t" + "STR r11, [r0, #28]\n\t" /* a[i+8] += m[8] * mu */ - "LDR r12, [%[m], #32]\n\t" - "LDR r11, [%[a], #32]\n\t" + "LDR r12, [r1, #32]\n\t" + "LDR r11, [r0, #32]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #32]\n\t" + "STR r11, [r0, #32]\n\t" /* a[i+9] += m[9] * mu */ - "LDR r12, [%[m], #36]\n\t" - "LDR r11, [%[a], #36]\n\t" + "LDR r12, [r1, #36]\n\t" + "LDR r11, [r0, #36]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #36]\n\t" + "STR r11, [r0, #36]\n\t" /* a[i+10] += m[10] * mu */ - "LDR r12, [%[m], #40]\n\t" - "LDR r11, [%[a], #40]\n\t" + "LDR r12, [r1, #40]\n\t" + "LDR r11, [r0, #40]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #40]\n\t" + "STR r11, [r0, #40]\n\t" /* a[i+11] += m[11] * mu */ - "LDR r12, [%[m], #44]\n\t" - "LDR r11, [%[a], #44]\n\t" + "LDR r12, [r1, #44]\n\t" + "LDR r11, [r0, #44]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #44]\n\t" + "STR r11, [r0, #44]\n\t" /* a[i+12] += m[12] * mu */ - "LDR r12, [%[m], #48]\n\t" - "LDR r11, [%[a], #48]\n\t" + "LDR r12, [r1, #48]\n\t" + "LDR r11, [r0, #48]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #48]\n\t" + "STR r11, [r0, #48]\n\t" /* a[i+13] += m[13] * mu */ - "LDR r12, [%[m], #52]\n\t" - "LDR r11, [%[a], #52]\n\t" + "LDR r12, [r1, #52]\n\t" + "LDR r11, [r0, #52]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #52]\n\t" + "STR r11, [r0, #52]\n\t" /* a[i+14] += m[14] * mu */ - "LDR r12, [%[m], #56]\n\t" - "LDR r11, [%[a], #56]\n\t" + "LDR r12, [r1, #56]\n\t" + "LDR r11, [r0, #56]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #56]\n\t" + "STR r11, [r0, #56]\n\t" /* a[i+15] += m[15] * mu */ - "LDR r12, [%[m], #60]\n\t" - "LDR r11, [%[a], #60]\n\t" + "LDR r12, [r1, #60]\n\t" + "LDR r11, [r0, #60]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #60]\n\t" + "STR r11, [r0, #60]\n\t" /* a[i+16] += m[16] * mu */ - "LDR r12, [%[m], #64]\n\t" - "LDR r11, [%[a], #64]\n\t" + "LDR r12, [r1, #64]\n\t" + "LDR r11, [r0, #64]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "LDR lr, [%[a], #68]\n\t" + "LDR lr, [r0, #68]\n\t" "MOV r12, #0\n\t" "UMAAL r3, lr, r12, r12\n\t" - "STR r11, [%[a], #64]\n\t" + "STR r11, [r0, #64]\n\t" "ADDS r3, r3, r5\n\t" "ADC r5, lr, #0\n\t" - "STR r3, [%[a], #68]\n\t" + "STR r3, [r0, #68]\n\t" /* i += 1 */ "ADD r4, r4, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r4, #0x44\n\t" #if defined(__GNUC__) "BLT L_sp_521_mont_reduce_order_17_word_%=\n\t" @@ -58291,92 +62015,103 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_reduce_order_17( "BLT.W L_sp_521_mont_reduce_order_17_word_%=\n\t" #endif /* Loop Done */ - "STR r6, [%[a]]\n\t" - "STR r7, [%[a], #4]\n\t" - "STR r8, [%[a], #8]\n\t" - "STR r9, [%[a], #12]\n\t" - "STR r10, [%[a], #16]\n\t" - "SUB %[a], %[a], #4\n\t" - "LDR r12, [%[a]]\n\t" - "LDR r3, [%[a], #4]\n\t" + "STR r6, [r0]\n\t" + "STR r7, [r0, #4]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #12]\n\t" + "STR r10, [r0, #16]\n\t" + "SUB r0, r0, #4\n\t" + "LDR r12, [r0]\n\t" + "LDR r3, [r0, #4]\n\t" "LSR r12, r12, #9\n\t" "ORR r12, r12, r3, LSL #23\n\t" - "STR r12, [%[a], #4]\n\t" - "LDR r12, [%[a], #8]\n\t" + "STR r12, [r0, #4]\n\t" + "LDR r12, [r0, #8]\n\t" "LSR r3, r3, #9\n\t" "ORR r3, r3, r12, LSL #23\n\t" - "STR r3, [%[a], #8]\n\t" - "LDR r3, [%[a], #12]\n\t" + "STR r3, [r0, #8]\n\t" + "LDR r3, [r0, #12]\n\t" "LSR r12, r12, #9\n\t" "ORR r12, r12, r3, LSL #23\n\t" - "STR r12, [%[a], #12]\n\t" - "LDR r12, [%[a], #16]\n\t" + "STR r12, [r0, #12]\n\t" + "LDR r12, [r0, #16]\n\t" "LSR r3, r3, #9\n\t" "ORR r3, r3, r12, LSL #23\n\t" - "STR r3, [%[a], #16]\n\t" - "LDR r3, [%[a], #20]\n\t" + "STR r3, [r0, #16]\n\t" + "LDR r3, [r0, #20]\n\t" "LSR r12, r12, #9\n\t" "ORR r12, r12, r3, LSL #23\n\t" - "STR r12, [%[a], #20]\n\t" - "LDR r12, [%[a], #24]\n\t" + "STR r12, [r0, #20]\n\t" + "LDR r12, [r0, #24]\n\t" "LSR r3, r3, #9\n\t" "ORR r3, r3, r12, LSL #23\n\t" - "STR r3, [%[a], #24]\n\t" - "LDR r3, [%[a], #28]\n\t" + "STR r3, [r0, #24]\n\t" + "LDR r3, [r0, #28]\n\t" "LSR r12, r12, #9\n\t" "ORR r12, r12, r3, LSL #23\n\t" - "STR r12, [%[a], #28]\n\t" - "LDR r12, [%[a], #32]\n\t" + "STR r12, [r0, #28]\n\t" + "LDR r12, [r0, #32]\n\t" "LSR r3, r3, #9\n\t" "ORR r3, r3, r12, LSL #23\n\t" - "STR r3, [%[a], #32]\n\t" - "LDR r3, [%[a], #36]\n\t" + "STR r3, [r0, #32]\n\t" + "LDR r3, [r0, #36]\n\t" "LSR r12, r12, #9\n\t" "ORR r12, r12, r3, LSL #23\n\t" - "STR r12, [%[a], #36]\n\t" - "LDR r12, [%[a], #40]\n\t" + "STR r12, [r0, #36]\n\t" + "LDR r12, [r0, #40]\n\t" "LSR r3, r3, #9\n\t" "ORR r3, r3, r12, LSL #23\n\t" - "STR r3, [%[a], #40]\n\t" - "LDR r3, [%[a], #44]\n\t" + "STR r3, [r0, #40]\n\t" + "LDR r3, [r0, #44]\n\t" "LSR r12, r12, #9\n\t" "ORR r12, r12, r3, LSL #23\n\t" - "STR r12, [%[a], #44]\n\t" - "LDR r12, [%[a], #48]\n\t" + "STR r12, [r0, #44]\n\t" + "LDR r12, [r0, #48]\n\t" "LSR r3, r3, #9\n\t" "ORR r3, r3, r12, LSL #23\n\t" - "STR r3, [%[a], #48]\n\t" - "LDR r3, [%[a], #52]\n\t" + "STR r3, [r0, #48]\n\t" + "LDR r3, [r0, #52]\n\t" "LSR r12, r12, #9\n\t" "ORR r12, r12, r3, LSL #23\n\t" - "STR r12, [%[a], #52]\n\t" - "LDR r12, [%[a], #56]\n\t" + "STR r12, [r0, #52]\n\t" + "LDR r12, [r0, #56]\n\t" "LSR r3, r3, #9\n\t" "ORR r3, r3, r12, LSL #23\n\t" - "STR r3, [%[a], #56]\n\t" - "LDR r3, [%[a], #60]\n\t" + "STR r3, [r0, #56]\n\t" + "LDR r3, [r0, #60]\n\t" "LSR r12, r12, #9\n\t" "ORR r12, r12, r3, LSL #23\n\t" - "STR r12, [%[a], #60]\n\t" - "LDR r12, [%[a], #64]\n\t" + "STR r12, [r0, #60]\n\t" + "LDR r12, [r0, #64]\n\t" "LSR r3, r3, #9\n\t" "ORR r3, r3, r12, LSL #23\n\t" - "STR r3, [%[a], #64]\n\t" + "STR r3, [r0, #64]\n\t" "LSR r12, r12, #9\n\t" - "STR r12, [%[a], #68]\n\t" + "STR r12, [r0, #68]\n\t" "LSR r5, r12, #9\n\t" - "ADD %[a], %[a], #4\n\t" - "MOV %[mp], r5\n\t" + "ADD r0, r0, #4\n\t" + "MOV r2, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_521_cond_sub_17(a - 17, a, m, (sp_digit)0 - mp); } @@ -58539,9 +62274,17 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0xffffffff\n\t" "MOV r8, #1\n\t" "MOV r7, #0\n\t" @@ -58554,8 +62297,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, #else "L_sp_521_cmp_17_words_%=:\n\t" #endif - "LDR r4, [%[a], r6]\n\t" - "LDR r5, [%[b], r6]\n\t" + "LDR r4, [r0, r6]\n\t" + "LDR r5, [r1, r6]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58573,8 +62316,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, #endif "EOR r2, r2, r3\n\t" #else - "LDR r4, [%[a], #64]\n\t" - "LDR r5, [%[b], #64]\n\t" + "LDR r4, [r0, #64]\n\t" + "LDR r5, [r1, #64]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58584,8 +62327,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #60]\n\t" - "LDR r5, [%[b], #60]\n\t" + "LDR r4, [r0, #60]\n\t" + "LDR r5, [r1, #60]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58595,8 +62338,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #56]\n\t" - "LDR r5, [%[b], #56]\n\t" + "LDR r4, [r0, #56]\n\t" + "LDR r5, [r1, #56]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58606,8 +62349,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #52]\n\t" - "LDR r5, [%[b], #52]\n\t" + "LDR r4, [r0, #52]\n\t" + "LDR r5, [r1, #52]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58617,8 +62360,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #48]\n\t" - "LDR r5, [%[b], #48]\n\t" + "LDR r4, [r0, #48]\n\t" + "LDR r5, [r1, #48]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58628,8 +62371,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #44]\n\t" - "LDR r5, [%[b], #44]\n\t" + "LDR r4, [r0, #44]\n\t" + "LDR r5, [r1, #44]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58639,8 +62382,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #40]\n\t" - "LDR r5, [%[b], #40]\n\t" + "LDR r4, [r0, #40]\n\t" + "LDR r5, [r1, #40]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58650,8 +62393,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #36]\n\t" - "LDR r5, [%[b], #36]\n\t" + "LDR r4, [r0, #36]\n\t" + "LDR r5, [r1, #36]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58661,8 +62404,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #32]\n\t" - "LDR r5, [%[b], #32]\n\t" + "LDR r4, [r0, #32]\n\t" + "LDR r5, [r1, #32]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58672,8 +62415,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #28]\n\t" - "LDR r5, [%[b], #28]\n\t" + "LDR r4, [r0, #28]\n\t" + "LDR r5, [r1, #28]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58683,8 +62426,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #24]\n\t" - "LDR r5, [%[b], #24]\n\t" + "LDR r4, [r0, #24]\n\t" + "LDR r5, [r1, #24]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58694,8 +62437,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #20]\n\t" - "LDR r5, [%[b], #20]\n\t" + "LDR r4, [r0, #20]\n\t" + "LDR r5, [r1, #20]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58705,8 +62448,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #16]\n\t" - "LDR r5, [%[b], #16]\n\t" + "LDR r4, [r0, #16]\n\t" + "LDR r5, [r1, #16]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58716,8 +62459,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #12]\n\t" - "LDR r5, [%[b], #12]\n\t" + "LDR r4, [r0, #12]\n\t" + "LDR r5, [r1, #12]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58727,8 +62470,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #8]\n\t" - "LDR r5, [%[b], #8]\n\t" + "LDR r4, [r0, #8]\n\t" + "LDR r5, [r1, #8]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58738,8 +62481,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #4]\n\t" - "LDR r5, [%[b], #4]\n\t" + "LDR r4, [r0, #4]\n\t" + "LDR r5, [r1, #4]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58749,8 +62492,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[b]]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r1]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -58762,16 +62505,26 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_521_cmp_17(const sp_digit* a, "movne r3, r7\n\t" "EOR r2, r2, r3\n\t" #endif /*WOLFSSL_SP_SMALL */ - "MOV %[a], r2\n\t" + "MOV r0, r2\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -58840,47 +62593,56 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_add_17(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r3, #0\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "ADDS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8}\n\t" - "LDM %[b]!, {r4}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8}\n\t" + "LDM r2!, {r4}\n\t" "ADCS r8, r8, r4\n\t" "MOV r12, #0x1ff\n\t" "LSR r3, r8, #9\n\t" "AND r8, r8, r12\n\t" - "STM %[r]!, {r8}\n\t" - "SUB %[r], %[r], #0x44\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r8}\n\t" + "SUB r0, r0, #0x44\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADDS r4, r4, r3\n\t" "ADCS r5, r5, #0\n\t" "ADCS r6, r6, #0\n\t" @@ -58889,8 +62651,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_add_17(sp_digit* r, "ADCS r9, r9, #0\n\t" "ADCS r10, r10, #0\n\t" "ADCS r11, r11, #0\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADCS r4, r4, #0\n\t" "ADCS r5, r5, #0\n\t" "ADCS r6, r6, #0\n\t" @@ -58899,24 +62661,34 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_add_17(sp_digit* r, "ADCS r9, r9, #0\n\t" "ADCS r10, r10, #0\n\t" "ADCS r11, r11, #0\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[r], {r4}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r0, {r4}\n\t" "ADCS r4, r4, #0\n\t" - "STM %[r]!, {r4}\n\t" + "STM r0!, {r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (const sp_digit*)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -58937,11 +62709,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_dbl_17(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADDS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -58950,8 +62730,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_dbl_17(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADCS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -58960,15 +62740,15 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_dbl_17(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4}\n\t" "ADCS r4, r4, r4\n\t" "MOV r3, #0x1ff\n\t" "LSR r2, r4, #9\n\t" "AND r4, r4, r3\n\t" - "STM %[r]!, {r4}\n\t" - "SUB %[r], %[r], #0x44\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4}\n\t" + "SUB r0, r0, #0x44\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADDS r4, r4, r2\n\t" "ADCS r5, r5, #0\n\t" "ADCS r6, r6, #0\n\t" @@ -58977,8 +62757,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_dbl_17(sp_digit* r, "ADCS r9, r9, #0\n\t" "ADCS r10, r10, #0\n\t" "ADCS r11, r11, #0\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADCS r4, r4, #0\n\t" "ADCS r5, r5, #0\n\t" "ADCS r6, r6, #0\n\t" @@ -58987,24 +62767,33 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_dbl_17(sp_digit* r, "ADCS r9, r9, #0\n\t" "ADCS r10, r10, #0\n\t" "ADCS r11, r11, #0\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[r], {r4}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r0, {r4}\n\t" "ADCS r4, r4, #0\n\t" - "STM %[r]!, {r4}\n\t" + "STM r0!, {r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r2", "r3" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r2", "r3" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -59025,11 +62814,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_tpl_17(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADDS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -59038,8 +62835,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_tpl_17(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADCS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -59048,49 +62845,49 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_tpl_17(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4}\n\t" "ADCS r4, r4, r4\n\t" - "STM %[r]!, {r4}\n\t" - "SUB %[r], %[r], #0x44\n\t" - "SUB %[a], %[a], #0x44\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4}\n\t" + "SUB r0, r0, #0x44\n\t" + "SUB r1, r1, #0x44\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" "ADDS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4}\n\t" - "LDM %[a]!, {r8}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4}\n\t" + "LDM r1!, {r8}\n\t" "ADCS r4, r4, r8\n\t" "MOV r3, #0x1ff\n\t" "LSR r2, r4, #9\n\t" "AND r4, r4, r3\n\t" - "STM %[r]!, {r4}\n\t" - "SUB %[r], %[r], #0x44\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4}\n\t" + "SUB r0, r0, #0x44\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADDS r4, r4, r2\n\t" "ADCS r5, r5, #0\n\t" "ADCS r6, r6, #0\n\t" @@ -59099,8 +62896,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_tpl_17(sp_digit* r, "ADCS r9, r9, #0\n\t" "ADCS r10, r10, #0\n\t" "ADCS r11, r11, #0\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADCS r4, r4, #0\n\t" "ADCS r5, r5, #0\n\t" "ADCS r6, r6, #0\n\t" @@ -59109,24 +62906,33 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_tpl_17(sp_digit* r, "ADCS r9, r9, #0\n\t" "ADCS r10, r10, #0\n\t" "ADCS r11, r11, #0\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[r], {r4}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r0, {r4}\n\t" "ADCS r4, r4, #0\n\t" - "STM %[r]!, {r4}\n\t" + "STM r0!, {r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r2", "r3" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r2", "r3" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG (void)m_p; -#else - (void)m; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ } @@ -59150,49 +62956,58 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_sub_17(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register const sp_digit* m __asm__ ("r3") = (const sp_digit*)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "MOV %[m], #0\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "MOV r3, #0\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "SUBS r8, r8, r4\n\t" "SBCS r9, r9, r5\n\t" "SBCS r10, r10, r6\n\t" "SBCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "SBCS r8, r8, r4\n\t" "SBCS r9, r9, r5\n\t" "SBCS r10, r10, r6\n\t" "SBCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "SBCS r8, r8, r4\n\t" "SBCS r9, r9, r5\n\t" "SBCS r10, r10, r6\n\t" "SBCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8, r9, r10, r11}\n\t" - "LDM %[b]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8, r9, r10, r11}\n\t" + "LDM r2!, {r4, r5, r6, r7}\n\t" "SBCS r8, r8, r4\n\t" "SBCS r9, r9, r5\n\t" "SBCS r10, r10, r6\n\t" "SBCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r8}\n\t" - "LDM %[b]!, {r4}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r8}\n\t" + "LDM r2!, {r4}\n\t" "SBCS r8, r8, r4\n\t" "MOV r12, #0x1ff\n\t" - "ASR %[m], r8, #9\n\t" + "ASR r3, r8, #9\n\t" "AND r8, r8, r12\n\t" - "neg %[m], %[m]\n\t" - "STM %[r]!, {r8}\n\t" - "SUB %[r], %[r], #0x44\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "SUBS r4, r4, %[m]\n\t" + "neg r3, r3\n\t" + "STM r0!, {r8}\n\t" + "SUB r0, r0, #0x44\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "SUBS r4, r4, r3\n\t" "SBCS r5, r5, #0\n\t" "SBCS r6, r6, #0\n\t" "SBCS r7, r7, #0\n\t" @@ -59200,8 +63015,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_sub_17(sp_digit* r, "SBCS r9, r9, #0\n\t" "SBCS r10, r10, #0\n\t" "SBCS r11, r11, #0\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[r], {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r0, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "SBCS r4, r4, #0\n\t" "SBCS r5, r5, #0\n\t" "SBCS r6, r6, #0\n\t" @@ -59210,20 +63025,32 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_521_mont_sub_17(sp_digit* r, "SBCS r9, r9, #0\n\t" "SBCS r10, r10, #0\n\t" "SBCS r11, r11, #0\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[r], {r4}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r0, {r4}\n\t" "SBCS r4, r4, #0\n\t" - "STM %[r]!, {r4}\n\t" + "STM r0!, {r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (const sp_digit*)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Shift number right one bit. @@ -59243,84 +63070,102 @@ WC_OMIT_FRAME_POINTER static void sp_521_rshift1_17(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1, {r2, r3}\n\t" "LSR r2, r2, #1\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #8]\n\t" - "STR r2, [%[r]]\n\t" + "LDR r4, [r1, #8]\n\t" + "STR r2, [r0]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #12]\n\t" - "STR r3, [%[r], #4]\n\t" + "LDR r2, [r1, #12]\n\t" + "STR r3, [r0, #4]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #16]\n\t" - "STR r4, [%[r], #8]\n\t" + "LDR r3, [r1, #16]\n\t" + "STR r4, [r0, #8]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #20]\n\t" - "STR r2, [%[r], #12]\n\t" + "LDR r4, [r1, #20]\n\t" + "STR r2, [r0, #12]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #24]\n\t" - "STR r3, [%[r], #16]\n\t" + "LDR r2, [r1, #24]\n\t" + "STR r3, [r0, #16]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #28]\n\t" - "STR r4, [%[r], #20]\n\t" + "LDR r3, [r1, #28]\n\t" + "STR r4, [r0, #20]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #32]\n\t" - "STR r2, [%[r], #24]\n\t" + "LDR r4, [r1, #32]\n\t" + "STR r2, [r0, #24]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #36]\n\t" - "STR r3, [%[r], #28]\n\t" + "LDR r2, [r1, #36]\n\t" + "STR r3, [r0, #28]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #40]\n\t" - "STR r4, [%[r], #32]\n\t" + "LDR r3, [r1, #40]\n\t" + "STR r4, [r0, #32]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #44]\n\t" - "STR r2, [%[r], #36]\n\t" + "LDR r4, [r1, #44]\n\t" + "STR r2, [r0, #36]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #48]\n\t" - "STR r3, [%[r], #40]\n\t" + "LDR r2, [r1, #48]\n\t" + "STR r3, [r0, #40]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #52]\n\t" - "STR r4, [%[r], #44]\n\t" + "LDR r3, [r1, #52]\n\t" + "STR r4, [r0, #44]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #56]\n\t" - "STR r2, [%[r], #48]\n\t" + "LDR r4, [r1, #56]\n\t" + "STR r2, [r0, #48]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #60]\n\t" - "STR r3, [%[r], #52]\n\t" + "LDR r2, [r1, #60]\n\t" + "STR r3, [r0, #52]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #64]\n\t" - "STR r4, [%[r], #56]\n\t" + "LDR r3, [r1, #64]\n\t" + "STR r4, [r0, #56]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "STR r2, [%[r], #60]\n\t" - "STR r3, [%[r], #64]\n\t" + "STR r2, [r0, #60]\n\t" + "STR r3, [r0, #64]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Divide the number by 2 mod the modulus (prime). (r = a / 2 % m) @@ -63420,45 +67265,62 @@ WC_OMIT_FRAME_POINTER static void sp_521_add_one_17(sp_digit* a) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; +#else + void* L_asm_args[1] = {(void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r1, r2, r3, r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r1, r2, r3, r4}\n\t" "ADDS r1, r1, #1\n\t" "ADCS r2, r2, #0\n\t" "ADCS r3, r3, #0\n\t" "ADCS r4, r4, #0\n\t" - "STM %[a]!, {r1, r2, r3, r4}\n\t" - "LDM %[a], {r1, r2, r3, r4}\n\t" + "STM r0!, {r1, r2, r3, r4}\n\t" + "LDM r0, {r1, r2, r3, r4}\n\t" "ADCS r1, r1, #0\n\t" "ADCS r2, r2, #0\n\t" "ADCS r3, r3, #0\n\t" "ADCS r4, r4, #0\n\t" - "STM %[a]!, {r1, r2, r3, r4}\n\t" - "LDM %[a], {r1, r2, r3, r4}\n\t" + "STM r0!, {r1, r2, r3, r4}\n\t" + "LDM r0, {r1, r2, r3, r4}\n\t" "ADCS r1, r1, #0\n\t" "ADCS r2, r2, #0\n\t" "ADCS r3, r3, #0\n\t" "ADCS r4, r4, #0\n\t" - "STM %[a]!, {r1, r2, r3, r4}\n\t" - "LDM %[a], {r1, r2, r3, r4}\n\t" + "STM r0!, {r1, r2, r3, r4}\n\t" + "LDM r0, {r1, r2, r3, r4}\n\t" "ADCS r1, r1, #0\n\t" "ADCS r2, r2, #0\n\t" "ADCS r3, r3, #0\n\t" "ADCS r4, r4, #0\n\t" - "STM %[a]!, {r1, r2, r3, r4}\n\t" - "LDM %[a], {r1}\n\t" + "STM r0!, {r1, r2, r3, r4}\n\t" + "LDM r0, {r1}\n\t" "ADCS r1, r1, #0\n\t" - "STM %[a]!, {r1}\n\t" + "STM r0!, {r1}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a) : + : "memory", "cc", "r1", "r2", "r3", "r4" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif @@ -63865,100 +67727,119 @@ WC_OMIT_FRAME_POINTER static void sp_521_rshift_17(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register byte n __asm__ ("r2") = (byte)n_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)n + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "RSB r7, %[n], #32\n\t" - "LDRD r4, r5, [%[a]]\n\t" - "LSR r4, r4, %[n]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "RSB r7, r2, #32\n\t" + "LDRD r4, r5, [r1]\n\t" + "LSR r4, r4, r2\n\t" "LSL r3, r5, r7\n\t" - "LSR r5, r5, %[n]\n\t" + "LSR r5, r5, r2\n\t" "ORR r4, r4, r3\n\t" - "LDR r6, [%[a], #8]\n\t" - "STR r4, [%[r]]\n\t" + "LDR r6, [r1, #8]\n\t" + "STR r4, [r0]\n\t" "LSL r3, r6, r7\n\t" - "LSR r6, r6, %[n]\n\t" + "LSR r6, r6, r2\n\t" "ORR r5, r5, r3\n\t" - "LDR r4, [%[a], #12]\n\t" - "STR r5, [%[r], #4]\n\t" + "LDR r4, [r1, #12]\n\t" + "STR r5, [r0, #4]\n\t" "LSL r3, r4, r7\n\t" - "LSR r4, r4, %[n]\n\t" + "LSR r4, r4, r2\n\t" "ORR r6, r6, r3\n\t" - "LDR r5, [%[a], #16]\n\t" - "STR r6, [%[r], #8]\n\t" + "LDR r5, [r1, #16]\n\t" + "STR r6, [r0, #8]\n\t" "LSL r3, r5, r7\n\t" - "LSR r5, r5, %[n]\n\t" + "LSR r5, r5, r2\n\t" "ORR r4, r4, r3\n\t" - "LDR r6, [%[a], #20]\n\t" - "STR r4, [%[r], #12]\n\t" + "LDR r6, [r1, #20]\n\t" + "STR r4, [r0, #12]\n\t" "LSL r3, r6, r7\n\t" - "LSR r6, r6, %[n]\n\t" + "LSR r6, r6, r2\n\t" "ORR r5, r5, r3\n\t" - "LDR r4, [%[a], #24]\n\t" - "STR r5, [%[r], #16]\n\t" + "LDR r4, [r1, #24]\n\t" + "STR r5, [r0, #16]\n\t" "LSL r3, r4, r7\n\t" - "LSR r4, r4, %[n]\n\t" + "LSR r4, r4, r2\n\t" "ORR r6, r6, r3\n\t" - "LDR r5, [%[a], #28]\n\t" - "STR r6, [%[r], #20]\n\t" + "LDR r5, [r1, #28]\n\t" + "STR r6, [r0, #20]\n\t" "LSL r3, r5, r7\n\t" - "LSR r5, r5, %[n]\n\t" + "LSR r5, r5, r2\n\t" "ORR r4, r4, r3\n\t" - "LDR r6, [%[a], #32]\n\t" - "STR r4, [%[r], #24]\n\t" + "LDR r6, [r1, #32]\n\t" + "STR r4, [r0, #24]\n\t" "LSL r3, r6, r7\n\t" - "LSR r6, r6, %[n]\n\t" + "LSR r6, r6, r2\n\t" "ORR r5, r5, r3\n\t" - "LDR r4, [%[a], #36]\n\t" - "STR r5, [%[r], #28]\n\t" + "LDR r4, [r1, #36]\n\t" + "STR r5, [r0, #28]\n\t" "LSL r3, r4, r7\n\t" - "LSR r4, r4, %[n]\n\t" + "LSR r4, r4, r2\n\t" "ORR r6, r6, r3\n\t" - "LDR r5, [%[a], #40]\n\t" - "STR r6, [%[r], #32]\n\t" + "LDR r5, [r1, #40]\n\t" + "STR r6, [r0, #32]\n\t" "LSL r3, r5, r7\n\t" - "LSR r5, r5, %[n]\n\t" + "LSR r5, r5, r2\n\t" "ORR r4, r4, r3\n\t" - "LDR r6, [%[a], #44]\n\t" - "STR r4, [%[r], #36]\n\t" + "LDR r6, [r1, #44]\n\t" + "STR r4, [r0, #36]\n\t" "LSL r3, r6, r7\n\t" - "LSR r6, r6, %[n]\n\t" + "LSR r6, r6, r2\n\t" "ORR r5, r5, r3\n\t" - "LDR r4, [%[a], #48]\n\t" - "STR r5, [%[r], #40]\n\t" + "LDR r4, [r1, #48]\n\t" + "STR r5, [r0, #40]\n\t" "LSL r3, r4, r7\n\t" - "LSR r4, r4, %[n]\n\t" + "LSR r4, r4, r2\n\t" "ORR r6, r6, r3\n\t" - "LDR r5, [%[a], #52]\n\t" - "STR r6, [%[r], #44]\n\t" + "LDR r5, [r1, #52]\n\t" + "STR r6, [r0, #44]\n\t" "LSL r3, r5, r7\n\t" - "LSR r5, r5, %[n]\n\t" + "LSR r5, r5, r2\n\t" "ORR r4, r4, r3\n\t" - "LDR r6, [%[a], #56]\n\t" - "STR r4, [%[r], #48]\n\t" + "LDR r6, [r1, #56]\n\t" + "STR r4, [r0, #48]\n\t" "LSL r3, r6, r7\n\t" - "LSR r6, r6, %[n]\n\t" + "LSR r6, r6, r2\n\t" "ORR r5, r5, r3\n\t" - "LDR r4, [%[a], #60]\n\t" - "STR r5, [%[r], #52]\n\t" + "LDR r4, [r1, #60]\n\t" + "STR r5, [r0, #52]\n\t" "LSL r3, r4, r7\n\t" - "LSR r4, r4, %[n]\n\t" + "LSR r4, r4, r2\n\t" "ORR r6, r6, r3\n\t" - "LDR r5, [%[a], #64]\n\t" - "STR r6, [%[r], #56]\n\t" + "LDR r5, [r1, #64]\n\t" + "STR r6, [r0, #56]\n\t" "LSL r3, r5, r7\n\t" - "LSR r5, r5, %[n]\n\t" + "LSR r5, r5, r2\n\t" "ORR r4, r4, r3\n\t" - "STRD r4, r5, [%[r], #60]\n\t" + "STRD r4, r5, [r0, #60]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [n] "+r" (n) : + : "memory", "cc", "r4", "r5", "r6", "r3", "r7" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [n] "r" (n) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r3", "r7" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + n = (byte)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif @@ -63983,121 +67864,140 @@ WC_OMIT_FRAME_POINTER static void sp_521_lshift_17(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register byte n __asm__ ("r2") = (byte)n_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)n + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "RSB r7, %[n], #31\n\t" - "LDR r5, [%[a], #64]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "RSB r7, r2, #31\n\t" + "LDR r5, [r1, #64]\n\t" "LSR r6, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r6, r6, r7\n\t" - "LDR r4, [%[a], #60]\n\t" - "STR r6, [%[r], #68]\n\t" + "LDR r4, [r1, #60]\n\t" + "STR r6, [r0, #68]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #56]\n\t" - "STR r5, [%[r], #64]\n\t" + "LDR r6, [r1, #56]\n\t" + "STR r5, [r0, #64]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #52]\n\t" - "STR r4, [%[r], #60]\n\t" + "LDR r5, [r1, #52]\n\t" + "STR r4, [r0, #60]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #48]\n\t" - "STR r6, [%[r], #56]\n\t" + "LDR r4, [r1, #48]\n\t" + "STR r6, [r0, #56]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #44]\n\t" - "STR r5, [%[r], #52]\n\t" + "LDR r6, [r1, #44]\n\t" + "STR r5, [r0, #52]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #40]\n\t" - "STR r4, [%[r], #48]\n\t" + "LDR r5, [r1, #40]\n\t" + "STR r4, [r0, #48]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #36]\n\t" - "STR r6, [%[r], #44]\n\t" + "LDR r4, [r1, #36]\n\t" + "STR r6, [r0, #44]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #32]\n\t" - "STR r5, [%[r], #40]\n\t" + "LDR r6, [r1, #32]\n\t" + "STR r5, [r0, #40]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #28]\n\t" - "STR r4, [%[r], #36]\n\t" + "LDR r5, [r1, #28]\n\t" + "STR r4, [r0, #36]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #24]\n\t" - "STR r6, [%[r], #32]\n\t" + "LDR r4, [r1, #24]\n\t" + "STR r6, [r0, #32]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #20]\n\t" - "STR r5, [%[r], #28]\n\t" + "LDR r6, [r1, #20]\n\t" + "STR r5, [r0, #28]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #16]\n\t" - "STR r4, [%[r], #24]\n\t" + "LDR r5, [r1, #16]\n\t" + "STR r4, [r0, #24]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #12]\n\t" - "STR r6, [%[r], #20]\n\t" + "LDR r4, [r1, #12]\n\t" + "STR r6, [r0, #20]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #8]\n\t" - "STR r5, [%[r], #16]\n\t" + "LDR r6, [r1, #8]\n\t" + "STR r5, [r0, #16]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #4]\n\t" - "STR r4, [%[r], #12]\n\t" + "LDR r5, [r1, #4]\n\t" + "STR r4, [r0, #12]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a]]\n\t" - "STR r6, [%[r], #8]\n\t" + "LDR r4, [r1]\n\t" + "STR r6, [r0, #8]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "STR r4, [%[r]]\n\t" - "STR r5, [%[r], #4]\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [n] "+r" (n) : + : "memory", "cc", "r4", "r5", "r6", "r3", "r7" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [n] "r" (n) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r3", "r7" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + n = (byte)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Shift number left by n bits. @@ -64118,223 +68018,242 @@ WC_OMIT_FRAME_POINTER static void sp_521_lshift_34(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register byte n __asm__ ("r2") = (byte)n_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)n + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "RSB r7, %[n], #31\n\t" - "LDR r5, [%[a], #132]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "RSB r7, r2, #31\n\t" + "LDR r5, [r1, #132]\n\t" "LSR r6, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r6, r6, r7\n\t" - "LDR r4, [%[a], #128]\n\t" - "STR r6, [%[r], #136]\n\t" + "LDR r4, [r1, #128]\n\t" + "STR r6, [r0, #136]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #124]\n\t" - "STR r5, [%[r], #132]\n\t" + "LDR r6, [r1, #124]\n\t" + "STR r5, [r0, #132]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #120]\n\t" - "STR r4, [%[r], #128]\n\t" + "LDR r5, [r1, #120]\n\t" + "STR r4, [r0, #128]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #116]\n\t" - "STR r6, [%[r], #124]\n\t" + "LDR r4, [r1, #116]\n\t" + "STR r6, [r0, #124]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #112]\n\t" - "STR r5, [%[r], #120]\n\t" + "LDR r6, [r1, #112]\n\t" + "STR r5, [r0, #120]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #108]\n\t" - "STR r4, [%[r], #116]\n\t" + "LDR r5, [r1, #108]\n\t" + "STR r4, [r0, #116]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #104]\n\t" - "STR r6, [%[r], #112]\n\t" + "LDR r4, [r1, #104]\n\t" + "STR r6, [r0, #112]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #100]\n\t" - "STR r5, [%[r], #108]\n\t" + "LDR r6, [r1, #100]\n\t" + "STR r5, [r0, #108]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #96]\n\t" - "STR r4, [%[r], #104]\n\t" + "LDR r5, [r1, #96]\n\t" + "STR r4, [r0, #104]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #92]\n\t" - "STR r6, [%[r], #100]\n\t" + "LDR r4, [r1, #92]\n\t" + "STR r6, [r0, #100]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #88]\n\t" - "STR r5, [%[r], #96]\n\t" + "LDR r6, [r1, #88]\n\t" + "STR r5, [r0, #96]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #84]\n\t" - "STR r4, [%[r], #92]\n\t" + "LDR r5, [r1, #84]\n\t" + "STR r4, [r0, #92]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #80]\n\t" - "STR r6, [%[r], #88]\n\t" + "LDR r4, [r1, #80]\n\t" + "STR r6, [r0, #88]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #76]\n\t" - "STR r5, [%[r], #84]\n\t" + "LDR r6, [r1, #76]\n\t" + "STR r5, [r0, #84]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #72]\n\t" - "STR r4, [%[r], #80]\n\t" + "LDR r5, [r1, #72]\n\t" + "STR r4, [r0, #80]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #68]\n\t" - "STR r6, [%[r], #76]\n\t" + "LDR r4, [r1, #68]\n\t" + "STR r6, [r0, #76]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #64]\n\t" - "STR r5, [%[r], #72]\n\t" + "LDR r6, [r1, #64]\n\t" + "STR r5, [r0, #72]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #60]\n\t" - "STR r4, [%[r], #68]\n\t" + "LDR r5, [r1, #60]\n\t" + "STR r4, [r0, #68]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #56]\n\t" - "STR r6, [%[r], #64]\n\t" + "LDR r4, [r1, #56]\n\t" + "STR r6, [r0, #64]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #52]\n\t" - "STR r5, [%[r], #60]\n\t" + "LDR r6, [r1, #52]\n\t" + "STR r5, [r0, #60]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #48]\n\t" - "STR r4, [%[r], #56]\n\t" + "LDR r5, [r1, #48]\n\t" + "STR r4, [r0, #56]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #44]\n\t" - "STR r6, [%[r], #52]\n\t" + "LDR r4, [r1, #44]\n\t" + "STR r6, [r0, #52]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #40]\n\t" - "STR r5, [%[r], #48]\n\t" + "LDR r6, [r1, #40]\n\t" + "STR r5, [r0, #48]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #36]\n\t" - "STR r4, [%[r], #44]\n\t" + "LDR r5, [r1, #36]\n\t" + "STR r4, [r0, #44]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #32]\n\t" - "STR r6, [%[r], #40]\n\t" + "LDR r4, [r1, #32]\n\t" + "STR r6, [r0, #40]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #28]\n\t" - "STR r5, [%[r], #36]\n\t" + "LDR r6, [r1, #28]\n\t" + "STR r5, [r0, #36]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #24]\n\t" - "STR r4, [%[r], #32]\n\t" + "LDR r5, [r1, #24]\n\t" + "STR r4, [r0, #32]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #20]\n\t" - "STR r6, [%[r], #28]\n\t" + "LDR r4, [r1, #20]\n\t" + "STR r6, [r0, #28]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #16]\n\t" - "STR r5, [%[r], #24]\n\t" + "LDR r6, [r1, #16]\n\t" + "STR r5, [r0, #24]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a], #12]\n\t" - "STR r4, [%[r], #20]\n\t" + "LDR r5, [r1, #12]\n\t" + "STR r4, [r0, #20]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "LDR r4, [%[a], #8]\n\t" - "STR r6, [%[r], #16]\n\t" + "LDR r4, [r1, #8]\n\t" + "STR r6, [r0, #16]\n\t" "LSR r3, r4, #1\n\t" - "LSL r4, r4, %[n]\n\t" + "LSL r4, r4, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r5, r5, r3\n\t" - "LDR r6, [%[a], #4]\n\t" - "STR r5, [%[r], #12]\n\t" + "LDR r6, [r1, #4]\n\t" + "STR r5, [r0, #12]\n\t" "LSR r3, r6, #1\n\t" - "LSL r6, r6, %[n]\n\t" + "LSL r6, r6, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r4, r4, r3\n\t" - "LDR r5, [%[a]]\n\t" - "STR r4, [%[r], #8]\n\t" + "LDR r5, [r1]\n\t" + "STR r4, [r0, #8]\n\t" "LSR r3, r5, #1\n\t" - "LSL r5, r5, %[n]\n\t" + "LSL r5, r5, r2\n\t" "LSR r3, r3, r7\n\t" "ORR r6, r6, r3\n\t" - "STR r5, [%[r]]\n\t" - "STR r6, [%[r], #4]\n\t" + "STR r5, [r0]\n\t" + "STR r6, [r0, #4]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [n] "+r" (n) : + : "memory", "cc", "r4", "r5", "r6", "r3", "r7" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [n] "r" (n) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r3", "r7" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + n = (byte)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifdef WOLFSSL_SP_SMALL @@ -64354,11 +68273,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_sub_in_place_17(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "ADD r11, %[a], #0x40\n\t" + "ADD r11, r0, #0x40\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_521_sub_in_place_17_word:\n\t" @@ -64366,15 +68293,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_sub_in_place_17(sp_digit* a, "L_sp_521_sub_in_place_17_word_%=:\n\t" #endif "RSBS r10, r10, #0\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" "SBC r10, r10, r10\n\t" - "CMP %[a], r11\n\t" + "CMP r0, r11\n\t" #if defined(__GNUC__) "BNE L_sp_521_sub_in_place_17_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -64383,21 +68310,31 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_sub_in_place_17(sp_digit* a, "BNE.N L_sp_521_sub_in_place_17_word_%=\n\t" #endif "RSBS r10, r10, #0\n\t" - "LDM %[a], {r2}\n\t" - "LDM %[b]!, {r6}\n\t" + "LDM r0, {r2}\n\t" + "LDM r1!, {r6}\n\t" "SBCS r2, r2, r6\n\t" - "STM %[a]!, {r2}\n\t" - "SBC %[a], %[a], %[a]\n\t" + "STM r0!, {r2}\n\t" + "SBC r0, r0, r0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -64418,51 +68355,69 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_sub_in_place_17(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SUBS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2}\n\t" - "LDM %[b]!, {r6}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2}\n\t" + "LDM r1!, {r6}\n\t" "SBCS r2, r2, r6\n\t" - "STM %[a]!, {r2}\n\t" - "SBC %[a], r9, r9\n\t" + "STM r0!, {r2}\n\t" + "SBC r0, r9, r9\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -64486,14 +68441,22 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_d_17(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDR r8, [%[a]]\n\t" - "UMULL r5, r3, %[b], r8\n\t" + "LDR r8, [r1]\n\t" + "UMULL r5, r3, r2, r8\n\t" "MOV r4, #0\n\t" - "STR r5, [%[r]]\n\t" + "STR r5, [r0]\n\t" "MOV r5, #0\n\t" "MOV r9, #4\n\t" "\n" @@ -64503,12 +68466,12 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_d_17(sp_digit* r, "L_sp_521_mul_d_17_word_%=:\n\t" #endif /* A[i] * B */ - "LDR r8, [%[a], r9]\n\t" - "UMULL r6, r7, %[b], r8\n\t" + "LDR r8, [r1, r9]\n\t" + "UMULL r6, r7, r2, r8\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], r9]\n\t" + "STR r3, [r0, r9]\n\t" "MOV r3, r4\n\t" "MOV r4, r5\n\t" "MOV r5, #0\n\t" @@ -64521,16 +68484,27 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_d_17(sp_digit* r, #else "BLT.N L_sp_521_mul_d_17_word_%=\n\t" #endif - "STR r3, [%[r], #68]\n\t" + "STR r3, [r0, #68]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -64552,103 +68526,122 @@ WC_OMIT_FRAME_POINTER static void sp_521_mul_d_17(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDM %[a]!, {r8}\n\t" - "UMULL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMULL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[1] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[2] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[3] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[4] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[5] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[6] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[7] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[8] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[9] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[10] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[11] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[12] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[13] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[14] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[15] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[16] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" - "STR r5, [%[r]]\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" + "STR r5, [r0]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -64675,53 +68668,73 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_521_word_17(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r8, %[div], #16\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r8, r2, #16\n\t" "ADD r5, r8, #1\n\t" - "UDIV r6, %[d1], r5\n\t" - "LSL r7, %[div], #16\n\t" + "UDIV r6, r0, r5\n\t" + "LSL r7, r2, #16\n\t" "LSL r6, r6, #16\n\t" - "UMULL r3, r4, %[div], r6\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "SUBS r3, %[d1], r5\n\t" + "UMULL r3, r4, r2, r6\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "SUBS r3, r0, r5\n\t" "SBC r9, r9, r9\n\t" "ADD r9, r9, #1\n\t" "RSB r10, r9, #0\n\t" "LSL r9, r9, #16\n\t" "AND r7, r7, r10\n\t" "AND r8, r8, r10\n\t" - "SUBS %[d0], %[d0], r7\n\t" + "SUBS r1, r1, r7\n\t" "ADD r6, r6, r9\n\t" - "SBC %[d1], %[d1], r8\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "SBC r0, r0, r8\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "UMULL r3, r4, %[div], r3\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "UMULL r3, r4, r2, r3\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "MUL r3, %[div], r3\n\t" - "SUB %[d0], %[d0], r3\n\t" - "UDIV r3, %[d0], %[div]\n\t" - "ADD %[d1], r6, r3\n\t" + "MUL r3, r2, r3\n\t" + "SUB r1, r1, r3\n\t" + "UDIV r3, r1, r2\n\t" + "ADD r0, r6, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -64748,13 +68761,22 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_521_word_17(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r5, %[div], #1\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r5, r2, #1\n\t" "ADD r5, r5, #1\n\t" - "MOV r6, %[d0]\n\t" - "MOV r7, %[d1]\n\t" + "MOV r6, r1\n\t" + "MOV r7, r0\n\t" /* Do top 32 */ "SUBS r8, r5, r7\n\t" "SBC r8, r8, r8\n\t" @@ -64788,29 +68810,40 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_521_word_17(sp_digit d1, #endif "ADD r3, r3, r3\n\t" "ADD r3, r3, #1\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "SUBS r8, r9, %[div]\n\t" - "ADC %[d1], r3, #0\n\t" + "SUBS r8, r9, r2\n\t" + "ADC r0, r3, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -65488,11 +69521,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_sub_17(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r11, #0\n\t" - "ADD r12, %[a], #0x40\n\t" + "ADD r12, r1, #0x40\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_521_sub_17_word:\n\t" @@ -65500,15 +69541,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_sub_17(sp_digit* r, "L_sp_521_sub_17_word_%=:\n\t" #endif "RSBS r11, r11, #0\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "SBC r11, r3, r3\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_521_sub_17_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -65517,21 +69558,32 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_sub_17(sp_digit* r, "BNE.N L_sp_521_sub_17_word_%=\n\t" #endif "RSBS r11, r11, #0\n\t" - "LDM %[a]!, {r3}\n\t" - "LDM %[b]!, {r7}\n\t" + "LDM r1!, {r3}\n\t" + "LDM r2!, {r7}\n\t" "SBCS r3, r3, r7\n\t" - "STM %[r]!, {r3}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -65554,51 +69606,70 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_521_sub_17(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3}\n\t" - "LDM %[b]!, {r7}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3}\n\t" + "LDM r2!, {r7}\n\t" "SBCS r3, r3, r7\n\t" - "STM %[r]!, {r3}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -65621,10 +69692,18 @@ WC_OMIT_FRAME_POINTER static void sp_521_div2_mod_17(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* m __asm__ ("r2") = (const sp_digit*)m_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r4}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r4}\n\t" "ANDS r3, r4, #1\n\t" #if defined(__GNUC__) "BEQ L_sp_521_div2_mod_17_even_%=\n\t" @@ -65634,38 +69713,38 @@ WC_OMIT_FRAME_POINTER static void sp_521_div2_mod_17(sp_digit* r, "BEQ.N L_sp_521_div2_mod_17_even_%=\n\t" #endif "MOV r12, #0\n\t" - "LDM %[a]!, {r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADDS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4}\n\t" - "LDM %[m]!, {r8}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4}\n\t" + "LDM r2!, {r8}\n\t" "ADCS r4, r4, r8\n\t" - "STM %[r]!, {r4}\n\t" + "STM r0!, {r4}\n\t" "ADC r3, r12, r12\n\t" #if defined(__GNUC__) "B L_sp_521_div2_mod_17_div2_%=\n\t" @@ -65680,100 +69759,111 @@ WC_OMIT_FRAME_POINTER static void sp_521_div2_mod_17(sp_digit* r, #else "L_sp_521_div2_mod_17_even_%=:\n\t" #endif - "LDM %[a]!, {r5, r6, r7}\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4}\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4}\n\t" + "STM r0!, {r4}\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_521_div2_mod_17_div2:\n\t" #else "L_sp_521_div2_mod_17_div2_%=:\n\t" #endif - "SUB %[r], %[r], #0x44\n\t" - "LDRD r8, r9, [%[r]]\n\t" + "SUB r0, r0, #0x44\n\t" + "LDRD r8, r9, [r0]\n\t" "LSR r8, r8, #1\n\t" "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" - "LDR r10, [%[r], #8]\n\t" - "STR r8, [%[r]]\n\t" + "LDR r10, [r0, #8]\n\t" + "STR r8, [r0]\n\t" "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" - "LDR r8, [%[r], #12]\n\t" - "STR r9, [%[r], #4]\n\t" + "LDR r8, [r0, #12]\n\t" + "STR r9, [r0, #4]\n\t" "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" - "LDR r9, [%[r], #16]\n\t" - "STR r10, [%[r], #8]\n\t" + "LDR r9, [r0, #16]\n\t" + "STR r10, [r0, #8]\n\t" "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" - "LDR r10, [%[r], #20]\n\t" - "STR r8, [%[r], #12]\n\t" + "LDR r10, [r0, #20]\n\t" + "STR r8, [r0, #12]\n\t" "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" - "LDR r8, [%[r], #24]\n\t" - "STR r9, [%[r], #16]\n\t" + "LDR r8, [r0, #24]\n\t" + "STR r9, [r0, #16]\n\t" "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" - "LDR r9, [%[r], #28]\n\t" - "STR r10, [%[r], #20]\n\t" + "LDR r9, [r0, #28]\n\t" + "STR r10, [r0, #20]\n\t" "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" - "LDR r10, [%[r], #32]\n\t" - "STR r8, [%[r], #24]\n\t" + "LDR r10, [r0, #32]\n\t" + "STR r8, [r0, #24]\n\t" "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" - "LDR r8, [%[r], #36]\n\t" - "STR r9, [%[r], #28]\n\t" + "LDR r8, [r0, #36]\n\t" + "STR r9, [r0, #28]\n\t" "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" - "LDR r9, [%[r], #40]\n\t" - "STR r10, [%[r], #32]\n\t" + "LDR r9, [r0, #40]\n\t" + "STR r10, [r0, #32]\n\t" "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" - "LDR r10, [%[r], #44]\n\t" - "STR r8, [%[r], #36]\n\t" + "LDR r10, [r0, #44]\n\t" + "STR r8, [r0, #36]\n\t" "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" - "LDR r8, [%[r], #48]\n\t" - "STR r9, [%[r], #40]\n\t" + "LDR r8, [r0, #48]\n\t" + "STR r9, [r0, #40]\n\t" "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" - "LDR r9, [%[r], #52]\n\t" - "STR r10, [%[r], #44]\n\t" + "LDR r9, [r0, #52]\n\t" + "STR r10, [r0, #44]\n\t" "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" - "LDR r10, [%[r], #56]\n\t" - "STR r8, [%[r], #48]\n\t" + "LDR r10, [r0, #56]\n\t" + "STR r8, [r0, #48]\n\t" "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" - "LDR r8, [%[r], #60]\n\t" - "STR r9, [%[r], #52]\n\t" + "LDR r8, [r0, #60]\n\t" + "STR r9, [r0, #52]\n\t" "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" - "LDR r9, [%[r], #64]\n\t" - "STR r10, [%[r], #56]\n\t" + "LDR r9, [r0, #64]\n\t" + "STR r10, [r0, #56]\n\t" "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" "ORR r9, r9, r3, LSL #31\n\t" - "STR r8, [%[r], #60]\n\t" - "STR r9, [%[r], #64]\n\t" + "STR r8, [r0, #60]\n\t" + "STR r9, [r0, #64]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Get the number of bits in the number. @@ -65790,10 +69880,18 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) { #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; +#else + void* L_asm_args[1] = {(void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR r1, [%[a], #64]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR r1, [r0, #64]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_16_%=\n\t" @@ -65818,7 +69916,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_16_%=:\n\t" #endif - "LDR r1, [%[a], #60]\n\t" + "LDR r1, [r0, #60]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_15_%=\n\t" @@ -65843,7 +69941,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_15_%=:\n\t" #endif - "LDR r1, [%[a], #56]\n\t" + "LDR r1, [r0, #56]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_14_%=\n\t" @@ -65868,7 +69966,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_14_%=:\n\t" #endif - "LDR r1, [%[a], #52]\n\t" + "LDR r1, [r0, #52]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_13_%=\n\t" @@ -65893,7 +69991,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_13_%=:\n\t" #endif - "LDR r1, [%[a], #48]\n\t" + "LDR r1, [r0, #48]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_12_%=\n\t" @@ -65918,7 +70016,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_12_%=:\n\t" #endif - "LDR r1, [%[a], #44]\n\t" + "LDR r1, [r0, #44]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_11_%=\n\t" @@ -65943,7 +70041,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_11_%=:\n\t" #endif - "LDR r1, [%[a], #40]\n\t" + "LDR r1, [r0, #40]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_10_%=\n\t" @@ -65968,7 +70066,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_10_%=:\n\t" #endif - "LDR r1, [%[a], #36]\n\t" + "LDR r1, [r0, #36]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_9_%=\n\t" @@ -65993,7 +70091,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_9_%=:\n\t" #endif - "LDR r1, [%[a], #32]\n\t" + "LDR r1, [r0, #32]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_8_%=\n\t" @@ -66018,7 +70116,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_8_%=:\n\t" #endif - "LDR r1, [%[a], #28]\n\t" + "LDR r1, [r0, #28]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_7_%=\n\t" @@ -66043,7 +70141,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_7_%=:\n\t" #endif - "LDR r1, [%[a], #24]\n\t" + "LDR r1, [r0, #24]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_6_%=\n\t" @@ -66068,7 +70166,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_6_%=:\n\t" #endif - "LDR r1, [%[a], #20]\n\t" + "LDR r1, [r0, #20]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_5_%=\n\t" @@ -66093,7 +70191,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_5_%=:\n\t" #endif - "LDR r1, [%[a], #16]\n\t" + "LDR r1, [r0, #16]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_4_%=\n\t" @@ -66118,7 +70216,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_4_%=:\n\t" #endif - "LDR r1, [%[a], #12]\n\t" + "LDR r1, [r0, #12]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_3_%=\n\t" @@ -66143,7 +70241,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_3_%=:\n\t" #endif - "LDR r1, [%[a], #8]\n\t" + "LDR r1, [r0, #8]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_2_%=\n\t" @@ -66168,7 +70266,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_2_%=:\n\t" #endif - "LDR r1, [%[a], #4]\n\t" + "LDR r1, [r0, #4]\n\t" "CMP r1, #0\n\t" #if defined(__GNUC__) "BEQ L_sp_521_num_bits_17_1_%=\n\t" @@ -66193,7 +70291,7 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_1_%=:\n\t" #endif - "LDR r1, [%[a]]\n\t" + "LDR r1, [r0]\n\t" "MOV r2, #32\n\t" "CLZ r4, r1\n\t" "SUB r4, r2, r4\n\t" @@ -66203,16 +70301,25 @@ WC_OMIT_FRAME_POINTER static int sp_521_num_bits_17(const sp_digit* a) #else "L_sp_521_num_bits_17_18_%=:\n\t" #endif - "MOV %[a], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a) : + : "memory", "cc", "r1", "r2", "r3", "r4", "r5" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r1", "r2", "r3", "r4", "r5" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -67142,1747 +71249,1755 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_16(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x40\n\t" /* A[0] * B[0] */ - "LDR r11, [%[a]]\n\t" - "LDR r12, [%[b]]\n\t" + "LDR r11, [r1]\n\t" + "LDR r12, [r2]\n\t" "UMULL r3, r4, r11, r12\n\t" "MOV r5, #0\n\t" "STR r3, [sp]\n\t" /* A[0] * B[1] */ - "LDR r9, [%[b], #4]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[0] */ - "LDR r8, [%[a], #4]\n\t" + "LDR r8, [r1, #4]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #4]\n\t" /* A[2] * B[0] */ - "LDR r8, [%[a], #8]\n\t" + "LDR r8, [r1, #8]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[1] */ - "LDR r11, [%[a], #4]\n\t" - "LDR r12, [%[b], #4]\n\t" + "LDR r11, [r1, #4]\n\t" + "LDR r12, [r2, #4]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[0] * B[2] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #8]\n\t" /* A[0] * B[3] */ - "LDR r9, [%[b], #12]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[2] */ - "LDR r9, [%[b], #8]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[1] */ - "LDR r8, [%[a], #8]\n\t" + "LDR r8, [r1, #8]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[0] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #12]\n\t" /* A[4] * B[0] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[1] */ - "LDR r8, [%[a], #12]\n\t" + "LDR r8, [r1, #12]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[2] */ - "LDR r11, [%[a], #8]\n\t" - "LDR r12, [%[b], #8]\n\t" + "LDR r11, [r1, #8]\n\t" + "LDR r12, [r2, #8]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[3] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[0] * B[4] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #16]\n\t" /* A[0] * B[5] */ - "LDR r9, [%[b], #20]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[4] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[3] */ - "LDR r9, [%[b], #12]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[2] */ - "LDR r8, [%[a], #12]\n\t" + "LDR r8, [r1, #12]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[1] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[0] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #20]\n\t" /* A[6] * B[0] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[1] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[2] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[3] */ - "LDR r11, [%[a], #12]\n\t" - "LDR r12, [%[b], #12]\n\t" + "LDR r11, [r1, #12]\n\t" + "LDR r12, [r2, #12]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[4] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[5] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[0] * B[6] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #24]\n\t" /* A[0] * B[7] */ - "LDR r9, [%[b], #28]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[6] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[5] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[4] */ - "LDR r9, [%[b], #16]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[3] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[2] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[1] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[0] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #28]\n\t" /* A[8] * B[0] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[1] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[2] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[3] */ - "LDR r8, [%[a], #20]\n\t" + "LDR r8, [r1, #20]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[4] */ - "LDR r11, [%[a], #16]\n\t" - "LDR r12, [%[b], #16]\n\t" + "LDR r11, [r1, #16]\n\t" + "LDR r12, [r2, #16]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[5] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[6] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[7] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[0] * B[8] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #32]\n\t" /* A[0] * B[9] */ - "LDR r9, [%[b], #36]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[8] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[7] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[6] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[5] */ - "LDR r9, [%[b], #20]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[4] */ - "LDR r8, [%[a], #20]\n\t" + "LDR r8, [r1, #20]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[3] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[2] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[1] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[0] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #36]\n\t" /* A[10] * B[0] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[1] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[2] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[3] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[4] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[5] */ - "LDR r11, [%[a], #20]\n\t" - "LDR r12, [%[b], #20]\n\t" + "LDR r11, [r1, #20]\n\t" + "LDR r12, [r2, #20]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[6] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[7] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[8] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[9] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[0] * B[10] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #40]\n\t" /* A[0] * B[11] */ - "LDR r9, [%[b], #44]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[10] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[9] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[8] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[7] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[6] */ - "LDR r9, [%[b], #24]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[5] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[4] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[3] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[2] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[1] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[0] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #44]\n\t" /* A[12] * B[0] */ - "LDR r8, [%[a], #48]\n\t" + "LDR r8, [r1, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[1] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[2] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[3] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[4] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[5] */ - "LDR r8, [%[a], #28]\n\t" + "LDR r8, [r1, #28]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[6] */ - "LDR r11, [%[a], #24]\n\t" - "LDR r12, [%[b], #24]\n\t" + "LDR r11, [r1, #24]\n\t" + "LDR r12, [r2, #24]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[7] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[8] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[9] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[10] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[11] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[0] * B[12] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #48]\n\t" /* A[0] * B[13] */ - "LDR r9, [%[b], #52]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[12] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[11] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[10] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[9] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[8] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[7] */ - "LDR r9, [%[b], #28]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[6] */ - "LDR r8, [%[a], #28]\n\t" + "LDR r8, [r1, #28]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[5] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[4] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[3] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[2] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[12] * B[1] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[0] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #52]\n\t" /* A[14] * B[0] */ - "LDR r8, [%[a], #56]\n\t" + "LDR r8, [r1, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[13] * B[1] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[12] * B[2] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[3] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[4] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[5] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[6] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[7] */ - "LDR r11, [%[a], #28]\n\t" - "LDR r12, [%[b], #28]\n\t" + "LDR r11, [r1, #28]\n\t" + "LDR r12, [r2, #28]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[8] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[9] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[10] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[11] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[2] * B[12] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[1] * B[13] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[0] * B[14] */ - "LDR r8, [%[a]]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" "STR r5, [sp, #56]\n\t" /* A[0] * B[15] */ - "LDR r9, [%[b], #60]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[1] * B[14] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[2] * B[13] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[12] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[11] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[10] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[9] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[8] */ - "LDR r9, [%[b], #32]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[7] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[6] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[5] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[4] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[12] * B[3] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[13] * B[2] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[14] * B[1] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #4]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[15] * B[0] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b]]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" "STR r3, [sp, #60]\n\t" /* A[15] * B[1] */ - "LDR r9, [%[b], #4]\n\t" + "LDR r9, [r2, #4]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[14] * B[2] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[3] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[12] * B[4] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[5] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[6] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[7] */ - "LDR r8, [%[a], #36]\n\t" + "LDR r8, [r1, #36]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[8] */ - "LDR r11, [%[a], #32]\n\t" - "LDR r12, [%[b], #32]\n\t" + "LDR r11, [r1, #32]\n\t" + "LDR r12, [r2, #32]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[9] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[10] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[11] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[4] * B[12] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[3] * B[13] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[2] * B[14] */ - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #8]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[1] * B[15] */ - "LDR r8, [%[a], #4]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #4]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #64]\n\t" + "STR r4, [r0, #64]\n\t" /* A[2] * B[15] */ - "LDR r8, [%[a], #8]\n\t" + "LDR r8, [r1, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[3] * B[14] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[4] * B[13] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[12] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[11] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[10] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[9] */ - "LDR r9, [%[b], #36]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[8] */ - "LDR r8, [%[a], #36]\n\t" + "LDR r8, [r1, #36]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[7] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[6] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[12] * B[5] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[13] * B[4] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[14] * B[3] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #12]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[15] * B[2] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #8]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #8]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #68]\n\t" + "STR r5, [r0, #68]\n\t" /* A[15] * B[3] */ - "LDR r9, [%[b], #12]\n\t" + "LDR r9, [r2, #12]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[14] * B[4] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[13] * B[5] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[12] * B[6] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[7] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[8] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[9] */ - "LDR r11, [%[a], #36]\n\t" - "LDR r12, [%[b], #36]\n\t" + "LDR r11, [r1, #36]\n\t" + "LDR r12, [r2, #36]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[10] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[11] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[6] * B[12] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[5] * B[13] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[4] * B[14] */ - "LDR r8, [%[a], #16]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #16]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[3] * B[15] */ - "LDR r8, [%[a], #12]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #12]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #72]\n\t" + "STR r3, [r0, #72]\n\t" /* A[4] * B[15] */ - "LDR r8, [%[a], #16]\n\t" + "LDR r8, [r1, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[5] * B[14] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[6] * B[13] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[12] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[11] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[10] */ - "LDR r9, [%[b], #40]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[9] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[8] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[12] * B[7] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[6] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[14] * B[5] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #20]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[15] * B[4] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #16]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #16]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #76]\n\t" + "STR r4, [r0, #76]\n\t" /* A[15] * B[5] */ - "LDR r9, [%[b], #20]\n\t" + "LDR r9, [r2, #20]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[14] * B[6] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[13] * B[7] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[12] * B[8] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[9] */ - "LDR r8, [%[a], #44]\n\t" + "LDR r8, [r1, #44]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[10] */ - "LDR r11, [%[a], #40]\n\t" - "LDR r12, [%[b], #40]\n\t" + "LDR r11, [r1, #40]\n\t" + "LDR r12, [r2, #40]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[11] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[8] * B[12] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[7] * B[13] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[6] * B[14] */ - "LDR r8, [%[a], #24]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #24]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[5] * B[15] */ - "LDR r8, [%[a], #20]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #20]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #80]\n\t" + "STR r5, [r0, #80]\n\t" /* A[6] * B[15] */ - "LDR r8, [%[a], #24]\n\t" + "LDR r8, [r1, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[7] * B[14] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[8] * B[13] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[12] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[11] */ - "LDR r9, [%[b], #44]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[10] */ - "LDR r8, [%[a], #44]\n\t" + "LDR r8, [r1, #44]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[12] * B[9] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[13] * B[8] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[14] * B[7] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #28]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[15] * B[6] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #24]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #24]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #84]\n\t" + "STR r3, [r0, #84]\n\t" /* A[15] * B[7] */ - "LDR r9, [%[b], #28]\n\t" + "LDR r9, [r2, #28]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[14] * B[8] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[9] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[12] * B[10] */ - "LDR r8, [%[a], #48]\n\t" + "LDR r8, [r1, #48]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[11] */ - "LDR r11, [%[a], #44]\n\t" - "LDR r12, [%[b], #44]\n\t" + "LDR r11, [r1, #44]\n\t" + "LDR r12, [r2, #44]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[10] * B[12] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[9] * B[13] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[8] * B[14] */ - "LDR r8, [%[a], #32]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #32]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[7] * B[15] */ - "LDR r8, [%[a], #28]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #28]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #88]\n\t" + "STR r4, [r0, #88]\n\t" /* A[8] * B[15] */ - "LDR r8, [%[a], #32]\n\t" + "LDR r8, [r1, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[9] * B[14] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[10] * B[13] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[12] */ - "LDR r9, [%[b], #48]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[12] * B[11] */ - "LDR r8, [%[a], #48]\n\t" + "LDR r8, [r1, #48]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[13] * B[10] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[14] * B[9] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #36]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[15] * B[8] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #32]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #32]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #92]\n\t" + "STR r5, [r0, #92]\n\t" /* A[15] * B[9] */ - "LDR r9, [%[b], #36]\n\t" + "LDR r9, [r2, #36]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[14] * B[10] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[13] * B[11] */ - "LDR r8, [%[a], #52]\n\t" + "LDR r8, [r1, #52]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[12] * B[12] */ - "LDR r11, [%[a], #48]\n\t" - "LDR r12, [%[b], #48]\n\t" + "LDR r11, [r1, #48]\n\t" + "LDR r12, [r2, #48]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[11] * B[13] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #52]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[10] * B[14] */ - "LDR r8, [%[a], #40]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #40]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[9] * B[15] */ - "LDR r8, [%[a], #36]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #36]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #96]\n\t" + "STR r3, [r0, #96]\n\t" /* A[10] * B[15] */ - "LDR r8, [%[a], #40]\n\t" + "LDR r8, [r1, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[11] * B[14] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[12] * B[13] */ - "LDR r9, [%[b], #52]\n\t" + "LDR r9, [r2, #52]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[12] */ - "LDR r8, [%[a], #52]\n\t" + "LDR r8, [r1, #52]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[14] * B[11] */ - "LDR r8, [%[a], #56]\n\t" - "LDR r9, [%[b], #44]\n\t" + "LDR r8, [r1, #56]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[15] * B[10] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #40]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #40]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #100]\n\t" + "STR r4, [r0, #100]\n\t" /* A[15] * B[11] */ - "LDR r9, [%[b], #44]\n\t" + "LDR r9, [r2, #44]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[14] * B[12] */ - "LDR r8, [%[a], #56]\n\t" + "LDR r8, [r1, #56]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[13] * B[13] */ - "LDR r11, [%[a], #52]\n\t" - "LDR r12, [%[b], #52]\n\t" + "LDR r11, [r1, #52]\n\t" + "LDR r12, [r2, #52]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[12] * B[14] */ - "LDR r8, [%[a], #48]\n\t" - "LDR r9, [%[b], #56]\n\t" + "LDR r8, [r1, #48]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" /* A[11] * B[15] */ - "LDR r8, [%[a], #44]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #44]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #104]\n\t" + "STR r5, [r0, #104]\n\t" /* A[12] * B[15] */ - "LDR r8, [%[a], #48]\n\t" + "LDR r8, [r1, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "MOV r5, #0\n\t" "ADC r5, r5, #0\n\t" /* A[13] * B[14] */ - "LDR r9, [%[b], #56]\n\t" + "LDR r9, [r2, #56]\n\t" "UMULL r6, r7, r11, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[14] * B[13] */ - "LDR r8, [%[a], #56]\n\t" + "LDR r8, [r1, #56]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" /* A[15] * B[12] */ - "LDR r8, [%[a], #60]\n\t" - "LDR r9, [%[b], #48]\n\t" + "LDR r8, [r1, #60]\n\t" + "LDR r9, [r2, #48]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], #108]\n\t" + "STR r3, [r0, #108]\n\t" /* A[15] * B[13] */ "UMULL r6, r7, r8, r12\n\t" "ADDS r4, r4, r6\n\t" @@ -68890,20 +73005,20 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_16(sp_digit* r, const sp_digit* a, "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[14] * B[14] */ - "LDR r11, [%[a], #56]\n\t" - "LDR r12, [%[b], #56]\n\t" + "LDR r11, [r1, #56]\n\t" + "LDR r12, [r2, #56]\n\t" "UMULL r6, r7, r11, r12\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" /* A[13] * B[15] */ - "LDR r8, [%[a], #52]\n\t" - "LDR r9, [%[b], #60]\n\t" + "LDR r8, [r1, #52]\n\t" + "LDR r9, [r2, #60]\n\t" "UMULL r6, r7, r8, r9\n\t" "ADDS r4, r4, r6\n\t" "ADCS r5, r5, r7\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #112]\n\t" + "STR r4, [r0, #112]\n\t" /* A[14] * B[15] */ "UMULL r6, r7, r11, r9\n\t" "ADDS r5, r5, r6\n\t" @@ -68911,34 +73026,45 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_16(sp_digit* r, const sp_digit* a, "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[15] * B[14] */ - "LDR r8, [%[a], #60]\n\t" + "LDR r8, [r1, #60]\n\t" "UMULL r6, r7, r8, r12\n\t" "ADDS r5, r5, r6\n\t" "ADCS r3, r3, r7\n\t" "ADC r4, r4, #0\n\t" - "STR r5, [%[r], #116]\n\t" + "STR r5, [r0, #116]\n\t" /* A[15] * B[15] */ "UMLAL r3, r4, r8, r9\n\t" - "STR r3, [%[r], #120]\n\t" - "STR r4, [%[r], #124]\n\t" + "STR r3, [r0, #120]\n\t" + "STR r4, [r0, #124]\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" "LDM sp!, {r3, r4, r5, r6}\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r11", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r11", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Square a and put result in r. (r = a * a) @@ -68956,18 +73082,26 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x40\n\t" /* A[0] * A[0] */ - "LDR r10, [%[a]]\n\t" + "LDR r10, [r1]\n\t" "UMULL r8, r3, r10, r10\n\t" "MOV r4, #0\n\t" "STR r8, [sp]\n\t" /* A[0] * A[1] */ - "LDR r10, [%[a], #4]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #4]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -68979,8 +73113,8 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r2, r2, #0\n\t" "STR r3, [sp, #4]\n\t" /* A[0] * A[2] */ - "LDR r10, [%[a], #8]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #8]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" @@ -68991,15 +73125,15 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[1] * A[1] */ - "LDR r10, [%[a], #4]\n\t" + "LDR r10, [r1, #4]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" "ADC r3, r3, #0\n\t" "STR r4, [sp, #8]\n\t" /* A[0] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -69010,8 +73144,8 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[1] * A[2] */ - "LDR r10, [%[a], #8]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #8]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -69021,8 +73155,8 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r4, r4, #0\n\t" "STR r2, [sp, #12]\n\t" /* A[0] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -69033,8 +73167,8 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "MOV r2, #0\n\t" "ADC r2, r2, #0\n\t" /* A[1] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -69043,28 +73177,28 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" /* A[2] * A[2] */ - "LDR r10, [%[a], #8]\n\t" + "LDR r10, [r1, #8]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" "STR r3, [sp, #16]\n\t" /* A[0] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[3] */ - "LDR r10, [%[a], #12]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #12]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -69077,27 +73211,27 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #20]\n\t" /* A[0] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[3] */ - "LDR r10, [%[a], #12]\n\t" + "LDR r10, [r1, #12]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -69110,28 +73244,28 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #24]\n\t" /* A[0] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[4] */ - "LDR r10, [%[a], #16]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #16]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -69144,34 +73278,34 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r2, r2, r7\n\t" "STR r3, [sp, #28]\n\t" /* A[0] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[4] */ - "LDR r10, [%[a], #16]\n\t" + "LDR r10, [r1, #16]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -69184,35 +73318,35 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #32]\n\t" /* A[0] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[5] */ - "LDR r10, [%[a], #20]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #20]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -69225,41 +73359,41 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #36]\n\t" /* A[0] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[5] */ - "LDR r10, [%[a], #20]\n\t" + "LDR r10, [r1, #20]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -69272,42 +73406,42 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r2, r2, r7\n\t" "STR r3, [sp, #40]\n\t" /* A[0] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[6] */ - "LDR r10, [%[a], #24]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #24]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -69320,48 +73454,48 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #44]\n\t" /* A[0] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[6] */ - "LDR r10, [%[a], #24]\n\t" + "LDR r10, [r1, #24]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -69374,49 +73508,49 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #48]\n\t" /* A[0] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[7] */ - "LDR r10, [%[a], #28]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #28]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -69429,55 +73563,55 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r2, r2, r7\n\t" "STR r3, [sp, #52]\n\t" /* A[0] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[7] */ - "LDR r10, [%[a], #28]\n\t" + "LDR r10, [r1, #28]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -69490,56 +73624,56 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r3, r3, r7\n\t" "STR r4, [sp, #56]\n\t" /* A[0] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a]]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[1] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[2] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[8] */ - "LDR r10, [%[a], #32]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #32]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -69552,55 +73686,55 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADC r4, r4, r7\n\t" "STR r2, [sp, #60]\n\t" /* A[1] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #4]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #4]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[2] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[3] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[8] */ - "LDR r10, [%[a], #32]\n\t" + "LDR r10, [r1, #32]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -69611,51 +73745,51 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r5\n\t" "ADCS r4, r4, r6\n\t" "ADC r2, r2, r7\n\t" - "STR r3, [%[r], #64]\n\t" + "STR r3, [r0, #64]\n\t" /* A[2] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #8]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #8]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[3] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[4] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[9] */ - "LDR r10, [%[a], #36]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #36]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -69666,50 +73800,50 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r5\n\t" "ADCS r2, r2, r6\n\t" "ADC r3, r3, r7\n\t" - "STR r4, [%[r], #68]\n\t" + "STR r4, [r0, #68]\n\t" /* A[3] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #12]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[4] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[5] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[9] * A[9] */ - "LDR r10, [%[a], #36]\n\t" + "LDR r10, [r1, #36]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -69720,44 +73854,44 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r5\n\t" "ADCS r3, r3, r6\n\t" "ADC r4, r4, r7\n\t" - "STR r2, [%[r], #72]\n\t" + "STR r2, [r0, #72]\n\t" /* A[4] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #16]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[5] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[6] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[9] * A[10] */ - "LDR r10, [%[a], #40]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #40]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -69768,43 +73902,43 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r5\n\t" "ADCS r4, r4, r6\n\t" "ADC r2, r2, r7\n\t" - "STR r3, [%[r], #76]\n\t" + "STR r3, [r0, #76]\n\t" /* A[5] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #20]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[6] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[7] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[9] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[10] * A[10] */ - "LDR r10, [%[a], #40]\n\t" + "LDR r10, [r1, #40]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -69815,37 +73949,37 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r5\n\t" "ADCS r2, r2, r6\n\t" "ADC r3, r3, r7\n\t" - "STR r4, [%[r], #80]\n\t" + "STR r4, [r0, #80]\n\t" /* A[6] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #24]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[7] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[8] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[9] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[10] * A[11] */ - "LDR r10, [%[a], #44]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #44]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -69856,36 +73990,36 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r5\n\t" "ADCS r3, r3, r6\n\t" "ADC r4, r4, r7\n\t" - "STR r2, [%[r], #84]\n\t" + "STR r2, [r0, #84]\n\t" /* A[7] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #28]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[8] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[9] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[10] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[11] * A[11] */ - "LDR r10, [%[a], #44]\n\t" + "LDR r10, [r1, #44]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -69896,30 +74030,30 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r5\n\t" "ADCS r4, r4, r6\n\t" "ADC r2, r2, r7\n\t" - "STR r3, [%[r], #88]\n\t" + "STR r3, [r0, #88]\n\t" /* A[8] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #32]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r3, #0\n\t" "MOV r7, #0\n\t" /* A[9] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[10] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[11] * A[12] */ - "LDR r10, [%[a], #48]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r10, [r1, #48]\n\t" + "LDR r12, [r1, #44]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -69930,29 +74064,29 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADDS r4, r4, r5\n\t" "ADCS r2, r2, r6\n\t" "ADC r3, r3, r7\n\t" - "STR r4, [%[r], #92]\n\t" + "STR r4, [r0, #92]\n\t" /* A[9] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #36]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r4, #0\n\t" "MOV r7, #0\n\t" /* A[10] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[11] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #44]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[12] * A[12] */ - "LDR r10, [%[a], #48]\n\t" + "LDR r10, [r1, #48]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -69963,23 +74097,23 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r5\n\t" "ADCS r3, r3, r6\n\t" "ADC r4, r4, r7\n\t" - "STR r2, [%[r], #96]\n\t" + "STR r2, [r0, #96]\n\t" /* A[10] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #40]\n\t" "UMULL r5, r6, r10, r12\n\t" "MOV r2, #0\n\t" "MOV r7, #0\n\t" /* A[11] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #44]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" "ADC r7, r7, #0\n\t" /* A[12] * A[13] */ - "LDR r10, [%[a], #52]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r10, [r1, #52]\n\t" + "LDR r12, [r1, #48]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r5, r5, r8\n\t" "ADCS r6, r6, r9\n\t" @@ -69990,10 +74124,10 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADDS r3, r3, r5\n\t" "ADCS r4, r4, r6\n\t" "ADC r2, r2, r7\n\t" - "STR r3, [%[r], #100]\n\t" + "STR r3, [r0, #100]\n\t" /* A[11] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #44]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" @@ -70004,8 +74138,8 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" /* A[12] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #48]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" @@ -70014,15 +74148,15 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADCS r2, r2, r9\n\t" "ADC r3, r3, #0\n\t" /* A[13] * A[13] */ - "LDR r10, [%[a], #52]\n\t" + "LDR r10, [r1, #52]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #104]\n\t" + "STR r4, [r0, #104]\n\t" /* A[12] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #48]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -70033,8 +74167,8 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "MOV r4, #0\n\t" "ADC r4, r4, #0\n\t" /* A[13] * A[14] */ - "LDR r10, [%[a], #56]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r10, [r1, #56]\n\t" + "LDR r12, [r1, #52]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" @@ -70042,10 +74176,10 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADDS r2, r2, r8\n\t" "ADCS r3, r3, r9\n\t" "ADC r4, r4, #0\n\t" - "STR r2, [%[r], #108]\n\t" + "STR r2, [r0, #108]\n\t" /* A[13] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #52]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" @@ -70056,15 +74190,15 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "MOV r2, #0\n\t" "ADC r2, r2, #0\n\t" /* A[14] * A[14] */ - "LDR r10, [%[a], #56]\n\t" + "LDR r10, [r1, #56]\n\t" "UMULL r8, r9, r10, r10\n\t" "ADDS r3, r3, r8\n\t" "ADCS r4, r4, r9\n\t" "ADC r2, r2, #0\n\t" - "STR r3, [%[r], #112]\n\t" + "STR r3, [r0, #112]\n\t" /* A[14] * A[15] */ - "LDR r10, [%[a], #60]\n\t" - "LDR r12, [%[a], #56]\n\t" + "LDR r10, [r1, #60]\n\t" + "LDR r12, [r1, #56]\n\t" "UMULL r8, r9, r10, r12\n\t" "ADDS r4, r4, r8\n\t" "ADCS r2, r2, r9\n\t" @@ -70074,30 +74208,40 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_16(sp_digit* r, const sp_digit* a) "ADCS r2, r2, r9\n\t" "MOV r3, #0\n\t" "ADC r3, r3, #0\n\t" - "STR r4, [%[r], #116]\n\t" + "STR r4, [r0, #116]\n\t" /* A[15] * A[15] */ - "LDR r10, [%[a], #60]\n\t" + "LDR r10, [r1, #60]\n\t" "UMLAL r2, r3, r10, r10\n\t" - "STR r2, [%[r], #120]\n\t" - "STR r3, [%[r], #124]\n\t" + "STR r2, [r0, #120]\n\t" + "STR r3, [r0, #124]\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" "LDM sp!, {r2, r3, r4, r8}\n\t" - "STM %[r]!, {r2, r3, r4, r8}\n\t" + "STM r0!, {r2, r3, r4, r8}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Add b to a into r. (r = a + b) @@ -70118,48 +74262,67 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_add_16(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -70179,75 +74342,93 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_sub_in_place_32(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SUBS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" - "SBC %[a], r9, r9\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" + "SBC r0, r9, r9\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -70269,76 +74450,95 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_add_32(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADDS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "ADCS r3, r3, r7\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "MOV %[r], #0\n\t" - "ADC %[r], %[r], #0\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "MOV r0, #0\n\t" + "ADC r0, r0, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -70429,47 +74629,66 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_sub_16(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SUBS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "LDM %[a]!, {r3, r4, r5, r6}\n\t" - "LDM %[b]!, {r7, r8, r9, r10}\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "LDM r1!, {r3, r4, r5, r6}\n\t" + "LDM r2!, {r7, r8, r9, r10}\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" - "STM %[r]!, {r3, r4, r5, r6}\n\t" - "SBC %[r], r6, r6\n\t" + "STM r0!, {r3, r4, r5, r6}\n\t" + "SBC r0, r6, r6\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -70528,12 +74747,20 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_32(sp_digit* r, const sp_digit* a, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x100\n\t" - "LDR lr, [%[a]]\n\t" - "LDR r11, [%[b]]\n\t" + "LDR lr, [r1]\n\t" + "LDR r11, [r2]\n\t" "UMULL r8, r6, lr, r11\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -70555,14 +74782,14 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_32(sp_digit* r, const sp_digit* a, #else "L_sp_1024_mul_32_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" "ADC r8, r8, #0\n\t" - "LDR lr, [%[a], r4]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r4]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -70584,8 +74811,8 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_32(sp_digit* r, const sp_digit* a, #else "BLT.N L_sp_1024_mul_32_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[b], r3]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r2, r3]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -70609,8 +74836,8 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_32(sp_digit* r, const sp_digit* a, #else "BLE.N L_sp_1024_mul_32_outer_%=\n\t" #endif - "LDR lr, [%[a], #124]\n\t" - "LDR r11, [%[b], #124]\n\t" + "LDR lr, [r1, #124]\n\t" + "LDR r11, [r2, #124]\n\t" "UMLAL r6, r7, lr, r11\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -70622,7 +74849,7 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_32(sp_digit* r, const sp_digit* a, "L_sp_1024_mul_32_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_1024_mul_32_store_%=\n\t" @@ -70631,16 +74858,27 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_32(sp_digit* r, const sp_digit* a, #else "BGT.N L_sp_1024_mul_32_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Square a and put result in r. (r = a * a) @@ -70658,11 +74896,19 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_32(sp_digit* r, const sp_digit* a) #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "SUB sp, sp, #0x100\n\t" - "LDR lr, [%[a]]\n\t" + "LDR lr, [r1]\n\t" "UMULL r8, r6, lr, lr\n\t" "STR r8, [sp]\n\t" "MOV r7, #0\n\t" @@ -70684,8 +74930,8 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_32(sp_digit* r, const sp_digit* a) #else "L_sp_1024_sqr_32_inner_%=:\n\t" #endif - "LDR lr, [%[a], r3]\n\t" - "LDR r11, [%[a], r4]\n\t" + "LDR lr, [r1, r3]\n\t" + "LDR r11, [r1, r4]\n\t" "UMULL r9, r10, lr, r11\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -70710,7 +74956,7 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_32(sp_digit* r, const sp_digit* a) #else "BLT.N L_sp_1024_sqr_32_inner_%=\n\t" #endif - "LDR lr, [%[a], r3]\n\t" + "LDR lr, [r1, r3]\n\t" "UMULL r9, r10, lr, lr\n\t" "ADDS r6, r6, r9\n\t" "ADCS r7, r7, r10\n\t" @@ -70734,7 +74980,7 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_32(sp_digit* r, const sp_digit* a) #else "BLE.N L_sp_1024_sqr_32_outer_%=\n\t" #endif - "LDR lr, [%[a], #124]\n\t" + "LDR lr, [r1, #124]\n\t" "UMLAL r6, r7, lr, lr\n\t" "STR r6, [sp, r5]\n\t" "ADD r5, r5, #4\n\t" @@ -70746,7 +74992,7 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_32(sp_digit* r, const sp_digit* a) "L_sp_1024_sqr_32_store_%=:\n\t" #endif "LDM sp!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" - "STM %[r]!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r3, r4, r6, r7, r8, r9, r10, r11}\n\t" "SUBS r5, r5, #32\n\t" #if defined(__GNUC__) "BGT L_sp_1024_sqr_32_store_%=\n\t" @@ -70755,16 +75001,26 @@ WC_OMIT_FRAME_POINTER static void sp_1024_sqr_32(sp_digit* r, const sp_digit* a) #else "BGT.N L_sp_1024_sqr_32_store_%=\n\t" #endif +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* !WOLFSSL_SP_SMALL */ @@ -70870,11 +75126,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_sub_in_place_32(sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "ADD r11, %[a], #0x80\n\t" + "ADD r11, r0, #0x80\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_1024_sub_in_place_32_word:\n\t" @@ -70882,15 +75146,15 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_sub_in_place_32(sp_digit* a, "L_sp_1024_sub_in_place_32_word_%=:\n\t" #endif "RSBS r10, r10, #0\n\t" - "LDM %[a], {r2, r3, r4, r5}\n\t" - "LDM %[b]!, {r6, r7, r8, r9}\n\t" + "LDM r0, {r2, r3, r4, r5}\n\t" + "LDM r1!, {r6, r7, r8, r9}\n\t" "SBCS r2, r2, r6\n\t" "SBCS r3, r3, r7\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" - "STM %[a]!, {r2, r3, r4, r5}\n\t" + "STM r0!, {r2, r3, r4, r5}\n\t" "SBC r10, r10, r10\n\t" - "CMP %[a], r11\n\t" + "CMP r0, r11\n\t" #if defined(__GNUC__) "BNE L_sp_1024_sub_in_place_32_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -70898,17 +75162,27 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_sub_in_place_32(sp_digit* a, #else "BNE.N L_sp_1024_sub_in_place_32_word_%=\n\t" #endif - "MOV %[a], r10\n\t" + "MOV r0, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -70936,9 +75210,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_cond_sub_32(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r8, #0\n\t" "MOV r4, #0\n\t" "MOV r5, #0\n\t" @@ -70949,12 +75232,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_cond_sub_32(sp_digit* r, "L_sp_1024_cond_sub_32_words_%=:\n\t" #endif "SUBS r4, r8, r4\n\t" - "LDR r6, [%[a], r5]\n\t" - "LDR r7, [%[b], r5]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r5]\n\t" + "LDR r7, [r2, r5]\n\t" + "AND r7, r7, r3\n\t" "SBCS r6, r6, r7\n\t" "SBC r4, r8, r8\n\t" - "STR r6, [%[r], r5]\n\t" + "STR r6, [r0, r5]\n\t" "ADD r5, r5, #4\n\t" "CMP r5, #0x80\n\t" #if defined(__GNUC__) @@ -70964,16 +75247,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_cond_sub_32(sp_digit* r, #else "BLT.N L_sp_1024_cond_sub_32_words_%=\n\t" #endif - "MOV %[r], r4\n\t" + "MOV r0, r4\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -71000,132 +75295,153 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_cond_sub_32(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SUBS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "SBCS r6, r6, r8\n\t" "SBCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "SBC %[r], r5, r5\n\t" + "STM r0!, {r6, r7}\n\t" + "SBC r0, r5, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -71149,11 +75465,19 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_add_32(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r3, #0\n\t" - "ADD r12, %[a], #0x80\n\t" + "ADD r12, r1, #0x80\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_1024_add_32_word:\n\t" @@ -71161,16 +75485,16 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_add_32(sp_digit* r, "L_sp_1024_add_32_word_%=:\n\t" #endif "ADDS r3, r3, #0xffffffff\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "MOV r4, #0\n\t" "ADC r3, r4, #0\n\t" - "CMP %[a], r12\n\t" + "CMP r1, r12\n\t" #if defined(__GNUC__) "BNE L_sp_1024_add_32_word_%=\n\t" #elif defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) @@ -71178,17 +75502,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_add_32(sp_digit* r, #else "BNE.N L_sp_1024_add_32_word_%=\n\t" #endif - "MOV %[r], r3\n\t" + "MOV r0, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r3", "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r3", "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -71212,14 +75547,22 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_d_32(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDR r8, [%[a]]\n\t" - "UMULL r5, r3, %[b], r8\n\t" + "LDR r8, [r1]\n\t" + "UMULL r5, r3, r2, r8\n\t" "MOV r4, #0\n\t" - "STR r5, [%[r]]\n\t" + "STR r5, [r0]\n\t" "MOV r5, #0\n\t" "MOV r9, #4\n\t" "\n" @@ -71229,12 +75572,12 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_d_32(sp_digit* r, "L_sp_1024_mul_d_32_word_%=:\n\t" #endif /* A[i] * B */ - "LDR r8, [%[a], r9]\n\t" - "UMULL r6, r7, %[b], r8\n\t" + "LDR r8, [r1, r9]\n\t" + "UMULL r6, r7, r2, r8\n\t" "ADDS r3, r3, r6\n\t" "ADCS r4, r4, r7\n\t" "ADC r5, r5, #0\n\t" - "STR r3, [%[r], r9]\n\t" + "STR r3, [r0, r9]\n\t" "MOV r3, r4\n\t" "MOV r4, r5\n\t" "MOV r5, #0\n\t" @@ -71247,16 +75590,27 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_d_32(sp_digit* r, #else "BLT.N L_sp_1024_mul_d_32_word_%=\n\t" #endif - "STR r3, [%[r], #128]\n\t" + "STR r3, [r0, #128]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #else @@ -71278,178 +75632,197 @@ WC_OMIT_FRAME_POINTER static void sp_1024_mul_d_32(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register sp_digit b __asm__ ("r2") = (sp_digit)b_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* A[0] * B */ - "LDM %[a]!, {r8}\n\t" - "UMULL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMULL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[1] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[2] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[3] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[4] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[5] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[6] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[7] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[8] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[9] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[10] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[11] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[12] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[13] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[14] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[15] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[16] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[17] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[18] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[19] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[20] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[21] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[22] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[23] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[24] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[25] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[26] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[27] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[28] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" "MOV r3, #0\n\t" /* A[29] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r5, r3, %[b], r8\n\t" - "STM %[r]!, {r5}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r5, r3, r2, r8\n\t" + "STM r0!, {r5}\n\t" "MOV r4, #0\n\t" /* A[30] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r3, r4, %[b], r8\n\t" - "STM %[r]!, {r3}\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r3, r4, r2, r8\n\t" + "STM r0!, {r3}\n\t" "MOV r5, #0\n\t" /* A[31] * B */ - "LDM %[a]!, {r8}\n\t" - "UMLAL r4, r5, %[b], r8\n\t" - "STM %[r]!, {r4}\n\t" - "STR r5, [%[r]]\n\t" + "LDM r1!, {r8}\n\t" + "UMLAL r4, r5, r2, r8\n\t" + "STM r0!, {r4}\n\t" + "STR r5, [r0]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #endif /* WOLFSSL_SP_SMALL */ @@ -71476,53 +75849,73 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_1024_word_32(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r8, %[div], #16\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r8, r2, #16\n\t" "ADD r5, r8, #1\n\t" - "UDIV r6, %[d1], r5\n\t" - "LSL r7, %[div], #16\n\t" + "UDIV r6, r0, r5\n\t" + "LSL r7, r2, #16\n\t" "LSL r6, r6, #16\n\t" - "UMULL r3, r4, %[div], r6\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "SUBS r3, %[d1], r5\n\t" + "UMULL r3, r4, r2, r6\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "SUBS r3, r0, r5\n\t" "SBC r9, r9, r9\n\t" "ADD r9, r9, #1\n\t" "RSB r10, r9, #0\n\t" "LSL r9, r9, #16\n\t" "AND r7, r7, r10\n\t" "AND r8, r8, r10\n\t" - "SUBS %[d0], %[d0], r7\n\t" + "SUBS r1, r1, r7\n\t" "ADD r6, r6, r9\n\t" - "SBC %[d1], %[d1], r8\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "SBC r0, r0, r8\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "UMULL r3, r4, %[div], r3\n\t" - "SUBS %[d0], %[d0], r3\n\t" - "SBC %[d1], %[d1], r4\n\t" - "LSL r4, %[d1], #16\n\t" - "LSR r3, %[d0], #16\n\t" + "UMULL r3, r4, r2, r3\n\t" + "SUBS r1, r1, r3\n\t" + "SBC r0, r0, r4\n\t" + "LSL r4, r0, #16\n\t" + "LSR r3, r1, #16\n\t" "ORR r3, r3, r4\n\t" "UDIV r3, r3, r5\n\t" "ADD r6, r6, r3\n\t" - "MUL r3, %[div], r3\n\t" - "SUB %[d0], %[d0], r3\n\t" - "UDIV r3, %[d0], %[div]\n\t" - "ADD %[d1], r6, r3\n\t" + "MUL r3, r2, r3\n\t" + "SUB r1, r1, r3\n\t" + "UDIV r3, r1, r2\n\t" + "ADD r0, r6, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -71549,13 +75942,22 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_1024_word_32(sp_digit d1, register sp_digit d1 __asm__ ("r0") = (sp_digit)d1_p; register sp_digit d0 __asm__ ("r1") = (sp_digit)d0_p; register sp_digit div __asm__ ("r2") = (sp_digit)div_p; +#else + void* L_asm_args[3] = {(void*)(size_t)d1, (void*)(size_t)d0, + (void*)(size_t)div + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LSR r5, %[div], #1\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LSR r5, r2, #1\n\t" "ADD r5, r5, #1\n\t" - "MOV r6, %[d0]\n\t" - "MOV r7, %[d1]\n\t" + "MOV r6, r1\n\t" + "MOV r7, r0\n\t" /* Do top 32 */ "SUBS r8, r5, r7\n\t" "SBC r8, r8, r8\n\t" @@ -71589,29 +75991,40 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE sp_digit div_1024_word_32(sp_digit d1, #endif "ADD r3, r3, r3\n\t" "ADD r3, r3, #1\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "UMULL r6, r7, r3, %[div]\n\t" - "SUBS r9, %[d0], r6\n\t" - "SBC r10, %[d1], r7\n\t" + "UMULL r6, r7, r3, r2\n\t" + "SUBS r9, r1, r6\n\t" + "SBC r10, r0, r7\n\t" "ADD r3, r3, r10\n\t" - "SUBS r8, r9, %[div]\n\t" - "ADC %[d1], r3, #0\n\t" + "SUBS r8, r9, r2\n\t" + "ADC r0, r3, #0\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [d1] "+r" (d1), [d0] "+r" (d0), [div] "+r" (div) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [d1] "r" (d1), [d0] "r" (d0), [div] "r" (div) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + d1 = (sp_digit)(size_t)L_asm_args[0]; + d0 = (sp_digit)(size_t)L_asm_args[1]; + div = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)d1; } @@ -71665,9 +76078,17 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register const sp_digit* a __asm__ ("r0") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r1") = (const sp_digit*)b_p; +#else + void* L_asm_args[2] = {(void*)(size_t)a, (void*)(size_t)b + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r2, #0xffffffff\n\t" "MOV r8, #1\n\t" "MOV r7, #0\n\t" @@ -71680,8 +76101,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, #else "L_sp_1024_cmp_32_words_%=:\n\t" #endif - "LDR r4, [%[a], r6]\n\t" - "LDR r5, [%[b], r6]\n\t" + "LDR r4, [r0, r6]\n\t" + "LDR r5, [r1, r6]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71699,8 +76120,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, #endif "EOR r2, r2, r3\n\t" #else - "LDR r4, [%[a], #124]\n\t" - "LDR r5, [%[b], #124]\n\t" + "LDR r4, [r0, #124]\n\t" + "LDR r5, [r1, #124]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71710,8 +76131,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #120]\n\t" - "LDR r5, [%[b], #120]\n\t" + "LDR r4, [r0, #120]\n\t" + "LDR r5, [r1, #120]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71721,8 +76142,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #116]\n\t" - "LDR r5, [%[b], #116]\n\t" + "LDR r4, [r0, #116]\n\t" + "LDR r5, [r1, #116]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71732,8 +76153,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #112]\n\t" - "LDR r5, [%[b], #112]\n\t" + "LDR r4, [r0, #112]\n\t" + "LDR r5, [r1, #112]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71743,8 +76164,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #108]\n\t" - "LDR r5, [%[b], #108]\n\t" + "LDR r4, [r0, #108]\n\t" + "LDR r5, [r1, #108]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71754,8 +76175,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #104]\n\t" - "LDR r5, [%[b], #104]\n\t" + "LDR r4, [r0, #104]\n\t" + "LDR r5, [r1, #104]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71765,8 +76186,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #100]\n\t" - "LDR r5, [%[b], #100]\n\t" + "LDR r4, [r0, #100]\n\t" + "LDR r5, [r1, #100]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71776,8 +76197,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #96]\n\t" - "LDR r5, [%[b], #96]\n\t" + "LDR r4, [r0, #96]\n\t" + "LDR r5, [r1, #96]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71787,8 +76208,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #92]\n\t" - "LDR r5, [%[b], #92]\n\t" + "LDR r4, [r0, #92]\n\t" + "LDR r5, [r1, #92]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71798,8 +76219,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #88]\n\t" - "LDR r5, [%[b], #88]\n\t" + "LDR r4, [r0, #88]\n\t" + "LDR r5, [r1, #88]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71809,8 +76230,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #84]\n\t" - "LDR r5, [%[b], #84]\n\t" + "LDR r4, [r0, #84]\n\t" + "LDR r5, [r1, #84]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71820,8 +76241,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #80]\n\t" - "LDR r5, [%[b], #80]\n\t" + "LDR r4, [r0, #80]\n\t" + "LDR r5, [r1, #80]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71831,8 +76252,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #76]\n\t" - "LDR r5, [%[b], #76]\n\t" + "LDR r4, [r0, #76]\n\t" + "LDR r5, [r1, #76]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71842,8 +76263,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #72]\n\t" - "LDR r5, [%[b], #72]\n\t" + "LDR r4, [r0, #72]\n\t" + "LDR r5, [r1, #72]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71853,8 +76274,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #68]\n\t" - "LDR r5, [%[b], #68]\n\t" + "LDR r4, [r0, #68]\n\t" + "LDR r5, [r1, #68]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71864,8 +76285,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #64]\n\t" - "LDR r5, [%[b], #64]\n\t" + "LDR r4, [r0, #64]\n\t" + "LDR r5, [r1, #64]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71875,8 +76296,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #60]\n\t" - "LDR r5, [%[b], #60]\n\t" + "LDR r4, [r0, #60]\n\t" + "LDR r5, [r1, #60]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71886,8 +76307,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #56]\n\t" - "LDR r5, [%[b], #56]\n\t" + "LDR r4, [r0, #56]\n\t" + "LDR r5, [r1, #56]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71897,8 +76318,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #52]\n\t" - "LDR r5, [%[b], #52]\n\t" + "LDR r4, [r0, #52]\n\t" + "LDR r5, [r1, #52]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71908,8 +76329,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #48]\n\t" - "LDR r5, [%[b], #48]\n\t" + "LDR r4, [r0, #48]\n\t" + "LDR r5, [r1, #48]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71919,8 +76340,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #44]\n\t" - "LDR r5, [%[b], #44]\n\t" + "LDR r4, [r0, #44]\n\t" + "LDR r5, [r1, #44]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71930,8 +76351,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #40]\n\t" - "LDR r5, [%[b], #40]\n\t" + "LDR r4, [r0, #40]\n\t" + "LDR r5, [r1, #40]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71941,8 +76362,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #36]\n\t" - "LDR r5, [%[b], #36]\n\t" + "LDR r4, [r0, #36]\n\t" + "LDR r5, [r1, #36]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71952,8 +76373,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #32]\n\t" - "LDR r5, [%[b], #32]\n\t" + "LDR r4, [r0, #32]\n\t" + "LDR r5, [r1, #32]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71963,8 +76384,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #28]\n\t" - "LDR r5, [%[b], #28]\n\t" + "LDR r4, [r0, #28]\n\t" + "LDR r5, [r1, #28]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71974,8 +76395,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #24]\n\t" - "LDR r5, [%[b], #24]\n\t" + "LDR r4, [r0, #24]\n\t" + "LDR r5, [r1, #24]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71985,8 +76406,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #20]\n\t" - "LDR r5, [%[b], #20]\n\t" + "LDR r4, [r0, #20]\n\t" + "LDR r5, [r1, #20]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -71996,8 +76417,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #16]\n\t" - "LDR r5, [%[b], #16]\n\t" + "LDR r4, [r0, #16]\n\t" + "LDR r5, [r1, #16]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -72007,8 +76428,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #12]\n\t" - "LDR r5, [%[b], #12]\n\t" + "LDR r4, [r0, #12]\n\t" + "LDR r5, [r1, #12]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -72018,8 +76439,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #8]\n\t" - "LDR r5, [%[b], #8]\n\t" + "LDR r4, [r0, #8]\n\t" + "LDR r5, [r1, #8]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -72029,8 +76450,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a], #4]\n\t" - "LDR r5, [%[b], #4]\n\t" + "LDR r4, [r0, #4]\n\t" + "LDR r5, [r1, #4]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -72040,8 +76461,8 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movlo r2, r3\n\t" "IT ne\n\t" "movne r3, r7\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[b]]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r1]\n\t" "AND r4, r4, r3\n\t" "AND r5, r5, r3\n\t" "SUBS r4, r4, r5\n\t" @@ -72053,16 +76474,26 @@ WC_OMIT_FRAME_POINTER static sp_int32 sp_1024_cmp_32(const sp_digit* a, "movne r3, r7\n\t" "EOR r2, r2, r3\n\t" #endif /*WOLFSSL_SP_SMALL */ - "MOV %[a], r2\n\t" + "MOV r0, r2\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [b] "+r" (b) : + : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [b] "r" (b) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (const sp_digit*)(size_t)L_asm_args[0]; + b = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)a; } @@ -72421,15 +76852,24 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_reduce_32( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDR lr, [%[m]]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDR lr, [r1]\n\t" /* i = 0 */ "MOV r11, #0\n\t" "MOV r3, #0\n\t" - "LDR r4, [%[a]]\n\t" - "LDR r5, [%[a], #4]\n\t" + "LDR r4, [r0]\n\t" + "LDR r5, [r0, #4]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_1024_mont_reduce_32_word:\n\t" @@ -72437,265 +76877,265 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_reduce_32( "L_sp_1024_mont_reduce_32_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL r10, %[mp], r4\n\t" + "MUL r10, r2, r4\n\t" /* a[i+0] += m[0] * mu */ "MOV r7, #0\n\t" "UMLAL r4, r7, r10, lr\n\t" /* a[i+1] += m[1] * mu */ - "LDR r9, [%[m], #4]\n\t" + "LDR r9, [r1, #4]\n\t" "MOV r6, #0\n\t" "UMLAL r5, r6, r10, r9\n\t" "MOV r4, r5\n\t" "ADDS r4, r4, r7\n\t" "ADC r6, r6, #0\n\t" /* a[i+2] += m[2] * mu */ - "LDR r9, [%[m], #8]\n\t" - "LDR r5, [%[a], #8]\n\t" + "LDR r9, [r1, #8]\n\t" + "LDR r5, [r0, #8]\n\t" "MOV r7, #0\n\t" "UMLAL r5, r7, r10, r9\n\t" "ADDS r5, r5, r6\n\t" "ADC r7, r7, #0\n\t" /* a[i+3] += m[3] * mu */ - "LDR r9, [%[m], #12]\n\t" - "LDR r12, [%[a], #12]\n\t" + "LDR r9, [r1, #12]\n\t" + "LDR r12, [r0, #12]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #12]\n\t" + "STR r12, [r0, #12]\n\t" "ADC r6, r6, #0\n\t" /* a[i+4] += m[4] * mu */ - "LDR r9, [%[m], #16]\n\t" - "LDR r12, [%[a], #16]\n\t" + "LDR r9, [r1, #16]\n\t" + "LDR r12, [r0, #16]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #16]\n\t" + "STR r12, [r0, #16]\n\t" "ADC r7, r7, #0\n\t" /* a[i+5] += m[5] * mu */ - "LDR r9, [%[m], #20]\n\t" - "LDR r12, [%[a], #20]\n\t" + "LDR r9, [r1, #20]\n\t" + "LDR r12, [r0, #20]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #20]\n\t" + "STR r12, [r0, #20]\n\t" "ADC r6, r6, #0\n\t" /* a[i+6] += m[6] * mu */ - "LDR r9, [%[m], #24]\n\t" - "LDR r12, [%[a], #24]\n\t" + "LDR r9, [r1, #24]\n\t" + "LDR r12, [r0, #24]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #24]\n\t" + "STR r12, [r0, #24]\n\t" "ADC r7, r7, #0\n\t" /* a[i+7] += m[7] * mu */ - "LDR r9, [%[m], #28]\n\t" - "LDR r12, [%[a], #28]\n\t" + "LDR r9, [r1, #28]\n\t" + "LDR r12, [r0, #28]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #28]\n\t" + "STR r12, [r0, #28]\n\t" "ADC r6, r6, #0\n\t" /* a[i+8] += m[8] * mu */ - "LDR r9, [%[m], #32]\n\t" - "LDR r12, [%[a], #32]\n\t" + "LDR r9, [r1, #32]\n\t" + "LDR r12, [r0, #32]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #32]\n\t" + "STR r12, [r0, #32]\n\t" "ADC r7, r7, #0\n\t" /* a[i+9] += m[9] * mu */ - "LDR r9, [%[m], #36]\n\t" - "LDR r12, [%[a], #36]\n\t" + "LDR r9, [r1, #36]\n\t" + "LDR r12, [r0, #36]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #36]\n\t" + "STR r12, [r0, #36]\n\t" "ADC r6, r6, #0\n\t" /* a[i+10] += m[10] * mu */ - "LDR r9, [%[m], #40]\n\t" - "LDR r12, [%[a], #40]\n\t" + "LDR r9, [r1, #40]\n\t" + "LDR r12, [r0, #40]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #40]\n\t" + "STR r12, [r0, #40]\n\t" "ADC r7, r7, #0\n\t" /* a[i+11] += m[11] * mu */ - "LDR r9, [%[m], #44]\n\t" - "LDR r12, [%[a], #44]\n\t" + "LDR r9, [r1, #44]\n\t" + "LDR r12, [r0, #44]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #44]\n\t" + "STR r12, [r0, #44]\n\t" "ADC r6, r6, #0\n\t" /* a[i+12] += m[12] * mu */ - "LDR r9, [%[m], #48]\n\t" - "LDR r12, [%[a], #48]\n\t" + "LDR r9, [r1, #48]\n\t" + "LDR r12, [r0, #48]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #48]\n\t" + "STR r12, [r0, #48]\n\t" "ADC r7, r7, #0\n\t" /* a[i+13] += m[13] * mu */ - "LDR r9, [%[m], #52]\n\t" - "LDR r12, [%[a], #52]\n\t" + "LDR r9, [r1, #52]\n\t" + "LDR r12, [r0, #52]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #52]\n\t" + "STR r12, [r0, #52]\n\t" "ADC r6, r6, #0\n\t" /* a[i+14] += m[14] * mu */ - "LDR r9, [%[m], #56]\n\t" - "LDR r12, [%[a], #56]\n\t" + "LDR r9, [r1, #56]\n\t" + "LDR r12, [r0, #56]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #56]\n\t" + "STR r12, [r0, #56]\n\t" "ADC r7, r7, #0\n\t" /* a[i+15] += m[15] * mu */ - "LDR r9, [%[m], #60]\n\t" - "LDR r12, [%[a], #60]\n\t" + "LDR r9, [r1, #60]\n\t" + "LDR r12, [r0, #60]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #60]\n\t" + "STR r12, [r0, #60]\n\t" "ADC r6, r6, #0\n\t" /* a[i+16] += m[16] * mu */ - "LDR r9, [%[m], #64]\n\t" - "LDR r12, [%[a], #64]\n\t" + "LDR r9, [r1, #64]\n\t" + "LDR r12, [r0, #64]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #64]\n\t" + "STR r12, [r0, #64]\n\t" "ADC r7, r7, #0\n\t" /* a[i+17] += m[17] * mu */ - "LDR r9, [%[m], #68]\n\t" - "LDR r12, [%[a], #68]\n\t" + "LDR r9, [r1, #68]\n\t" + "LDR r12, [r0, #68]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #68]\n\t" + "STR r12, [r0, #68]\n\t" "ADC r6, r6, #0\n\t" /* a[i+18] += m[18] * mu */ - "LDR r9, [%[m], #72]\n\t" - "LDR r12, [%[a], #72]\n\t" + "LDR r9, [r1, #72]\n\t" + "LDR r12, [r0, #72]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #72]\n\t" + "STR r12, [r0, #72]\n\t" "ADC r7, r7, #0\n\t" /* a[i+19] += m[19] * mu */ - "LDR r9, [%[m], #76]\n\t" - "LDR r12, [%[a], #76]\n\t" + "LDR r9, [r1, #76]\n\t" + "LDR r12, [r0, #76]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #76]\n\t" + "STR r12, [r0, #76]\n\t" "ADC r6, r6, #0\n\t" /* a[i+20] += m[20] * mu */ - "LDR r9, [%[m], #80]\n\t" - "LDR r12, [%[a], #80]\n\t" + "LDR r9, [r1, #80]\n\t" + "LDR r12, [r0, #80]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #80]\n\t" + "STR r12, [r0, #80]\n\t" "ADC r7, r7, #0\n\t" /* a[i+21] += m[21] * mu */ - "LDR r9, [%[m], #84]\n\t" - "LDR r12, [%[a], #84]\n\t" + "LDR r9, [r1, #84]\n\t" + "LDR r12, [r0, #84]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #84]\n\t" + "STR r12, [r0, #84]\n\t" "ADC r6, r6, #0\n\t" /* a[i+22] += m[22] * mu */ - "LDR r9, [%[m], #88]\n\t" - "LDR r12, [%[a], #88]\n\t" + "LDR r9, [r1, #88]\n\t" + "LDR r12, [r0, #88]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #88]\n\t" + "STR r12, [r0, #88]\n\t" "ADC r7, r7, #0\n\t" /* a[i+23] += m[23] * mu */ - "LDR r9, [%[m], #92]\n\t" - "LDR r12, [%[a], #92]\n\t" + "LDR r9, [r1, #92]\n\t" + "LDR r12, [r0, #92]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #92]\n\t" + "STR r12, [r0, #92]\n\t" "ADC r6, r6, #0\n\t" /* a[i+24] += m[24] * mu */ - "LDR r9, [%[m], #96]\n\t" - "LDR r12, [%[a], #96]\n\t" + "LDR r9, [r1, #96]\n\t" + "LDR r12, [r0, #96]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #96]\n\t" + "STR r12, [r0, #96]\n\t" "ADC r7, r7, #0\n\t" /* a[i+25] += m[25] * mu */ - "LDR r9, [%[m], #100]\n\t" - "LDR r12, [%[a], #100]\n\t" + "LDR r9, [r1, #100]\n\t" + "LDR r12, [r0, #100]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #100]\n\t" + "STR r12, [r0, #100]\n\t" "ADC r6, r6, #0\n\t" /* a[i+26] += m[26] * mu */ - "LDR r9, [%[m], #104]\n\t" - "LDR r12, [%[a], #104]\n\t" + "LDR r9, [r1, #104]\n\t" + "LDR r12, [r0, #104]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #104]\n\t" + "STR r12, [r0, #104]\n\t" "ADC r7, r7, #0\n\t" /* a[i+27] += m[27] * mu */ - "LDR r9, [%[m], #108]\n\t" - "LDR r12, [%[a], #108]\n\t" + "LDR r9, [r1, #108]\n\t" + "LDR r12, [r0, #108]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #108]\n\t" + "STR r12, [r0, #108]\n\t" "ADC r6, r6, #0\n\t" /* a[i+28] += m[28] * mu */ - "LDR r9, [%[m], #112]\n\t" - "LDR r12, [%[a], #112]\n\t" + "LDR r9, [r1, #112]\n\t" + "LDR r12, [r0, #112]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #112]\n\t" + "STR r12, [r0, #112]\n\t" "ADC r7, r7, #0\n\t" /* a[i+29] += m[29] * mu */ - "LDR r9, [%[m], #116]\n\t" - "LDR r12, [%[a], #116]\n\t" + "LDR r9, [r1, #116]\n\t" + "LDR r12, [r0, #116]\n\t" "MOV r6, #0\n\t" "UMLAL r12, r6, r10, r9\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #116]\n\t" + "STR r12, [r0, #116]\n\t" "ADC r6, r6, #0\n\t" /* a[i+30] += m[30] * mu */ - "LDR r9, [%[m], #120]\n\t" - "LDR r12, [%[a], #120]\n\t" + "LDR r9, [r1, #120]\n\t" + "LDR r12, [r0, #120]\n\t" "MOV r7, #0\n\t" "UMLAL r12, r7, r10, r9\n\t" "ADDS r12, r12, r6\n\t" - "STR r12, [%[a], #120]\n\t" + "STR r12, [r0, #120]\n\t" "ADC r7, r7, #0\n\t" /* a[i+31] += m[31] * mu */ - "LDR r9, [%[m], #124]\n\t" - "LDR r12, [%[a], #124]\n\t" + "LDR r9, [r1, #124]\n\t" + "LDR r12, [r0, #124]\n\t" "UMULL r8, r9, r10, r9\n\t" "ADDS r7, r7, r8\n\t" "ADCS r6, r9, r3\n\t" "MOV r3, #0\n\t" "ADC r3, r3, r3\n\t" "ADDS r12, r12, r7\n\t" - "STR r12, [%[a], #124]\n\t" - "LDR r12, [%[a], #128]\n\t" + "STR r12, [r0, #124]\n\t" + "LDR r12, [r0, #128]\n\t" "ADCS r12, r12, r6\n\t" - "STR r12, [%[a], #128]\n\t" + "STR r12, [r0, #128]\n\t" "ADC r3, r3, #0\n\t" /* i += 1 */ "ADD r11, r11, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r11, #0x80\n\t" #if defined(__GNUC__) "BLT L_sp_1024_mont_reduce_32_word_%=\n\t" @@ -72705,24 +77145,35 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_reduce_32( "BLT.W L_sp_1024_mont_reduce_32_word_%=\n\t" #endif /* Loop Done */ - "STR r4, [%[a]]\n\t" - "STR r5, [%[a], #4]\n\t" - "LDR r8, [%[m], #124]\n\t" + "STR r4, [r0]\n\t" + "STR r5, [r0, #4]\n\t" + "LDR r8, [r1, #124]\n\t" "SUBS r12, r8, r12\n\t" "neg r3, r3\n\t" "SBC r12, r12, r12\n\t" "ORR r3, r3, r12\n\t" - "MOV %[mp], r3\n\t" + "MOV r2, r3\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_1024_cond_sub_32(a - 32, a, m, mp); } @@ -72746,17 +77197,26 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_reduce_32( register sp_digit* a __asm__ ("r0") = (sp_digit*)a_p; register const sp_digit* m __asm__ ("r1") = (const sp_digit*)m_p; register sp_digit mp __asm__ ("r2") = (sp_digit)mp_p; +#else + void* L_asm_args[3] = {(void*)(size_t)a, (void*)(size_t)m, + (void*)(size_t)mp + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ /* i = 0 */ "MOV r4, #0\n\t" "MOV r5, #0\n\t" - "LDR r6, [%[a]]\n\t" - "LDR r7, [%[a], #4]\n\t" - "LDR r8, [%[a], #8]\n\t" - "LDR r9, [%[a], #12]\n\t" - "LDR r10, [%[a], #16]\n\t" + "LDR r6, [r0]\n\t" + "LDR r7, [r0, #4]\n\t" + "LDR r8, [r0, #8]\n\t" + "LDR r9, [r0, #12]\n\t" + "LDR r10, [r0, #16]\n\t" "\n" #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ < 9000000) "L_sp_1024_mont_reduce_32_word:\n\t" @@ -72764,170 +77224,170 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_reduce_32( "L_sp_1024_mont_reduce_32_word_%=:\n\t" #endif /* mu = a[i] * mp */ - "MUL lr, %[mp], r6\n\t" + "MUL lr, r2, r6\n\t" /* a[i+0] += m[0] * mu */ - "LDR r12, [%[m]]\n\t" + "LDR r12, [r1]\n\t" "MOV r3, #0\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+1] += m[1] * mu */ - "LDR r12, [%[m], #4]\n\t" + "LDR r12, [r1, #4]\n\t" "MOV r6, r7\n\t" "UMAAL r6, r3, lr, r12\n\t" /* a[i+2] += m[2] * mu */ - "LDR r12, [%[m], #8]\n\t" + "LDR r12, [r1, #8]\n\t" "MOV r7, r8\n\t" "UMAAL r7, r3, lr, r12\n\t" /* a[i+3] += m[3] * mu */ - "LDR r12, [%[m], #12]\n\t" + "LDR r12, [r1, #12]\n\t" "MOV r8, r9\n\t" "UMAAL r8, r3, lr, r12\n\t" /* a[i+4] += m[4] * mu */ - "LDR r12, [%[m], #16]\n\t" + "LDR r12, [r1, #16]\n\t" "MOV r9, r10\n\t" "UMAAL r9, r3, lr, r12\n\t" /* a[i+5] += m[5] * mu */ - "LDR r12, [%[m], #20]\n\t" - "LDR r10, [%[a], #20]\n\t" + "LDR r12, [r1, #20]\n\t" + "LDR r10, [r0, #20]\n\t" "UMAAL r10, r3, lr, r12\n\t" /* a[i+6] += m[6] * mu */ - "LDR r12, [%[m], #24]\n\t" - "LDR r11, [%[a], #24]\n\t" + "LDR r12, [r1, #24]\n\t" + "LDR r11, [r0, #24]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #24]\n\t" + "STR r11, [r0, #24]\n\t" /* a[i+7] += m[7] * mu */ - "LDR r12, [%[m], #28]\n\t" - "LDR r11, [%[a], #28]\n\t" + "LDR r12, [r1, #28]\n\t" + "LDR r11, [r0, #28]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #28]\n\t" + "STR r11, [r0, #28]\n\t" /* a[i+8] += m[8] * mu */ - "LDR r12, [%[m], #32]\n\t" - "LDR r11, [%[a], #32]\n\t" + "LDR r12, [r1, #32]\n\t" + "LDR r11, [r0, #32]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #32]\n\t" + "STR r11, [r0, #32]\n\t" /* a[i+9] += m[9] * mu */ - "LDR r12, [%[m], #36]\n\t" - "LDR r11, [%[a], #36]\n\t" + "LDR r12, [r1, #36]\n\t" + "LDR r11, [r0, #36]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #36]\n\t" + "STR r11, [r0, #36]\n\t" /* a[i+10] += m[10] * mu */ - "LDR r12, [%[m], #40]\n\t" - "LDR r11, [%[a], #40]\n\t" + "LDR r12, [r1, #40]\n\t" + "LDR r11, [r0, #40]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #40]\n\t" + "STR r11, [r0, #40]\n\t" /* a[i+11] += m[11] * mu */ - "LDR r12, [%[m], #44]\n\t" - "LDR r11, [%[a], #44]\n\t" + "LDR r12, [r1, #44]\n\t" + "LDR r11, [r0, #44]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #44]\n\t" + "STR r11, [r0, #44]\n\t" /* a[i+12] += m[12] * mu */ - "LDR r12, [%[m], #48]\n\t" - "LDR r11, [%[a], #48]\n\t" + "LDR r12, [r1, #48]\n\t" + "LDR r11, [r0, #48]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #48]\n\t" + "STR r11, [r0, #48]\n\t" /* a[i+13] += m[13] * mu */ - "LDR r12, [%[m], #52]\n\t" - "LDR r11, [%[a], #52]\n\t" + "LDR r12, [r1, #52]\n\t" + "LDR r11, [r0, #52]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #52]\n\t" + "STR r11, [r0, #52]\n\t" /* a[i+14] += m[14] * mu */ - "LDR r12, [%[m], #56]\n\t" - "LDR r11, [%[a], #56]\n\t" + "LDR r12, [r1, #56]\n\t" + "LDR r11, [r0, #56]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #56]\n\t" + "STR r11, [r0, #56]\n\t" /* a[i+15] += m[15] * mu */ - "LDR r12, [%[m], #60]\n\t" - "LDR r11, [%[a], #60]\n\t" + "LDR r12, [r1, #60]\n\t" + "LDR r11, [r0, #60]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #60]\n\t" + "STR r11, [r0, #60]\n\t" /* a[i+16] += m[16] * mu */ - "LDR r12, [%[m], #64]\n\t" - "LDR r11, [%[a], #64]\n\t" + "LDR r12, [r1, #64]\n\t" + "LDR r11, [r0, #64]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #64]\n\t" + "STR r11, [r0, #64]\n\t" /* a[i+17] += m[17] * mu */ - "LDR r12, [%[m], #68]\n\t" - "LDR r11, [%[a], #68]\n\t" + "LDR r12, [r1, #68]\n\t" + "LDR r11, [r0, #68]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #68]\n\t" + "STR r11, [r0, #68]\n\t" /* a[i+18] += m[18] * mu */ - "LDR r12, [%[m], #72]\n\t" - "LDR r11, [%[a], #72]\n\t" + "LDR r12, [r1, #72]\n\t" + "LDR r11, [r0, #72]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #72]\n\t" + "STR r11, [r0, #72]\n\t" /* a[i+19] += m[19] * mu */ - "LDR r12, [%[m], #76]\n\t" - "LDR r11, [%[a], #76]\n\t" + "LDR r12, [r1, #76]\n\t" + "LDR r11, [r0, #76]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #76]\n\t" + "STR r11, [r0, #76]\n\t" /* a[i+20] += m[20] * mu */ - "LDR r12, [%[m], #80]\n\t" - "LDR r11, [%[a], #80]\n\t" + "LDR r12, [r1, #80]\n\t" + "LDR r11, [r0, #80]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #80]\n\t" + "STR r11, [r0, #80]\n\t" /* a[i+21] += m[21] * mu */ - "LDR r12, [%[m], #84]\n\t" - "LDR r11, [%[a], #84]\n\t" + "LDR r12, [r1, #84]\n\t" + "LDR r11, [r0, #84]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #84]\n\t" + "STR r11, [r0, #84]\n\t" /* a[i+22] += m[22] * mu */ - "LDR r12, [%[m], #88]\n\t" - "LDR r11, [%[a], #88]\n\t" + "LDR r12, [r1, #88]\n\t" + "LDR r11, [r0, #88]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #88]\n\t" + "STR r11, [r0, #88]\n\t" /* a[i+23] += m[23] * mu */ - "LDR r12, [%[m], #92]\n\t" - "LDR r11, [%[a], #92]\n\t" + "LDR r12, [r1, #92]\n\t" + "LDR r11, [r0, #92]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #92]\n\t" + "STR r11, [r0, #92]\n\t" /* a[i+24] += m[24] * mu */ - "LDR r12, [%[m], #96]\n\t" - "LDR r11, [%[a], #96]\n\t" + "LDR r12, [r1, #96]\n\t" + "LDR r11, [r0, #96]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #96]\n\t" + "STR r11, [r0, #96]\n\t" /* a[i+25] += m[25] * mu */ - "LDR r12, [%[m], #100]\n\t" - "LDR r11, [%[a], #100]\n\t" + "LDR r12, [r1, #100]\n\t" + "LDR r11, [r0, #100]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #100]\n\t" + "STR r11, [r0, #100]\n\t" /* a[i+26] += m[26] * mu */ - "LDR r12, [%[m], #104]\n\t" - "LDR r11, [%[a], #104]\n\t" + "LDR r12, [r1, #104]\n\t" + "LDR r11, [r0, #104]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #104]\n\t" + "STR r11, [r0, #104]\n\t" /* a[i+27] += m[27] * mu */ - "LDR r12, [%[m], #108]\n\t" - "LDR r11, [%[a], #108]\n\t" + "LDR r12, [r1, #108]\n\t" + "LDR r11, [r0, #108]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #108]\n\t" + "STR r11, [r0, #108]\n\t" /* a[i+28] += m[28] * mu */ - "LDR r12, [%[m], #112]\n\t" - "LDR r11, [%[a], #112]\n\t" + "LDR r12, [r1, #112]\n\t" + "LDR r11, [r0, #112]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #112]\n\t" + "STR r11, [r0, #112]\n\t" /* a[i+29] += m[29] * mu */ - "LDR r12, [%[m], #116]\n\t" - "LDR r11, [%[a], #116]\n\t" + "LDR r12, [r1, #116]\n\t" + "LDR r11, [r0, #116]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #116]\n\t" + "STR r11, [r0, #116]\n\t" /* a[i+30] += m[30] * mu */ - "LDR r12, [%[m], #120]\n\t" - "LDR r11, [%[a], #120]\n\t" + "LDR r12, [r1, #120]\n\t" + "LDR r11, [r0, #120]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "STR r11, [%[a], #120]\n\t" + "STR r11, [r0, #120]\n\t" /* a[i+31] += m[31] * mu */ - "LDR r12, [%[m], #124]\n\t" - "LDR r11, [%[a], #124]\n\t" + "LDR r12, [r1, #124]\n\t" + "LDR r11, [r0, #124]\n\t" "UMAAL r11, r3, lr, r12\n\t" - "LDR lr, [%[a], #128]\n\t" + "LDR lr, [r0, #128]\n\t" "MOV r12, #0\n\t" "UMAAL r3, lr, r12, r12\n\t" - "STR r11, [%[a], #124]\n\t" + "STR r11, [r0, #124]\n\t" "ADDS r3, r3, r5\n\t" "ADC r5, lr, #0\n\t" - "STR r3, [%[a], #128]\n\t" + "STR r3, [r0, #128]\n\t" /* i += 1 */ "ADD r4, r4, #4\n\t" - "ADD %[a], %[a], #4\n\t" + "ADD r0, r0, #4\n\t" "CMP r4, #0x80\n\t" #if defined(__GNUC__) "BLT L_sp_1024_mont_reduce_32_word_%=\n\t" @@ -72937,27 +77397,38 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_reduce_32( "BLT.W L_sp_1024_mont_reduce_32_word_%=\n\t" #endif /* Loop Done */ - "STR r6, [%[a]]\n\t" - "STR r7, [%[a], #4]\n\t" - "STR r8, [%[a], #8]\n\t" - "STR r9, [%[a], #12]\n\t" - "STR r10, [%[a], #16]\n\t" - "LDR r12, [%[m], #124]\n\t" + "STR r6, [r0]\n\t" + "STR r7, [r0, #4]\n\t" + "STR r8, [r0, #8]\n\t" + "STR r9, [r0, #12]\n\t" + "STR r10, [r0, #16]\n\t" + "LDR r12, [r1, #124]\n\t" "SUBS r3, r12, r3\n\t" "neg r5, r5\n\t" "SBC r3, r3, r3\n\t" "ORR r5, r5, r3\n\t" - "MOV %[mp], r5\n\t" + "MOV r2, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [a] "+r" (a), [m] "+r" (m), [mp] "+r" (mp) : + : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "lr" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [a] "r" (a), [m] "r" (m), [mp] "r" (mp) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", - "r11", "r12", "lr" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + a = (sp_digit*)(size_t)L_asm_args[0]; + m = (const sp_digit*)(size_t)L_asm_args[1]; + mp = (sp_digit)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ sp_1024_cond_sub_32(a - 32, a, m, mp); } @@ -73119,75 +77590,84 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_add_32(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register const sp_digit* m __asm__ ("r3") = (const sp_digit*)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r12, #0\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADDS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "ADCS r4, r4, r8\n\t" "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDR r11, [%[m], #124]\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDR r11, [r3, #124]\n\t" "ADC r12, r12, #0\n\t" "SUBS r11, r11, r7\n\t" "neg r12, r12\n\t" "SBC r11, r11, r11\n\t" - "SUB %[r], %[r], #0x80\n\t" + "SUB r0, r0, #0x80\n\t" "ORR r12, r12, r11\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73196,9 +77676,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_add_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73207,9 +77687,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_add_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73218,9 +77698,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_add_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73229,9 +77709,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_add_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73240,9 +77720,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_add_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73251,9 +77731,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_add_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73262,9 +77742,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_add_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73273,17 +77753,29 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_add_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBC r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (const sp_digit*)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Double a Montgomery form number (r = a + a % m). @@ -73304,11 +77796,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* m __asm__ ("r2") = (const sp_digit*)m_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r12, #0\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADDS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -73317,8 +77817,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADCS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -73327,8 +77827,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADCS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -73337,8 +77837,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADCS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -73347,16 +77847,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDR r4, [%[m], #124]\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDR r4, [r2, #124]\n\t" "ADC r12, r12, #0\n\t" "SUBS r4, r4, r11\n\t" "neg r12, r12\n\t" "SBC r4, r4, r4\n\t" - "SUB %[r], %[r], #0x80\n\t" + "SUB r0, r0, #0x80\n\t" "ORR r12, r12, r4\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73365,9 +77865,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73376,9 +77876,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73387,9 +77887,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73398,9 +77898,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73409,9 +77909,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73420,9 +77920,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73431,9 +77931,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73442,17 +77942,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_dbl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBC r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [m] "+r" (m) : + : "memory", "cc", "r8", "r9", "r10", "r11", "r4", "r5", "r6", "r7", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r8", "r9", "r10", "r11", "r4", "r5", "r6", "r7", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Triple a Montgomery form number (r = a + a + a % m). @@ -73473,11 +77984,19 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* m __asm__ ("r2") = (const sp_digit*)m_p; +#else + void* L_asm_args[3] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r12, #0\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADDS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -73486,8 +78005,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADCS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -73496,8 +78015,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADCS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -73506,8 +78025,8 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" "ADCS r4, r4, r4\n\t" "ADCS r5, r5, r5\n\t" "ADCS r6, r6, r6\n\t" @@ -73516,16 +78035,16 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "ADCS r9, r9, r9\n\t" "ADCS r10, r10, r10\n\t" "ADCS r11, r11, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" - "LDR r4, [%[m], #124]\n\t" + "STM r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n\t" + "LDR r4, [r2, #124]\n\t" "ADC r12, r12, #0\n\t" "SUBS r4, r4, r11\n\t" "neg r12, r12\n\t" "SBC r4, r4, r4\n\t" - "SUB %[r], %[r], #0x80\n\t" + "SUB r0, r0, #0x80\n\t" "ORR r12, r12, r4\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73534,9 +78053,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73545,9 +78064,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73556,9 +78075,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73567,9 +78086,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73578,9 +78097,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73589,9 +78108,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73600,9 +78119,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73611,76 +78130,76 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBC r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "SUB %[r], %[r], #0x80\n\t" - "SUB %[m], %[m], #0x80\n\t" - "SUB %[a], %[a], #0x80\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "SUB r0, r0, #0x80\n\t" + "SUB r2, r2, #0x80\n\t" + "SUB r1, r1, #0x80\n\t" "MOV r12, #0\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADDS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r8, r9, r10, r11}\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r8, r9, r10, r11}\n\t" "ADCS r8, r8, r4\n\t" "ADCS r9, r9, r5\n\t" "ADCS r10, r10, r6\n\t" "ADCS r11, r11, r7\n\t" - "STM %[r]!, {r8, r9, r10, r11}\n\t" - "LDR r7, [%[m], #124]\n\t" + "STM r0!, {r8, r9, r10, r11}\n\t" + "LDR r7, [r2, #124]\n\t" "ADC r12, r12, #0\n\t" "SUBS r7, r7, r11\n\t" "neg r12, r12\n\t" "SBC r7, r7, r7\n\t" - "SUB %[r], %[r], #0x80\n\t" + "SUB r0, r0, #0x80\n\t" "ORR r12, r12, r7\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73689,9 +78208,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73700,9 +78219,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73711,9 +78230,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73722,9 +78241,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73733,9 +78252,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73744,9 +78263,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73755,9 +78274,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73766,17 +78285,28 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_tpl_32(sp_digit* r, "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBC r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [m] "+r" (m) : + : "memory", "cc", "r8", "r9", "r10", "r11", "r4", "r5", "r6", "r7", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r8", "r9", "r10", "r11", "r4", "r5", "r6", "r7", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + m = (const sp_digit*)(size_t)L_asm_args[2]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Subtract two Montgomery form numbers (r = a - b % m). @@ -73799,69 +78329,78 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_sub_32(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register const sp_digit* m __asm__ ("r3") = (const sp_digit*)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "SUBS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[a]!, {r4, r5, r6, r7}\n\t" - "LDM %[b]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r1!, {r4, r5, r6, r7}\n\t" + "LDM r2!, {r8, r9, r10, r11}\n\t" "SBCS r4, r4, r8\n\t" "SBCS r5, r5, r9\n\t" "SBCS r6, r6, r10\n\t" "SBCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" "SBC r12, r12, r12\n\t" - "SUB %[r], %[r], #0x80\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "SUB r0, r0, #0x80\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73870,9 +78409,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_sub_32(sp_digit* r, "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73881,9 +78420,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_sub_32(sp_digit* r, "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73892,9 +78431,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_sub_32(sp_digit* r, "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73903,9 +78442,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_sub_32(sp_digit* r, "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73914,9 +78453,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_sub_32(sp_digit* r, "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73925,9 +78464,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_sub_32(sp_digit* r, "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73936,9 +78475,9 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_sub_32(sp_digit* r, "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADCS r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" - "LDM %[r], {r4, r5, r6, r7}\n\t" - "LDM %[m]!, {r8, r9, r10, r11}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" + "LDM r0, {r4, r5, r6, r7}\n\t" + "LDM r3!, {r8, r9, r10, r11}\n\t" "AND r8, r8, r12\n\t" "AND r9, r9, r12\n\t" "AND r10, r10, r12\n\t" @@ -73947,17 +78486,29 @@ WC_OMIT_FRAME_POINTER static SP_NOINLINE void sp_1024_mont_sub_32(sp_digit* r, "ADCS r5, r5, r9\n\t" "ADCS r6, r6, r10\n\t" "ADC r7, r7, r11\n\t" - "STM %[r]!, {r4, r5, r6, r7}\n\t" + "STM r0!, {r4, r5, r6, r7}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + "r12" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", - "r12" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (const sp_digit*)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } #ifdef WOLFSSL_SP_SMALL @@ -73983,9 +78534,18 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_cond_add_32(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r5, #0\n\t" "MOV r8, #0\n\t" "MOV r4, #0\n\t" @@ -73996,12 +78556,12 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_cond_add_32(sp_digit* r, "L_sp_1024_cond_add_32_words_%=:\n\t" #endif "ADDS r5, r5, #0xffffffff\n\t" - "LDR r6, [%[a], r4]\n\t" - "LDR r7, [%[b], r4]\n\t" - "AND r7, r7, %[m]\n\t" + "LDR r6, [r1, r4]\n\t" + "LDR r7, [r2, r4]\n\t" + "AND r7, r7, r3\n\t" "ADCS r6, r6, r7\n\t" "ADC r5, r8, r8\n\t" - "STR r6, [%[r], r4]\n\t" + "STR r6, [r0, r4]\n\t" "ADD r4, r4, #4\n\t" "CMP r4, #0x80\n\t" #if defined(__GNUC__) @@ -74011,16 +78571,28 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_cond_add_32(sp_digit* r, #else "BLT.N L_sp_1024_cond_add_32_words_%=\n\t" #endif - "MOV %[r], r5\n\t" + "MOV r0, r5\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -74047,132 +78619,153 @@ WC_OMIT_FRAME_POINTER static sp_digit sp_1024_cond_add_32(sp_digit* r, register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; register const sp_digit* b __asm__ ("r2") = (const sp_digit*)b_p; register sp_digit m __asm__ ("r3") = (sp_digit)m_p; +#else + void* L_asm_args[4] = {(void*)(size_t)r, (void*)(size_t)a, (void*)(size_t)b, + (void*)(size_t)m + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ "MOV r10, #0\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADDS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "LDM %[a]!, {r6, r7}\n\t" - "LDM %[b]!, {r8, r9}\n\t" - "AND r8, r8, %[m]\n\t" - "AND r9, r9, %[m]\n\t" + "STM r0!, {r6, r7}\n\t" + "LDM r1!, {r6, r7}\n\t" + "LDM r2!, {r8, r9}\n\t" + "AND r8, r8, r3\n\t" + "AND r9, r9, r3\n\t" "ADCS r6, r6, r8\n\t" "ADCS r7, r7, r9\n\t" - "STM %[r]!, {r6, r7}\n\t" - "ADC %[r], r10, r10\n\t" + "STM r0!, {r6, r7}\n\t" + "ADC r0, r10, r10\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1, r2, r3}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b), [m] "+r" (m) : + : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a), [b] "r" (b), [m] "r" (m) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r4", "r5", "r6", "r7", "r8", "r9", "r10" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; + b = (const sp_digit*)(size_t)L_asm_args[2]; + m = (sp_digit)(size_t)L_asm_args[3]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ return (word32)(size_t)r; } @@ -74194,144 +78787,162 @@ WC_OMIT_FRAME_POINTER static void sp_1024_rshift1_32(sp_digit* r, #ifndef WOLFSSL_NO_VAR_ASSIGN_REG register sp_digit* r __asm__ ("r0") = (sp_digit*)r_p; register const sp_digit* a __asm__ ("r1") = (const sp_digit*)a_p; +#else + void* L_asm_args[2] = {(void*)(size_t)r, (void*)(size_t)a + }; + void** L_asm_args_p = L_asm_args; #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ __asm__ __volatile__ ( - "LDM %[a], {r2, r3}\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "PUSH {%[L_asm_args]}\n\t" + "LDM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ + "LDM r1, {r2, r3}\n\t" "LSR r2, r2, #1\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #8]\n\t" - "STR r2, [%[r]]\n\t" + "LDR r4, [r1, #8]\n\t" + "STR r2, [r0]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #12]\n\t" - "STR r3, [%[r], #4]\n\t" + "LDR r2, [r1, #12]\n\t" + "STR r3, [r0, #4]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #16]\n\t" - "STR r4, [%[r], #8]\n\t" + "LDR r3, [r1, #16]\n\t" + "STR r4, [r0, #8]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #20]\n\t" - "STR r2, [%[r], #12]\n\t" + "LDR r4, [r1, #20]\n\t" + "STR r2, [r0, #12]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #24]\n\t" - "STR r3, [%[r], #16]\n\t" + "LDR r2, [r1, #24]\n\t" + "STR r3, [r0, #16]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #28]\n\t" - "STR r4, [%[r], #20]\n\t" + "LDR r3, [r1, #28]\n\t" + "STR r4, [r0, #20]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #32]\n\t" - "STR r2, [%[r], #24]\n\t" + "LDR r4, [r1, #32]\n\t" + "STR r2, [r0, #24]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #36]\n\t" - "STR r3, [%[r], #28]\n\t" + "LDR r2, [r1, #36]\n\t" + "STR r3, [r0, #28]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #40]\n\t" - "STR r4, [%[r], #32]\n\t" + "LDR r3, [r1, #40]\n\t" + "STR r4, [r0, #32]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #44]\n\t" - "STR r2, [%[r], #36]\n\t" + "LDR r4, [r1, #44]\n\t" + "STR r2, [r0, #36]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #48]\n\t" - "STR r3, [%[r], #40]\n\t" + "LDR r2, [r1, #48]\n\t" + "STR r3, [r0, #40]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #52]\n\t" - "STR r4, [%[r], #44]\n\t" + "LDR r3, [r1, #52]\n\t" + "STR r4, [r0, #44]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #56]\n\t" - "STR r2, [%[r], #48]\n\t" + "LDR r4, [r1, #56]\n\t" + "STR r2, [r0, #48]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #60]\n\t" - "STR r3, [%[r], #52]\n\t" + "LDR r2, [r1, #60]\n\t" + "STR r3, [r0, #52]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #64]\n\t" - "STR r4, [%[r], #56]\n\t" + "LDR r3, [r1, #64]\n\t" + "STR r4, [r0, #56]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #68]\n\t" - "STR r2, [%[r], #60]\n\t" + "LDR r4, [r1, #68]\n\t" + "STR r2, [r0, #60]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #72]\n\t" - "STR r3, [%[r], #64]\n\t" + "LDR r2, [r1, #72]\n\t" + "STR r3, [r0, #64]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #76]\n\t" - "STR r4, [%[r], #68]\n\t" + "LDR r3, [r1, #76]\n\t" + "STR r4, [r0, #68]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #80]\n\t" - "STR r2, [%[r], #72]\n\t" + "LDR r4, [r1, #80]\n\t" + "STR r2, [r0, #72]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #84]\n\t" - "STR r3, [%[r], #76]\n\t" + "LDR r2, [r1, #84]\n\t" + "STR r3, [r0, #76]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #88]\n\t" - "STR r4, [%[r], #80]\n\t" + "LDR r3, [r1, #88]\n\t" + "STR r4, [r0, #80]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #92]\n\t" - "STR r2, [%[r], #84]\n\t" + "LDR r4, [r1, #92]\n\t" + "STR r2, [r0, #84]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #96]\n\t" - "STR r3, [%[r], #88]\n\t" + "LDR r2, [r1, #96]\n\t" + "STR r3, [r0, #88]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #100]\n\t" - "STR r4, [%[r], #92]\n\t" + "LDR r3, [r1, #100]\n\t" + "STR r4, [r0, #92]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #104]\n\t" - "STR r2, [%[r], #96]\n\t" + "LDR r4, [r1, #104]\n\t" + "STR r2, [r0, #96]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #108]\n\t" - "STR r3, [%[r], #100]\n\t" + "LDR r2, [r1, #108]\n\t" + "STR r3, [r0, #100]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #112]\n\t" - "STR r4, [%[r], #104]\n\t" + "LDR r3, [r1, #112]\n\t" + "STR r4, [r0, #104]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "LDR r4, [%[a], #116]\n\t" - "STR r2, [%[r], #108]\n\t" + "LDR r4, [r1, #116]\n\t" + "STR r2, [r0, #108]\n\t" "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" - "LDR r2, [%[a], #120]\n\t" - "STR r3, [%[r], #112]\n\t" + "LDR r2, [r1, #120]\n\t" + "STR r3, [r0, #112]\n\t" "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" - "LDR r3, [%[a], #124]\n\t" - "STR r4, [%[r], #116]\n\t" + "LDR r3, [r1, #124]\n\t" + "STR r4, [r0, #116]\n\t" "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" - "STR r2, [%[r], #120]\n\t" - "STR r3, [%[r], #124]\n\t" + "STR r2, [r0, #120]\n\t" + "STR r3, [r0, #124]\n\t" +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + "POP {%[L_asm_args]}\n\t" + "STM %[L_asm_args], {r0, r1}\n\t" +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ #ifndef WOLFSSL_NO_VAR_ASSIGN_REG : [r] "+r" (r), [a] "+r" (a) : + : "memory", "cc", "r2", "r3", "r4" #else + : [L_asm_args] "+r" (L_asm_args_p) : - : [r] "r" (r), [a] "r" (a) + : "memory", "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", + "r9", "r10", "r11", "lr" #endif /* !WOLFSSL_NO_VAR_ASSIGN_REG */ - : "memory", "cc", "r2", "r3", "r4" ); +#ifdef WOLFSSL_NO_VAR_ASSIGN_REG + r = (sp_digit*)(size_t)L_asm_args[0]; + a = (const sp_digit*)(size_t)L_asm_args[1]; +#endif /* WOLFSSL_NO_VAR_ASSIGN_REG */ } /* Divide the number by 2 mod the modulus (prime). (r = a / 2 % m)