From b088d6b6a53cb4d057526f71b7a1d598c58e7301 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 1 Jul 2026 17:57:21 +0200 Subject: [PATCH 1/2] chore(variants): update against CubeMX DB release 6.0.180 Warning: STM32G71xx not updated due to missing TIM5 declaration in CMSIS device headers. Signed-off-by: Frederic Pillon --- .../C011D6Y_C011F(4-6)(P-U)/PeripheralPins.c | 2 +- .../STM32C0xx/C011J(4-6)M/PeripheralPins.c | 2 +- .../C031C(4-6)(T-U)/PeripheralPins.c | 2 +- .../STM32C0xx/C031F(4-6)P/PeripheralPins.c | 2 +- .../STM32C0xx/C031G(4-6)U/PeripheralPins.c | 2 +- .../C031K(4-6)(T-U)/PeripheralPins.c | 2 +- .../C051C(6-8)(T-U)/PeripheralPins.c | 2 +- .../C051D8Y_C051F(6-8)P/PeripheralPins.c | 2 +- .../STM32C0xx/C051G(6-8)U/PeripheralPins.c | 2 +- .../C051K6(T-U)_C051K8T/PeripheralPins.c | 2 +- .../C071C(8-B)(T-U)/PeripheralPins.c | 2 +- .../C071C(8-B)(T-U)xN/PeripheralPins.c | 2 +- .../STM32C0xx/C071F(8-B)PxN/PeripheralPins.c | 2 +- .../C071F8P_C071FB(P-Y)/PeripheralPins.c | 2 +- .../STM32C0xx/C071G(8-B)U/PeripheralPins.c | 2 +- .../STM32C0xx/C071G(8-B)UxN/PeripheralPins.c | 2 +- .../C071K(8-B)(T-U)/PeripheralPins.c | 2 +- .../C071K(8-B)(T-U)xN/PeripheralPins.c | 2 +- .../STM32C0xx/C071R(8-B)T/PeripheralPins.c | 2 +- .../C071R8TxN_C071RB(I-T)xN/PeripheralPins.c | 2 +- .../C091C(B-C)(T-U)/PeripheralPins.c | 2 +- .../C091ECY_C091F(B-C)P/PeripheralPins.c | 2 +- .../STM32C0xx/C091G(B-C)U/PeripheralPins.c | 2 +- .../C091K(B-C)(T-U)/PeripheralPins.c | 2 +- .../C091RBT_C091RC(I-T)/PeripheralPins.c | 2 +- .../C092C(B-C)(T-U)/PeripheralPins.c | 2 +- .../C092ECY_C092F(B-C)P/PeripheralPins.c | 2 +- .../STM32C0xx/C092G(B-C)U/PeripheralPins.c | 2 +- .../C092K(B-C)(T-U)/PeripheralPins.c | 2 +- .../C092RBT_C092RC(I-T)/PeripheralPins.c | 2 +- variants/STM32F0xx/F030C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030C8T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030CCT/PeripheralPins.c | 2 +- variants/STM32F0xx/F030F4P/PeripheralPins.c | 2 +- variants/STM32F0xx/F030K6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030R8T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030RCT/PeripheralPins.c | 2 +- .../STM32F0xx/F031C(4-6)T/PeripheralPins.c | 2 +- .../F031E6Y_F038E6Y/PeripheralPins.c | 2 +- .../STM32F0xx/F031F(4-6)P/PeripheralPins.c | 2 +- .../STM32F0xx/F031G(4-6)U/PeripheralPins.c | 2 +- .../STM32F0xx/F031K(4-6)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F031K6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F038C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F038F6P/PeripheralPins.c | 2 +- variants/STM32F0xx/F038G6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F038K6U/PeripheralPins.c | 2 +- .../F042C(4-6)(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F042F(4-6)P/PeripheralPins.c | 2 +- .../STM32F0xx/F042G(4-6)U/PeripheralPins.c | 2 +- .../STM32F0xx/F042K(4-6)T/PeripheralPins.c | 2 +- .../STM32F0xx/F042K(4-6)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F042T6Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F048C6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F048G6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F048T6Y/PeripheralPins.c | 2 +- .../STM32F0xx/F051C4(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F051C6(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F051C8(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F051K(6-8)T/PeripheralPins.c | 2 +- .../STM32F0xx/F051K(6-8)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F051K4T/PeripheralPins.c | 2 +- variants/STM32F0xx/F051K4U/PeripheralPins.c | 2 +- variants/STM32F0xx/F051R4T/PeripheralPins.c | 2 +- variants/STM32F0xx/F051R6T/PeripheralPins.c | 2 +- .../STM32F0xx/F051R8(H-T)/PeripheralPins.c | 2 +- variants/STM32F0xx/F051T8Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F058C8U/PeripheralPins.c | 2 +- .../STM32F0xx/F058R8(H-T)/PeripheralPins.c | 2 +- variants/STM32F0xx/F058T8Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F070C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F070CBT/PeripheralPins.c | 2 +- variants/STM32F0xx/F070F6P/PeripheralPins.c | 2 +- variants/STM32F0xx/F070RBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32F0xx/F071RBT/PeripheralPins.c | 2 +- .../F071V(8-B)(H-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F072R8T_F072RB(H-I-T)/PeripheralPins.c | 2 +- .../F072V(8-B)(H-T)/PeripheralPins.c | 2 +- .../STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c | 2 +- .../STM32F0xx/F078RB(H-T)/PeripheralPins.c | 2 +- .../STM32F0xx/F078VB(H-T)/PeripheralPins.c | 2 +- .../F091C(B-C)(T-U)/PeripheralPins.c | 2 +- .../F091RBT_F091RC(H-T-Y)/PeripheralPins.c | 2 +- .../F091VBT_F091VC(H-T)/PeripheralPins.c | 2 +- .../STM32F0xx/F098CC(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c | 2 +- .../STM32F0xx/F098VC(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F100C(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100C(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(4-6)H/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(8-B)H/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100V(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100V(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101C(4-6)T/PeripheralPins.c | 2 +- .../F101C(8-B)(T-U)/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(F-G)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F101RBH/PeripheralPins.c | 2 +- .../STM32F1xx/F101T(4-6)U/PeripheralPins.c | 2 +- .../STM32F1xx/F101T(8-B)U/PeripheralPins.c | 2 +- .../STM32F1xx/F101V(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101V(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101V(F-G)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101Z(F-G)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102C(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102C(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102R(8-B)T/PeripheralPins.c | 2 +- .../F103C4T_F103C6(T-U)/PeripheralPins.c | 2 +- .../F103C8T_F103CB(T-U)/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(4-6)H/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(8-B)H/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(F-G)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103T(4-6)U/PeripheralPins.c | 2 +- .../STM32F1xx/F103T(8-B)U/PeripheralPins.c | 2 +- .../F103V(C-D-E)(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F103V(F-G)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F103Z(C-D-E)(H-T)/PeripheralPins.c | 2 +- .../F103Z(F-G)(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F105R(8-B-C)T/PeripheralPins.c | 2 +- .../F105V(8-B)(H-T)_F105VCT/PeripheralPins.c | 2 +- .../STM32F1xx/F107R(B-C)T/PeripheralPins.c | 2 +- .../F107VBT_F107VC(H-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F301C6T_F301C8(T-Y)/PeripheralPins.c | 2 +- .../STM32F3xx/F301K(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F301K(6-8)U/PeripheralPins.c | 2 +- .../STM32F3xx/F301R(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302C(B-C)T/PeripheralPins.c | 2 +- .../F302C6T_F302C8(T-Y)/PeripheralPins.c | 2 +- .../STM32F3xx/F302K(6-8)U/PeripheralPins.c | 2 +- .../STM32F3xx/F302R(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302R(B-C)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302R(D-E)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302V(B-C)T/PeripheralPins.c | 2 +- .../F302V(D-E)(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F302VCY/PeripheralPins.c | 2 +- .../STM32F3xx/F302Z(D-E)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32F3xx/F303C(B-C)T/PeripheralPins.c | 2 +- .../F303C8Y_F334C8Y/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F303R(6-8)T_F334R(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F303R(B-C)T/PeripheralPins.c | 2 +- .../STM32F3xx/F303R(D-E)T/PeripheralPins.c | 2 +- .../STM32F3xx/F303V(B-C)T/PeripheralPins.c | 2 +- .../F303V(D-E)(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F303VCY/PeripheralPins.c | 2 +- variants/STM32F3xx/F303VEY/PeripheralPins.c | 2 +- .../STM32F3xx/F303Z(D-E)T/PeripheralPins.c | 2 +- .../STM32F3xx/F318C8(T-Y)/PeripheralPins.c | 2 +- variants/STM32F3xx/F318K8U/PeripheralPins.c | 2 +- variants/STM32F3xx/F328C8T/PeripheralPins.c | 2 +- variants/STM32F3xx/F358CCT/PeripheralPins.c | 2 +- variants/STM32F3xx/F358RCT/PeripheralPins.c | 2 +- variants/STM32F3xx/F358VCT/PeripheralPins.c | 2 +- .../STM32F3xx/F373C(8-B-C)T/PeripheralPins.c | 2 +- .../STM32F3xx/F373R(8-B-C)T/PeripheralPins.c | 2 +- .../F373V(8-B-C)(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F378CCT/PeripheralPins.c | 2 +- .../STM32F3xx/F378RC(T-Y)/PeripheralPins.c | 2 +- .../STM32F3xx/F378VC(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F398VET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F401R(B-C-D-E)T/PeripheralPins.c | 2 +- .../F401V(B-C-D-E)H/PeripheralPins.c | 2 +- .../F401V(B-C-D-E)T/PeripheralPins.c | 2 +- .../F405O(E-G)Y_F415OGY/PeripheralPins.c | 2 +- .../F405RGT_F415RGT/PeripheralPins.c | 2 +- .../F405VGT_F415VGT/PeripheralPins.c | 2 +- .../F405ZGT_F415ZGT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F407V(E-G)T_F417V(E-G)T/PeripheralPins.c | 2 +- .../F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c | 2 +- .../STM32F4xx/F410C(8-B)T/PeripheralPins.c | 2 +- .../STM32F4xx/F410C(8-B)U/PeripheralPins.c | 2 +- .../F410R(8-B)(I-T)/PeripheralPins.c | 2 +- .../STM32F4xx/F410T(8-B)Y/PeripheralPins.c | 2 +- .../F411C(C-E)(U-Y)/PeripheralPins.c | 2 +- .../STM32F4xx/F411R(C-E)T/PeripheralPins.c | 2 +- .../STM32F4xx/F411V(C-E)H/PeripheralPins.c | 2 +- .../STM32F4xx/F411V(C-E)T/PeripheralPins.c | 2 +- .../STM32F4xx/F412C(E-G)U/PeripheralPins.c | 2 +- .../F412R(E-G)(T-Y)x(P)/PeripheralPins.c | 2 +- .../STM32F4xx/F412V(E-G)H/PeripheralPins.c | 2 +- .../STM32F4xx/F412V(E-G)T/PeripheralPins.c | 2 +- .../F412Z(E-G)(J-T)/PeripheralPins.c | 2 +- .../F413C(G-H)U_F423CHU/PeripheralPins.c | 2 +- .../F413M(G-H)Y_F423MHY/PeripheralPins.c | 2 +- .../F413R(G-H)T_F423RHT/PeripheralPins.c | 2 +- .../F413V(G-H)H_F423VHH/PeripheralPins.c | 2 +- .../F413V(G-H)T_F423VHT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32F4xx/F446M(C-E)Y/PeripheralPins.c | 2 +- .../STM32F4xx/F446R(C-E)T/PeripheralPins.c | 2 +- .../STM32F4xx/F446V(C-E)T/PeripheralPins.c | 2 +- .../F446Z(C-E)(H-J-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F722Z(C-E)T_F732ZET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 17 +- .../PinNamesVar.h | 42 +- .../STM32F7xx/F723R(C-E)V/PeripheralPins.c | 15 +- variants/STM32F7xx/F723R(C-E)V/PinNamesVar.h | 32 +- .../PeripheralPins.c | 15 +- .../F723V(C-E)(T-Y)_F733VE(T-Y)/PinNamesVar.h | 32 +- .../PeripheralPins.c | 15 +- .../PinNamesVar.h | 32 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F769I(G-I)T_F779IIT/PeripheralPins.c | 2 +- .../STM32G0xx/G030C(6-8)T/PeripheralPins.c | 2 +- variants/STM32G0xx/G030F6P/PeripheralPins.c | 2 +- variants/STM32G0xx/G030J6M/PeripheralPins.c | 2 +- .../STM32G0xx/G030K(6-8)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G031J(4-6)M_G041J6M/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32G0xx/G050C(6-8)T/PeripheralPins.c | 2 +- variants/STM32G0xx/G050F6P/PeripheralPins.c | 2 +- .../STM32G0xx/G050K(6-8)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G051G(6-8)U_G061G(6-8)U/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32G0xx/G070CBT/PeripheralPins.c | 2 +- variants/STM32G0xx/G070KBT/PeripheralPins.c | 2 +- variants/STM32G0xx/G070RBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G071EBY_G081EBY/PeripheralPins.c | 2 +- .../G071G(6-8-B)U_G081GBU/PeripheralPins.c | 2 +- .../G071G(8-B)UxN_G081GBUxN/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0CET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0KET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0RET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0VET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G0B1NEY_G0C1NEY/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32G4xx/G411C(6-8-B)T/PeripheralPins.c | 2 +- .../STM32G4xx/G411C(6-8-B)U/PeripheralPins.c | 2 +- variants/STM32G4xx/G411CCT/PeripheralPins.c | 2 +- variants/STM32G4xx/G411CCU/PeripheralPins.c | 2 +- .../G411K(6-8-B)(T-U)/PeripheralPins.c | 2 +- .../STM32G4xx/G411M(6-8-B)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G411MCT/PeripheralPins.c | 2 +- .../STM32G4xx/G411R(6-8-B)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G411RCT/PeripheralPins.c | 2 +- .../STM32G4xx/G414C(B-C)T/PeripheralPins.c | 2 +- .../STM32G4xx/G414C(B-C)U/PeripheralPins.c | 2 +- .../STM32G4xx/G414M(B-C)T/PeripheralPins.c | 2 +- .../STM32G4xx/G414R(B-C)T/PeripheralPins.c | 2 +- .../STM32G4xx/G414V(B-C)T/PeripheralPins.c | 2 +- .../G431C(6-8-B)T_G441CBT/PeripheralPins.c | 2 +- .../G431C(6-8-B)U_G441CBU/PeripheralPins.c | 2 +- variants/STM32G4xx/G431CBTxZ/PeripheralPins.c | 2 +- .../G431CBY_G441CBY/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G431M(6-8-B)T_G441MBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G431V(6-8-B)T_G441VBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G491C(C-E)T_G4A1CET/PeripheralPins.c | 2 +- .../STM32G4xx/G491C(C-E)U/PeripheralPins.c | 2 +- .../G491K(C-E)U_G4A1KEU/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G491V(C-E)T_G4A1VET/PeripheralPins.c | 2 +- variants/STM32G4xx/G4A1CEU/PeripheralPins.c | 2 +- .../STM32H5xx/H503CB(T-U)/PeripheralPins.c | 2 +- variants/STM32H5xx/H503EBY/PeripheralPins.c | 2 +- variants/STM32H5xx/H503KBU/PeripheralPins.c | 2 +- variants/STM32H5xx/H503RBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H523HEY_H533HEY/PeripheralPins.c | 2 +- .../H523R(C-E)T_H533RET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 397 +++++++++ .../H543C(E-G)(T-U)_H553CG(T-U)/PinNamesVar.h | 67 ++ .../boards_entry.txt | 59 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 74 ++ .../variant_generic.h | 201 +++++ .../H543R(E-G)T_H553RGT/PeripheralPins.c | 611 ++++++++++++++ .../H543R(E-G)T_H553RGT/PinNamesVar.h | 81 ++ .../H543R(E-G)T_H553RGT/boards_entry.txt | 32 + .../H543R(E-G)T_H553RGT}/generic_clock.c | 6 +- .../H543R(E-G)T_H553RGT/variant_generic.cpp | 93 +++ .../H543R(E-G)T_H553RGT/variant_generic.h | 238 ++++++ .../H543UGY_H553UGY/PeripheralPins.c | 589 +++++++++++++ .../STM32H5xx/H543UGY_H553UGY/PinNamesVar.h | 80 ++ .../H543UGY_H553UGY/boards_entry.txt | 23 + .../STM32H5xx/H543UGY_H553UGY/generic_clock.c | 27 + .../H543UGY_H553UGY/variant_generic.cpp | 90 ++ .../H543UGY_H553UGY/variant_generic.h | 236 ++++++ .../PeripheralPins.c | 736 ++++++++++++++++ .../PinNamesVar.h | 85 ++ .../boards_entry.txt | 86 ++ .../generic_clock.c | 31 + .../variant_generic.cpp | 134 +++ .../variant_generic.h | 270 ++++++ .../PeripheralPins.c | 788 ++++++++++++++++++ .../PinNamesVar.h | 89 ++ .../boards_entry.txt | 86 ++ .../generic_clock.c | 31 + .../variant_generic.cpp | 170 ++++ .../variant_generic.h | 306 +++++++ .../STM32H5xx/H562A(G-I)I/PeripheralPins.c | 2 +- .../H562I(G-I)(K-T)/PeripheralPins.c | 2 +- .../STM32H5xx/H562R(G-I)T/PeripheralPins.c | 2 +- .../STM32H5xx/H562R(G-I)V/PeripheralPins.c | 2 +- .../STM32H5xx/H562V(G-I)T/PeripheralPins.c | 2 +- .../STM32H5xx/H562Z(G-I)T/PeripheralPins.c | 2 +- .../H563A(G-I)I_H573AII/PeripheralPins.c | 81 +- .../H563A(G-I)I_H573AII/PinNamesVar.h | 5 + .../H563A(G-I)I_H573AII/variant_generic.h | 5 + .../H563AIIxQ_H573AIIxQ/PeripheralPins.c | 72 +- .../H563AIIxQ_H573AIIxQ/PinNamesVar.h | 3 + .../H563AIIxQ_H573AIIxQ/variant_generic.h | 3 + .../PeripheralPins.c | 83 +- .../PinNamesVar.h | 5 + .../variant_generic.h | 5 + .../H563IIKxQ_H573IIKxQ/PeripheralPins.c | 83 +- .../H563IIKxQ_H573IIKxQ/PinNamesVar.h | 5 + .../H563IIKxQ_H573IIKxQ/variant_generic.h | 5 + .../H563IITxQ_H573IITxQ/PeripheralPins.c | 83 +- .../H563IITxQ_H573IITxQ/PinNamesVar.h | 5 + .../H563IITxQ_H573IITxQ/variant_generic.h | 5 + .../H563MIYxQ_H573MIYxQ/PeripheralPins.c | 54 +- .../H563MIYxQ_H573MIYxQ/PinNamesVar.h | 1 + .../H563MIYxQ_H573MIYxQ/variant_generic.h | 1 + .../H563R(G-I)T_H573RIT/PeripheralPins.c | 54 +- .../H563R(G-I)T_H573RIT/PinNamesVar.h | 1 + .../H563R(G-I)T_H573RIT/variant_generic.h | 1 + .../H563R(G-I)V_H573RIV/PeripheralPins.c | 57 +- .../H563R(G-I)V_H573RIV/PinNamesVar.h | 2 + .../H563R(G-I)V_H573RIV/variant_generic.h | 2 + .../H563V(G-I)T_H573VIT/PeripheralPins.c | 56 +- .../H563V(G-I)T_H573VIT/PinNamesVar.h | 1 + .../H563V(G-I)T_H573VIT/variant_generic.h | 1 + .../H563VITxQ_H573VITxQ/PeripheralPins.c | 2 +- .../H563Z(G-I)T_H573ZIT/PeripheralPins.c | 70 +- .../H563Z(G-I)T_H573ZIT/PinNamesVar.h | 4 + .../H563Z(G-I)T_H573ZIT/variant_generic.h | 4 + .../H563ZITxQ_H573ZITxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H725R(E-G)V_H735RGV/PeripheralPins.c | 2 +- .../H725V(E-G)H_H735VGH/PeripheralPins.c | 2 +- .../H725V(E-G)T_H735VGT/PeripheralPins.c | 2 +- .../H725VGY_H735VGY/PeripheralPins.c | 2 +- .../H725Z(E-G)T_H735ZGT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H745B(G-I)T_H755BIT/PeripheralPins.c | 2 +- .../H745I(G-I)K_H755IIK/PeripheralPins.c | 2 +- .../H745I(G-I)T_H755IIT/PeripheralPins.c | 2 +- .../H745Z(G-I)T_H755ZIT/PeripheralPins.c | 2 +- .../H747B(G-I)T_H757BIT/PeripheralPins.c | 2 +- .../H747ZIY_H757ZIY/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c | 2 +- .../H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c | 2 +- .../H7A3N(G-I)H_H7B3NIH/PeripheralPins.c | 2 +- .../H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c | 2 +- .../H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c | 2 +- variants/STM32L0xx/L010C6T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L0xx/L010K8T/PeripheralPins.c | 2 +- variants/STM32L0xx/L010R8T/PeripheralPins.c | 2 +- variants/STM32L0xx/L010RBT/PeripheralPins.c | 2 +- .../L011D(3-4)P_L021D4P/PeripheralPins.c | 2 +- .../STM32L0xx/L011E(3-4)Y/PeripheralPins.c | 2 +- .../L011F(3-4)U_L021F4U/PeripheralPins.c | 2 +- .../L011G(3-4)U_L021G4U/PeripheralPins.c | 2 +- .../L011K(3-4)U_L021K4U/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L031E(4-6)Y_L041E6Y/PeripheralPins.c | 2 +- .../L031F(4-6)P_L041F6P/PeripheralPins.c | 2 +- .../L031G(4-6)U_L041G6U/PeripheralPins.c | 2 +- .../L031G6UxS_L041G6UxS/PeripheralPins.c | 2 +- .../L031K(4-6)T_L041K6T/PeripheralPins.c | 2 +- .../L031K(4-6)U_L041K6U/PeripheralPins.c | 2 +- .../L051C(6-8)(T-U)/PeripheralPins.c | 2 +- .../STM32L0xx/L051K(6-8)T/PeripheralPins.c | 2 +- .../STM32L0xx/L051K(6-8)U/PeripheralPins.c | 2 +- .../STM32L0xx/L051R(6-8)H/PeripheralPins.c | 2 +- .../STM32L0xx/L051R(6-8)T/PeripheralPins.c | 2 +- .../STM32L0xx/L051T(6-8)Y/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L052K(6-8)T_L062K8T/PeripheralPins.c | 2 +- .../L052K(6-8)U_L062K8U/PeripheralPins.c | 2 +- .../L052R(6-8)H_L053R(6-8)H/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L052T6Y_L052T8(F-Y)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L0xx/L071C(B-Z)Y/PeripheralPins.c | 2 +- .../L071K(8-B-Z)U_L081KZU/PeripheralPins.c | 2 +- .../L071K(B-Z)T_L081KZT/PeripheralPins.c | 2 +- .../STM32L0xx/L071R(B-Z)H/PeripheralPins.c | 2 +- .../STM32L0xx/L071R(B-Z)T/PeripheralPins.c | 2 +- .../L071V(8-B-Z)(I-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c | 2 +- .../L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L1xx/L100RCT/PeripheralPins.c | 2 +- .../L151CC(T-U)_L152CC(T-U)/PeripheralPins.c | 2 +- .../L151QCH_L152QCH_L162QCH/PeripheralPins.c | 2 +- .../L151QDH_L152QDH_L162QDH/PeripheralPins.c | 2 +- .../L151QEH_L152QEH/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L151RET_L152RET_L162RET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L151VDT_L152VDT_L162VDT/PeripheralPins.c | 2 +- .../L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c | 2 +- .../L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c | 2 +- .../L151ZET_L152ZET_L162ZET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L4xx/L412CB(T-U)xP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L4xx/L412RB(I-T)xP/PeripheralPins.c | 2 +- .../L412T(8-B)Y_L422TBY/PeripheralPins.c | 2 +- variants/STM32L4xx/L412TBYxP/PeripheralPins.c | 2 +- .../L431C(B-C)(T-U)/PeripheralPins.c | 2 +- .../STM32L4xx/L431C(B-C)Y/PeripheralPins.c | 2 +- .../STM32L4xx/L431K(B-C)U/PeripheralPins.c | 2 +- .../L431R(B-C)(I-T-Y)/PeripheralPins.c | 2 +- .../STM32L4xx/L431VC(I-T)/PeripheralPins.c | 2 +- .../L432K(B-C)U_L442KCU/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L433RCTxP/PeripheralPins.c | 2 +- .../L433VC(I-T)_L443VC(I-T)/PeripheralPins.c | 2 +- .../L451CCU_L451CE(T-U)/PeripheralPins.c | 2 +- .../L451R(C-E)(I-T-Y)/PeripheralPins.c | 2 +- .../L451V(C-E)(I-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L452RETxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L4xx/L471Q(E-G)I/PeripheralPins.c | 2 +- .../STM32L4xx/L471R(E-G)T/PeripheralPins.c | 2 +- .../STM32L4xx/L471V(E-G)T/PeripheralPins.c | 2 +- .../L471Z(E-G)(J-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L476JGYxP/PeripheralPins.c | 2 +- .../STM32L4xx/L476M(E-G)Y/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L476VGYxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L476ZGTxP/PeripheralPins.c | 2 +- .../L496A(E-G)I_L4A6AGI/PeripheralPins.c | 2 +- .../L496AGIxP_L4A6AGIxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L496QGIxP_L4A6QGIxP/PeripheralPins.c | 2 +- .../L496R(E-G)T_L4A6RGT/PeripheralPins.c | 2 +- variants/STM32L4xx/L496RGTxP/PeripheralPins.c | 2 +- .../L496V(E-G)T_L4A6VGT/PeripheralPins.c | 2 +- .../L496VGTxP_L4A6VGTxP/PeripheralPins.c | 2 +- .../L496VGY_L4A6VGY/PeripheralPins.c | 2 +- .../L496VGYxP_L4A6VGYxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L496WGYxP/PeripheralPins.c | 2 +- .../L496Z(E-G)T_L4A6ZGT/PeripheralPins.c | 2 +- .../L496ZGTxP_L4A6ZGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c | 2 +- .../L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c | 2 +- .../L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c | 2 +- .../L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 4 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 13 +- .../STM32L4xx/L4P5R(G-E)T/generic_clock.c | 27 + .../variant_generic.cpp | 3 +- .../variant_generic.h | 0 .../L4P5R(G-E)T_L4Q5RGT/CMakeLists.txt | 31 - .../L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c | 2 +- .../L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c | 2 +- .../L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c | 2 +- .../L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c | 2 +- .../L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c | 2 +- .../L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c | 2 +- .../L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4Q5RGT/PeripheralPins.c | 542 ++++++++++++ variants/STM32L4xx/L4Q5RGT/PinNamesVar.h | 91 ++ variants/STM32L4xx/L4Q5RGT/boards_entry.txt | 14 + variants/STM32L4xx/L4Q5RGT/generic_clock.c | 27 + .../STM32L4xx/L4Q5RGT/variant_generic.cpp | 92 ++ variants/STM32L4xx/L4Q5RGT/variant_generic.h | 221 +++++ .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c | 2 +- .../L4R9A(G-I)I_L4S9AII/PeripheralPins.c | 2 +- .../L4R9V(G-I)T_L4S9VIT/PeripheralPins.c | 2 +- .../L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c | 2 +- .../L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c | 2 +- variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L552MEYxP_L562MEYxP/PeripheralPins.c | 2 +- .../L552MEYxQ_L562MEYxQ/PeripheralPins.c | 2 +- .../L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c | 2 +- .../L552QEI_L562QEI/PeripheralPins.c | 2 +- .../L552QEIxP_L562QEIxP/PeripheralPins.c | 2 +- .../L552R(C-E)T_L562RET/PeripheralPins.c | 2 +- .../L552RETxP_L562RETxP/PeripheralPins.c | 2 +- .../L552RETxQ_L562RETxQ/PeripheralPins.c | 2 +- .../L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c | 2 +- .../L552VET_L562VET/PeripheralPins.c | 2 +- .../L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c | 2 +- .../L552ZET_L562ZET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U031C(6-8)(T-U)/PeripheralPins.c | 2 +- .../STM32U0xx/U031F(4-6-8)P/PeripheralPins.c | 2 +- .../STM32U0xx/U031G(6-8)Y/PeripheralPins.c | 2 +- .../STM32U0xx/U031K(4-6-8)U/PeripheralPins.c | 2 +- .../U031R(6-8)(I-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U073H(8-B-C)Y_U083HCY/PeripheralPins.c | 2 +- .../U073K(8-B-C)U_U083KCU/PeripheralPins.c | 2 +- .../U073M(8-B-C)I_U083MCI/PeripheralPins.c | 2 +- .../U073M(8-B-C)T_U083MCT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 372 +++++++++ .../U335C(B-C)(T-U)_U345CC(T-U)/PinNamesVar.h | 82 ++ .../boards_entry.txt | 59 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 74 ++ .../variant_generic.h | 203 +++++ .../PeripheralPins.c | 354 ++++++++ .../PinNamesVar.h | 75 ++ .../boards_entry.txt | 59 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 69 ++ .../variant_generic.h | 196 +++++ .../U335C(B-C)YxQ_U345CCYxQ/PeripheralPins.c | 337 ++++++++ .../U335C(B-C)YxQ_U345CCYxQ/PinNamesVar.h | 58 ++ .../U335C(B-C)YxQ_U345CCYxQ/boards_entry.txt | 32 + .../U335C(B-C)YxQ_U345CCYxQ/generic_clock.c | 28 + .../variant_generic.cpp | 65 ++ .../U335C(B-C)YxQ_U345CCYxQ/variant_generic.h | 184 ++++ .../U335K(B-C)U_U345KCU/PeripheralPins.c | 333 ++++++++ .../U335K(B-C)U_U345KCU/PinNamesVar.h | 62 ++ .../U335K(B-C)U_U345KCU/boards_entry.txt | 32 + .../U335K(B-C)U_U345KCU/generic_clock.c | 28 + .../U335K(B-C)U_U345KCU/variant_generic.cpp | 60 ++ .../U335K(B-C)U_U345KCU/variant_generic.h | 181 ++++ .../U335K(B-C)YxQ_U345KCYxQ/PeripheralPins.c | 313 +++++++ .../U335K(B-C)YxQ_U345KCYxQ/PinNamesVar.h | 52 ++ .../U335K(B-C)YxQ_U345KCYxQ/boards_entry.txt | 32 + .../U335K(B-C)YxQ_U345KCYxQ/generic_clock.c | 28 + .../variant_generic.cpp | 57 ++ .../U335K(B-C)YxQ_U345KCYxQ/variant_generic.h | 172 ++++ .../U335R(B-C)I_U345RCI/PeripheralPins.c | 417 +++++++++ .../U335R(B-C)I_U345RCI/PinNamesVar.h | 87 ++ .../U335R(B-C)I_U345RCI/boards_entry.txt | 32 + .../U335R(B-C)I_U345RCI/generic_clock.c | 28 + .../U335R(B-C)I_U345RCI/variant_generic.cpp | 91 ++ .../U335R(B-C)I_U345RCI/variant_generic.h | 220 +++++ .../U335R(B-C)IxQ_U345RCIxQ/PeripheralPins.c | 402 +++++++++ .../U335R(B-C)IxQ_U345RCIxQ/PinNamesVar.h | 83 ++ .../U335R(B-C)IxQ_U345RCIxQ/boards_entry.txt | 32 + .../U335R(B-C)IxQ_U345RCIxQ/generic_clock.c | 28 + .../variant_generic.cpp | 85 ++ .../U335R(B-C)IxQ_U345RCIxQ/variant_generic.h | 214 +++++ .../U335R(B-C)T_U345RCT/PeripheralPins.c | 417 +++++++++ .../U335R(B-C)T_U345RCT/PinNamesVar.h | 87 ++ .../U335R(B-C)T_U345RCT/boards_entry.txt | 32 + .../U335R(B-C)T_U345RCT/generic_clock.c | 28 + .../U335R(B-C)T_U345RCT/variant_generic.cpp | 91 ++ .../U335R(B-C)T_U345RCT/variant_generic.h | 220 +++++ .../U335R(B-C)TxQ_U345RCTxQ/PeripheralPins.c | 402 +++++++++ .../U335R(B-C)TxQ_U345RCTxQ/PinNamesVar.h | 83 ++ .../U335R(B-C)TxQ_U345RCTxQ/boards_entry.txt | 32 + .../U335R(B-C)TxQ_U345RCTxQ/generic_clock.c | 28 + .../variant_generic.cpp | 85 ++ .../U335R(B-C)TxQ_U345RCTxQ/variant_generic.h | 214 +++++ .../PeripheralPins.c | 359 ++++++++ .../U356C(C-E)(T-U)_U366CE(T-U)/PinNamesVar.h | 84 ++ .../boards_entry.txt | 59 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 74 ++ .../variant_generic.h | 204 +++++ .../PeripheralPins.c | 343 ++++++++ .../PinNamesVar.h | 77 ++ .../boards_entry.txt | 59 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 69 ++ .../variant_generic.h | 197 +++++ .../U356C(C-E)YxQ_U366CEYxQ/PeripheralPins.c | 338 ++++++++ .../U356C(C-E)YxQ_U366CEYxQ/PinNamesVar.h | 74 ++ .../U356C(C-E)YxQ_U366CEYxQ/boards_entry.txt | 32 + .../U356C(C-E)YxQ_U366CEYxQ/generic_clock.c | 28 + .../variant_generic.cpp | 67 ++ .../U356C(C-E)YxQ_U366CEYxQ/variant_generic.h | 195 +++++ .../U356K(C-E)U_U366KEU/PeripheralPins.c | 323 +++++++ .../U356K(C-E)U_U366KEU/PinNamesVar.h | 64 ++ .../U356K(C-E)U_U366KEU/boards_entry.txt | 32 + .../U356K(C-E)U_U366KEU/generic_clock.c | 28 + .../U356K(C-E)U_U366KEU/variant_generic.cpp | 60 ++ .../U356K(C-E)U_U366KEU/variant_generic.h | 182 ++++ .../U356R(C-E)I_U366REI/PeripheralPins.c | 408 +++++++++ .../U356R(C-E)I_U366REI/PinNamesVar.h | 96 +++ .../U356R(C-E)I_U366REI/boards_entry.txt | 32 + .../U356R(C-E)I_U366REI/generic_clock.c | 28 + .../U356R(C-E)I_U366REI/variant_generic.cpp | 93 +++ .../U356R(C-E)I_U366REI/variant_generic.h | 223 +++++ .../U356R(C-E)IxQ_U366REIxQ/PeripheralPins.c | 393 +++++++++ .../U356R(C-E)IxQ_U366REIxQ/PinNamesVar.h | 90 ++ .../U356R(C-E)IxQ_U366REIxQ/boards_entry.txt | 32 + .../U356R(C-E)IxQ_U366REIxQ/generic_clock.c | 28 + .../variant_generic.cpp | 87 ++ .../U356R(C-E)IxQ_U366REIxQ/variant_generic.h | 215 +++++ .../U356R(C-E)T_U366RET/PeripheralPins.c | 408 +++++++++ .../U356R(C-E)T_U366RET/PinNamesVar.h | 96 +++ .../U356R(C-E)T_U366RET/boards_entry.txt | 32 + .../U356R(C-E)T_U366RET/generic_clock.c | 28 + .../U356R(C-E)T_U366RET/variant_generic.cpp | 93 +++ .../U356R(C-E)T_U366RET/variant_generic.h | 223 +++++ .../U356R(C-E)TxQ_U366RETxQ/PeripheralPins.c | 393 +++++++++ .../U356R(C-E)TxQ_U366RETxQ/PinNamesVar.h | 90 ++ .../U356R(C-E)TxQ_U366RETxQ/boards_entry.txt | 32 + .../U356R(C-E)TxQ_U366RETxQ/generic_clock.c | 28 + .../variant_generic.cpp | 87 ++ .../U356R(C-E)TxQ_U366RETxQ/variant_generic.h | 215 +++++ .../U356R(C-E)YxQ_U366REYxQ/PeripheralPins.c | 394 +++++++++ .../U356R(C-E)YxQ_U366REYxQ/PinNamesVar.h | 91 ++ .../U356R(C-E)YxQ_U366REYxQ/boards_entry.txt | 32 + .../U356R(C-E)YxQ_U366REYxQ/generic_clock.c | 28 + .../variant_generic.cpp | 87 ++ .../U356R(C-E)YxQ_U366REYxQ/variant_generic.h | 216 +++++ .../U356V(C-E)I_U366VEI/PeripheralPins.c | 457 ++++++++++ .../U356V(C-E)I_U366VEI/PinNamesVar.h | 111 +++ .../U356V(C-E)I_U366VEI/boards_entry.txt | 32 + .../U356V(C-E)I_U366VEI/generic_clock.c | 28 + .../U356V(C-E)I_U366VEI/variant_generic.cpp | 127 +++ .../U356V(C-E)I_U366VEI/variant_generic.h | 259 ++++++ .../U356V(C-E)IxQ_U366VEIxQ/PeripheralPins.c | 449 ++++++++++ .../U356V(C-E)IxQ_U366VEIxQ/PinNamesVar.h | 106 +++ .../U356V(C-E)IxQ_U366VEIxQ/boards_entry.txt | 32 + .../U356V(C-E)IxQ_U366VEIxQ/generic_clock.c | 28 + .../variant_generic.cpp | 122 +++ .../U356V(C-E)IxQ_U366VEIxQ/variant_generic.h | 253 ++++++ .../U356V(C-E)T_U366VET/PeripheralPins.c | 457 ++++++++++ .../U356V(C-E)T_U366VET/PinNamesVar.h | 111 +++ .../U356V(C-E)T_U366VET/boards_entry.txt | 32 + .../U356V(C-E)T_U366VET/generic_clock.c | 28 + .../U356V(C-E)T_U366VET/variant_generic.cpp | 127 +++ .../U356V(C-E)T_U366VET/variant_generic.h | 259 ++++++ .../U356V(C-E)TxQ_U366VETxQ/PeripheralPins.c | 449 ++++++++++ .../U356V(C-E)TxQ_U366VETxQ/PinNamesVar.h | 106 +++ .../U356V(C-E)TxQ_U366VETxQ/boards_entry.txt | 32 + .../U356V(C-E)TxQ_U366VETxQ/generic_clock.c | 28 + .../variant_generic.cpp | 122 +++ .../U356V(C-E)TxQ_U366VETxQ/variant_generic.h | 253 ++++++ .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U375C(E-G)YxQ_U385CGYxQ/PeripheralPins.c | 2 +- .../U375K(E-G)U_U385KGU/PeripheralPins.c | 2 +- .../U375R(E-G)I_U385RGI/PeripheralPins.c | 2 +- .../U375R(E-G)IxQ_U385RGIxQ/PeripheralPins.c | 2 +- .../U375R(E-G)T_U385RGT/PeripheralPins.c | 2 +- .../U375R(E-G)TxQ_U385RGTxQ/PeripheralPins.c | 2 +- .../U375R(E-G)YxG_U385RGYxG/PeripheralPins.c | 2 +- .../U375R(E-G)YxQ_U385RGYxQ/PeripheralPins.c | 2 +- .../U375V(E-G)I_U385VGI/PeripheralPins.c | 2 +- .../U375V(E-G)IxQ_U385VGIxQ/PeripheralPins.c | 2 +- .../U375V(E-G)T_U385VGT/PeripheralPins.c | 2 +- .../U375V(E-G)TxQ_U385VGTxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U3B5J(G-I)YxQ_U3C5JIYxQ/PeripheralPins.c | 2 +- .../U3B5Q(G-I)I_U3C5QII/PeripheralPins.c | 2 +- .../U3B5Q(G-I)IxQ_U3C5QIIxQ/PeripheralPins.c | 2 +- .../U3B5R(G-I)T_U3C5RIT/PeripheralPins.c | 2 +- .../U3B5R(G-I)TxQ_U3C5RITxQ/PeripheralPins.c | 2 +- .../U3B5V(G-I)T_U3C5VIT/PeripheralPins.c | 2 +- .../U3B5V(G-I)TxQ_U3C5VITxQ/PeripheralPins.c | 2 +- .../U3B5V(G-I)YxQ_U3C5VIYxQ/PeripheralPins.c | 2 +- .../U3B5W(G-I)YxQ_U3C5WIYxQ/PeripheralPins.c | 2 +- .../U3B5Z(G-I)T_U3C5ZIT/PeripheralPins.c | 2 +- .../U3B5Z(G-I)TxQ_U3C5ZITxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535JEYxQ_U545JEYxQ/PeripheralPins.c | 2 +- .../U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c | 2 +- .../U535R(B-C-E)I_U545REI/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535R(B-C-E)T_U545RET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535V(C-E)I_U545VEI/PeripheralPins.c | 2 +- .../U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c | 2 +- .../U535V(C-E)T_U545VET/PeripheralPins.c | 2 +- .../U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c | 2 +- .../U575A(G-I)I_U585AII/PeripheralPins.c | 2 +- .../U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c | 2 +- .../U575Q(G-I)I_U585QII/PeripheralPins.c | 2 +- .../U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c | 2 +- .../U575R(G-I)T_U585RIT/PeripheralPins.c | 2 +- .../U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c | 2 +- .../U575V(G-I)T_U585VIT/PeripheralPins.c | 2 +- .../U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c | 2 +- .../U575Z(G-I)T_U585ZIT/PeripheralPins.c | 2 +- .../U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c | 2 +- .../U595A(I-J)H_U5A5AJH/PeripheralPins.c | 2 +- .../U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c | 2 +- .../U595Q(I-J)I_U5A5QJI/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U595R(I-J)T_U5A5RJT/PeripheralPins.c | 2 +- .../U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U595Z(I-J)T_U5A5ZJT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c | 2 +- .../U599BJYxQ_U5A9BJYxQ/PeripheralPins.c | 2 +- .../U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c | 2 +- .../U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c | 2 +- .../STM32U5xx/U5F7V(I-J)T/PeripheralPins.c | 2 +- .../STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c | 2 +- .../U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c | 2 +- .../STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c | 2 +- .../STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c | 2 +- .../STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G7VJT/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../WB06CCF_WB07CCF/PeripheralPins.c | 2 +- .../WB06CCV_WB07CCV/PeripheralPins.c | 2 +- .../WB06KCV_WB07KCV/PeripheralPins.c | 2 +- variants/STM32WBAxx/WBA23CEU/PeripheralPins.c | 2 +- variants/STM32WBAxx/WBA23KEU/PeripheralPins.c | 2 +- variants/STM32WBAxx/WBA25CEU/PeripheralPins.c | 2 +- variants/STM32WBAxx/WBA25HEF/PeripheralPins.c | 2 +- variants/STM32WBAxx/WBA50KGU/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c | 2 +- .../STM32WBAxx/WBA55H(E-G)F/PeripheralPins.c | 2 +- .../STM32WBAxx/WBA55H(E-G)F/boards_entry.txt | 1 - .../STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c | 2 +- variants/STM32WBAxx/WBA5MMGH/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32WBAxx/WBA63C(G-I)U/PeripheralPins.c | 2 +- .../STM32WBAxx/WBA65C(G-I)U/PeripheralPins.c | 2 +- .../STM32WBAxx/WBA65R(G-I)V/PeripheralPins.c | 2 +- variants/STM32WBAxx/WBA6MOIH/PeripheralPins.c | 2 +- variants/STM32WBxx/WB10CCU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCUxE/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCY/PeripheralPins.c | 2 +- variants/STM32WBxx/WB1MMCH/PeripheralPins.c | 2 +- .../WB30CEUxA_WB50CGU/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32WBxx/WB5MMGH/PeripheralPins.c | 2 +- .../STM32WL3x/WL30K(8-B)V/PeripheralPins.c | 2 +- .../STM32WL3x/WL31C(8-B)V/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../WL33C(8-B-C)Vx(X)/PeripheralPins.c | 2 +- .../WL3RK(8-B)Vx(X)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32WLxx/WL5MOCHx(S)/PeripheralPins.c | 2 +- 873 files changed, 26435 insertions(+), 1056 deletions(-) create mode 100644 variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/PeripheralPins.c create mode 100644 variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/PinNamesVar.h create mode 100644 variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/boards_entry.txt create mode 100644 variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/generic_clock.c create mode 100644 variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/variant_generic.cpp create mode 100644 variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/variant_generic.h create mode 100644 variants/STM32H5xx/H543R(E-G)T_H553RGT/PeripheralPins.c create mode 100644 variants/STM32H5xx/H543R(E-G)T_H553RGT/PinNamesVar.h create mode 100644 variants/STM32H5xx/H543R(E-G)T_H553RGT/boards_entry.txt rename variants/{STM32L4xx/L4P5R(G-E)T_L4Q5RGT => STM32H5xx/H543R(E-G)T_H553RGT}/generic_clock.c (82%) create mode 100644 variants/STM32H5xx/H543R(E-G)T_H553RGT/variant_generic.cpp create mode 100644 variants/STM32H5xx/H543R(E-G)T_H553RGT/variant_generic.h create mode 100644 variants/STM32H5xx/H543UGY_H553UGY/PeripheralPins.c create mode 100644 variants/STM32H5xx/H543UGY_H553UGY/PinNamesVar.h create mode 100644 variants/STM32H5xx/H543UGY_H553UGY/boards_entry.txt create mode 100644 variants/STM32H5xx/H543UGY_H553UGY/generic_clock.c create mode 100644 variants/STM32H5xx/H543UGY_H553UGY/variant_generic.cpp create mode 100644 variants/STM32H5xx/H543UGY_H553UGY/variant_generic.h create mode 100644 variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/PeripheralPins.c create mode 100644 variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/PinNamesVar.h create mode 100644 variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/boards_entry.txt create mode 100644 variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/generic_clock.c create mode 100644 variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/variant_generic.cpp create mode 100644 variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/variant_generic.h create mode 100644 variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/PeripheralPins.c create mode 100644 variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/PinNamesVar.h create mode 100644 variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/boards_entry.txt create mode 100644 variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/generic_clock.c create mode 100644 variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/variant_generic.cpp create mode 100644 variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/variant_generic.h rename variants/STM32L4xx/{L4P5R(G-E)T_L4Q5RGT => L4P5R(G-E)T}/PeripheralPins.c (99%) rename variants/STM32L4xx/{L4P5R(G-E)T_L4Q5RGT => L4P5R(G-E)T}/PinNamesVar.h (100%) rename variants/STM32L4xx/{L4P5R(G-E)T_L4Q5RGT => L4P5R(G-E)T}/boards_entry.txt (69%) create mode 100644 variants/STM32L4xx/L4P5R(G-E)T/generic_clock.c rename variants/STM32L4xx/{L4P5R(G-E)T_L4Q5RGT => L4P5R(G-E)T}/variant_generic.cpp (94%) rename variants/STM32L4xx/{L4P5R(G-E)T_L4Q5RGT => L4P5R(G-E)T}/variant_generic.h (100%) delete mode 100644 variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/CMakeLists.txt create mode 100644 variants/STM32L4xx/L4Q5RGT/PeripheralPins.c create mode 100644 variants/STM32L4xx/L4Q5RGT/PinNamesVar.h create mode 100644 variants/STM32L4xx/L4Q5RGT/boards_entry.txt create mode 100644 variants/STM32L4xx/L4Q5RGT/generic_clock.c create mode 100644 variants/STM32L4xx/L4Q5RGT/variant_generic.cpp create mode 100644 variants/STM32L4xx/L4Q5RGT/variant_generic.h create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/PeripheralPins.c create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/PinNamesVar.h create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/boards_entry.txt create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/generic_clock.c create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/variant_generic.cpp create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/variant_generic.h create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/generic_clock.c create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/variant_generic.h create mode 100644 variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/generic_clock.c create mode 100644 variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/variant_generic.h create mode 100644 variants/STM32U3xx/U335K(B-C)U_U345KCU/PeripheralPins.c create mode 100644 variants/STM32U3xx/U335K(B-C)U_U345KCU/PinNamesVar.h create mode 100644 variants/STM32U3xx/U335K(B-C)U_U345KCU/boards_entry.txt create mode 100644 variants/STM32U3xx/U335K(B-C)U_U345KCU/generic_clock.c create mode 100644 variants/STM32U3xx/U335K(B-C)U_U345KCU/variant_generic.cpp create mode 100644 variants/STM32U3xx/U335K(B-C)U_U345KCU/variant_generic.h create mode 100644 variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/generic_clock.c create mode 100644 variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/variant_generic.h create mode 100644 variants/STM32U3xx/U335R(B-C)I_U345RCI/PeripheralPins.c create mode 100644 variants/STM32U3xx/U335R(B-C)I_U345RCI/PinNamesVar.h create mode 100644 variants/STM32U3xx/U335R(B-C)I_U345RCI/boards_entry.txt create mode 100644 variants/STM32U3xx/U335R(B-C)I_U345RCI/generic_clock.c create mode 100644 variants/STM32U3xx/U335R(B-C)I_U345RCI/variant_generic.cpp create mode 100644 variants/STM32U3xx/U335R(B-C)I_U345RCI/variant_generic.h create mode 100644 variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/generic_clock.c create mode 100644 variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/variant_generic.h create mode 100644 variants/STM32U3xx/U335R(B-C)T_U345RCT/PeripheralPins.c create mode 100644 variants/STM32U3xx/U335R(B-C)T_U345RCT/PinNamesVar.h create mode 100644 variants/STM32U3xx/U335R(B-C)T_U345RCT/boards_entry.txt create mode 100644 variants/STM32U3xx/U335R(B-C)T_U345RCT/generic_clock.c create mode 100644 variants/STM32U3xx/U335R(B-C)T_U345RCT/variant_generic.cpp create mode 100644 variants/STM32U3xx/U335R(B-C)T_U345RCT/variant_generic.h create mode 100644 variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/generic_clock.c create mode 100644 variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/variant_generic.h create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/boards_entry.txt create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/generic_clock.c create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/variant_generic.h create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/generic_clock.c create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/variant_generic.h create mode 100644 variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/generic_clock.c create mode 100644 variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/variant_generic.h create mode 100644 variants/STM32U3xx/U356K(C-E)U_U366KEU/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356K(C-E)U_U366KEU/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356K(C-E)U_U366KEU/boards_entry.txt create mode 100644 variants/STM32U3xx/U356K(C-E)U_U366KEU/generic_clock.c create mode 100644 variants/STM32U3xx/U356K(C-E)U_U366KEU/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356K(C-E)U_U366KEU/variant_generic.h create mode 100644 variants/STM32U3xx/U356R(C-E)I_U366REI/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356R(C-E)I_U366REI/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356R(C-E)I_U366REI/boards_entry.txt create mode 100644 variants/STM32U3xx/U356R(C-E)I_U366REI/generic_clock.c create mode 100644 variants/STM32U3xx/U356R(C-E)I_U366REI/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356R(C-E)I_U366REI/variant_generic.h create mode 100644 variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/generic_clock.c create mode 100644 variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/variant_generic.h create mode 100644 variants/STM32U3xx/U356R(C-E)T_U366RET/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356R(C-E)T_U366RET/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356R(C-E)T_U366RET/boards_entry.txt create mode 100644 variants/STM32U3xx/U356R(C-E)T_U366RET/generic_clock.c create mode 100644 variants/STM32U3xx/U356R(C-E)T_U366RET/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356R(C-E)T_U366RET/variant_generic.h create mode 100644 variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/generic_clock.c create mode 100644 variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/variant_generic.h create mode 100644 variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/generic_clock.c create mode 100644 variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/variant_generic.h create mode 100644 variants/STM32U3xx/U356V(C-E)I_U366VEI/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356V(C-E)I_U366VEI/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356V(C-E)I_U366VEI/boards_entry.txt create mode 100644 variants/STM32U3xx/U356V(C-E)I_U366VEI/generic_clock.c create mode 100644 variants/STM32U3xx/U356V(C-E)I_U366VEI/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356V(C-E)I_U366VEI/variant_generic.h create mode 100644 variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/generic_clock.c create mode 100644 variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/variant_generic.h create mode 100644 variants/STM32U3xx/U356V(C-E)T_U366VET/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356V(C-E)T_U366VET/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356V(C-E)T_U366VET/boards_entry.txt create mode 100644 variants/STM32U3xx/U356V(C-E)T_U366VET/generic_clock.c create mode 100644 variants/STM32U3xx/U356V(C-E)T_U366VET/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356V(C-E)T_U366VET/variant_generic.h create mode 100644 variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/PeripheralPins.c create mode 100644 variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/PinNamesVar.h create mode 100644 variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/boards_entry.txt create mode 100644 variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/generic_clock.c create mode 100644 variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/variant_generic.cpp create mode 100644 variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/variant_generic.h diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)/PeripheralPins.c b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)/PeripheralPins.c index b8a898ecbd..929c97febf 100644 --- a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C011D6Yx.xml, STM32C011F(4-6)Px.xml * STM32C011F(4-6)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c b/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c index 96f196402e..31cb4b715a 100644 --- a/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c +++ b/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C011J(4-6)Mx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c index 6782d13e63..f773ad3a75 100644 --- a/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031C(4-6)Tx.xml, STM32C031C(4-6)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031F(4-6)P/PeripheralPins.c b/variants/STM32C0xx/C031F(4-6)P/PeripheralPins.c index 7ff2cfcae0..06aeef8db6 100644 --- a/variants/STM32C0xx/C031F(4-6)P/PeripheralPins.c +++ b/variants/STM32C0xx/C031F(4-6)P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031F(4-6)Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c b/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c index b6e8343381..a9bdcd93d5 100644 --- a/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c +++ b/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031G(4-6)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c index 1f3405a80f..f424b23d2e 100644 --- a/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031K(4-6)Tx.xml, STM32C031K(4-6)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c index cfb1cd0dc9..1f5947a19d 100644 --- a/variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C051C6Tx.xml, STM32C051C6Ux.xml * STM32C051C8Tx.xml, STM32C051C8Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c index 04020e5713..56a8ae572f 100644 --- a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c +++ b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C051D8Yx.xml, STM32C051F6Px.xml * STM32C051F8Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c b/variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c index 13bea1a0fd..78566fc163 100644 --- a/variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c +++ b/variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C051G6Ux.xml, STM32C051G8Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c b/variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c index 15ea301c55..bbeb08423e 100644 --- a/variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c +++ b/variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C051K6Tx.xml, STM32C051K6Ux.xml * STM32C051K8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c index 2141e4b168..346a4aa63e 100644 --- a/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071C8Tx.xml, STM32C071C8Ux.xml * STM32C071CBTx.xml, STM32C071CBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c b/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c index 1a717543a2..615260516f 100644 --- a/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c +++ b/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071C8TxN.xml, STM32C071C8UxN.xml * STM32C071CBTxN.xml, STM32C071CBUxN.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c b/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c index 1a9ffc3e7f..81556aebd6 100644 --- a/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c +++ b/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071F8PxN.xml, STM32C071FBPxN.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c b/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c index 594cb2442b..a027bcf894 100644 --- a/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c +++ b/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071F8Px.xml, STM32C071FBPx.xml * STM32C071FBYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c b/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c index a690c3eb44..4e6bf76f51 100644 --- a/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c +++ b/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071G8Ux.xml, STM32C071GBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c b/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c index 389413f265..592ef678a6 100644 --- a/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c +++ b/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071G8UxN.xml, STM32C071GBUxN.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c index af571dc590..394cef63a0 100644 --- a/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071K8Tx.xml, STM32C071K8Ux.xml * STM32C071KBTx.xml, STM32C071KBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c b/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c index adc6fe2bb1..c33e131506 100644 --- a/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c +++ b/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071K8TxN.xml, STM32C071K8UxN.xml * STM32C071KBTxN.xml, STM32C071KBUxN.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c b/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c index 0beaa21f47..7077a13457 100644 --- a/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c +++ b/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071R8Tx.xml, STM32C071RBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c b/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c index 9d01a9d233..f990b569c8 100644 --- a/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c +++ b/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071R8TxN.xml, STM32C071RBIxN.xml * STM32C071RBTxN.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c index 4458de8ff6..16dca97033 100644 --- a/variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C091CBTx.xml, STM32C091CBUx.xml * STM32C091CCTx.xml, STM32C091CCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c b/variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c index 376f56da2e..d562fa6a1b 100644 --- a/variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c +++ b/variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C091ECYx.xml, STM32C091FBPx.xml * STM32C091FCPx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c b/variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c index 144a422c56..505a9e78d1 100644 --- a/variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c +++ b/variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C091GBUx.xml, STM32C091GCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c index 07c84645f3..85202f09c2 100644 --- a/variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C091KBTx.xml, STM32C091KBUx.xml * STM32C091KCTx.xml, STM32C091KCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c b/variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c index 65d2c1731c..b7cd73a5e2 100644 --- a/variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c +++ b/variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C091RBTx.xml, STM32C091RCIx.xml * STM32C091RCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C092C(B-C)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C092C(B-C)(T-U)/PeripheralPins.c index cb9abdb4d0..b83cb3c349 100644 --- a/variants/STM32C0xx/C092C(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C092C(B-C)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C092CBTx.xml, STM32C092CBUx.xml * STM32C092CCTx.xml, STM32C092CCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c b/variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c index 78fe2776f9..578b3e8201 100644 --- a/variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c +++ b/variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C092ECYx.xml, STM32C092FBPx.xml * STM32C092FCPx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c b/variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c index 4965b15ecd..753e3ca5ab 100644 --- a/variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c +++ b/variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C092GBUx.xml, STM32C092GCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c index e45acc440f..5c87541427 100644 --- a/variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C092KBTx.xml, STM32C092KBUx.xml * STM32C092KCTx.xml, STM32C092KCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C092RBT_C092RC(I-T)/PeripheralPins.c b/variants/STM32C0xx/C092RBT_C092RC(I-T)/PeripheralPins.c index ab9c261a97..7a4a4e3e9e 100644 --- a/variants/STM32C0xx/C092RBT_C092RC(I-T)/PeripheralPins.c +++ b/variants/STM32C0xx/C092RBT_C092RC(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C092RBTx.xml, STM32C092RCIx.xml * STM32C092RCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030C6T/PeripheralPins.c b/variants/STM32F0xx/F030C6T/PeripheralPins.c index f4c152510b..d5d7a353a9 100644 --- a/variants/STM32F0xx/F030C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F030C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030C6Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030C8T/PeripheralPins.c b/variants/STM32F0xx/F030C8T/PeripheralPins.c index d9c2cdd9bc..f67f79476e 100644 --- a/variants/STM32F0xx/F030C8T/PeripheralPins.c +++ b/variants/STM32F0xx/F030C8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030C8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030CCT/PeripheralPins.c b/variants/STM32F0xx/F030CCT/PeripheralPins.c index 57415269e3..d3a0f57d0d 100644 --- a/variants/STM32F0xx/F030CCT/PeripheralPins.c +++ b/variants/STM32F0xx/F030CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030CCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030F4P/PeripheralPins.c b/variants/STM32F0xx/F030F4P/PeripheralPins.c index 1d59745b36..1487ab865f 100644 --- a/variants/STM32F0xx/F030F4P/PeripheralPins.c +++ b/variants/STM32F0xx/F030F4P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030F4Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030K6T/PeripheralPins.c b/variants/STM32F0xx/F030K6T/PeripheralPins.c index e10a252984..5c9cc4761e 100644 --- a/variants/STM32F0xx/F030K6T/PeripheralPins.c +++ b/variants/STM32F0xx/F030K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030K6Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030R8T/PeripheralPins.c b/variants/STM32F0xx/F030R8T/PeripheralPins.c index 0e4f3c10da..87f087324f 100644 --- a/variants/STM32F0xx/F030R8T/PeripheralPins.c +++ b/variants/STM32F0xx/F030R8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030R8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030RCT/PeripheralPins.c b/variants/STM32F0xx/F030RCT/PeripheralPins.c index ae1b4b092f..06abb86d9f 100644 --- a/variants/STM32F0xx/F030RCT/PeripheralPins.c +++ b/variants/STM32F0xx/F030RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030RCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c b/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c index f4ad659ecd..ffbae95f5d 100644 --- a/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c +++ b/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031C(4-6)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c b/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c index fdb848a6ca..ab6823b9ef 100644 --- a/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031E6Yx.xml, STM32F038E6Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c b/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c index 67a1de2ca0..25340f22f1 100644 --- a/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c +++ b/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031F(4-6)Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c index 88a0488f41..af5ca45bac 100644 --- a/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031G(4-6)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c index 1a5f8b789f..050b76d122 100644 --- a/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031K(4-6)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031K6T/PeripheralPins.c b/variants/STM32F0xx/F031K6T/PeripheralPins.c index 6bc602c48e..389f20a2c4 100644 --- a/variants/STM32F0xx/F031K6T/PeripheralPins.c +++ b/variants/STM32F0xx/F031K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031K6Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038C6T/PeripheralPins.c b/variants/STM32F0xx/F038C6T/PeripheralPins.c index 341c20e38c..6130dbdb4f 100644 --- a/variants/STM32F0xx/F038C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F038C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038C6Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038F6P/PeripheralPins.c b/variants/STM32F0xx/F038F6P/PeripheralPins.c index fdcce49177..a42e9b0d21 100644 --- a/variants/STM32F0xx/F038F6P/PeripheralPins.c +++ b/variants/STM32F0xx/F038F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038F6Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038G6U/PeripheralPins.c b/variants/STM32F0xx/F038G6U/PeripheralPins.c index ecc521fa31..11a44bbbd9 100644 --- a/variants/STM32F0xx/F038G6U/PeripheralPins.c +++ b/variants/STM32F0xx/F038G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038G6Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038K6U/PeripheralPins.c b/variants/STM32F0xx/F038K6U/PeripheralPins.c index 6dd11ef48b..afc1906cf1 100644 --- a/variants/STM32F0xx/F038K6U/PeripheralPins.c +++ b/variants/STM32F0xx/F038K6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038K6Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c b/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c index a9b7a7b233..aeef2e6d30 100644 --- a/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042C(4-6)Tx.xml, STM32F042C(4-6)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c b/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c index d519ad7500..184bcdc3ff 100644 --- a/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c +++ b/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042F4Px.xml, STM32F042F6Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c index 05339d29de..c009189803 100644 --- a/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042G(4-6)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c b/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c index 4a8ac1e43b..b6428af84a 100644 --- a/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c +++ b/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042K(4-6)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c index e2fb9e1816..568ca57fb6 100644 --- a/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042K(4-6)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042T6Y/PeripheralPins.c b/variants/STM32F0xx/F042T6Y/PeripheralPins.c index a945083ee6..254d5d4623 100644 --- a/variants/STM32F0xx/F042T6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F042T6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042T6Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048C6U/PeripheralPins.c b/variants/STM32F0xx/F048C6U/PeripheralPins.c index 5429a2c212..7c8faeb81b 100644 --- a/variants/STM32F0xx/F048C6U/PeripheralPins.c +++ b/variants/STM32F0xx/F048C6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048C6Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048G6U/PeripheralPins.c b/variants/STM32F0xx/F048G6U/PeripheralPins.c index 8aa49e3ed1..93dd2aff82 100644 --- a/variants/STM32F0xx/F048G6U/PeripheralPins.c +++ b/variants/STM32F0xx/F048G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048G6Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048T6Y/PeripheralPins.c b/variants/STM32F0xx/F048T6Y/PeripheralPins.c index 9b9a04820b..57a4077d3e 100644 --- a/variants/STM32F0xx/F048T6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F048T6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048T6Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c index 39e6487ade..634e643a80 100644 --- a/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C4Tx.xml, STM32F051C4Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c index 35a68b1b66..9980e26856 100644 --- a/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C6Tx.xml, STM32F051C6Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c index 7b7a908343..7be570b0e6 100644 --- a/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C8Tx.xml, STM32F051C8Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c b/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c index 43814237f3..66b54af26e 100644 --- a/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c +++ b/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K6Tx.xml, STM32F051K8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c b/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c index 9b2a821b14..7ce08b0ebc 100644 --- a/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c +++ b/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K6Ux.xml, STM32F051K8Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K4T/PeripheralPins.c b/variants/STM32F0xx/F051K4T/PeripheralPins.c index 294a92626f..e194e351a1 100644 --- a/variants/STM32F0xx/F051K4T/PeripheralPins.c +++ b/variants/STM32F0xx/F051K4T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K4Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K4U/PeripheralPins.c b/variants/STM32F0xx/F051K4U/PeripheralPins.c index 1857848e46..6697624d94 100644 --- a/variants/STM32F0xx/F051K4U/PeripheralPins.c +++ b/variants/STM32F0xx/F051K4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K4Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R4T/PeripheralPins.c b/variants/STM32F0xx/F051R4T/PeripheralPins.c index 731301f8d3..b632d95bec 100644 --- a/variants/STM32F0xx/F051R4T/PeripheralPins.c +++ b/variants/STM32F0xx/F051R4T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R4Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R6T/PeripheralPins.c b/variants/STM32F0xx/F051R6T/PeripheralPins.c index 44f6847093..67a235ba03 100644 --- a/variants/STM32F0xx/F051R6T/PeripheralPins.c +++ b/variants/STM32F0xx/F051R6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R6Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c b/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c index 5eb3a10e34..5018a06be8 100644 --- a/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R8Hx.xml, STM32F051R8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051T8Y/PeripheralPins.c b/variants/STM32F0xx/F051T8Y/PeripheralPins.c index 4f7256ae97..f1f094f940 100644 --- a/variants/STM32F0xx/F051T8Y/PeripheralPins.c +++ b/variants/STM32F0xx/F051T8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051T8Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058C8U/PeripheralPins.c b/variants/STM32F0xx/F058C8U/PeripheralPins.c index c84f74a8e4..eed0bd2879 100644 --- a/variants/STM32F0xx/F058C8U/PeripheralPins.c +++ b/variants/STM32F0xx/F058C8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058C8Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c b/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c index 4c3d645f8b..26e3431af7 100644 --- a/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058R8Hx.xml, STM32F058R8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058T8Y/PeripheralPins.c b/variants/STM32F0xx/F058T8Y/PeripheralPins.c index 9a05722753..e1fcd9b2b2 100644 --- a/variants/STM32F0xx/F058T8Y/PeripheralPins.c +++ b/variants/STM32F0xx/F058T8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058T8Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070C6T/PeripheralPins.c b/variants/STM32F0xx/F070C6T/PeripheralPins.c index ed3d15d315..1c57a00d02 100644 --- a/variants/STM32F0xx/F070C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F070C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070C6Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070CBT/PeripheralPins.c b/variants/STM32F0xx/F070CBT/PeripheralPins.c index 7ce1e58533..35aab3e270 100644 --- a/variants/STM32F0xx/F070CBT/PeripheralPins.c +++ b/variants/STM32F0xx/F070CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070CBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070F6P/PeripheralPins.c b/variants/STM32F0xx/F070F6P/PeripheralPins.c index 71e6fe8680..867e592b25 100644 --- a/variants/STM32F0xx/F070F6P/PeripheralPins.c +++ b/variants/STM32F0xx/F070F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070F6Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070RBT/PeripheralPins.c b/variants/STM32F0xx/F070RBT/PeripheralPins.c index 4cb60322d0..bd4158b068 100644 --- a/variants/STM32F0xx/F070RBT/PeripheralPins.c +++ b/variants/STM32F0xx/F070RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070RBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c index c085f33fed..763d012f66 100644 --- a/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F071C(8-B)Tx.xml, STM32F071C(8-B)Ux.xml * STM32F071CBYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F071RBT/PeripheralPins.c b/variants/STM32F0xx/F071RBT/PeripheralPins.c index 32dc06838d..6c12997d5f 100644 --- a/variants/STM32F0xx/F071RBT/PeripheralPins.c +++ b/variants/STM32F0xx/F071RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F071RBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c b/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c index 9f5fb38f50..2ea1fd06d8 100644 --- a/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F071V(8-B)Hx.xml, STM32F071V(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c index 07798003a1..ccb9c21eb4 100644 --- a/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F072C(8-B)Tx.xml, STM32F072C(8-B)Ux.xml * STM32F072CBYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c b/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c index 29e3511a17..543189b6e5 100644 --- a/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F072R(8-B)Tx.xml, STM32F072RBHx.xml * STM32F072RBIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c b/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c index 500c426f65..f58039302c 100644 --- a/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F072V(8-B)Hx.xml, STM32F072V(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c index 08f7b1e449..1366bf5d25 100644 --- a/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F078CBTx.xml, STM32F078CBUx.xml * STM32F078CBYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c b/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c index 586268a247..aee444660a 100644 --- a/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F078RBHx.xml, STM32F078RBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c b/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c index fd77fcdc89..9b232bbe05 100644 --- a/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F078VBHx.xml, STM32F078VBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c b/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c index a5113e47fa..8287f7ac05 100644 --- a/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F091C(B-C)Tx.xml, STM32F091C(B-C)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c b/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c index f3cbae29c6..906bb4798f 100644 --- a/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F091R(B-C)Tx.xml, STM32F091RCHx.xml * STM32F091RCYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c b/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c index f99d6cd93a..648b450006 100644 --- a/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F091V(B-C)Tx.xml, STM32F091VCHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c b/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c index 7b5bd1b44e..71ff260f0c 100644 --- a/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F098CCTx.xml, STM32F098CCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c b/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c index bd09513419..bed84ce65f 100644 --- a/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F098RCHx.xml, STM32F098RCTx.xml * STM32F098RCYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c b/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c index 3291204b98..59d192d273 100644 --- a/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F098VCHx.xml, STM32F098VCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c index 6edcfc0594..9b3d67e04a 100644 --- a/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100C(4-6)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c index e4f5249f2a..1ed0b4f559 100644 --- a/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100C(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c b/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c index 6fd53cc5fc..708259782d 100644 --- a/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(4-6)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c index 686d9e0a36..0de265e7e6 100644 --- a/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(4-6)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c b/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c index 9416bb610d..7ccff55ecd 100644 --- a/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(8-B)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c index 7e49d06a95..93790d122d 100644 --- a/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c index 10db8d0824..50e558cde6 100644 --- a/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(C-D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c index 7e5b4a688d..21be7dc892 100644 --- a/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100V(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c index 24e61ca86c..8773c787e4 100644 --- a/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100V(C-D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c index d85f675981..84fc90ee65 100644 --- a/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c index 275ea58d05..6238a07eb1 100644 --- a/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101C(4-6)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c b/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c index 88f1bbac43..de67562e13 100644 --- a/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101C(8-B)Tx.xml, STM32F101C(8-B)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c index 6c4755341a..e8101a3174 100644 --- a/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(4-6)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c index a8a10b7109..450229b64a 100644 --- a/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c index 6a7fbc1c14..067952cc57 100644 --- a/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(C-D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c index a4ccf34c92..724297dbe5 100644 --- a/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(F-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101RBH/PeripheralPins.c b/variants/STM32F1xx/F101RBH/PeripheralPins.c index f6c8a8b170..cc235358cd 100644 --- a/variants/STM32F1xx/F101RBH/PeripheralPins.c +++ b/variants/STM32F1xx/F101RBH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101RBHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c b/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c index 8fa28d12ee..b286eb700a 100644 --- a/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c +++ b/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101T(4-6)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c b/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c index 17b5721cad..18c43a6d0a 100644 --- a/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c +++ b/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101T(8-B)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c index acb6026974..f02abbb014 100644 --- a/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c index 67337ed9a6..b408b47a8d 100644 --- a/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(C-D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c index d903e9eaca..99a7b1afff 100644 --- a/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(F-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c index 9bc7733f11..ada81510e2 100644 --- a/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c index d1227058ca..8196940721 100644 --- a/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101Z(F-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c index 140950dffb..7bfbf3bdda 100644 --- a/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102C(4-6)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c index 35d76f20a2..72a817fb55 100644 --- a/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102C(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c index 93e5396219..439bdb93c8 100644 --- a/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102R(4-6)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c index 8484045270..f4dd747e2b 100644 --- a/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102R(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c b/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c index 3423afea41..a007a5c073 100644 --- a/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103C(4-6)Tx.xml, STM32F103C6Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c b/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c index c29bfb1098..6c9666087d 100644 --- a/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103C(8-B)Tx.xml, STM32F103CBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c b/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c index 0985ee93fb..0c2d235efe 100644 --- a/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(4-6)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c index 18a4bd3719..c0ab0d26cc 100644 --- a/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(4-6)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c b/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c index e5f3e981e8..0c81b5493b 100644 --- a/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(8-B)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c index 7f8698277f..03d533bd8f 100644 --- a/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c index 3f80d82d3b..67f7c62dcc 100644 --- a/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(C-D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c b/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c index e08ffffe3f..9689f6a72c 100644 --- a/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(C-D-E)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c index 986e9d3ec7..022d2e3467 100644 --- a/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(F-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c b/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c index 4fd366253f..409f55c239 100644 --- a/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c +++ b/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103T(4-6)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c b/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c index 81e88c7532..985c813de2 100644 --- a/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c +++ b/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103T(8-B)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c index 1380644009..01399979a8 100644 --- a/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103V(C-D-E)Hx.xml, STM32F103V(C-D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c index 9a38169c63..52a925c1f2 100644 --- a/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103V(F-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c b/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c index 43514a4c5f..858c6c523c 100644 --- a/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F103V(8-B)Hx.xml, STM32F103V(8-B)Tx.xml * STM32F103VBIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c index 4b8c95b880..965ecbb70c 100644 --- a/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103Z(C-D-E)Hx.xml, STM32F103Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c index d9d43f6bf2..13f466c1eb 100644 --- a/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103Z(F-G)Hx.xml, STM32F103Z(F-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c b/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c index 4d4f6061d3..a4c47d91bb 100644 --- a/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F105R(8-B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c b/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c index 8841bbcb27..fdd31b7aaf 100644 --- a/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c +++ b/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F105V(8-B)Hx.xml, STM32F105V(8-B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c b/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c index 07b61f83cd..f451c98242 100644 --- a/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c +++ b/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F107R(B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c b/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c index c02ce98d66..333388b7bd 100644 --- a/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F107V(B-C)Tx.xml, STM32F107VCHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c index f8f77b39ee..9da9c0620f 100644 --- a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F205R(B-C-E-F-G)Tx.xml, STM32F205R(E-G)Yx.xml * STM32F205RGEx.xml, STM32F215R(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c index 146b52f438..302026f842 100644 --- a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F205V(B-C-E-F-G)Tx.xml, STM32F215V(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c index 1d8f5c8efb..cfc8fc38b4 100644 --- a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F205Z(C-E-F-G)Tx.xml, STM32F215Z(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c index c5564c1c01..929f6a57e8 100644 --- a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F207I(C-E-F-G)Hx.xml, STM32F207I(C-E-F-G)Tx.xml * STM32F217I(E-G)Hx.xml, STM32F217I(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c index 0c1ffdb5b7..d4e41b1cca 100644 --- a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F207V(C-E-F-G)Tx.xml, STM32F217V(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c index 49c027bbb6..720a4d1912 100644 --- a/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F207Z(C-E-F-G)Tx.xml, STM32F217Z(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c index f86b603a62..efd22e5822 100644 --- a/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301C(6-8)Tx.xml, STM32F301C8Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c index 883109cc70..bfcd6552ea 100644 --- a/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301K(6-8)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c b/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c index f127d53b53..23129ff11e 100644 --- a/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301K(6-8)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c index af84c9b89a..9c2a0495dd 100644 --- a/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301R(6-8)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c index e262089c8d..c8401eeff7 100644 --- a/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302C(B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c index 6380dd8ae6..1552e7667b 100644 --- a/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302C(6-8)Tx.xml, STM32F302C8Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c b/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c index 242659ea55..80e48324d0 100644 --- a/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302K(6-8)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c index 95cbb71d7d..f002ac7e3e 100644 --- a/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(6-8)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c index 7dd881cc57..b1bcc4989f 100644 --- a/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c index abc1ba413b..541b582427 100644 --- a/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c index 294f7de130..6060349e64 100644 --- a/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302V(B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c index df47aea2a8..93b34e01ac 100644 --- a/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302V(D-E)Hx.xml, STM32F302V(D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302VCY/PeripheralPins.c b/variants/STM32F3xx/F302VCY/PeripheralPins.c index ec8bad4c7f..0ec9d7f352 100644 --- a/variants/STM32F3xx/F302VCY/PeripheralPins.c +++ b/variants/STM32F3xx/F302VCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302VCYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c index 13a97a51ff..e911202d62 100644 --- a/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302Z(D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c index e54e867135..58fa91da3d 100644 --- a/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C(6-8)Tx.xml, STM32F334C(4-6-8)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c index 8fa97a4e5f..6759d9faee 100644 --- a/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C(B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c b/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c index a1f12a861e..f06fddac53 100644 --- a/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c +++ b/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C8Yx.xml, STM32F334C8Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c index fdaa781dac..ecde07086d 100644 --- a/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303K(6-8)Tx.xml, STM32F334K(4-6-8)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c b/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c index 1e5e388eba..eaff78c5be 100644 --- a/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303K(6-8)Ux.xml, STM32F334K(4-6-8)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c index ee70e3d382..3a4d1e141e 100644 --- a/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(6-8)Tx.xml, STM32F334R(6-8)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c index 5e07a3abb7..ae8c867499 100644 --- a/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c index ff5e97623c..b78ebf7a03 100644 --- a/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c index d6e2d44c02..1f68a11e5d 100644 --- a/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303V(B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c index 748e5dfe5e..8d84024332 100644 --- a/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303V(D-E)Hx.xml, STM32F303V(D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303VCY/PeripheralPins.c b/variants/STM32F3xx/F303VCY/PeripheralPins.c index 08f9ca83f6..3a756e0a8a 100644 --- a/variants/STM32F3xx/F303VCY/PeripheralPins.c +++ b/variants/STM32F3xx/F303VCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303VCYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303VEY/PeripheralPins.c b/variants/STM32F3xx/F303VEY/PeripheralPins.c index 8cb85c6b21..2ab8a50819 100644 --- a/variants/STM32F3xx/F303VEY/PeripheralPins.c +++ b/variants/STM32F3xx/F303VEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303VEYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c index 332611d7c1..7059db319d 100644 --- a/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303Z(D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c index 75023c26f8..b55576decf 100644 --- a/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F318C8Tx.xml, STM32F318C8Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F318K8U/PeripheralPins.c b/variants/STM32F3xx/F318K8U/PeripheralPins.c index c617ccf00a..d143567d9b 100644 --- a/variants/STM32F3xx/F318K8U/PeripheralPins.c +++ b/variants/STM32F3xx/F318K8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F318K8Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F328C8T/PeripheralPins.c b/variants/STM32F3xx/F328C8T/PeripheralPins.c index 2e57acf35a..3b147735ff 100644 --- a/variants/STM32F3xx/F328C8T/PeripheralPins.c +++ b/variants/STM32F3xx/F328C8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F328C8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358CCT/PeripheralPins.c b/variants/STM32F3xx/F358CCT/PeripheralPins.c index 6ad4c94583..e401d28656 100644 --- a/variants/STM32F3xx/F358CCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358CCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358RCT/PeripheralPins.c b/variants/STM32F3xx/F358RCT/PeripheralPins.c index d6962287c1..80d4ab5944 100644 --- a/variants/STM32F3xx/F358RCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358RCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358VCT/PeripheralPins.c b/variants/STM32F3xx/F358VCT/PeripheralPins.c index 8b4c8f5b2b..7eaac07b76 100644 --- a/variants/STM32F3xx/F358VCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358VCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358VCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c b/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c index 270b395353..55fe19b928 100644 --- a/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373C(8-B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c b/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c index aec6e77eb0..f72db0756e 100644 --- a/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373R(8-B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c index 313f0d4398..ac78efc96b 100644 --- a/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373V(8-B-C)Hx.xml, STM32F373V(8-B-C)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378CCT/PeripheralPins.c b/variants/STM32F3xx/F378CCT/PeripheralPins.c index 8c3bd3a65d..07e7852158 100644 --- a/variants/STM32F3xx/F378CCT/PeripheralPins.c +++ b/variants/STM32F3xx/F378CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378CCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c index 7e51ad5216..6edc9fe665 100644 --- a/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378RCTx.xml, STM32F378RCYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c b/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c index bc8ef0c359..57a0305f78 100644 --- a/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378VCHx.xml, STM32F378VCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F398VET/PeripheralPins.c b/variants/STM32F3xx/F398VET/PeripheralPins.c index 2ce5a1ff54..b6ec9f5415 100644 --- a/variants/STM32F3xx/F398VET/PeripheralPins.c +++ b/variants/STM32F3xx/F398VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F398VETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c b/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c index c23ea46d3d..95f0214573 100644 --- a/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F401C(B-C)Ux.xml, STM32F401C(B-C)Yx.xml * STM32F401C(D-E)Ux.xml, STM32F401C(D-E)Yx.xml * STM32F401CCFx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c b/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c index 90c453edbf..a5a78b3c1d 100644 --- a/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401R(B-C)Tx.xml, STM32F401R(D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c b/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c index 241ffb0550..e178312064 100644 --- a/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c +++ b/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401V(B-C)Hx.xml, STM32F401V(D-E)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c b/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c index eb075f8b6e..32d048e3ad 100644 --- a/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401V(B-C)Tx.xml, STM32F401V(D-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c b/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c index e336d4215c..98d5fb5605 100644 --- a/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c +++ b/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405O(E-G)Yx.xml, STM32F415OGYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c b/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c index 9d27b98bb0..b692c1e023 100644 --- a/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405RGTx.xml, STM32F415RGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c b/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c index 2921423078..ae021a50db 100644 --- a/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405VGTx.xml, STM32F415VGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c b/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c index 2d65af1923..ac70b27c21 100644 --- a/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405ZGTx.xml, STM32F415ZGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c index d33d8d2b68..98222dd1ba 100644 --- a/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F407I(E-G)Hx.xml, STM32F407I(E-G)Tx.xml * STM32F417I(E-G)Hx.xml, STM32F417I(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c index 4a3bfbe6f5..38515dabfd 100644 --- a/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F407V(E-G)Tx.xml, STM32F417V(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c index 2474166d22..0ce9552d3a 100644 --- a/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F407Z(E-G)Tx.xml, STM32F417Z(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c b/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c index c945f23d94..5d252810e2 100644 --- a/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c +++ b/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410C(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c b/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c index 1d4df0b3b0..d83e43fa2b 100644 --- a/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c +++ b/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410C(8-B)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c b/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c index b83b8b9ef6..611f84ba60 100644 --- a/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410R(8-B)Ix.xml, STM32F410R(8-B)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c b/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c index 1f02cb512b..67fe8e6b18 100644 --- a/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c +++ b/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410T(8-B)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c b/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c index 885fd695ae..484993db5a 100644 --- a/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411C(C-E)Ux.xml, STM32F411C(C-E)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c index d7038b7bc1..c061870750 100644 --- a/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411R(C-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c b/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c index f9e84fe3a3..e9b5fbf612 100644 --- a/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c +++ b/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411V(C-E)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c index 84e2dbbab3..2546413cc5 100644 --- a/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411V(C-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c b/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c index a530611ef0..f8c20f932f 100644 --- a/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c +++ b/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412C(E-G)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c b/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c index 3a20d22951..9313432cc8 100644 --- a/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c +++ b/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F412R(E-G)Tx.xml, STM32F412R(E-G)Yx.xml * STM32F412R(E-G)YxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c b/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c index 257140044d..c89a5b78ed 100644 --- a/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c +++ b/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412V(E-G)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c index 9e1d62a0c2..b32536714b 100644 --- a/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412V(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c b/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c index 44bd98bd9f..5dc0fdf80d 100644 --- a/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412Z(E-G)Jx.xml, STM32F412Z(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c b/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c index 782cbe9f82..179fb55032 100644 --- a/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c +++ b/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413C(G-H)Ux.xml, STM32F423CHUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c b/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c index 9e6db9530e..9e6176d759 100644 --- a/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c +++ b/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413M(G-H)Yx.xml, STM32F423MHYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c b/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c index e2e2072395..c5e256b877 100644 --- a/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c +++ b/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413R(G-H)Tx.xml, STM32F423RHTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c b/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c index acf2e61a60..959e80f000 100644 --- a/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c +++ b/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413V(G-H)Hx.xml, STM32F423VHHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c b/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c index cec23647f4..680aecad05 100644 --- a/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c +++ b/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413V(G-H)Tx.xml, STM32F423VHTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c b/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c index 3cfb21072e..95739fbd6a 100644 --- a/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F413Z(G-H)Jx.xml, STM32F413Z(G-H)Tx.xml * STM32F423ZHJx.xml, STM32F423ZHTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c b/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c index 71de65651a..85d12c23c6 100644 --- a/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c +++ b/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F427A(G-I)Hx.xml, STM32F429A(G-I)Hx.xml * STM32F437AIHx.xml, STM32F439AIHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c index 7540605ab1..199d6c10ce 100644 --- a/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32F429IITx.xml, STM32F437I(G-I)Hx.xml * STM32F437I(G-I)Tx.xml, STM32F439I(G-I)Hx.xml * STM32F439I(G-I)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c index 7d9a7b699d..363ca51a19 100644 --- a/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F427V(G-I)Tx.xml, STM32F429V(E-G)Tx.xml * STM32F429VITx.xml, STM32F437V(G-I)Tx.xml * STM32F439V(G-I)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c index cc4bb02451..d691387d11 100644 --- a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F429ZGYx.xml, STM32F429ZITx.xml * STM32F429ZIYx.xml, STM32F437Z(G-I)Tx.xml * STM32F439Z(G-I)Tx.xml, STM32F439Z(G-I)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c b/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c index 0638bbec0c..698a5d7092 100644 --- a/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c +++ b/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F429B(E-G-I)Tx.xml, STM32F429N(E-G)Hx.xml * STM32F429NIHx.xml, STM32F439B(G-I)Tx.xml * STM32F439N(G-I)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c b/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c index da079a533e..40c5dea64b 100644 --- a/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c +++ b/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446M(C-E)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c index 0bb54e8bed..d5d524235f 100644 --- a/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446R(C-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c index 4a95245336..659f3c03c9 100644 --- a/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446V(C-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c index d70f25bd0b..55357762ae 100644 --- a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F446Z(C-E)Hx.xml, STM32F446Z(C-E)Jx.xml * STM32F446Z(C-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c b/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c index 2bb5d55b78..26cd4054af 100644 --- a/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469A(E-G-I)Hx.xml, STM32F469A(E-G-I)Yx.xml * STM32F479A(G-I)Hx.xml, STM32F479A(G-I)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c b/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c index a69ed8a865..b44922ab62 100644 --- a/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c +++ b/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F469B(E-G-I)Tx.xml, STM32F469N(E-G)Hx.xml * STM32F469NIHx.xml, STM32F479B(G-I)Tx.xml * STM32F479N(G-I)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c index 99c60fd588..25adeae806 100644 --- a/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F469I(E-G)Tx.xml, STM32F469I(E-G-I)Hx.xml * STM32F469IITx.xml, STM32F479I(G-I)Hx.xml * STM32F479I(G-I)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c index 63e7ef5c79..7ab41eb0a5 100644 --- a/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469V(E-G)Tx.xml, STM32F469VITx.xml * STM32F479V(G-I)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c index eec62b1c28..ffd3ec28fd 100644 --- a/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469Z(E-G)Tx.xml, STM32F469ZITx.xml * STM32F479Z(G-I)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c b/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c index a9bc3787e4..743e71eed8 100644 --- a/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722I(C-E)Kx.xml, STM32F722I(C-E)Tx.xml * STM32F732IEKx.xml, STM32F732IETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c b/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c index db681e11f8..dad2b98b43 100644 --- a/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c +++ b/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722R(C-E)Tx.xml, STM32F730R8Tx.xml * STM32F732RETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c b/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c index 175bd98d3b..e53ad5b1a2 100644 --- a/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c +++ b/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722V(C-E)Tx.xml, STM32F730V8Tx.xml * STM32F732VETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c index 0164fec851..251845e246 100644 --- a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c +++ b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F722Z(C-E)Tx.xml, STM32F732ZETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c index 341347a0ef..1be6473f17 100644 --- a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F723I(C-E)Kx.xml, STM32F723I(C-E)Tx.xml * STM32F730I8Kx.xml, STM32F733IEKx.xml * STM32F733IETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -476,6 +476,21 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS {PB_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM {PB_15, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP +#else + {PA_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1 + {PB_1, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6 + {PC_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP + {PC_2, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR + {PC_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT + {PH_4, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT + {PI_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR #endif /* USE_USB_HS_IN_FS */ {NC, NP, 0} }; diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PinNamesVar.h b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PinNamesVar.h index 8c6fb4290f..cb9ccc56b6 100644 --- a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PinNamesVar.h +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PinNamesVar.h @@ -68,14 +68,36 @@ PC_11_ALT1 = PC_11 | ALT1, /* USB */ #ifdef USBCON - USB_OTG_FS_DM = PA_11, - USB_OTG_FS_DP = PA_12, - USB_OTG_FS_ID = PA_10, - USB_OTG_FS_SOF = PA_8, - USB_OTG_FS_VBUS = PA_9, - USB_OTG_HS_DM = PB_14, - USB_OTG_HS_DP = PB_15, - USB_OTG_HS_ID = PB_12, - USB_OTG_HS_SOF = PA_4, - USB_OTG_HS_VBUS = PB_13, + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + #ifdef USB_OTG_HS_ULPI_DIR_PC_2 + USB_OTG_HS_ULPI_DIR = PC_2, + #endif + #ifdef USB_OTG_HS_ULPI_DIR_PI_11 + USB_OTG_HS_ULPI_DIR = PI_11, + #endif + #ifdef USB_OTG_HS_ULPI_NXT_PC_3 + USB_OTG_HS_ULPI_NXT = PC_3, + #endif + #ifdef USB_OTG_HS_ULPI_NXT_PH_4 + USB_OTG_HS_ULPI_NXT = PH_4, + #endif + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, #endif diff --git a/variants/STM32F7xx/F723R(C-E)V/PeripheralPins.c b/variants/STM32F7xx/F723R(C-E)V/PeripheralPins.c index d0177ed2f6..763c4e8e52 100644 --- a/variants/STM32F7xx/F723R(C-E)V/PeripheralPins.c +++ b/variants/STM32F7xx/F723R(C-E)V/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F723RCVx.xml, STM32F723REVx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -352,6 +352,19 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS {PB_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM {PB_15, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP +#else + {PA_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1 + {PB_1, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6 + {PC_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP + {PC_2, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR + {PC_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT #endif /* USE_USB_HS_IN_FS */ {NC, NP, 0} }; diff --git a/variants/STM32F7xx/F723R(C-E)V/PinNamesVar.h b/variants/STM32F7xx/F723R(C-E)V/PinNamesVar.h index ab9e841ab3..1ea2e99c13 100644 --- a/variants/STM32F7xx/F723R(C-E)V/PinNamesVar.h +++ b/variants/STM32F7xx/F723R(C-E)V/PinNamesVar.h @@ -67,14 +67,26 @@ PC_11_ALT1 = PC_11 | ALT1, /* USB */ #ifdef USBCON - USB_OTG_FS_DM = PA_11, - USB_OTG_FS_DP = PA_12, - USB_OTG_FS_ID = PA_10, - USB_OTG_FS_SOF = PA_8, - USB_OTG_FS_VBUS = PA_9, - USB_OTG_HS_DM = PB_14, - USB_OTG_HS_DP = PB_15, - USB_OTG_HS_ID = PB_12, - USB_OTG_HS_SOF = PA_4, - USB_OTG_HS_VBUS = PB_13, + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PC_2, + USB_OTG_HS_ULPI_NXT = PC_3, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, #endif diff --git a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c index 6e6d0c8b01..9efc1f4f7c 100644 --- a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c +++ b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F723V(C-E)Tx.xml, STM32F723V(C-E)Yx.xml * STM32F733VETx.xml, STM32F733VEYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -406,6 +406,19 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS {PB_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM {PB_15, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP +#else + {PA_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1 + {PB_1, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6 + {PC_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP + {PC_2, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR + {PC_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT #endif /* USE_USB_HS_IN_FS */ {NC, NP, 0} }; diff --git a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PinNamesVar.h b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PinNamesVar.h index cca69bb5b3..cfaca53e63 100644 --- a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PinNamesVar.h +++ b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PinNamesVar.h @@ -68,14 +68,26 @@ PC_11_ALT1 = PC_11 | ALT1, /* USB */ #ifdef USBCON - USB_OTG_FS_DM = PA_11, - USB_OTG_FS_DP = PA_12, - USB_OTG_FS_ID = PA_10, - USB_OTG_FS_SOF = PA_8, - USB_OTG_FS_VBUS = PA_9, - USB_OTG_HS_DM = PB_14, - USB_OTG_HS_DP = PB_15, - USB_OTG_HS_ID = PB_12, - USB_OTG_HS_SOF = PA_4, - USB_OTG_HS_VBUS = PB_13, + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PC_2, + USB_OTG_HS_ULPI_NXT = PC_3, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, #endif diff --git a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c index 7c362a74d0..c8a863d2f0 100644 --- a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F723Z(C-E)Ix.xml, STM32F723Z(C-E)Tx.xml * STM32F730Z8Tx.xml, STM32F733ZEIx.xml * STM32F733ZETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -444,6 +444,19 @@ WEAK const PinMap PinMap_USB_OTG_HS[] = { {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS {PB_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM {PB_15, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP +#else + {PA_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1 + {PB_1, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6 + {PC_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP + {PC_2, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR + {PC_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT #endif /* USE_USB_HS_IN_FS */ {NC, NP, 0} }; diff --git a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PinNamesVar.h b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PinNamesVar.h index cca69bb5b3..cfaca53e63 100644 --- a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PinNamesVar.h +++ b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PinNamesVar.h @@ -68,14 +68,26 @@ PC_11_ALT1 = PC_11 | ALT1, /* USB */ #ifdef USBCON - USB_OTG_FS_DM = PA_11, - USB_OTG_FS_DP = PA_12, - USB_OTG_FS_ID = PA_10, - USB_OTG_FS_SOF = PA_8, - USB_OTG_FS_VBUS = PA_9, - USB_OTG_HS_DM = PB_14, - USB_OTG_HS_DP = PB_15, - USB_OTG_HS_ID = PB_12, - USB_OTG_HS_SOF = PA_4, - USB_OTG_HS_VBUS = PB_13, + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PC_2, + USB_OTG_HS_ULPI_NXT = PC_3, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, #endif diff --git a/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c b/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c index d5c9c56f63..c1000ebc3a 100644 --- a/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746I(E-G)Kx.xml, STM32F746IETx.xml * STM32F746IGTx.xml, STM32F756IGKx.xml * STM32F756IGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c b/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c index 824b672965..486dc1a414 100644 --- a/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746V(E-G)Hx.xml, STM32F746VETx.xml * STM32F746VGTx.xml, STM32F750V8Tx.xml * STM32F756VGHx.xml, STM32F756VGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c index 1392ddddc7..4c34553874 100644 --- a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c +++ b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746ZETx.xml, STM32F746ZGTx.xml * STM32F750Z8Tx.xml, STM32F756ZGTx.xml * STM32F756ZGYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c b/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c index 30a1405cc8..d0e30c8d6c 100644 --- a/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c +++ b/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F746B(E-G)Tx.xml, STM32F746NEHx.xml * STM32F746NGHx.xml, STM32F750N8Hx.xml * STM32F756BGTx.xml, STM32F756NGHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c b/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c index 474f471981..40e10ba2df 100644 --- a/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c +++ b/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F765B(G-I)Tx.xml, STM32F765N(G-I)Hx.xml * STM32F767B(G-I)Tx.xml, STM32F767N(G-I)Hx.xml * STM32F777BITx.xml, STM32F777NIHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c b/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c index ac0de379fc..bc469ae3c3 100644 --- a/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F765I(G-I)Kx.xml, STM32F765I(G-I)Tx.xml * STM32F767I(G-I)Kx.xml, STM32F767I(G-I)Tx.xml * STM32F777IIKx.xml, STM32F777IITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c index 1ddf5f64df..797ace4da0 100644 --- a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F767VGHx.xml, STM32F767VGTx.xml * STM32F767VIHx.xml, STM32F767VITx.xml * STM32F777VIHx.xml, STM32F777VITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c index 37183f219f..cdc73a931f 100644 --- a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c +++ b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F765Z(G-I)Tx.xml, STM32F767ZGTx.xml * STM32F767ZITx.xml, STM32F777ZITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c b/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c index fe0d053d62..10749096b8 100644 --- a/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c +++ b/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F768AIYx.xml, STM32F769A(G-I)Yx.xml * STM32F778AIYx.xml, STM32F779AIYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c b/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c index 28373c3ad6..9a983d0716 100644 --- a/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c +++ b/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F769B(G-I)Tx.xml, STM32F769NGHx.xml * STM32F769NIHx.xml, STM32F779BITx.xml * STM32F779NIHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c b/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c index 01b2a8d11e..6846438619 100644 --- a/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c +++ b/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F769IGTx.xml, STM32F769IITx.xml * STM32F779IITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c index aff07db7bd..69397c59ef 100644 --- a/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030C(6-8)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030F6P/PeripheralPins.c b/variants/STM32G0xx/G030F6P/PeripheralPins.c index 4f91fb80a3..be8dbfef97 100644 --- a/variants/STM32G0xx/G030F6P/PeripheralPins.c +++ b/variants/STM32G0xx/G030F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030F6Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030J6M/PeripheralPins.c b/variants/STM32G0xx/G030J6M/PeripheralPins.c index 4629b48195..22ba98aeff 100644 --- a/variants/STM32G0xx/G030J6M/PeripheralPins.c +++ b/variants/STM32G0xx/G030J6M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030J6Mx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c index 8cfd87cb9f..9a73f962a4 100644 --- a/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030K(6-8)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c index 1d9815b8f7..2ffbb79469 100644 --- a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031C(4-6-8)Tx.xml, STM32G031C(4-6-8)Ux.xml * STM32G041C(6-8)Tx.xml, STM32G041C(6-8)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c b/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c index aea89f8397..5cea0594c8 100644 --- a/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c +++ b/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031F(4-6-8)Px.xml, STM32G031Y8Yx.xml * STM32G041F(6-8)Px.xml, STM32G041Y8Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c index 812709a275..02c5b09270 100644 --- a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c +++ b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G031G(4-6-8)Ux.xml, STM32G041G(6-8)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c b/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c index 0795bfb799..680cfe6f8d 100644 --- a/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c +++ b/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G031J(4-6)Mx.xml, STM32G041J6Mx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c index e1f3a30c72..8fe07b63a2 100644 --- a/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031K(4-6-8)Tx.xml, STM32G031K(4-6-8)Ux.xml * STM32G041K(6-8)Tx.xml, STM32G041K(6-8)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c index e5787fc8d4..92302b8a7e 100644 --- a/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050C6Tx.xml, STM32G050C8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050F6P/PeripheralPins.c b/variants/STM32G0xx/G050F6P/PeripheralPins.c index 69f49309b8..6fc654639e 100644 --- a/variants/STM32G0xx/G050F6P/PeripheralPins.c +++ b/variants/STM32G0xx/G050F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050F6Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c index 8b52f7731f..30dbbb3c9d 100644 --- a/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050K6Tx.xml, STM32G050K8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c index 42069cd1ed..9081e7bdc7 100644 --- a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051C(6-8)Tx.xml, STM32G051C(6-8)Ux.xml * STM32G061C(6-8)Tx.xml, STM32G061C(6-8)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c index eb4116be41..7b714fbbe9 100644 --- a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c +++ b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051F(6-8)Px.xml, STM32G051F8Yx.xml * STM32G061F(6-8)Px.xml, STM32G061F8Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c index 742c613fe2..cd6b5a4da7 100644 --- a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c +++ b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G051G(6-8)Ux.xml, STM32G061G(6-8)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c index 140680eab7..210375e06b 100644 --- a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051K(6-8)Tx.xml, STM32G051K(6-8)Ux.xml * STM32G061K(6-8)Tx.xml, STM32G061K(6-8)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070CBT/PeripheralPins.c b/variants/STM32G0xx/G070CBT/PeripheralPins.c index e53595a522..3360278e3b 100644 --- a/variants/STM32G0xx/G070CBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070CBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070KBT/PeripheralPins.c b/variants/STM32G0xx/G070KBT/PeripheralPins.c index 2199c577ea..533b0d5d81 100644 --- a/variants/STM32G0xx/G070KBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070KBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070KBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070RBT/PeripheralPins.c b/variants/STM32G0xx/G070RBT/PeripheralPins.c index 935353b910..ef9a17c686 100644 --- a/variants/STM32G0xx/G070RBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070RBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c b/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c index 50c3b6e357..dc11465e72 100644 --- a/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071C(6-8-B)Tx.xml, STM32G071C(6-8-B)Ux.xml * STM32G081CBTx.xml, STM32G081CBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c b/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c index 869f9b8882..38304cd7e1 100644 --- a/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c +++ b/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071EBYx.xml, STM32G081EBYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c index d1c64ae1da..18cc3a5b5e 100644 --- a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c +++ b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071G(6-8-B)Ux.xml, STM32G081GBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c index ee9e9c3d29..ea206c70ec 100644 --- a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c +++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071G(8-B)UxN.xml, STM32G081GBUxN.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c index 9cf23bff81..4f12a1527d 100644 --- a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071K(6-8-B)Tx.xml, STM32G071K(6-8-B)Ux.xml * STM32G081KBTx.xml, STM32G081KBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c index 67377c34b4..905b17707c 100644 --- a/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071K(8-B)TxN.xml, STM32G071K(8-B)UxN.xml * STM32G081KBTxN.xml, STM32G081KBUxN.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c b/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c index be489bacdb..0c67bc7bd8 100644 --- a/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c +++ b/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071R(6-8-B)Tx.xml, STM32G071RBIx.xml * STM32G081RBIx.xml, STM32G081RBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0CET/PeripheralPins.c b/variants/STM32G0xx/G0B0CET/PeripheralPins.c index e566188458..8cb36d4c9d 100644 --- a/variants/STM32G0xx/G0B0CET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0CET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0CETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0KET/PeripheralPins.c b/variants/STM32G0xx/G0B0KET/PeripheralPins.c index 6ffdd38da6..49015c9469 100644 --- a/variants/STM32G0xx/G0B0KET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0KET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0KETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0RET/PeripheralPins.c b/variants/STM32G0xx/G0B0RET/PeripheralPins.c index e8e1c4cf64..ebd8ec9411 100644 --- a/variants/STM32G0xx/G0B0RET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0RET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0RETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0VET/PeripheralPins.c b/variants/STM32G0xx/G0B0VET/PeripheralPins.c index bcc372332e..afd90f0f98 100644 --- a/variants/STM32G0xx/G0B0VET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0VETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c index 1d4e484b27..a2dd498035 100644 --- a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1C(B-C-E)Tx.xml, STM32G0B1C(B-C-E)Ux.xml * STM32G0C1C(C-E)Tx.xml, STM32G0C1C(C-E)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c index c691d8df2e..12bd09e2f6 100644 --- a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1C(B-C-E)TxN.xml, STM32G0B1C(B-C-E)UxN.xml * STM32G0C1C(C-E)TxN.xml, STM32G0C1C(C-E)UxN.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c index 485c329d43..a6dab0cbd2 100644 --- a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1K(B-C-E)Tx.xml, STM32G0B1K(B-C-E)Ux.xml * STM32G0C1K(C-E)Tx.xml, STM32G0C1K(C-E)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c index cd91069a2c..adf58ec323 100644 --- a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1K(B-C-E)TxN.xml, STM32G0B1K(B-C-E)UxN.xml * STM32G0C1K(C-E)TxN.xml, STM32G0C1K(C-E)UxN.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c index 139094e88a..4b66edbce9 100644 --- a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1M(B-C-E)Tx.xml, STM32G0C1M(C-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c b/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c index 37b65bd59e..71f7b46d2c 100644 --- a/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1NEYx.xml, STM32G0C1NEYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c index c528942326..98cc830814 100644 --- a/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1R(B-C-E)IxN.xml, STM32G0B1R(B-C-E)TxN.xml * STM32G0C1R(C-E)IxN.xml, STM32G0C1R(C-E)TxN.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c index 9cda7315a4..73b467d508 100644 --- a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1R(B-C-E)Tx.xml, STM32G0C1R(C-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c index 0e16c40050..4d2925ab58 100644 --- a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1V(B-C-E)Ix.xml, STM32G0B1V(B-C-E)Tx.xml * STM32G0C1V(C-E)Ix.xml, STM32G0C1V(C-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c b/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c index f439a78c51..df844a6ed5 100644 --- a/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c +++ b/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411C6Tx.xml, STM32G411C8Tx.xml * STM32G411CBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c b/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c index c319e3ce75..09f58d609c 100644 --- a/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c +++ b/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411C6Ux.xml, STM32G411C8Ux.xml * STM32G411CBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411CCT/PeripheralPins.c b/variants/STM32G4xx/G411CCT/PeripheralPins.c index 447c4f9170..0af9cc0e57 100644 --- a/variants/STM32G4xx/G411CCT/PeripheralPins.c +++ b/variants/STM32G4xx/G411CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G411CCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411CCU/PeripheralPins.c b/variants/STM32G4xx/G411CCU/PeripheralPins.c index dbf387c046..840f3eb5b4 100644 --- a/variants/STM32G4xx/G411CCU/PeripheralPins.c +++ b/variants/STM32G4xx/G411CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G411CCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c b/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c index a1e5b64a04..c6418e0c9b 100644 --- a/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G411K6Tx.xml, STM32G411K6Ux.xml * STM32G411K8Tx.xml, STM32G411K8Ux.xml * STM32G411KBTx.xml, STM32G411KBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c b/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c index e906dce84a..40846933c2 100644 --- a/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c +++ b/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411M6Tx.xml, STM32G411M8Tx.xml * STM32G411MBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411MCT/PeripheralPins.c b/variants/STM32G4xx/G411MCT/PeripheralPins.c index a65adce836..2638d32c00 100644 --- a/variants/STM32G4xx/G411MCT/PeripheralPins.c +++ b/variants/STM32G4xx/G411MCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G411MCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c b/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c index f354a4e394..f284098d95 100644 --- a/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c +++ b/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411R6Tx.xml, STM32G411R8Tx.xml * STM32G411RBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411RCT/PeripheralPins.c b/variants/STM32G4xx/G411RCT/PeripheralPins.c index 6ebbfa951c..c053c16dc5 100644 --- a/variants/STM32G4xx/G411RCT/PeripheralPins.c +++ b/variants/STM32G4xx/G411RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G411RCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c index 3c5e9699b3..eaf698701e 100644 --- a/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414CBTx.xml, STM32G414CCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c b/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c index 659cdd4422..09c1857eb1 100644 --- a/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c +++ b/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414CBUx.xml, STM32G414CCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c index e61c1bcd05..f0d27eab02 100644 --- a/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414MBTx.xml, STM32G414MCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c index 0b92c4ce2b..2f2f710653 100644 --- a/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414RBTx.xml, STM32G414RCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c index 031c238169..de5d25f4d6 100644 --- a/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414VBTx.xml, STM32G414VCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c index 5c22cfe825..b951671615 100644 --- a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431C(6-8-B)Tx.xml, STM32G441CBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c index f1b4a3d646..d87bccda5e 100644 --- a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c +++ b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431C(6-8-B)Ux.xml, STM32G441CBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c b/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c index ca336bf945..dc23431fd6 100644 --- a/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c +++ b/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431CBTxZ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c b/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c index f9e5e729d9..03d4488b8a 100644 --- a/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c +++ b/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431CBYx.xml, STM32G441CBYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c index fb03498688..a24712688a 100644 --- a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c +++ b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G431K(6-8-B)Tx.xml, STM32G431K(6-8-B)Ux.xml * STM32G441KBTx.xml, STM32G441KBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c index 46b0380392..cbc7b95809 100644 --- a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431M(6-8-B)Tx.xml, STM32G441MBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c b/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c index e6c9eb537f..baf345cea2 100644 --- a/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G431R(6-8-B)Ix.xml, STM32G431R(6-8-B)Tx.xml * STM32G431RBTxZ.xml, STM32G441RBIx.xml * STM32G441RBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c index 8ff7dfb20b..21bb179919 100644 --- a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431V(6-8-B)Tx.xml, STM32G441VBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c index 303c7731a8..1c4a00b790 100644 --- a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c +++ b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473C(B-C-E)Tx.xml, STM32G474C(B-C-E)Tx.xml * STM32G483CETx.xml, STM32G484CETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c index a7609523c7..4595c64071 100644 --- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473C(B-C-E)Ux.xml, STM32G474C(B-C-E)Ux.xml * STM32G483CEUx.xml, STM32G484CEUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c index 4a8c6532dd..4486e09142 100644 --- a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c +++ b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473M(B-C-E)Tx.xml, STM32G474M(B-C-E)Tx.xml * STM32G483METx.xml, STM32G484METx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c b/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c index d4496f37d7..c07421c9ce 100644 --- a/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c +++ b/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473MEYx.xml, STM32G474MEYx.xml * STM32G483MEYx.xml, STM32G484MEYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c index 71a22878dd..dd3afaaafb 100644 --- a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c +++ b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473P(B-C-E)Ix.xml, STM32G474P(B-C-E)Ix.xml * STM32G483PEIx.xml, STM32G484PEIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c b/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c index 279bc5addd..411fc1dad3 100644 --- a/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c +++ b/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G473Q(B-C-E)Tx.xml, STM32G473QETxZ.xml * STM32G474Q(B-C-E)Tx.xml, STM32G483QETx.xml * STM32G484QETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c b/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c index 5fb0bb3215..5155b28acf 100644 --- a/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c +++ b/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G473R(B-C-E)Tx.xml, STM32G473RETxZ.xml * STM32G474R(B-C-E)Tx.xml, STM32G483RETx.xml * STM32G484RETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c index a038b72869..88898ac6f1 100644 --- a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32G474V(B-C-E)Hx.xml, STM32G474V(B-C-E)Tx.xml * STM32G483VEHx.xml, STM32G483VETx.xml * STM32G484VEHx.xml, STM32G484VETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c index 80aa58f892..d0db377626 100644 --- a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c +++ b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491C(C-E)Tx.xml, STM32G4A1CETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491C(C-E)U/PeripheralPins.c b/variants/STM32G4xx/G491C(C-E)U/PeripheralPins.c index 863b9d95c5..d57b4b4900 100644 --- a/variants/STM32G4xx/G491C(C-E)U/PeripheralPins.c +++ b/variants/STM32G4xx/G491C(C-E)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491C(C-E)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c index 178d947ac2..a19359dac8 100644 --- a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c +++ b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491K(C-E)Ux.xml, STM32G4A1KEUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c index edefcc74fd..f6d89a4aa6 100644 --- a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G491M(C-E)Sx.xml, STM32G491M(C-E)Tx.xml * STM32G4A1MESx.xml, STM32G4A1METx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c b/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c index fcbf44d4d6..da09387f3c 100644 --- a/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c +++ b/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32G491RETxZ.xml, STM32G491REYx.xml * STM32G4A1REIx.xml, STM32G4A1RETx.xml * STM32G4A1REYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c index 7aa5b27684..fe50b612f4 100644 --- a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c +++ b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491V(C-E)Tx.xml, STM32G4A1VETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G4A1CEU/PeripheralPins.c b/variants/STM32G4xx/G4A1CEU/PeripheralPins.c index 1c6665a096..f2f9e3a142 100644 --- a/variants/STM32G4xx/G4A1CEU/PeripheralPins.c +++ b/variants/STM32G4xx/G4A1CEU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G4A1CEUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c index 2d459e7a16..0df5f12903 100644 --- a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c +++ b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503CBTx.xml, STM32H503CBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503EBY/PeripheralPins.c b/variants/STM32H5xx/H503EBY/PeripheralPins.c index 10538bcad8..03c35bae12 100644 --- a/variants/STM32H5xx/H503EBY/PeripheralPins.c +++ b/variants/STM32H5xx/H503EBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503EBYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503KBU/PeripheralPins.c b/variants/STM32H5xx/H503KBU/PeripheralPins.c index 8775051235..cf32a334a9 100644 --- a/variants/STM32H5xx/H503KBU/PeripheralPins.c +++ b/variants/STM32H5xx/H503KBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503KBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503RBT/PeripheralPins.c b/variants/STM32H5xx/H503RBT/PeripheralPins.c index 4ba6424fe9..0f8b89810f 100644 --- a/variants/STM32H5xx/H503RBT/PeripheralPins.c +++ b/variants/STM32H5xx/H503RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503RBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c index 5e4cb322a2..ffd8db1635 100644 --- a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c +++ b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H523CCTx.xml, STM32H523CCUx.xml * STM32H523CETx.xml, STM32H523CEUx.xml * STM32H533CETx.xml, STM32H533CEUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c b/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c index 47ce7ebda3..513e037df2 100644 --- a/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c +++ b/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H523HEYx.xml, STM32H533HEYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c b/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c index 5d0250c690..84b7ebdd8b 100644 --- a/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c +++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H523RCTx.xml, STM32H523RETx.xml * STM32H533RETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c index 6526de398a..dad47e24b8 100644 --- a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H523VCIx.xml, STM32H523VCTx.xml * STM32H523VEIx.xml, STM32H523VETx.xml * STM32H533VEIx.xml, STM32H533VETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c index bab3368d7e..011c7c4749 100644 --- a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H523ZCJx.xml, STM32H523ZCTx.xml * STM32H523ZEJx.xml, STM32H523ZETx.xml * STM32H533ZEJx.xml, STM32H533ZETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/PeripheralPins.c b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..083a95b847 --- /dev/null +++ b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/PeripheralPins.c @@ -0,0 +1,397 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H543CETx.xml, STM32H543CEUx.xml + * STM32H543CGTx.xml, STM32H543CGUx.xml + * STM32H553CGTx.xml, STM32H553CGUx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_INP5 + {PB_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_INP0 + {PB_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_INP3 + {PB_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_INP2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF9_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_3, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PB_4, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_8, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_I3C2)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_10, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PA_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PB_5, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_SPI3)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_8, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI1)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_7, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_SPI3)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI2)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_0, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PA_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PA_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/PinNamesVar.h b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..d521e25ca7 --- /dev/null +++ b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/PinNamesVar.h @@ -0,0 +1,67 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/boards_entry.txt b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/boards_entry.txt new file mode 100644 index 0000000000..8b7539eb3a --- /dev/null +++ b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/boards_entry.txt @@ -0,0 +1,59 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H543CETx +GenH5.menu.pnum.GENERIC_H543CETX=Generic H543CETx +GenH5.menu.pnum.GENERIC_H543CETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H543CETX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543CETX.build.board=GENERIC_H543CETX +GenH5.menu.pnum.GENERIC_H543CETX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543CETX.build.variant=STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U) +GenH5.menu.pnum.GENERIC_H543CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543CEUx +GenH5.menu.pnum.GENERIC_H543CEUX=Generic H543CEUx +GenH5.menu.pnum.GENERIC_H543CEUX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H543CEUX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543CEUX.build.board=GENERIC_H543CEUX +GenH5.menu.pnum.GENERIC_H543CEUX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543CEUX.build.variant=STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U) +GenH5.menu.pnum.GENERIC_H543CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543CGTx +GenH5.menu.pnum.GENERIC_H543CGTX=Generic H543CGTx +GenH5.menu.pnum.GENERIC_H543CGTX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H543CGTX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543CGTX.build.board=GENERIC_H543CGTX +GenH5.menu.pnum.GENERIC_H543CGTX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543CGTX.build.variant=STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U) +GenH5.menu.pnum.GENERIC_H543CGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543CGUx +GenH5.menu.pnum.GENERIC_H543CGUX=Generic H543CGUx +GenH5.menu.pnum.GENERIC_H543CGUX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H543CGUX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543CGUX.build.board=GENERIC_H543CGUX +GenH5.menu.pnum.GENERIC_H543CGUX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543CGUX.build.variant=STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U) +GenH5.menu.pnum.GENERIC_H543CGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H553CGTx +GenH5.menu.pnum.GENERIC_H553CGTX=Generic H553CGTx +GenH5.menu.pnum.GENERIC_H553CGTX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H553CGTX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H553CGTX.build.board=GENERIC_H553CGTX +GenH5.menu.pnum.GENERIC_H553CGTX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H553CGTX.build.variant=STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U) +GenH5.menu.pnum.GENERIC_H553CGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H553.svd + +# Generic H553CGUx +GenH5.menu.pnum.GENERIC_H553CGUX=Generic H553CGUx +GenH5.menu.pnum.GENERIC_H553CGUX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H553CGUX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H553CGUX.build.board=GENERIC_H553CGUX +GenH5.menu.pnum.GENERIC_H553CGUX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H553CGUX.build.variant=STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U) +GenH5.menu.pnum.GENERIC_H553CGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H553.svd + diff --git a/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/generic_clock.c b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/generic_clock.c new file mode 100644 index 0000000000..6ff9b2f4bd --- /dev/null +++ b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H543CETX) || defined(ARDUINO_GENERIC_H543CEUX) ||\ + defined(ARDUINO_GENERIC_H543CGTX) || defined(ARDUINO_GENERIC_H543CGUX) ||\ + defined(ARDUINO_GENERIC_H553CGTX) || defined(ARDUINO_GENERIC_H553CGUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/variant_generic.cpp b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..60d2fe85d9 --- /dev/null +++ b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/variant_generic.cpp @@ -0,0 +1,74 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H543CETX) || defined(ARDUINO_GENERIC_H543CEUX) ||\ + defined(ARDUINO_GENERIC_H543CGTX) || defined(ARDUINO_GENERIC_H543CGUX) ||\ + defined(ARDUINO_GENERIC_H553CGTX) || defined(ARDUINO_GENERIC_H553CGUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_12, // D26/A11 + PB_13, // D27 + PB_14, // D28 + PB_15, // D29/A12 + PC_13, // D30 + PC_14, // D31 + PC_15, // D32 + PH_0, // D33 + PH_1 // D34 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 26, // A11, PB12 + 29 // A12, PB15 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/variant_generic.h b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/variant_generic.h new file mode 100644 index 0000000000..8c8f231e9e --- /dev/null +++ b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/variant_generic.h @@ -0,0 +1,201 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB12 PIN_A11 +#define PB13 27 +#define PB14 28 +#define PB15 PIN_A12 +#define PC13 30 +#define PC14 31 +#define PC15 32 +#define PH0 33 +#define PH1 34 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 35 +#define NUM_ANALOG_INPUTS 13 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB4 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PB3 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA8 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H543R(E-G)T_H553RGT/PeripheralPins.c b/variants/STM32H5xx/H543R(E-G)T_H553RGT/PeripheralPins.c new file mode 100644 index 0000000000..79a4118a5d --- /dev/null +++ b/variants/STM32H5xx/H543R(E-G)T_H553RGT/PeripheralPins.c @@ -0,0 +1,611 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H543RETx.xml, STM32H543RGTx.xml + * STM32H553RGTx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_INP5 + {PB_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_INP0 + {PB_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_INP3 + {PB_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_INP2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_INP8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF9_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_3, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PB_4, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PC_7, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF10_I3C2)}, + {PC_9, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF10_I3C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_8, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_I3C2)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_10, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)}, + {PC_6, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF10_I3C2)}, + {PC_10, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PA_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PB_5, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_SPI3)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_8, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI1)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1_ALT1, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_7, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_SPI3)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI2)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_0, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PA_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CLK + {PA_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_PHY_INTN + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PB_2_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PB_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_ETH)}, // ETH_MDC + {PB_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_MDIO + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PC_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_PPS_OUT + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PA_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PA_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H543R(E-G)T_H553RGT/PinNamesVar.h b/variants/STM32H5xx/H543R(E-G)T_H553RGT/PinNamesVar.h new file mode 100644 index 0000000000..2bf5e4b098 --- /dev/null +++ b/variants/STM32H5xx/H543R(E-G)T_H553RGT/PinNamesVar.h @@ -0,0 +1,81 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H543R(E-G)T_H553RGT/boards_entry.txt b/variants/STM32H5xx/H543R(E-G)T_H553RGT/boards_entry.txt new file mode 100644 index 0000000000..faf8a716bd --- /dev/null +++ b/variants/STM32H5xx/H543R(E-G)T_H553RGT/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H543RETx +GenH5.menu.pnum.GENERIC_H543RETX=Generic H543RETx +GenH5.menu.pnum.GENERIC_H543RETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H543RETX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543RETX.build.board=GENERIC_H543RETX +GenH5.menu.pnum.GENERIC_H543RETX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543RETX.build.variant=STM32H5xx/H543R(E-G)T_H553RGT +GenH5.menu.pnum.GENERIC_H543RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543RGTx +GenH5.menu.pnum.GENERIC_H543RGTX=Generic H543RGTx +GenH5.menu.pnum.GENERIC_H543RGTX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H543RGTX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543RGTX.build.board=GENERIC_H543RGTX +GenH5.menu.pnum.GENERIC_H543RGTX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543RGTX.build.variant=STM32H5xx/H543R(E-G)T_H553RGT +GenH5.menu.pnum.GENERIC_H543RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H553RGTx +GenH5.menu.pnum.GENERIC_H553RGTX=Generic H553RGTx +GenH5.menu.pnum.GENERIC_H553RGTX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H553RGTX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H553RGTX.build.board=GENERIC_H553RGTX +GenH5.menu.pnum.GENERIC_H553RGTX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H553RGTX.build.variant=STM32H5xx/H543R(E-G)T_H553RGT +GenH5.menu.pnum.GENERIC_H553RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H553.svd + diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/generic_clock.c b/variants/STM32H5xx/H543R(E-G)T_H553RGT/generic_clock.c similarity index 82% rename from variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/generic_clock.c rename to variants/STM32H5xx/H543R(E-G)T_H553RGT/generic_clock.c index e6a75e2bda..361515a06b 100644 --- a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/generic_clock.c +++ b/variants/STM32H5xx/H543R(E-G)T_H553RGT/generic_clock.c @@ -1,6 +1,6 @@ /* ******************************************************************************* - * Copyright (c) 2020-2021, STMicroelectronics + * Copyright (c) 2020-2026, STMicroelectronics * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -10,8 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_L4P5RETX) || defined(ARDUINO_GENERIC_L4P5RGTX) ||\ - defined(ARDUINO_GENERIC_L4Q5RGTX) +#if defined(ARDUINO_GENERIC_H543RETX) || defined(ARDUINO_GENERIC_H543RGTX) ||\ + defined(ARDUINO_GENERIC_H553RGTX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H543R(E-G)T_H553RGT/variant_generic.cpp b/variants/STM32H5xx/H543R(E-G)T_H553RGT/variant_generic.cpp new file mode 100644 index 0000000000..98710d99c9 --- /dev/null +++ b/variants/STM32H5xx/H543R(E-G)T_H553RGT/variant_generic.cpp @@ -0,0 +1,93 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H543RETX) || defined(ARDUINO_GENERIC_H543RGTX) ||\ + defined(ARDUINO_GENERIC_H553RGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_12, // D26/A11 + PB_13, // D27 + PB_14, // D28 + PB_15, // D29/A12 + PC_0, // D30/A13 + PC_1, // D31/A14 + PC_2, // D32/A15 + PC_3, // D33/A16 + PC_4, // D34/A17 + PC_5, // D35/A18 + PC_6, // D36 + PC_7, // D37 + PC_8, // D38 + PC_9, // D39 + PC_10, // D40 + PC_11, // D41 + PC_12, // D42 + PC_13, // D43 + PC_14, // D44 + PC_15, // D45 + PD_2, // D46 + PH_0, // D47 + PH_1 // D48 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 26, // A11, PB12 + 29, // A12, PB15 + 30, // A13, PC0 + 31, // A14, PC1 + 32, // A15, PC2 + 33, // A16, PC3 + 34, // A17, PC4 + 35 // A18, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H543R(E-G)T_H553RGT/variant_generic.h b/variants/STM32H5xx/H543R(E-G)T_H553RGT/variant_generic.h new file mode 100644 index 0000000000..1725fc4a36 --- /dev/null +++ b/variants/STM32H5xx/H543R(E-G)T_H553RGT/variant_generic.h @@ -0,0 +1,238 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB12 PIN_A11 +#define PB13 27 +#define PB14 28 +#define PB15 PIN_A12 +#define PC0 PIN_A13 +#define PC1 PIN_A14 +#define PC2 PIN_A15 +#define PC3 PIN_A16 +#define PC4 PIN_A17 +#define PC5 PIN_A18 +#define PC6 36 +#define PC7 37 +#define PC8 38 +#define PC9 39 +#define PC10 40 +#define PC11 41 +#define PC12 42 +#define PC13 43 +#define PC14 44 +#define PC15 45 +#define PD2 46 +#define PH0 47 +#define PH1 48 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 49 +#define NUM_ANALOG_INPUTS 19 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB4 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PB3 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA8 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// SDMMC signals not available +#define SDMMC_CDIR_NA + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H543UGY_H553UGY/PeripheralPins.c b/variants/STM32H5xx/H543UGY_H553UGY/PeripheralPins.c new file mode 100644 index 0000000000..5820f7837b --- /dev/null +++ b/variants/STM32H5xx/H543UGY_H553UGY/PeripheralPins.c @@ -0,0 +1,589 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H543UGYx.xml, STM32H553UGYx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_INP5 + {PB_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_INP0 + {PB_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_INP3 + {PB_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_INP2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_INP8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF9_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_3, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PB_4, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PC_7, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF10_I3C2)}, + {PC_9, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF10_I3C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_8, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_I3C2)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_10, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)}, + {PC_10, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PA_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PB_5, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_SPI3)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_8, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI1)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1_ALT1, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_7, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_SPI3)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI2)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_0, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PA_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CLK + {PA_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_PHY_INTN + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PB_2_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PB_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_ETH)}, // ETH_MDC + {PB_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_MDIO + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PC_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_PPS_OUT + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PA_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PA_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H543UGY_H553UGY/PinNamesVar.h b/variants/STM32H5xx/H543UGY_H553UGY/PinNamesVar.h new file mode 100644 index 0000000000..48e7c8f68e --- /dev/null +++ b/variants/STM32H5xx/H543UGY_H553UGY/PinNamesVar.h @@ -0,0 +1,80 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H543UGY_H553UGY/boards_entry.txt b/variants/STM32H5xx/H543UGY_H553UGY/boards_entry.txt new file mode 100644 index 0000000000..2cc26b1e68 --- /dev/null +++ b/variants/STM32H5xx/H543UGY_H553UGY/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H543UGYx +GenH5.menu.pnum.GENERIC_H543UGYX=Generic H543UGYx +GenH5.menu.pnum.GENERIC_H543UGYX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H543UGYX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543UGYX.build.board=GENERIC_H543UGYX +GenH5.menu.pnum.GENERIC_H543UGYX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543UGYX.build.variant=STM32H5xx/H543UGY_H553UGY +GenH5.menu.pnum.GENERIC_H543UGYX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H553UGYx +GenH5.menu.pnum.GENERIC_H553UGYX=Generic H553UGYx +GenH5.menu.pnum.GENERIC_H553UGYX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H553UGYX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H553UGYX.build.board=GENERIC_H553UGYX +GenH5.menu.pnum.GENERIC_H553UGYX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H553UGYX.build.variant=STM32H5xx/H543UGY_H553UGY +GenH5.menu.pnum.GENERIC_H553UGYX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H553.svd + diff --git a/variants/STM32H5xx/H543UGY_H553UGY/generic_clock.c b/variants/STM32H5xx/H543UGY_H553UGY/generic_clock.c new file mode 100644 index 0000000000..bb162fcd48 --- /dev/null +++ b/variants/STM32H5xx/H543UGY_H553UGY/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H543UGYX) || defined(ARDUINO_GENERIC_H553UGYX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H543UGY_H553UGY/variant_generic.cpp b/variants/STM32H5xx/H543UGY_H553UGY/variant_generic.cpp new file mode 100644 index 0000000000..7d9c279c9c --- /dev/null +++ b/variants/STM32H5xx/H543UGY_H553UGY/variant_generic.cpp @@ -0,0 +1,90 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H543UGYX) || defined(ARDUINO_GENERIC_H553UGYX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_12, // D26/A11 + PB_13, // D27 + PB_14, // D28 + PB_15, // D29/A12 + PC_0, // D30/A13 + PC_1, // D31/A14 + PC_2, // D32/A15 + PC_3, // D33/A16 + PC_4, // D34/A17 + PC_5, // D35/A18 + PC_7, // D36 + PC_8, // D37 + PC_9, // D38 + PC_10, // D39 + PC_11, // D40 + PC_12, // D41 + PC_13, // D42 + PC_14, // D43 + PC_15, // D44 + PH_0, // D45 + PH_1 // D46 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 26, // A11, PB12 + 29, // A12, PB15 + 30, // A13, PC0 + 31, // A14, PC1 + 32, // A15, PC2 + 33, // A16, PC3 + 34, // A17, PC4 + 35 // A18, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H543UGY_H553UGY/variant_generic.h b/variants/STM32H5xx/H543UGY_H553UGY/variant_generic.h new file mode 100644 index 0000000000..5a450a0d14 --- /dev/null +++ b/variants/STM32H5xx/H543UGY_H553UGY/variant_generic.h @@ -0,0 +1,236 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB12 PIN_A11 +#define PB13 27 +#define PB14 28 +#define PB15 PIN_A12 +#define PC0 PIN_A13 +#define PC1 PIN_A14 +#define PC2 PIN_A15 +#define PC3 PIN_A16 +#define PC4 PIN_A17 +#define PC5 PIN_A18 +#define PC7 36 +#define PC8 37 +#define PC9 38 +#define PC10 39 +#define PC11 40 +#define PC12 41 +#define PC13 42 +#define PC14 43 +#define PC15 44 +#define PH0 45 +#define PH1 46 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 47 +#define NUM_ANALOG_INPUTS 19 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB4 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PB3 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA8 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// SDMMC signals not available +#define SDMMC_CDIR_NA +#define SDMMC_D0DIR_NA + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/PeripheralPins.c b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/PeripheralPins.c new file mode 100644 index 0000000000..56ef781cd2 --- /dev/null +++ b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/PeripheralPins.c @@ -0,0 +1,736 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H543VEIx.xml, STM32H543VETx.xml + * STM32H543VEZx.xml, STM32H543VGIx.xml + * STM32H543VGTx.xml, STM32H543VGZx.xml + * STM32H553VGIx.xml, STM32H553VGTx.xml + * STM32H553VGZx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_INP5 + {PB_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_INP0 + {PB_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_INP3 + {PB_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_INP2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_INP8 + {PE_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_INP1 + {PE_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC3_INP4 + {PE_11, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC3_INP5 + {PE_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC3_INP6 + {PE_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC3_INP7 + {PE_14, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC3_INP8 + {PE_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC3_INP9 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF9_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PD_6, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_3, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PB_4, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PC_7, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF10_I3C2)}, + {PC_9, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF10_I3C2)}, + {PD_7, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_8, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_I3C2)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_10, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)}, + {PC_6, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF10_I3C2)}, + {PC_10, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PD_6, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PA_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PB_5, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, + {PE_4, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF13_UART8)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, + {PE_5, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF13_UART8)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_SPI3)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_8, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI1)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1_ALT1, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_7, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_SPI3)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI2)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_0, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PA_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CLK + {PA_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_PHY_INTN + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PB_2_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PB_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_ETH)}, // ETH_MDC + {PB_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_MDIO + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PC_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_PPS_OUT + {PD_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PD_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PD_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CLK + {PD_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_ETH)}, // ETH_MII_CRS + {PD_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_ETH)}, // ETH_MII_RXD0 + {PD_8_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_ETH)}, // ETH_RMII_RXD0 + {PD_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_ETH)}, // ETH_MII_CRS + {PD_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PTP_AUX_TS + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PE_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PE_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PE_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PE_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PE_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PA_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PA_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS1 + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF11_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF11_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/PinNamesVar.h b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/PinNamesVar.h new file mode 100644 index 0000000000..6a7e48684a --- /dev/null +++ b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/PinNamesVar.h @@ -0,0 +1,85 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PD_1_ALT1 = PD_1 | ALT1, +PD_8_ALT1 = PD_8 | ALT1, +PE_4_ALT1 = PE_4 | ALT1, +PE_5_ALT1 = PE_5 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PD_3, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/boards_entry.txt b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/boards_entry.txt new file mode 100644 index 0000000000..d7b5cf9ac4 --- /dev/null +++ b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/boards_entry.txt @@ -0,0 +1,86 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H543VEIx +GenH5.menu.pnum.GENERIC_H543VEIX=Generic H543VEIx +GenH5.menu.pnum.GENERIC_H543VEIX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H543VEIX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543VEIX.build.board=GENERIC_H543VEIX +GenH5.menu.pnum.GENERIC_H543VEIX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543VEIX.build.variant=STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z) +GenH5.menu.pnum.GENERIC_H543VEIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543VETx +GenH5.menu.pnum.GENERIC_H543VETX=Generic H543VETx +GenH5.menu.pnum.GENERIC_H543VETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H543VETX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543VETX.build.board=GENERIC_H543VETX +GenH5.menu.pnum.GENERIC_H543VETX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543VETX.build.variant=STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z) +GenH5.menu.pnum.GENERIC_H543VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543VEZx +GenH5.menu.pnum.GENERIC_H543VEZX=Generic H543VEZx +GenH5.menu.pnum.GENERIC_H543VEZX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H543VEZX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543VEZX.build.board=GENERIC_H543VEZX +GenH5.menu.pnum.GENERIC_H543VEZX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543VEZX.build.variant=STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z) +GenH5.menu.pnum.GENERIC_H543VEZX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543VGIx +GenH5.menu.pnum.GENERIC_H543VGIX=Generic H543VGIx +GenH5.menu.pnum.GENERIC_H543VGIX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H543VGIX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543VGIX.build.board=GENERIC_H543VGIX +GenH5.menu.pnum.GENERIC_H543VGIX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543VGIX.build.variant=STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z) +GenH5.menu.pnum.GENERIC_H543VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543VGTx +GenH5.menu.pnum.GENERIC_H543VGTX=Generic H543VGTx +GenH5.menu.pnum.GENERIC_H543VGTX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H543VGTX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543VGTX.build.board=GENERIC_H543VGTX +GenH5.menu.pnum.GENERIC_H543VGTX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543VGTX.build.variant=STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z) +GenH5.menu.pnum.GENERIC_H543VGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543VGZx +GenH5.menu.pnum.GENERIC_H543VGZX=Generic H543VGZx +GenH5.menu.pnum.GENERIC_H543VGZX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H543VGZX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543VGZX.build.board=GENERIC_H543VGZX +GenH5.menu.pnum.GENERIC_H543VGZX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543VGZX.build.variant=STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z) +GenH5.menu.pnum.GENERIC_H543VGZX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H553VGIx +GenH5.menu.pnum.GENERIC_H553VGIX=Generic H553VGIx +GenH5.menu.pnum.GENERIC_H553VGIX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H553VGIX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H553VGIX.build.board=GENERIC_H553VGIX +GenH5.menu.pnum.GENERIC_H553VGIX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H553VGIX.build.variant=STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z) +GenH5.menu.pnum.GENERIC_H553VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H553.svd + +# Generic H553VGTx +GenH5.menu.pnum.GENERIC_H553VGTX=Generic H553VGTx +GenH5.menu.pnum.GENERIC_H553VGTX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H553VGTX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H553VGTX.build.board=GENERIC_H553VGTX +GenH5.menu.pnum.GENERIC_H553VGTX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H553VGTX.build.variant=STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z) +GenH5.menu.pnum.GENERIC_H553VGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H553.svd + +# Generic H553VGZx +GenH5.menu.pnum.GENERIC_H553VGZX=Generic H553VGZx +GenH5.menu.pnum.GENERIC_H553VGZX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H553VGZX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H553VGZX.build.board=GENERIC_H553VGZX +GenH5.menu.pnum.GENERIC_H553VGZX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H553VGZX.build.variant=STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z) +GenH5.menu.pnum.GENERIC_H553VGZX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H553.svd + diff --git a/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/generic_clock.c b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/generic_clock.c new file mode 100644 index 0000000000..1339788be3 --- /dev/null +++ b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/generic_clock.c @@ -0,0 +1,31 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H543VEIX) || defined(ARDUINO_GENERIC_H543VETX) ||\ + defined(ARDUINO_GENERIC_H543VEZX) || defined(ARDUINO_GENERIC_H543VGIX) ||\ + defined(ARDUINO_GENERIC_H543VGTX) || defined(ARDUINO_GENERIC_H543VGZX) ||\ + defined(ARDUINO_GENERIC_H553VGIX) || defined(ARDUINO_GENERIC_H553VGTX) ||\ + defined(ARDUINO_GENERIC_H553VGZX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/variant_generic.cpp b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/variant_generic.cpp new file mode 100644 index 0000000000..ff54eca910 --- /dev/null +++ b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/variant_generic.cpp @@ -0,0 +1,134 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H543VEIX) || defined(ARDUINO_GENERIC_H543VETX) ||\ + defined(ARDUINO_GENERIC_H543VEZX) || defined(ARDUINO_GENERIC_H543VGIX) ||\ + defined(ARDUINO_GENERIC_H543VGTX) || defined(ARDUINO_GENERIC_H543VGZX) ||\ + defined(ARDUINO_GENERIC_H553VGIX) || defined(ARDUINO_GENERIC_H553VGTX) ||\ + defined(ARDUINO_GENERIC_H553VGZX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27/A11 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30/A12 + PC_0, // D31/A13 + PC_1, // D32/A14 + PC_2, // D33/A15 + PC_3, // D34/A16 + PC_4, // D35/A17 + PC_5, // D36/A18 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_2, // D64 + PE_3, // D65 + PE_4, // D66 + PE_5, // D67 + PE_6, // D68 + PE_7, // D69/A19 + PE_8, // D70 + PE_9, // D71 + PE_10, // D72/A20 + PE_11, // D73/A21 + PE_12, // D74/A22 + PE_13, // D75/A23 + PE_14, // D76/A24 + PE_15, // D77/A25 + PH_0, // D78 + PH_1 // D79 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 27, // A11, PB12 + 30, // A12, PB15 + 31, // A13, PC0 + 32, // A14, PC1 + 33, // A15, PC2 + 34, // A16, PC3 + 35, // A17, PC4 + 36, // A18, PC5 + 69, // A19, PE7 + 72, // A20, PE10 + 73, // A21, PE11 + 74, // A22, PE12 + 75, // A23, PE13 + 76, // A24, PE14 + 77 // A25, PE15 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/variant_generic.h b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/variant_generic.h new file mode 100644 index 0000000000..07c22e6481 --- /dev/null +++ b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/variant_generic.h @@ -0,0 +1,270 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 PIN_A11 +#define PB13 28 +#define PB14 29 +#define PB15 PIN_A12 +#define PC0 PIN_A13 +#define PC1 PIN_A14 +#define PC2 PIN_A15 +#define PC3 PIN_A16 +#define PC4 PIN_A17 +#define PC5 PIN_A18 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE2 64 +#define PE3 65 +#define PE4 66 +#define PE5 67 +#define PE6 68 +#define PE7 PIN_A19 +#define PE8 70 +#define PE9 71 +#define PE10 PIN_A20 +#define PE11 PIN_A21 +#define PE12 PIN_A22 +#define PE13 PIN_A23 +#define PE14 PIN_A24 +#define PE15 PIN_A25 +#define PH0 78 +#define PH1 79 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PD1_ALT1 (PD1 | ALT1) +#define PD8_ALT1 (PD8 | ALT1) +#define PE4_ALT1 (PE4 | ALT1) +#define PE5_ALT1 (PE5 | ALT1) + +#define NUM_DIGITAL_PINS 80 +#define NUM_ANALOG_INPUTS 26 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PD12 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PB3 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA8 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/PeripheralPins.c b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/PeripheralPins.c new file mode 100644 index 0000000000..33ec5f1db3 --- /dev/null +++ b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/PeripheralPins.c @@ -0,0 +1,788 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H543ZEJx.xml, STM32H543ZETx.xml + * STM32H543ZEZx.xml, STM32H543ZGJx.xml + * STM32H543ZGTx.xml, STM32H543ZGZx.xml + * STM32H553ZGJx.xml, STM32H553ZGTx.xml + * STM32H553ZGZx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_INP5 + {PB_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_INP0 + {PB_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_INP3 + {PB_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_INP2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_INP8 + {PE_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_INP1 + {PE_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC3_INP4 + {PE_11, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC3_INP5 + {PE_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC3_INP6 + {PE_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC3_INP7 + {PE_14, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC3_INP8 + {PE_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC3_INP9 + {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_INP6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF9_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PD_6, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_3, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PB_4, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PC_7, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF10_I3C2)}, + {PC_9, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF10_I3C2)}, + {PD_7, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PF_0, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_8, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_I3C2)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PB_10, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_I3C2)}, + {PC_6, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF10_I3C2)}, + {PC_10, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PD_6, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PF_1, I3C2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C2)}, + {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM8, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PA_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PB_5, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, + {PE_4, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF13_UART8)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_UART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, + {PE_5, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF13_UART8)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_USART6)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART7)}, + {PG_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_SPI3)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_8, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI1)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1_ALT1, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI2)}, + {PG_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_7, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF4_SPI3)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI4)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI2)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_0, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PA_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CLK + {PA_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_PHY_INTN + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PB_2_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PB_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_ETH)}, // ETH_MDC + {PB_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_MDIO + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PC_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_PPS_OUT + {PD_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PD_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PD_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CLK + {PD_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_ETH)}, // ETH_MII_CRS + {PD_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_ETH)}, // ETH_MII_RXD0 + {PD_8_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_ETH)}, // ETH_RMII_RXD0 + {PD_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_ETH)}, // ETH_MII_CRS + {PD_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PTP_AUX_TS + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PE_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PE_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PE_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PE_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PE_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PF_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PF_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PF_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CLK + {PG_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_ETH)}, // ETH_MII_RX_ER + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PG_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PG_13_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_14_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PA_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PA_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS2 + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS1 + {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS1 + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF11_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF11_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PG_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {PG_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {PG_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {PG_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/PinNamesVar.h b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/PinNamesVar.h new file mode 100644 index 0000000000..8ba0c6fe32 --- /dev/null +++ b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/PinNamesVar.h @@ -0,0 +1,89 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PD_1_ALT1 = PD_1 | ALT1, +PD_8_ALT1 = PD_8 | ALT1, +PE_4_ALT1 = PE_4 | ALT1, +PE_5_ALT1 = PE_5 | ALT1, +PG_11_ALT1 = PG_11 | ALT1, +PG_12_ALT1 = PG_12 | ALT1, +PG_13_ALT1 = PG_13 | ALT1, +PG_14_ALT1 = PG_14 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PD_3, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/boards_entry.txt b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/boards_entry.txt new file mode 100644 index 0000000000..54d0181b5a --- /dev/null +++ b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/boards_entry.txt @@ -0,0 +1,86 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H543ZEJx +GenH5.menu.pnum.GENERIC_H543ZEJX=Generic H543ZEJx +GenH5.menu.pnum.GENERIC_H543ZEJX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H543ZEJX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543ZEJX.build.board=GENERIC_H543ZEJX +GenH5.menu.pnum.GENERIC_H543ZEJX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543ZEJX.build.variant=STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z) +GenH5.menu.pnum.GENERIC_H543ZEJX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543ZETx +GenH5.menu.pnum.GENERIC_H543ZETX=Generic H543ZETx +GenH5.menu.pnum.GENERIC_H543ZETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H543ZETX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543ZETX.build.board=GENERIC_H543ZETX +GenH5.menu.pnum.GENERIC_H543ZETX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543ZETX.build.variant=STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z) +GenH5.menu.pnum.GENERIC_H543ZETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543ZEZx +GenH5.menu.pnum.GENERIC_H543ZEZX=Generic H543ZEZx +GenH5.menu.pnum.GENERIC_H543ZEZX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H543ZEZX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543ZEZX.build.board=GENERIC_H543ZEZX +GenH5.menu.pnum.GENERIC_H543ZEZX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543ZEZX.build.variant=STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z) +GenH5.menu.pnum.GENERIC_H543ZEZX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543ZGJx +GenH5.menu.pnum.GENERIC_H543ZGJX=Generic H543ZGJx +GenH5.menu.pnum.GENERIC_H543ZGJX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H543ZGJX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543ZGJX.build.board=GENERIC_H543ZGJX +GenH5.menu.pnum.GENERIC_H543ZGJX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543ZGJX.build.variant=STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z) +GenH5.menu.pnum.GENERIC_H543ZGJX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543ZGTx +GenH5.menu.pnum.GENERIC_H543ZGTX=Generic H543ZGTx +GenH5.menu.pnum.GENERIC_H543ZGTX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H543ZGTX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543ZGTX.build.board=GENERIC_H543ZGTX +GenH5.menu.pnum.GENERIC_H543ZGTX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543ZGTX.build.variant=STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z) +GenH5.menu.pnum.GENERIC_H543ZGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H543ZGZx +GenH5.menu.pnum.GENERIC_H543ZGZX=Generic H543ZGZx +GenH5.menu.pnum.GENERIC_H543ZGZX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H543ZGZX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H543ZGZX.build.board=GENERIC_H543ZGZX +GenH5.menu.pnum.GENERIC_H543ZGZX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H543ZGZX.build.variant=STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z) +GenH5.menu.pnum.GENERIC_H543ZGZX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H543.svd + +# Generic H553ZGJx +GenH5.menu.pnum.GENERIC_H553ZGJX=Generic H553ZGJx +GenH5.menu.pnum.GENERIC_H553ZGJX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H553ZGJX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H553ZGJX.build.board=GENERIC_H553ZGJX +GenH5.menu.pnum.GENERIC_H553ZGJX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H553ZGJX.build.variant=STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z) +GenH5.menu.pnum.GENERIC_H553ZGJX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H553.svd + +# Generic H553ZGTx +GenH5.menu.pnum.GENERIC_H553ZGTX=Generic H553ZGTx +GenH5.menu.pnum.GENERIC_H553ZGTX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H553ZGTX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H553ZGTX.build.board=GENERIC_H553ZGTX +GenH5.menu.pnum.GENERIC_H553ZGTX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H553ZGTX.build.variant=STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z) +GenH5.menu.pnum.GENERIC_H553ZGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H553.svd + +# Generic H553ZGZx +GenH5.menu.pnum.GENERIC_H553ZGZX=Generic H553ZGZx +GenH5.menu.pnum.GENERIC_H553ZGZX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H553ZGZX.upload.maximum_data_size=311296 +GenH5.menu.pnum.GENERIC_H553ZGZX.build.board=GENERIC_H553ZGZX +GenH5.menu.pnum.GENERIC_H553ZGZX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H553ZGZX.build.variant=STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z) +GenH5.menu.pnum.GENERIC_H553ZGZX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H553.svd + diff --git a/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/generic_clock.c b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/generic_clock.c new file mode 100644 index 0000000000..88d4320de4 --- /dev/null +++ b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/generic_clock.c @@ -0,0 +1,31 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H543ZEJX) || defined(ARDUINO_GENERIC_H543ZETX) ||\ + defined(ARDUINO_GENERIC_H543ZEZX) || defined(ARDUINO_GENERIC_H543ZGJX) ||\ + defined(ARDUINO_GENERIC_H543ZGTX) || defined(ARDUINO_GENERIC_H543ZGZX) ||\ + defined(ARDUINO_GENERIC_H553ZGJX) || defined(ARDUINO_GENERIC_H553ZGTX) ||\ + defined(ARDUINO_GENERIC_H553ZGZX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/variant_generic.cpp b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/variant_generic.cpp new file mode 100644 index 0000000000..5b1a8f6464 --- /dev/null +++ b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/variant_generic.cpp @@ -0,0 +1,170 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H543ZEJX) || defined(ARDUINO_GENERIC_H543ZETX) ||\ + defined(ARDUINO_GENERIC_H543ZEZX) || defined(ARDUINO_GENERIC_H543ZGJX) ||\ + defined(ARDUINO_GENERIC_H543ZGTX) || defined(ARDUINO_GENERIC_H543ZGZX) ||\ + defined(ARDUINO_GENERIC_H553ZGJX) || defined(ARDUINO_GENERIC_H553ZGTX) ||\ + defined(ARDUINO_GENERIC_H553ZGZX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27/A11 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30/A12 + PC_0, // D31/A13 + PC_1, // D32/A14 + PC_2, // D33/A15 + PC_3, // D34/A16 + PC_4, // D35/A17 + PC_5, // D36/A18 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_2, // D64 + PE_3, // D65 + PE_4, // D66 + PE_5, // D67 + PE_6, // D68 + PE_7, // D69/A19 + PE_8, // D70 + PE_9, // D71 + PE_10, // D72/A20 + PE_11, // D73/A21 + PE_12, // D74/A22 + PE_13, // D75/A23 + PE_14, // D76/A24 + PE_15, // D77/A25 + PF_0, // D78 + PF_1, // D79 + PF_2, // D80 + PF_3, // D81 + PF_4, // D82 + PF_5, // D83 + PF_6, // D84 + PF_7, // D85 + PF_8, // D86 + PF_9, // D87 + PF_10, // D88 + PF_11, // D89/A26 + PF_12, // D90/A27 + PF_13, // D91/A28 + PF_14, // D92/A29 + PF_15, // D93 + PG_0, // D94 + PG_1, // D95 + PG_2, // D96 + PG_3, // D97 + PG_4, // D98 + PG_5, // D99 + PG_6, // D100 + PG_7, // D101 + PG_8, // D102 + PG_9, // D103 + PG_10, // D104 + PG_11, // D105 + PG_12, // D106 + PG_13, // D107 + PG_14, // D108 + PG_15, // D109 + PH_0, // D110 + PH_1 // D111 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 27, // A11, PB12 + 30, // A12, PB15 + 31, // A13, PC0 + 32, // A14, PC1 + 33, // A15, PC2 + 34, // A16, PC3 + 35, // A17, PC4 + 36, // A18, PC5 + 69, // A19, PE7 + 72, // A20, PE10 + 73, // A21, PE11 + 74, // A22, PE12 + 75, // A23, PE13 + 76, // A24, PE14 + 77, // A25, PE15 + 89, // A26, PF11 + 90, // A27, PF12 + 91, // A28, PF13 + 92 // A29, PF14 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/variant_generic.h b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/variant_generic.h new file mode 100644 index 0000000000..a510edd737 --- /dev/null +++ b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/variant_generic.h @@ -0,0 +1,306 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 PIN_A11 +#define PB13 28 +#define PB14 29 +#define PB15 PIN_A12 +#define PC0 PIN_A13 +#define PC1 PIN_A14 +#define PC2 PIN_A15 +#define PC3 PIN_A16 +#define PC4 PIN_A17 +#define PC5 PIN_A18 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE2 64 +#define PE3 65 +#define PE4 66 +#define PE5 67 +#define PE6 68 +#define PE7 PIN_A19 +#define PE8 70 +#define PE9 71 +#define PE10 PIN_A20 +#define PE11 PIN_A21 +#define PE12 PIN_A22 +#define PE13 PIN_A23 +#define PE14 PIN_A24 +#define PE15 PIN_A25 +#define PF0 78 +#define PF1 79 +#define PF2 80 +#define PF3 81 +#define PF4 82 +#define PF5 83 +#define PF6 84 +#define PF7 85 +#define PF8 86 +#define PF9 87 +#define PF10 88 +#define PF11 PIN_A26 +#define PF12 PIN_A27 +#define PF13 PIN_A28 +#define PF14 PIN_A29 +#define PF15 93 +#define PG0 94 +#define PG1 95 +#define PG2 96 +#define PG3 97 +#define PG4 98 +#define PG5 99 +#define PG6 100 +#define PG7 101 +#define PG8 102 +#define PG9 103 +#define PG10 104 +#define PG11 105 +#define PG12 106 +#define PG13 107 +#define PG14 108 +#define PG15 109 +#define PH0 110 +#define PH1 111 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PD1_ALT1 (PD1 | ALT1) +#define PD8_ALT1 (PD8 | ALT1) +#define PE4_ALT1 (PE4 | ALT1) +#define PE5_ALT1 (PE5 | ALT1) +#define PG11_ALT1 (PG11 | ALT1) +#define PG12_ALT1 (PG12 | ALT1) +#define PG13_ALT1 (PG13 | ALT1) +#define PG14_ALT1 (PG14 | ALT1) + +#define NUM_DIGITAL_PINS 112 +#define NUM_ANALOG_INPUTS 30 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PD12 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PB3 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA8 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c index 0c376d3a61..ac73e22b91 100644 --- a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c +++ b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562AGIx.xml, STM32H562AIIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c index 6b857463d0..d822cc9898 100644 --- a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H562IGKx.xml, STM32H562IGTx.xml * STM32H562IIKx.xml, STM32H562IITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c index 42b4958f7c..fac64537dc 100644 --- a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGTx.xml, STM32H562RITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c index 18d766eb1e..2ab6deebbf 100644 --- a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGVx.xml, STM32H562RIVx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c index f691cfc2f2..fc51378e93 100644 --- a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562VGTx.xml, STM32H562VITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c index 3af63dcce3..422df63fb2 100644 --- a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562ZGTx.xml, STM32H562ZITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c b/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c index e06afe2316..7112aa3c85 100644 --- a/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c +++ b/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563AGIx.xml, STM32H563AIIx.xml * STM32H573AIIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -546,40 +546,51 @@ WEAK const PinMap PinMap_CAN_TD[] = { #ifdef HAL_ETH_MODULE_ENABLED WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {NC, NP, 0} + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PB_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PG_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PG_13_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_14_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/PinNamesVar.h b/variants/STM32H5xx/H563A(G-I)I_H573AII/PinNamesVar.h index f6532dee66..f26c759b84 100644 --- a/variants/STM32H5xx/H563A(G-I)I_H573AII/PinNamesVar.h +++ b/variants/STM32H5xx/H563A(G-I)I_H573AII/PinNamesVar.h @@ -34,6 +34,8 @@ PB_6_ALT2 = PB_6 | ALT2, PB_7_ALT1 = PB_7 | ALT1, PB_8_ALT1 = PB_8 | ALT1, PB_9_ALT1 = PB_9 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, PB_14_ALT1 = PB_14 | ALT1, PB_14_ALT2 = PB_14 | ALT2, PB_15_ALT1 = PB_15 | ALT1, @@ -52,7 +54,10 @@ PC_10_ALT1 = PC_10 | ALT1, PC_11_ALT1 = PC_11 | ALT1, PF_8_ALT1 = PF_8 | ALT1, PF_9_ALT1 = PF_9 | ALT1, +PG_11_ALT1 = PG_11 | ALT1, +PG_12_ALT1 = PG_12 | ALT1, PG_13_ALT1 = PG_13 | ALT1, +PG_14_ALT1 = PG_14 | ALT1, PH_6_ALT1 = PH_6 | ALT1, PH_6_ALT2 = PH_6 | ALT2, PH_7_ALT1 = PH_7 | ALT1, diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.h b/variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.h index 445346ec6b..a4cab6a6e5 100644 --- a/variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.h +++ b/variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.h @@ -188,6 +188,8 @@ #define PB7_ALT1 (PB7 | ALT1) #define PB8_ALT1 (PB8 | ALT1) #define PB9_ALT1 (PB9 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) #define PB14_ALT1 (PB14 | ALT1) #define PB14_ALT2 (PB14 | ALT2) #define PB15_ALT1 (PB15 | ALT1) @@ -206,7 +208,10 @@ #define PC11_ALT1 (PC11 | ALT1) #define PF8_ALT1 (PF8 | ALT1) #define PF9_ALT1 (PF9 | ALT1) +#define PG11_ALT1 (PG11 | ALT1) +#define PG12_ALT1 (PG12 | ALT1) #define PG13_ALT1 (PG13 | ALT1) +#define PG14_ALT1 (PG14 | ALT1) #define PH6_ALT1 (PH6 | ALT1) #define PH6_ALT2 (PH6 | ALT2) #define PH7_ALT1 (PH7 | ALT1) diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c index 5d64e4ee1b..b5a659b663 100644 --- a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563AIIxQ.xml, STM32H573AIIxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -541,37 +541,45 @@ WEAK const PinMap PinMap_CAN_TD[] = { #ifdef HAL_ETH_MODULE_ENABLED WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {NC, NP, 0} + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PB_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PinNamesVar.h b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PinNamesVar.h index 912e35d030..00166556ff 100644 --- a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PinNamesVar.h +++ b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PinNamesVar.h @@ -34,6 +34,8 @@ PB_6_ALT2 = PB_6 | ALT2, PB_7_ALT1 = PB_7 | ALT1, PB_8_ALT1 = PB_8 | ALT1, PB_9_ALT1 = PB_9 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, PB_14_ALT1 = PB_14 | ALT1, PB_14_ALT2 = PB_14 | ALT2, PB_15_ALT1 = PB_15 | ALT1, @@ -52,6 +54,7 @@ PC_10_ALT1 = PC_10 | ALT1, PC_11_ALT1 = PC_11 | ALT1, PF_8_ALT1 = PF_8 | ALT1, PF_9_ALT1 = PF_9 | ALT1, +PG_12_ALT1 = PG_12 | ALT1, PH_6_ALT1 = PH_6 | ALT1, PH_6_ALT2 = PH_6 | ALT2, PH_7_ALT1 = PH_7 | ALT1, diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.h b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.h index 5afe4a81c8..09ad42685c 100644 --- a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.h +++ b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.h @@ -186,6 +186,8 @@ #define PB7_ALT1 (PB7 | ALT1) #define PB8_ALT1 (PB8 | ALT1) #define PB9_ALT1 (PB9 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) #define PB14_ALT1 (PB14 | ALT1) #define PB14_ALT2 (PB14 | ALT2) #define PB15_ALT1 (PB15 | ALT1) @@ -204,6 +206,7 @@ #define PC11_ALT1 (PC11 | ALT1) #define PF8_ALT1 (PF8 | ALT1) #define PF9_ALT1 (PF9 | ALT1) +#define PG12_ALT1 (PG12 | ALT1) #define PH6_ALT1 (PH6 | ALT1) #define PH6_ALT2 (PH6 | ALT2) #define PH7_ALT1 (PH7 | ALT1) diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/PeripheralPins.c b/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/PeripheralPins.c index d38d8301d7..122bfb8af5 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32H563IIKx.xml, STM32H563IITx.xml * STM32H563LIHxQ.xml, STM32H573IIKx.xml * STM32H573IITx.xml, STM32H573LIHxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -556,41 +556,52 @@ WEAK const PinMap PinMap_CAN_TD[] = { #ifdef HAL_ETH_MODULE_ENABLED WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {NC, NP, 0} + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PB_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PG_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PG_13_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_14_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/PinNamesVar.h b/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/PinNamesVar.h index ddf97db984..232a34378c 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/PinNamesVar.h +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/PinNamesVar.h @@ -34,6 +34,8 @@ PB_6_ALT2 = PB_6 | ALT2, PB_7_ALT1 = PB_7 | ALT1, PB_8_ALT1 = PB_8 | ALT1, PB_9_ALT1 = PB_9 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, PB_14_ALT1 = PB_14 | ALT1, PB_14_ALT2 = PB_14 | ALT2, PB_15_ALT1 = PB_15 | ALT1, @@ -52,7 +54,10 @@ PC_10_ALT1 = PC_10 | ALT1, PC_11_ALT1 = PC_11 | ALT1, PF_8_ALT1 = PF_8 | ALT1, PF_9_ALT1 = PF_9 | ALT1, +PG_11_ALT1 = PG_11 | ALT1, +PG_12_ALT1 = PG_12 | ALT1, PG_13_ALT1 = PG_13 | ALT1, +PG_14_ALT1 = PG_14 | ALT1, PH_6_ALT1 = PH_6 | ALT1, PH_6_ALT2 = PH_6 | ALT2, PH_7_ALT1 = PH_7 | ALT1, diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/variant_generic.h b/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/variant_generic.h index c276491c76..f7e5241b2e 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/variant_generic.h +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/variant_generic.h @@ -192,6 +192,8 @@ #define PB7_ALT1 (PB7 | ALT1) #define PB8_ALT1 (PB8 | ALT1) #define PB9_ALT1 (PB9 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) #define PB14_ALT1 (PB14 | ALT1) #define PB14_ALT2 (PB14 | ALT2) #define PB15_ALT1 (PB15 | ALT1) @@ -210,7 +212,10 @@ #define PC11_ALT1 (PC11 | ALT1) #define PF8_ALT1 (PF8 | ALT1) #define PF9_ALT1 (PF9 | ALT1) +#define PG11_ALT1 (PG11 | ALT1) +#define PG12_ALT1 (PG12 | ALT1) #define PG13_ALT1 (PG13 | ALT1) +#define PG14_ALT1 (PG14 | ALT1) #define PH6_ALT1 (PH6 | ALT1) #define PH6_ALT2 (PH6 | ALT2) #define PH7_ALT1 (PH7 | ALT1) diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c index 3eae573165..0ef56938ad 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563IIKxQ.xml, STM32H573IIKxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -551,41 +551,52 @@ WEAK const PinMap PinMap_CAN_TD[] = { #ifdef HAL_ETH_MODULE_ENABLED WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {NC, NP, 0} + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PB_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PG_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PG_13_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_14_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PinNamesVar.h b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PinNamesVar.h index ddf97db984..232a34378c 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PinNamesVar.h +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PinNamesVar.h @@ -34,6 +34,8 @@ PB_6_ALT2 = PB_6 | ALT2, PB_7_ALT1 = PB_7 | ALT1, PB_8_ALT1 = PB_8 | ALT1, PB_9_ALT1 = PB_9 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, PB_14_ALT1 = PB_14 | ALT1, PB_14_ALT2 = PB_14 | ALT2, PB_15_ALT1 = PB_15 | ALT1, @@ -52,7 +54,10 @@ PC_10_ALT1 = PC_10 | ALT1, PC_11_ALT1 = PC_11 | ALT1, PF_8_ALT1 = PF_8 | ALT1, PF_9_ALT1 = PF_9 | ALT1, +PG_11_ALT1 = PG_11 | ALT1, +PG_12_ALT1 = PG_12 | ALT1, PG_13_ALT1 = PG_13 | ALT1, +PG_14_ALT1 = PG_14 | ALT1, PH_6_ALT1 = PH_6 | ALT1, PH_6_ALT2 = PH_6 | ALT2, PH_7_ALT1 = PH_7 | ALT1, diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.h b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.h index d2612c958b..ca7b3bba0e 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.h +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.h @@ -191,6 +191,8 @@ #define PB7_ALT1 (PB7 | ALT1) #define PB8_ALT1 (PB8 | ALT1) #define PB9_ALT1 (PB9 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) #define PB14_ALT1 (PB14 | ALT1) #define PB14_ALT2 (PB14 | ALT2) #define PB15_ALT1 (PB15 | ALT1) @@ -209,7 +211,10 @@ #define PC11_ALT1 (PC11 | ALT1) #define PF8_ALT1 (PF8 | ALT1) #define PF9_ALT1 (PF9 | ALT1) +#define PG11_ALT1 (PG11 | ALT1) +#define PG12_ALT1 (PG12 | ALT1) #define PG13_ALT1 (PG13 | ALT1) +#define PG14_ALT1 (PG14 | ALT1) #define PH6_ALT1 (PH6 | ALT1) #define PH6_ALT2 (PH6 | ALT2) #define PH7_ALT1 (PH7 | ALT1) diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c index b5ffdc0524..cb8050409d 100644 --- a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563IITxQ.xml, STM32H573IITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -546,41 +546,52 @@ WEAK const PinMap PinMap_CAN_TD[] = { #ifdef HAL_ETH_MODULE_ENABLED WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {NC, NP, 0} + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PB_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PG_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PG_13_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_14_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PinNamesVar.h b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PinNamesVar.h index e57cfd85f3..0e3293537e 100644 --- a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PinNamesVar.h +++ b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PinNamesVar.h @@ -34,6 +34,8 @@ PB_6_ALT2 = PB_6 | ALT2, PB_7_ALT1 = PB_7 | ALT1, PB_8_ALT1 = PB_8 | ALT1, PB_9_ALT1 = PB_9 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, PB_14_ALT1 = PB_14 | ALT1, PB_14_ALT2 = PB_14 | ALT2, PB_15_ALT1 = PB_15 | ALT1, @@ -52,7 +54,10 @@ PC_10_ALT1 = PC_10 | ALT1, PC_11_ALT1 = PC_11 | ALT1, PF_8_ALT1 = PF_8 | ALT1, PF_9_ALT1 = PF_9 | ALT1, +PG_11_ALT1 = PG_11 | ALT1, +PG_12_ALT1 = PG_12 | ALT1, PG_13_ALT1 = PG_13 | ALT1, +PG_14_ALT1 = PG_14 | ALT1, PH_6_ALT1 = PH_6 | ALT1, PH_6_ALT2 = PH_6 | ALT2, PH_7_ALT1 = PH_7 | ALT1, diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.h b/variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.h index a2b23b55ba..4bf5e62410 100644 --- a/variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.h +++ b/variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.h @@ -188,6 +188,8 @@ #define PB7_ALT1 (PB7 | ALT1) #define PB8_ALT1 (PB8 | ALT1) #define PB9_ALT1 (PB9 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) #define PB14_ALT1 (PB14 | ALT1) #define PB14_ALT2 (PB14 | ALT2) #define PB15_ALT1 (PB15 | ALT1) @@ -206,7 +208,10 @@ #define PC11_ALT1 (PC11 | ALT1) #define PF8_ALT1 (PF8 | ALT1) #define PF9_ALT1 (PF9 | ALT1) +#define PG11_ALT1 (PG11 | ALT1) +#define PG12_ALT1 (PG12 | ALT1) #define PG13_ALT1 (PG13 | ALT1) +#define PG14_ALT1 (PG14 | ALT1) #define PH6_ALT1 (PH6 | ALT1) #define PH6_ALT2 (PH6 | ALT2) #define PH7_ALT1 (PH7 | ALT1) diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c index 697629e3df..8c6324a4c6 100644 --- a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563MIYxQ.xml, STM32H573MIYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -386,29 +386,35 @@ WEAK const PinMap PinMap_CAN_TD[] = { #ifdef HAL_ETH_MODULE_ENABLED WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {NC, NP, 0} + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h index c06b9e6d50..24d0a399c3 100644 --- a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h @@ -33,6 +33,7 @@ PB_6_ALT1 = PB_6 | ALT1, PB_6_ALT2 = PB_6 | ALT2, PB_7_ALT1 = PB_7 | ALT1, PB_8_ALT1 = PB_8 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, PB_14_ALT1 = PB_14 | ALT1, PB_14_ALT2 = PB_14 | ALT2, PB_15_ALT1 = PB_15 | ALT1, diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.h b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.h index 06da07bd58..7738461e0a 100644 --- a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.h +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.h @@ -108,6 +108,7 @@ #define PB6_ALT2 (PB6 | ALT2) #define PB7_ALT1 (PB7 | ALT1) #define PB8_ALT1 (PB8 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) #define PB14_ALT1 (PB14 | ALT1) #define PB14_ALT2 (PB14 | ALT2) #define PB15_ALT1 (PB15 | ALT1) diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c index a1c042e581..d89854003b 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563RGTx.xml, STM32H563RITx.xml * STM32H573RITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -364,29 +364,35 @@ WEAK const PinMap PinMap_CAN_TD[] = { #ifdef HAL_ETH_MODULE_ENABLED WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {NC, NP, 0} + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h index c06b9e6d50..24d0a399c3 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h @@ -33,6 +33,7 @@ PB_6_ALT1 = PB_6 | ALT1, PB_6_ALT2 = PB_6 | ALT2, PB_7_ALT1 = PB_7 | ALT1, PB_8_ALT1 = PB_8 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, PB_14_ALT1 = PB_14 | ALT1, PB_14_ALT2 = PB_14 | ALT2, PB_15_ALT1 = PB_15 | ALT1, diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.h b/variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.h index 201035dd12..409fc3a206 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.h +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.h @@ -100,6 +100,7 @@ #define PB6_ALT2 (PB6 | ALT2) #define PB7_ALT1 (PB7 | ALT1) #define PB8_ALT1 (PB8 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) #define PB14_ALT1 (PB14 | ALT1) #define PB14_ALT2 (PB14 | ALT2) #define PB15_ALT1 (PB15 | ALT1) diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c index df39c5858d..53d5fed298 100644 --- a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563RGVx.xml, STM32H563RIVx.xml * STM32H573RIVx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -382,30 +382,37 @@ WEAK const PinMap PinMap_CAN_TD[] = { #ifdef HAL_ETH_MODULE_ENABLED WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {NC, NP, 0} + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PB_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h index 1ee6296ec3..db3a325074 100644 --- a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h @@ -34,6 +34,8 @@ PB_6_ALT2 = PB_6 | ALT2, PB_7_ALT1 = PB_7 | ALT1, PB_8_ALT1 = PB_8 | ALT1, PB_9_ALT1 = PB_9 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, PB_14_ALT1 = PB_14 | ALT1, PB_14_ALT2 = PB_14 | ALT2, PB_15_ALT1 = PB_15 | ALT1, diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.h b/variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.h index 5683ad57a5..3283360900 100644 --- a/variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.h +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.h @@ -105,6 +105,8 @@ #define PB7_ALT1 (PB7 | ALT1) #define PB8_ALT1 (PB8 | ALT1) #define PB9_ALT1 (PB9 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) #define PB14_ALT1 (PB14 | ALT1) #define PB14_ALT2 (PB14 | ALT2) #define PB15_ALT1 (PB15 | ALT1) diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c index 2a222a7696..5de1d659fa 100644 --- a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563VGTx.xml, STM32H563VITx.xml * STM32H573VITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -441,30 +441,36 @@ WEAK const PinMap PinMap_CAN_TD[] = { #ifdef HAL_ETH_MODULE_ENABLED WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {NC, NP, 0} + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PinNamesVar.h b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PinNamesVar.h index 118d5c80d2..b6f3b0c0d6 100644 --- a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PinNamesVar.h +++ b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PinNamesVar.h @@ -34,6 +34,7 @@ PB_6_ALT2 = PB_6 | ALT2, PB_7_ALT1 = PB_7 | ALT1, PB_8_ALT1 = PB_8 | ALT1, PB_9_ALT1 = PB_9 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, PB_14_ALT1 = PB_14 | ALT1, PB_14_ALT2 = PB_14 | ALT2, PB_15_ALT1 = PB_15 | ALT1, diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.h b/variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.h index bdd8401e4b..84dc195e4b 100644 --- a/variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.h +++ b/variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.h @@ -132,6 +132,7 @@ #define PB7_ALT1 (PB7 | ALT1) #define PB8_ALT1 (PB8 | ALT1) #define PB9_ALT1 (PB9 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) #define PB14_ALT1 (PB14 | ALT1) #define PB14_ALT2 (PB14 | ALT2) #define PB15_ALT1 (PB15 | ALT1) diff --git a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c index fd6d5c3b4b..523c479206 100644 --- a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563VITxQ.xml, STM32H573VITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c index 715e5170bf..b6e64d711e 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563ZGTx.xml, STM32H563ZITx.xml * STM32H573ZITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -498,35 +498,45 @@ WEAK const PinMap PinMap_CAN_TD[] = { #ifdef HAL_ETH_MODULE_ENABLED WEAK const PinMap PinMap_Ethernet[] = { - {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS - {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_REF_CLK - {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_CLK - {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO - {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_COL - {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_CRS_DV - {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_DV - {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_ER - {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD2 - {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD3 - {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RX_ER - {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC - {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD2 - {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_CLK - {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD0 - {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RXD1 - {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD3 - {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT - {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TX_EN - {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD0 - {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_TXD1 - {NC, NP, 0} + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TX_EN + {PG_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD0 + {PG_13_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_MII_TXD1 + {PG_14_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_ETH)}, // ETH_RMII_TXD1 + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PinNamesVar.h b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PinNamesVar.h index df96a15ce4..41ceb84b84 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PinNamesVar.h +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PinNamesVar.h @@ -34,6 +34,7 @@ PB_6_ALT2 = PB_6 | ALT2, PB_7_ALT1 = PB_7 | ALT1, PB_8_ALT1 = PB_8 | ALT1, PB_9_ALT1 = PB_9 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, PB_14_ALT1 = PB_14 | ALT1, PB_14_ALT2 = PB_14 | ALT2, PB_15_ALT1 = PB_15 | ALT1, @@ -52,7 +53,10 @@ PC_10_ALT1 = PC_10 | ALT1, PC_11_ALT1 = PC_11 | ALT1, PF_8_ALT1 = PF_8 | ALT1, PF_9_ALT1 = PF_9 | ALT1, +PG_11_ALT1 = PG_11 | ALT1, +PG_12_ALT1 = PG_12 | ALT1, PG_13_ALT1 = PG_13 | ALT1, +PG_14_ALT1 = PG_14 | ALT1, /* SYS_WKUP */ #ifdef PWR_WAKEUP_PIN1 diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.h b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.h index eada11799f..328f73cdc5 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.h +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.h @@ -164,6 +164,7 @@ #define PB7_ALT1 (PB7 | ALT1) #define PB8_ALT1 (PB8 | ALT1) #define PB9_ALT1 (PB9 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) #define PB14_ALT1 (PB14 | ALT1) #define PB14_ALT2 (PB14 | ALT2) #define PB15_ALT1 (PB15 | ALT1) @@ -182,7 +183,10 @@ #define PC11_ALT1 (PC11 | ALT1) #define PF8_ALT1 (PF8 | ALT1) #define PF9_ALT1 (PF9 | ALT1) +#define PG11_ALT1 (PG11 | ALT1) +#define PG12_ALT1 (PG12 | ALT1) #define PG13_ALT1 (PG13 | ALT1) +#define PG14_ALT1 (PG14 | ALT1) #define NUM_DIGITAL_PINS 112 #define NUM_ANALOG_INPUTS 20 diff --git a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c index eeb3b7fca0..06ac80922d 100644 --- a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563ZITxQ.xml, STM32H573ZITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c index dffac4a4f8..2080e784a7 100644 --- a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32H723VGHx.xml, STM32H723VGTx.xml * STM32H730VBHx.xml, STM32H730VBTx.xml * STM32H733VGHx.xml, STM32H733VGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c b/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c index b116f8139f..196da654a7 100644 --- a/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c +++ b/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H723ZEIx.xml, STM32H723ZGIx.xml * STM32H730ZBIx.xml, STM32H733ZGIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c index 1f1eb598f5..3b72b61ac6 100644 --- a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c +++ b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H723ZETx.xml, STM32H723ZGTx.xml * STM32H730ZBTx.xml, STM32H733ZGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c index c41b95ba27..6f3968d465 100644 --- a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c +++ b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725AEIx.xml, STM32H725AGIx.xml * STM32H730ABIxQ.xml, STM32H735AGIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c index 801080dbe3..cc02c6edf2 100644 --- a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c +++ b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725IEKx.xml, STM32H725IGKx.xml * STM32H730IBKxQ.xml, STM32H735IGKx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c index 4867dc2867..c867791787 100644 --- a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725IETx.xml, STM32H725IGTx.xml * STM32H730IBTxQ.xml, STM32H735IGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c b/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c index b7a9274432..5762160c13 100644 --- a/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c +++ b/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725REVx.xml, STM32H725RGVx.xml * STM32H735RGVx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c b/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c index caa8f9f8b3..10b0dd142e 100644 --- a/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c +++ b/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725VEHx.xml, STM32H725VGHx.xml * STM32H735VGHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c b/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c index 1d806da21f..0c90ca2ea0 100644 --- a/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725VETx.xml, STM32H725VGTx.xml * STM32H735VGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c b/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c index b77182857a..0489db768c 100644 --- a/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c +++ b/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H725VGYx.xml, STM32H735VGYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c b/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c index f3a35a9b04..dfa6691af2 100644 --- a/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725ZETx.xml, STM32H725ZGTx.xml * STM32H735ZGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c b/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c index cde36b8eac..09b49fd67d 100644 --- a/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c +++ b/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H742A(G-I)Ix.xml, STM32H743A(G-I)Ix.xml * STM32H753AIIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c b/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c index 07385f19bf..6200bb5c51 100644 --- a/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H742B(G-I)Tx.xml, STM32H743BGTx.xml * STM32H743BITx.xml, STM32H753BITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c index e85e479733..0a98f9407c 100644 --- a/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32H743IIKx.xml, STM32H743IITx.xml * STM32H750IBKx.xml, STM32H750IBTx.xml * STM32H753IIKx.xml, STM32H753IITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c index d70770d0fd..bcd45d6bd2 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32H743V(G-I)Hx.xml, STM32H743VGTx.xml * STM32H743VITx.xml, STM32H750VBTx.xml * STM32H753VIHx.xml, STM32H753VITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c index 67e82a900e..229f680230 100644 --- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c @@ -17,7 +17,7 @@ * STM32H747XIHx.xml, STM32H750XBHx.xml * STM32H753XIHx.xml, STM32H755XIHx.xml * STM32H757XIHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c index cc2017f5d3..a27c8e76f6 100644 --- a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32H747IGTx.xml, STM32H747IITx.xml * STM32H750ZBTx.xml, STM32H753ZITx.xml * STM32H757AIIx.xml, STM32H757IITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c b/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c index 64cf49183a..2958ad35c6 100644 --- a/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745BGTx.xml, STM32H745BITx.xml * STM32H755BITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c b/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c index 49cd4f4a1c..caa257e26e 100644 --- a/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c +++ b/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745IGKx.xml, STM32H745IIKx.xml * STM32H755IIKx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c b/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c index 4c2c246f15..9a565324c2 100644 --- a/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745IGTx.xml, STM32H745IITx.xml * STM32H755IITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c index afe8274153..80b854d3ed 100644 --- a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745ZGTx.xml, STM32H745ZITx.xml * STM32H755ZITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c b/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c index 7d361fa0d1..a5699944e0 100644 --- a/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H747BGTx.xml, STM32H747BITx.xml * STM32H757BITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c b/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c index fe1350cc0d..2a6e5eb618 100644 --- a/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c +++ b/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H747ZIYx.xml, STM32H757ZIYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c index 65650c3fce..7a05ce0cb5 100644 --- a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3A(G-I)IxQ.xml, STM32H7B0ABIxQ.xml * STM32H7B3AIIxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c index 4281881aec..c68afbb616 100644 --- a/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H7A3I(G-I)Kx.xml, STM32H7A3I(G-I)Tx.xml * STM32H7B0IBTx.xml, STM32H7B3IIKx.xml * STM32H7B3IITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c index 58ca57be45..6e69dba43b 100644 --- a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3I(G-I)KxQ.xml, STM32H7B0IBKxQ.xml * STM32H7B3IIKxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c index 240a354072..4c96004557 100644 --- a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3I(G-I)TxQ.xml, STM32H7B3IITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c index 7273b89cb2..60b881ee4c 100644 --- a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3L(G-I)HxQ.xml, STM32H7B3LIHxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c b/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c index 18f02a7aa0..d325d8dea4 100644 --- a/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3N(G-I)Hx.xml, STM32H7B3NIHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c index 908d9008e4..c8a8963f86 100644 --- a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3QIYxQ.xml, STM32H7B3QIYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c b/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c index c03292189d..56c5962531 100644 --- a/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3R(G-I)Tx.xml, STM32H7B0RBTx.xml * STM32H7B3RITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c index 018cce5616..674244e446 100644 --- a/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H7A3V(G-I)Hx.xml, STM32H7A3V(G-I)Tx.xml * STM32H7B0VBTx.xml, STM32H7B3VIHx.xml * STM32H7B3VITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c index c8c8e7b6df..becb7d93fe 100644 --- a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3V(G-I)HxQ.xml, STM32H7B3VIHxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c index 7e31ea5682..73f79828f8 100644 --- a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3V(G-I)TxQ.xml, STM32H7B3VITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c b/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c index d0e1009622..b659e955ee 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3Z(G-I)Tx.xml, STM32H7B0ZBTx.xml * STM32H7B3ZITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c index 587051c629..52ba74aff7 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3Z(G-I)TxQ.xml, STM32H7B3ZITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010C6T/PeripheralPins.c b/variants/STM32L0xx/L010C6T/PeripheralPins.c index 008ba84808..66c0f75830 100644 --- a/variants/STM32L0xx/L010C6T/PeripheralPins.c +++ b/variants/STM32L0xx/L010C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010C6Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c index ddc19c33ac..57ece327f3 100644 --- a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c +++ b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L010F4Px.xml, STM32L011F(3-4)Px.xml * STM32L021F4Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c index 01871198e4..d9b9df8366 100644 --- a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c +++ b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L010K4Tx.xml, STM32L011K(3-4)Tx.xml * STM32L021K4Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010K8T/PeripheralPins.c b/variants/STM32L0xx/L010K8T/PeripheralPins.c index fa70fb9a2e..e73f65b42a 100644 --- a/variants/STM32L0xx/L010K8T/PeripheralPins.c +++ b/variants/STM32L0xx/L010K8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010K8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010R8T/PeripheralPins.c b/variants/STM32L0xx/L010R8T/PeripheralPins.c index 905127ee7f..04b2420dcd 100644 --- a/variants/STM32L0xx/L010R8T/PeripheralPins.c +++ b/variants/STM32L0xx/L010R8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010R8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010RBT/PeripheralPins.c b/variants/STM32L0xx/L010RBT/PeripheralPins.c index c10d2a3aa1..81f5c33d1a 100644 --- a/variants/STM32L0xx/L010RBT/PeripheralPins.c +++ b/variants/STM32L0xx/L010RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010RBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c b/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c index e47c160b3c..9f7ee8e7fa 100644 --- a/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c +++ b/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011D(3-4)Px.xml, STM32L021D4Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c b/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c index b69b9c15f5..b646306c1a 100644 --- a/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011E(3-4)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c b/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c index 4355e201bb..598acfde33 100644 --- a/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011F(3-4)Ux.xml, STM32L021F4Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c b/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c index ce4aeee9eb..652d78da90 100644 --- a/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011G(3-4)Ux.xml, STM32L021G4Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c b/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c index d33b98481e..a15cd71805 100644 --- a/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011K(3-4)Ux.xml, STM32L021K4Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c index e118b6422a..6ac7505f57 100644 --- a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L031C(4-6)Tx.xml, STM32L031C(4-6)Ux.xml * STM32L041C(4-6)Tx.xml, STM32L041C6Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c index 1de7d3b223..761bd7db6b 100644 --- a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c +++ b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031E(4-6)Yx.xml, STM32L041E6Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c b/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c index 520fd0fa75..2b90d25736 100644 --- a/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c +++ b/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031F(4-6)Px.xml, STM32L041F6Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c b/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c index bedfb4eb5b..f30cafd6e4 100644 --- a/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c +++ b/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031G(4-6)Ux.xml, STM32L041G6Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c b/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c index 9c1256081f..dffb0993ee 100644 --- a/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c +++ b/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031G6UxS.xml, STM32L041G6UxS.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c b/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c index b78ac8976f..fe5b8b69ca 100644 --- a/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c +++ b/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031K(4-6)Tx.xml, STM32L041K6Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c b/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c index c87d7210ae..cade47c11a 100644 --- a/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c +++ b/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031K(4-6)Ux.xml, STM32L041K6Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c b/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c index c152ae0b57..42e7c60055 100644 --- a/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051C(6-8)Tx.xml, STM32L051C(6-8)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c b/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c index 2972211e36..8570114461 100644 --- a/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c +++ b/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051K(6-8)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c b/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c index b3968834f4..c90cde7614 100644 --- a/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c +++ b/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051K(6-8)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c b/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c index d89510a854..2aab9a2293 100644 --- a/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c +++ b/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051R(6-8)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c b/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c index e49a88cd66..3617bf5b81 100644 --- a/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c +++ b/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051R(6-8)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c b/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c index d2400603b9..c09407fde6 100644 --- a/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051T(6-8)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c index f4620fea73..3d98216faa 100644 --- a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L053C(6-8)Tx.xml, STM32L053C(6-8)Ux.xml * STM32L062C8Ux.xml, STM32L063C8Tx.xml * STM32L063C8Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c b/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c index 0e1690d313..1c1df1402a 100644 --- a/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c +++ b/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052K(6-8)Tx.xml, STM32L062K8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c b/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c index 51175411f5..87ac72ade8 100644 --- a/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c +++ b/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052K(6-8)Ux.xml, STM32L062K8Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c index 7d4636c6f5..6a0e09491e 100644 --- a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c +++ b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052R(6-8)Hx.xml, STM32L053R(6-8)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c b/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c index e59286d7ef..1ee998c674 100644 --- a/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c +++ b/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L052R(6-8)Tx.xml, STM32L053R(6-8)Tx.xml * STM32L063R8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c index a8058ef477..dff7c0505f 100644 --- a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c +++ b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052T(6-8)Yx.xml, STM32L052T8Fx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c b/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c index a1f8a13fc2..a159697945 100644 --- a/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L071C(B-Z)Tx.xml, STM32L071C(B-Z)Ux.xml * STM32L071C8Tx.xml, STM32L071C8Ux.xml * STM32L081C(B-Z)Tx.xml, STM32L081CZUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c b/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c index 2404129899..424aaedf21 100644 --- a/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071C(B-Z)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c b/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c index ad91d3c1d0..2ca6013c3e 100644 --- a/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c +++ b/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L071K(B-Z)Ux.xml, STM32L071K8Ux.xml * STM32L081KZUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c b/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c index ba16e41bd7..db576849c4 100644 --- a/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c +++ b/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071K(B-Z)Tx.xml, STM32L081KZTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c b/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c index 999387070b..98345c3461 100644 --- a/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c +++ b/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071R(B-Z)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c index e17d1005d3..f242699cb7 100644 --- a/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071R(B-Z)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c b/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c index 57cfb8f630..ed8b9008ed 100644 --- a/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c +++ b/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L071V(B-Z)Ix.xml, STM32L071V(B-Z)Tx.xml * STM32L071V8Ix.xml, STM32L071V8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c index c206493f07..48f9bdbf1a 100644 --- a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L073C(B-Z)Tx.xml, STM32L073C(B-Z)Ux.xml * STM32L082CZUx.xml, STM32L083C(B-Z)Tx.xml * STM32L083CZUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c b/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c index d1ecbe6582..7ff1b9ea41 100644 --- a/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c +++ b/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L072C(B-Z)Yx.xml, STM32L072CZEx.xml * STM32L073CZYx.xml, STM32L082CZYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c index c3605c9f34..869b2d423a 100644 --- a/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L072K(B-Z)Tx.xml, STM32L082K(B-Z)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c index 3ee60ff5f6..a14db73817 100644 --- a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c +++ b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L072K(B-Z)Ux.xml, STM32L082K(B-Z)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c index 8d03754ee6..aa8efdd42a 100644 --- a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c +++ b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L072R(B-Z)Hx.xml, STM32L072R(B-Z)Ix.xml * STM32L073R(B-Z)Hx.xml, STM32L073RZIx.xml * STM32L083R(B-Z)Hx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c index a81038ba48..44bd2f2ebf 100644 --- a/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L072R(B-Z)Tx.xml, STM32L073R(B-Z)Tx.xml * STM32L083R(B-Z)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c index ac2b936e4f..9f6cb68c6d 100644 --- a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c +++ b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c @@ -17,7 +17,7 @@ * STM32L073V8Ix.xml, STM32L073V8Tx.xml * STM32L083V(B-Z)Ix.xml, STM32L083V(B-Z)Tx.xml * STM32L083V8Ix.xml, STM32L083V8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c index 028cefd872..4aa960ca64 100644 --- a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L151C(6-8-B)Ux.xml, STM32L151C(6-8-B)UxA.xml * STM32L152C(6-8-B)Tx.xml, STM32L152C(6-8-B)TxA.xml * STM32L152C(6-8-B)Ux.xml, STM32L152C(6-8-B)UxA.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c index 666428910a..45e1c26b9b 100644 --- a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L100R(8-B)Tx.xml, STM32L100R(8-B)TxA.xml * STM32L151R(6-8-B)Tx.xml, STM32L151R(6-8-B)TxA.xml * STM32L152R(6-8-B)Tx.xml, STM32L152R(6-8-B)TxA.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100RCT/PeripheralPins.c b/variants/STM32L1xx/L100RCT/PeripheralPins.c index 77ad37c996..c02c55cb82 100644 --- a/variants/STM32L1xx/L100RCT/PeripheralPins.c +++ b/variants/STM32L1xx/L100RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L100RCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c b/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c index 0072c48b02..9ccdc8f299 100644 --- a/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c +++ b/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151CCTx.xml, STM32L151CCUx.xml * STM32L152CCTx.xml, STM32L152CCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c b/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c index ba4af9a6bd..e392ff52fd 100644 --- a/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151QCHx.xml, STM32L152QCHx.xml * STM32L162QCHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c b/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c index 5a53888fb1..ae5bd08972 100644 --- a/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151QDHx.xml, STM32L152QDHx.xml * STM32L162QDHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c b/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c index e2cf9932ba..ad1e8a680c 100644 --- a/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L151QEHx.xml, STM32L152QEHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c index bcb6808f94..2e6a4007cc 100644 --- a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151R(6-8-B)Hx.xml, STM32L151R(6-8-B)HxA.xml * STM32L152R(6-8-B)Hx.xml, STM32L152R(6-8-B)HxA.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c index 3f7d3a7f7c..1d35aef06b 100644 --- a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152RCTx.xml, STM32L152RCTxA.xml * STM32L152UCYx.xml, STM32L162RCTx.xml * STM32L162RCTxA.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c b/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c index 43a402969e..6f88f8665a 100644 --- a/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c +++ b/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L151RDTx.xml, STM32L151RDYx.xml * STM32L152RDTx.xml, STM32L152RDYx.xml * STM32L162RDTx.xml, STM32L162RDYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c b/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c index ffd08c2c46..0642e4bbc2 100644 --- a/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c +++ b/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151RETx.xml, STM32L152RETx.xml * STM32L162RETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c index fd98309768..5f4e092c31 100644 --- a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L151V(8-B)Tx.xml, STM32L151V(8-B)TxA.xml * STM32L152V(8-B)Hx.xml, STM32L152V(8-B)HxA.xml * STM32L152V(8-B)Tx.xml, STM32L152V(8-B)TxA.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c index ce3e7762c1..45ae67c24f 100644 --- a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152VCTx.xml, STM32L152VCTxA.xml * STM32L162VCHx.xml, STM32L162VCTx.xml * STM32L162VCTxA.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c b/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c index 0cb4d086df..330a86da57 100644 --- a/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c +++ b/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152VDTxX.xml, STM32L152VETx.xml * STM32L152VEYx.xml, STM32L162VDYxX.xml * STM32L162VETx.xml, STM32L162VEYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c b/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c index ea306139b6..17148fdab3 100644 --- a/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c +++ b/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151VDTx.xml, STM32L152VDTx.xml * STM32L162VDTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c b/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c index fdf6fbae8e..8bcba4c3e8 100644 --- a/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZCTx.xml, STM32L152ZCTx.xml * STM32L162ZCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c b/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c index eae5ab0724..ae2e2e95a7 100644 --- a/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZDTx.xml, STM32L152ZDTx.xml * STM32L162ZDTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c b/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c index a41ff85d7a..7976f575d7 100644 --- a/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZETx.xml, STM32L152ZETx.xml * STM32L162ZETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c index 1b843890e2..4fa9383581 100644 --- a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412C8Tx.xml, STM32L412C8Ux.xml * STM32L412CBTx.xml, STM32L412CBUx.xml * STM32L422CBTx.xml, STM32L422CBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c b/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c index b3514f1649..3976ad47f6 100644 --- a/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412CBTxP.xml, STM32L412CBUxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c index 8d9f2a9cc4..9faa6a4a44 100644 --- a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412K8Tx.xml, STM32L412K8Ux.xml * STM32L412KBTx.xml, STM32L412KBUx.xml * STM32L422KBTx.xml, STM32L422KBUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c index a07c756b9b..426f6a3822 100644 --- a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412R8Ix.xml, STM32L412R8Tx.xml * STM32L412RBIx.xml, STM32L412RBTx.xml * STM32L422RBIx.xml, STM32L422RBTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c b/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c index 32ee50e703..ce01e5c5be 100644 --- a/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412RBIxP.xml, STM32L412RBTxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c index 84fe9efd8f..4f2e6b7c2c 100644 --- a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c +++ b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L412T8Yx.xml, STM32L412TBYx.xml * STM32L422TBYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412TBYxP/PeripheralPins.c b/variants/STM32L4xx/L412TBYxP/PeripheralPins.c index 1377ef3542..e89b32e2f4 100644 --- a/variants/STM32L4xx/L412TBYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L412TBYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412TBYxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c b/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c index c40f41d34b..62fe3a8bac 100644 --- a/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431C(B-C)Tx.xml, STM32L431C(B-C)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c b/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c index 0bbfe82185..2b9a055a2f 100644 --- a/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c +++ b/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431C(B-C)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c b/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c index 7deeb0fd90..05834f27d0 100644 --- a/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c +++ b/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431K(B-C)Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c index 5640f5cf89..c40807ff86 100644 --- a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L431R(B-C)Ix.xml, STM32L431R(B-C)Tx.xml * STM32L431R(B-C)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c b/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c index 5f9ae7fb8b..dad1be1864 100644 --- a/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431VCIx.xml, STM32L431VCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c index 61f6bf4078..5a39cb1e31 100644 --- a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c +++ b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L432K(B-C)Ux.xml, STM32L442KCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c index 9b44156b90..b16a768afa 100644 --- a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433C(B-C)Tx.xml, STM32L433C(B-C)Ux.xml * STM32L443CCTx.xml, STM32L443CCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c index f43a795f65..a386cb3134 100644 --- a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433C(B-C)Yx.xml, STM32L443CCFx.xml * STM32L443CCYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c index 27f95f00f1..f231d8f2e3 100644 --- a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L433R(B-C)Ix.xml, STM32L433R(B-C)Tx.xml * STM32L433R(B-C)Yx.xml, STM32L443RCIx.xml * STM32L443RCTx.xml, STM32L443RCYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433RCTxP/PeripheralPins.c b/variants/STM32L4xx/L433RCTxP/PeripheralPins.c index 7f8aefc85a..c4bc9f7f34 100644 --- a/variants/STM32L4xx/L433RCTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L433RCTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L433RCTxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c index a167f0e6f0..55ad8d7d86 100644 --- a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433VCIx.xml, STM32L433VCTx.xml * STM32L443VCIx.xml, STM32L443VCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c index 509f3d399c..fb66834efa 100644 --- a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L451C(C-E)Ux.xml, STM32L451CETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c index c61215203d..9227cb5e7b 100644 --- a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L451R(C-E)Ix.xml, STM32L451R(C-E)Tx.xml * STM32L451R(C-E)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c b/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c index 80dd90676a..176b4ec89f 100644 --- a/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L451V(C-E)Ix.xml, STM32L451V(C-E)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c index e26ebfd412..ab9f70a687 100644 --- a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L452C(C-E)Ux.xml, STM32L452CETx.xml * STM32L452CETxP.xml, STM32L462CETx.xml * STM32L462CEUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c index 8c6b960763..d1bd4e6496 100644 --- a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L452R(C-E)Yx.xml, STM32L452REYxP.xml * STM32L462REIx.xml, STM32L462RETx.xml * STM32L462REYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452RETxP/PeripheralPins.c b/variants/STM32L4xx/L452RETxP/PeripheralPins.c index 5c421c5b9d..c95dd68a51 100644 --- a/variants/STM32L4xx/L452RETxP/PeripheralPins.c +++ b/variants/STM32L4xx/L452RETxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L452RETxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c index 43f3491c3e..9767818586 100644 --- a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L452V(C-E)Ix.xml, STM32L452V(C-E)Tx.xml * STM32L462VEIx.xml, STM32L462VETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c b/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c index f711507fe7..2012d8e5e1 100644 --- a/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c +++ b/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471Q(E-G)Ix.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c b/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c index fc6cf0eb47..78aa2cbc79 100644 --- a/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c +++ b/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471R(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c b/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c index 88889d6151..4e878766ba 100644 --- a/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c +++ b/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471V(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c b/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c index 779acb4fce..93e4fd5cbc 100644 --- a/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471Z(E-G)Jx.xml, STM32L471Z(E-G)Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c index 583c128682..b3a02759c3 100644 --- a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L475R(C-E-G)Tx.xml, STM32L476R(C-E-G)Tx.xml * STM32L486RGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c index 979eaeaebb..8e6410145b 100644 --- a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L475V(C-E-G)Tx.xml, STM32L476V(C-E-G)Tx.xml * STM32L486VGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c index f073b2620b..d606f9a314 100644 --- a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c +++ b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476J(E-G)Yx.xml, STM32L485J(C-E)Yx.xml * STM32L486JGYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476JGYxP/PeripheralPins.c b/variants/STM32L4xx/L476JGYxP/PeripheralPins.c index c5878320c4..b71b330046 100644 --- a/variants/STM32L4xx/L476JGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476JGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476JGYxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c b/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c index 2dc59354fd..e55ab88bef 100644 --- a/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c +++ b/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476M(E-G)Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c index ca411107ca..5fcb11913d 100644 --- a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476Q(E-G)Ix.xml, STM32L476QGIxP.xml * STM32L486QGIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476VGYxP/PeripheralPins.c b/variants/STM32L4xx/L476VGYxP/PeripheralPins.c index 415ca52b18..1d0f7507ad 100644 --- a/variants/STM32L4xx/L476VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476VGYxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c index 0e9c0ab9b5..2309661930 100644 --- a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476Z(E-G)Tx.xml, STM32L476ZGJx.xml * STM32L486ZGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c index 8895e7e9cd..255b6a969c 100644 --- a/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476ZGTxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c index 0ecc000fd1..c0c808e9f9 100644 --- a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c +++ b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496A(E-G)Ix.xml, STM32L4A6AGIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c index 0a67d29e9b..9b8a8601db 100644 --- a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496AGIxP.xml, STM32L4A6AGIxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c index 53967d0dfa..8e4d42eeb3 100644 --- a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L496Q(E-G)Ix.xml, STM32L496QGIxS.xml * STM32L4A6QGIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c index 5eb4126c84..4d3b3a3045 100644 --- a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496QGIxP.xml, STM32L4A6QGIxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c index 86c22c659f..1c0575b350 100644 --- a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496R(E-G)Tx.xml, STM32L4A6RGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496RGTxP/PeripheralPins.c b/variants/STM32L4xx/L496RGTxP/PeripheralPins.c index 21d3569daa..b664d7d456 100644 --- a/variants/STM32L4xx/L496RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496RGTxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c index 20388e7d9e..539ee85292 100644 --- a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496V(E-G)Tx.xml, STM32L4A6VGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c index a3fc813c14..64a61d6950 100644 --- a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGTxP.xml, STM32L4A6VGTxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c b/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c index d3644fcc1a..fab8348588 100644 --- a/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGYx.xml, STM32L4A6VGYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c index fb7733be50..5cb6023d86 100644 --- a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGYxP.xml, STM32L4A6VGYxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496WGYxP/PeripheralPins.c b/variants/STM32L4xx/L496WGYxP/PeripheralPins.c index 1d6ff037d2..3e116a0cbf 100644 --- a/variants/STM32L4xx/L496WGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496WGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496WGYxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c index d59d0b7797..27c9f457a7 100644 --- a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496Z(E-G)Tx.xml, STM32L4A6ZGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c index d13706fa38..e5edb91294 100644 --- a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496ZGTxP.xml, STM32L4A6ZGTxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c b/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c index 533122eec2..eeec73b7ec 100644 --- a/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4A6RGTxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c index 8f351b23b4..b09314ac48 100644 --- a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5A(G-E)Ix.xml, STM32L4Q5AGIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c index bedc6af23e..e6b1ab7379 100644 --- a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5AGIxP.xml, STM32L4Q5AGIxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c index 776c0d5688..0c5d282202 100644 --- a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5C(G-E)Tx.xml, STM32L4P5C(G-E)Ux.xml * STM32L4Q5CGTx.xml, STM32L4Q5CGUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c index ed514956b1..074a9a0c50 100644 --- a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5CGTxP.xml, STM32L4P5CGUxP.xml * STM32L4Q5CGTxP.xml, STM32L4Q5CGUxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c index 766801405a..67f1f0266c 100644 --- a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5Q(G-E)Ix.xml, STM32L4Q5QGIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c index 974e29bb9a..279c07b8a8 100644 --- a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5QGIxP.xml, STM32L4P5QGIxS.xml * STM32L4Q5QGIxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c b/variants/STM32L4xx/L4P5R(G-E)T/PeripheralPins.c similarity index 99% rename from variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c rename to variants/STM32L4xx/L4P5R(G-E)T/PeripheralPins.c index 94be4c975e..8ca84b675c 100644 --- a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5R(G-E)T/PeripheralPins.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32L4P5R(G-E)Tx.xml, STM32L4Q5RGTx.xml - * CubeMX DB release 6.0.170 + * Automatically generated from STM32L4P5R(G-E)Tx.xml + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PinNamesVar.h b/variants/STM32L4xx/L4P5R(G-E)T/PinNamesVar.h similarity index 100% rename from variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PinNamesVar.h rename to variants/STM32L4xx/L4P5R(G-E)T/PinNamesVar.h diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/boards_entry.txt b/variants/STM32L4xx/L4P5R(G-E)T/boards_entry.txt similarity index 69% rename from variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/boards_entry.txt rename to variants/STM32L4xx/L4P5R(G-E)T/boards_entry.txt index 65577be970..68d38c42ee 100644 --- a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/boards_entry.txt +++ b/variants/STM32L4xx/L4P5R(G-E)T/boards_entry.txt @@ -9,7 +9,7 @@ GenL4.menu.pnum.GENERIC_L4P5RGTX.upload.maximum_size=1048576 GenL4.menu.pnum.GENERIC_L4P5RGTX.upload.maximum_data_size=327680 GenL4.menu.pnum.GENERIC_L4P5RGTX.build.board=GENERIC_L4P5RGTX GenL4.menu.pnum.GENERIC_L4P5RGTX.build.product_line=STM32L4P5xx -GenL4.menu.pnum.GENERIC_L4P5RGTX.build.variant=STM32L4xx/L4P5R(G-E)T_L4Q5RGT +GenL4.menu.pnum.GENERIC_L4P5RGTX.build.variant=STM32L4xx/L4P5R(G-E)T GenL4.menu.pnum.GENERIC_L4P5RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4P5.svd # Generic L4P5RETx @@ -18,15 +18,6 @@ GenL4.menu.pnum.GENERIC_L4P5RETX.upload.maximum_size=524288 GenL4.menu.pnum.GENERIC_L4P5RETX.upload.maximum_data_size=327680 GenL4.menu.pnum.GENERIC_L4P5RETX.build.board=GENERIC_L4P5RETX GenL4.menu.pnum.GENERIC_L4P5RETX.build.product_line=STM32L4P5xx -GenL4.menu.pnum.GENERIC_L4P5RETX.build.variant=STM32L4xx/L4P5R(G-E)T_L4Q5RGT +GenL4.menu.pnum.GENERIC_L4P5RETX.build.variant=STM32L4xx/L4P5R(G-E)T GenL4.menu.pnum.GENERIC_L4P5RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4P5.svd -# Generic L4Q5RGTx -GenL4.menu.pnum.GENERIC_L4Q5RGTX=Generic L4Q5RGTx -GenL4.menu.pnum.GENERIC_L4Q5RGTX.upload.maximum_size=1048576 -GenL4.menu.pnum.GENERIC_L4Q5RGTX.upload.maximum_data_size=327680 -GenL4.menu.pnum.GENERIC_L4Q5RGTX.build.board=GENERIC_L4Q5RGTX -GenL4.menu.pnum.GENERIC_L4Q5RGTX.build.product_line=STM32L4Q5xx -GenL4.menu.pnum.GENERIC_L4Q5RGTX.build.variant=STM32L4xx/L4P5R(G-E)T_L4Q5RGT -GenL4.menu.pnum.GENERIC_L4Q5RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4Q5.svd - diff --git a/variants/STM32L4xx/L4P5R(G-E)T/generic_clock.c b/variants/STM32L4xx/L4P5R(G-E)T/generic_clock.c new file mode 100644 index 0000000000..3f13c1785c --- /dev/null +++ b/variants/STM32L4xx/L4P5R(G-E)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_L4P5RGTX) || defined(ARDUINO_GENERIC_L4P5RETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/variant_generic.cpp b/variants/STM32L4xx/L4P5R(G-E)T/variant_generic.cpp similarity index 94% rename from variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/variant_generic.cpp rename to variants/STM32L4xx/L4P5R(G-E)T/variant_generic.cpp index cf149e61bd..d0796a89a4 100644 --- a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/variant_generic.cpp +++ b/variants/STM32L4xx/L4P5R(G-E)T/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_L4P5RETX) || defined(ARDUINO_GENERIC_L4P5RGTX) ||\ - defined(ARDUINO_GENERIC_L4Q5RGTX) +#if defined(ARDUINO_GENERIC_L4P5RGTX) || defined(ARDUINO_GENERIC_L4P5RETX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/variant_generic.h b/variants/STM32L4xx/L4P5R(G-E)T/variant_generic.h similarity index 100% rename from variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/variant_generic.h rename to variants/STM32L4xx/L4P5R(G-E)T/variant_generic.h diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/CMakeLists.txt b/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c index a857f121e0..dfde5fd542 100644 --- a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5RGTxP.xml, STM32L4Q5RGTxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c index bc5537f3c3..9c857d3dde 100644 --- a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5V(G-E)Tx.xml, STM32L4Q5VGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c index bbf4b22e32..cce0350457 100644 --- a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5V(G-E)Yx.xml, STM32L4Q5VGYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c index 3adfdc0866..d17aba6e5e 100644 --- a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5VGTxP.xml, STM32L4Q5VGTxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c index dd4682c63d..c851d10e23 100644 --- a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5VGYxP.xml, STM32L4Q5VGYxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c index c8edabcf63..388ff457af 100644 --- a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5Z(G-E)Tx.xml, STM32L4Q5ZGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c index aef88592c4..dd085a61a9 100644 --- a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5ZGTxP.xml, STM32L4Q5ZGTxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4Q5RGT/PeripheralPins.c b/variants/STM32L4xx/L4Q5RGT/PeripheralPins.c new file mode 100644 index 0000000000..9429eebdce --- /dev/null +++ b/variants/STM32L4xx/L4Q5RGT/PeripheralPins.c @@ -0,0 +1,542 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32L4Q5RGTx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_IN12 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC2_IN15 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 16, 0)}, // ADC1_IN16 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 16, 0)}, // ADC2_IN16 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC2_IN14 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF5_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {PB_11_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C4)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF6_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF5_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {PB_10_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C4)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** CAN *** + +#if defined(HAL_CAN_MODULE_ENABLED) || defined(HAL_CAN_LEGACY_MODULE_ENABLED) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, + {PB_8, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, + {NC, NP, 0} +}; +#endif + +#if defined(HAL_CAN_MODULE_ENABLED) || defined(HAL_CAN_LEGACY_MODULE_ENABLED) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, + {PB_9, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PB_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 + {PB_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO7 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PA_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF_NONE)}, // OCTOSPIM_P2_NCS + {PB_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PC_4, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_FS[] = { + {PA_8, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF + {PA_9, USB_OTG_FS, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS + {PA_10, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID + {PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM + {PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP + {PA_13, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_NOE + {PA_14, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF + {PC_9, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_NOE + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC2)}, // SDMMC2_CMD + {PC_0, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PB_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SDMMC2)}, // SDMMC2_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_CKIN + {PC_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_SDMMC2)}, // SDMMC2_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32L4xx/L4Q5RGT/PinNamesVar.h b/variants/STM32L4xx/L4Q5RGT/PinNamesVar.h new file mode 100644 index 0000000000..0e90677743 --- /dev/null +++ b/variants/STM32L4xx/L4Q5RGT/PinNamesVar.h @@ -0,0 +1,91 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PC_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + #ifdef USB_OTG_FS_NOE_PA_13 + USB_OTG_FS_NOE = PA_13, + #endif + #ifdef USB_OTG_FS_NOE_PC_9 + USB_OTG_FS_NOE = PC_9, + #endif + #ifdef USB_OTG_FS_SOF_PA_8 + USB_OTG_FS_SOF = PA_8, + #endif + #ifdef USB_OTG_FS_SOF_PA_14 + USB_OTG_FS_SOF = PA_14, + #endif + USB_OTG_FS_VBUS = PA_9, +#endif diff --git a/variants/STM32L4xx/L4Q5RGT/boards_entry.txt b/variants/STM32L4xx/L4Q5RGT/boards_entry.txt new file mode 100644 index 0000000000..e18e028de1 --- /dev/null +++ b/variants/STM32L4xx/L4Q5RGT/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic L4Q5RGTx +GenL4.menu.pnum.GENERIC_L4Q5RGTX=Generic L4Q5RGTx +GenL4.menu.pnum.GENERIC_L4Q5RGTX.upload.maximum_size=1048576 +GenL4.menu.pnum.GENERIC_L4Q5RGTX.upload.maximum_data_size=327680 +GenL4.menu.pnum.GENERIC_L4Q5RGTX.build.board=GENERIC_L4Q5RGTX +GenL4.menu.pnum.GENERIC_L4Q5RGTX.build.product_line=STM32L4Q5xx +GenL4.menu.pnum.GENERIC_L4Q5RGTX.build.variant=STM32L4xx/L4Q5RGT +GenL4.menu.pnum.GENERIC_L4Q5RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4Q5.svd + diff --git a/variants/STM32L4xx/L4Q5RGT/generic_clock.c b/variants/STM32L4xx/L4Q5RGT/generic_clock.c new file mode 100644 index 0000000000..238b8801c6 --- /dev/null +++ b/variants/STM32L4xx/L4Q5RGT/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_L4Q5RGTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32L4xx/L4Q5RGT/variant_generic.cpp b/variants/STM32L4xx/L4Q5RGT/variant_generic.cpp new file mode 100644 index 0000000000..089fadec8b --- /dev/null +++ b/variants/STM32L4xx/L4Q5RGT/variant_generic.cpp @@ -0,0 +1,92 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_L4Q5RGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_12, // D28 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_0, // D32/A10 + PC_1, // D33/A11 + PC_2, // D34/A12 + PC_3, // D35/A13 + PC_4, // D36/A14 + PC_5, // D37/A15 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_2, // D48 + PH_0, // D49 + PH_1, // D50 + PH_3 // D51 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 32, // A10, PC0 + 33, // A11, PC1 + 34, // A12, PC2 + 35, // A13, PC3 + 36, // A14, PC4 + 37 // A15, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32L4xx/L4Q5RGT/variant_generic.h b/variants/STM32L4xx/L4Q5RGT/variant_generic.h new file mode 100644 index 0000000000..855ea03601 --- /dev/null +++ b/variants/STM32L4xx/L4Q5RGT/variant_generic.h @@ -0,0 +1,221 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD2 48 +#define PH0 49 +#define PH1 50 +#define PH3 51 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 52 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB4 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c index ed35d664c2..18950f8dea 100644 --- a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L4R5A(G-I)Ix.xml, STM32L4R5AIIxP.xml * STM32L4R7AIIx.xml, STM32L4S5AIIx.xml * STM32L4S7AIIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c index d6e661b1e8..fc3541262f 100644 --- a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Q(G-I)Ix.xml, STM32L4R5QGIxS.xml * STM32L4R5QIIxP.xml, STM32L4S5QIIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c index 01785df1f5..83d7cba597 100644 --- a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5V(G-I)Tx.xml, STM32L4R7VITx.xml * STM32L4S5VITx.xml, STM32L4S7VITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c index 30cbd0fb23..ae9b9a81d2 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Z(G-I)Tx.xml, STM32L4R7ZITx.xml * STM32L4S5ZITx.xml, STM32L4S7ZITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c index e1f2b5f042..84fdccf1de 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Z(G-I)Yx.xml, STM32L4R9Z(G-I)Yx.xml * STM32L4S5ZIYx.xml, STM32L4S9ZIYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c b/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c index 41f02a88f7..a03157cc3c 100644 --- a/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R5ZITxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c index e7143ed26d..52bdc09195 100644 --- a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9A(G-I)Ix.xml, STM32L4S9AIIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c index 86e2e39e04..646217fce8 100644 --- a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9V(G-I)Tx.xml, STM32L4S9VITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c index 8c6324ae7f..b89f0eec42 100644 --- a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9Z(G-I)Jx.xml, STM32L4S9ZIJx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c index b4d2ae8ca6..d00bdae0f9 100644 --- a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9Z(G-I)Tx.xml, STM32L4S9ZITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c b/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c index 64ab376288..1004d21e6d 100644 --- a/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9ZIYxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c b/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c index 48571fd843..d6eb41e977 100644 --- a/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c +++ b/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L552C(C-E)Tx.xml, STM32L552C(C-E)Ux.xml * STM32L562CETx.xml, STM32L562CEUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c b/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c index c3a0ef48ed..0119f42ed7 100644 --- a/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c +++ b/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L552CETxP.xml, STM32L552CEUxP.xml * STM32L562CETxP.xml, STM32L562CEUxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c b/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c index 4739d593e1..820ba87571 100644 --- a/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552MEYxP.xml, STM32L562MEYxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c b/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c index cb085f846c..52ef93e136 100644 --- a/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552MEYxQ.xml, STM32L562MEYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c index 57228174bc..d20f33ac3e 100644 --- a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552Q(C-E)IxQ.xml, STM32L562QEIxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c b/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c index c433f80fbb..10951892eb 100644 --- a/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c +++ b/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552QEIx.xml, STM32L562QEIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c b/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c index 9f56a853ff..84b80029ee 100644 --- a/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552QEIxP.xml, STM32L562QEIxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c b/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c index eac26975f9..9cba60c798 100644 --- a/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c +++ b/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552R(C-E)Tx.xml, STM32L562RETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c b/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c index 267ac662b1..47c26d717a 100644 --- a/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552RETxP.xml, STM32L562RETxP.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c b/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c index 04d5e3971e..667f32d270 100644 --- a/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552RETxQ.xml, STM32L562RETxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c b/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c index 1f62c7ec59..5eba2ff6e9 100644 --- a/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552V(C-E)TxQ.xml, STM32L562VETxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c b/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c index aea59c8793..aa0ac50452 100644 --- a/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c +++ b/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552VETx.xml, STM32L562VETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c b/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c index 5fdffb98c1..f3f17863c6 100644 --- a/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552Z(C-E)TxQ.xml, STM32L562ZETxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c b/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c index a4d7899fe1..b70ff059e8 100644 --- a/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c +++ b/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552ZETx.xml, STM32L562ZETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c b/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c index 33b34bc074..3377132544 100644 --- a/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP151CABx.xml, STM32MP151CADx.xml * STM32MP151DABx.xml, STM32MP151DADx.xml * STM32MP151FABx.xml, STM32MP151FADx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c b/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c index ceb32f7e85..2f86e950dd 100644 --- a/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32MP151AAAx.xml, STM32MP151CAAx.xml * STM32MP151DAAx.xml, STM32MP151FAAx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c b/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c index 4c40fe0670..e4239fd655 100644 --- a/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32MP151AACx.xml, STM32MP151CACx.xml * STM32MP151DACx.xml, STM32MP151FACx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c b/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c index 61a0bb4e46..0033048a4c 100644 --- a/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c @@ -19,7 +19,7 @@ * STM32MP157CABx.xml, STM32MP157CADx.xml * STM32MP157DABx.xml, STM32MP157DADx.xml * STM32MP157FABx.xml, STM32MP157FADx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c b/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c index 40691676dd..530dca87e5 100644 --- a/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP153DAAx.xml, STM32MP153FAAx.xml * STM32MP157AAAx.xml, STM32MP157CAAx.xml * STM32MP157DAAx.xml, STM32MP157FAAx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c index 57aab80ee3..ca2614d9d9 100644 --- a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP153DACx.xml, STM32MP153FACx.xml * STM32MP157AACx.xml, STM32MP157CACx.xml * STM32MP157DACx.xml, STM32MP157FACx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c b/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c index 55ac8ff1ec..4ed93accd8 100644 --- a/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031C6Tx.xml, STM32U031C6Ux.xml * STM32U031C8Tx.xml, STM32U031C8Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c b/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c index 9fb070c57a..15458b04bd 100644 --- a/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c +++ b/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031F4Px.xml, STM32U031F6Px.xml * STM32U031F8Px.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c b/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c index 067c0b3fb9..29a4625f8f 100644 --- a/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c +++ b/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U031G6Yx.xml, STM32U031G8Yx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c b/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c index eee5d3b7ff..a9e9cba765 100644 --- a/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c +++ b/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031K4Ux.xml, STM32U031K6Ux.xml * STM32U031K8Ux.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c b/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c index c7c0baf703..e72bfea016 100644 --- a/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c +++ b/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031R6Ix.xml, STM32U031R6Tx.xml * STM32U031R8Ix.xml, STM32U031R8Tx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c b/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c index bc252618d8..28845b0d5e 100644 --- a/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c +++ b/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U073CBTx.xml, STM32U073CBUx.xml * STM32U073CCTx.xml, STM32U073CCUx.xml * STM32U083CCTx.xml, STM32U083CCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c b/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c index 2344bc8bf4..6ca0ed7533 100644 --- a/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c +++ b/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073H8Yx.xml, STM32U073HBYx.xml * STM32U073HCYx.xml, STM32U083HCYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c b/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c index 79796efd6c..ea46bb7398 100644 --- a/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c +++ b/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073K8Ux.xml, STM32U073KBUx.xml * STM32U073KCUx.xml, STM32U083KCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c b/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c index c875b8ff8b..e7af35129e 100644 --- a/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c +++ b/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073M8Ix.xml, STM32U073MBIx.xml * STM32U073MCIx.xml, STM32U083MCIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c b/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c index 3bf027e5ec..2113b48762 100644 --- a/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c +++ b/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073M8Tx.xml, STM32U073MBTx.xml * STM32U073MCTx.xml, STM32U083MCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c b/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c index e2bdd402a4..95c6813f30 100644 --- a/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c +++ b/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U073RBIx.xml, STM32U073RBTx.xml * STM32U073RCIx.xml, STM32U073RCTx.xml * STM32U083RCIx.xml, STM32U083RCTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/PeripheralPins.c b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..9e83cc04c0 --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/PeripheralPins.c @@ -0,0 +1,372 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U335CBTx.xml, STM32U335CBUx.xml + * STM32U335CCTx.xml, STM32U335CCUx.xml + * STM32U345CCTx.xml, STM32U345CCUx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF8_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_I3C1)}, + {PB_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_13, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/PinNamesVar.h b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..e03eccd02b --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/PinNamesVar.h @@ -0,0 +1,82 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/boards_entry.txt b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/boards_entry.txt new file mode 100644 index 0000000000..d4cc9c8901 --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/boards_entry.txt @@ -0,0 +1,59 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U335CBTx +GenU3.menu.pnum.GENERIC_U335CBTX=Generic U335CBTx +GenU3.menu.pnum.GENERIC_U335CBTX.upload.maximum_size=131072 +GenU3.menu.pnum.GENERIC_U335CBTX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335CBTX.build.board=GENERIC_U335CBTX +GenU3.menu.pnum.GENERIC_U335CBTX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335CBTX.build.variant=STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U) +GenU3.menu.pnum.GENERIC_U335CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335CBUx +GenU3.menu.pnum.GENERIC_U335CBUX=Generic U335CBUx +GenU3.menu.pnum.GENERIC_U335CBUX.upload.maximum_size=131072 +GenU3.menu.pnum.GENERIC_U335CBUX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335CBUX.build.board=GENERIC_U335CBUX +GenU3.menu.pnum.GENERIC_U335CBUX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335CBUX.build.variant=STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U) +GenU3.menu.pnum.GENERIC_U335CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335CCTx +GenU3.menu.pnum.GENERIC_U335CCTX=Generic U335CCTx +GenU3.menu.pnum.GENERIC_U335CCTX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U335CCTX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335CCTX.build.board=GENERIC_U335CCTX +GenU3.menu.pnum.GENERIC_U335CCTX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335CCTX.build.variant=STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U) +GenU3.menu.pnum.GENERIC_U335CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335CCUx +GenU3.menu.pnum.GENERIC_U335CCUX=Generic U335CCUx +GenU3.menu.pnum.GENERIC_U335CCUX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U335CCUX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335CCUX.build.board=GENERIC_U335CCUX +GenU3.menu.pnum.GENERIC_U335CCUX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335CCUX.build.variant=STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U) +GenU3.menu.pnum.GENERIC_U335CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U345CCTx +GenU3.menu.pnum.GENERIC_U345CCTX=Generic U345CCTx +GenU3.menu.pnum.GENERIC_U345CCTX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U345CCTX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U345CCTX.build.board=GENERIC_U345CCTX +GenU3.menu.pnum.GENERIC_U345CCTX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U345CCTX.build.variant=STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U) +GenU3.menu.pnum.GENERIC_U345CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U345.svd + +# Generic U345CCUx +GenU3.menu.pnum.GENERIC_U345CCUX=Generic U345CCUx +GenU3.menu.pnum.GENERIC_U345CCUX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U345CCUX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U345CCUX.build.board=GENERIC_U345CCUX +GenU3.menu.pnum.GENERIC_U345CCUX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U345CCUX.build.variant=STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U) +GenU3.menu.pnum.GENERIC_U345CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U345.svd + diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/generic_clock.c b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/generic_clock.c new file mode 100644 index 0000000000..65c4952046 --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335CBTX) || defined(ARDUINO_GENERIC_U335CBUX) ||\ + defined(ARDUINO_GENERIC_U335CCTX) || defined(ARDUINO_GENERIC_U335CCUX) ||\ + defined(ARDUINO_GENERIC_U345CCTX) || defined(ARDUINO_GENERIC_U345CCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/variant_generic.cpp b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..dfcdba8afa --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/variant_generic.cpp @@ -0,0 +1,74 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335CBTX) || defined(ARDUINO_GENERIC_U335CBUX) ||\ + defined(ARDUINO_GENERIC_U335CCTX) || defined(ARDUINO_GENERIC_U335CCUX) ||\ + defined(ARDUINO_GENERIC_U345CCTX) || defined(ARDUINO_GENERIC_U345CCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_13, // D31 + PC_14, // D32 + PC_15, // D33 + PH_0, // D34 + PH_1, // D35 + PH_3 // D36 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18 // A10, PB2 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/variant_generic.h b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/variant_generic.h new file mode 100644 index 0000000000..e158c9531f --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/variant_generic.h @@ -0,0 +1,203 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC13 31 +#define PC14 32 +#define PC15 33 +#define PH0 34 +#define PH1 35 +#define PH3 36 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 37 +#define NUM_ANALOG_INPUTS 11 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/PeripheralPins.c b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/PeripheralPins.c new file mode 100644 index 0000000000..35f3a359aa --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/PeripheralPins.c @@ -0,0 +1,354 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U335CBTxQ.xml, STM32U335CBUxQ.xml + * STM32U335CCTxQ.xml, STM32U335CCUxQ.xml + * STM32U345CCTxQ.xml, STM32U345CCUxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF8_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_13, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/PinNamesVar.h b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/PinNamesVar.h new file mode 100644 index 0000000000..b25f134eef --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/PinNamesVar.h @@ -0,0 +1,75 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/boards_entry.txt b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/boards_entry.txt new file mode 100644 index 0000000000..65bb30680f --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/boards_entry.txt @@ -0,0 +1,59 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U335CBTxQ +GenU3.menu.pnum.GENERIC_U335CBTXQ=Generic U335CBTxQ +GenU3.menu.pnum.GENERIC_U335CBTXQ.upload.maximum_size=131072 +GenU3.menu.pnum.GENERIC_U335CBTXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335CBTXQ.build.board=GENERIC_U335CBTXQ +GenU3.menu.pnum.GENERIC_U335CBTXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335CBTXQ.build.variant=STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ +GenU3.menu.pnum.GENERIC_U335CBTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335CBUxQ +GenU3.menu.pnum.GENERIC_U335CBUXQ=Generic U335CBUxQ +GenU3.menu.pnum.GENERIC_U335CBUXQ.upload.maximum_size=131072 +GenU3.menu.pnum.GENERIC_U335CBUXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335CBUXQ.build.board=GENERIC_U335CBUXQ +GenU3.menu.pnum.GENERIC_U335CBUXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335CBUXQ.build.variant=STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ +GenU3.menu.pnum.GENERIC_U335CBUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335CCTxQ +GenU3.menu.pnum.GENERIC_U335CCTXQ=Generic U335CCTxQ +GenU3.menu.pnum.GENERIC_U335CCTXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U335CCTXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335CCTXQ.build.board=GENERIC_U335CCTXQ +GenU3.menu.pnum.GENERIC_U335CCTXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335CCTXQ.build.variant=STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ +GenU3.menu.pnum.GENERIC_U335CCTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335CCUxQ +GenU3.menu.pnum.GENERIC_U335CCUXQ=Generic U335CCUxQ +GenU3.menu.pnum.GENERIC_U335CCUXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U335CCUXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335CCUXQ.build.board=GENERIC_U335CCUXQ +GenU3.menu.pnum.GENERIC_U335CCUXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335CCUXQ.build.variant=STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ +GenU3.menu.pnum.GENERIC_U335CCUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U345CCTxQ +GenU3.menu.pnum.GENERIC_U345CCTXQ=Generic U345CCTxQ +GenU3.menu.pnum.GENERIC_U345CCTXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U345CCTXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U345CCTXQ.build.board=GENERIC_U345CCTXQ +GenU3.menu.pnum.GENERIC_U345CCTXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U345CCTXQ.build.variant=STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ +GenU3.menu.pnum.GENERIC_U345CCTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U345.svd + +# Generic U345CCUxQ +GenU3.menu.pnum.GENERIC_U345CCUXQ=Generic U345CCUxQ +GenU3.menu.pnum.GENERIC_U345CCUXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U345CCUXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U345CCUXQ.build.board=GENERIC_U345CCUXQ +GenU3.menu.pnum.GENERIC_U345CCUXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U345CCUXQ.build.variant=STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ +GenU3.menu.pnum.GENERIC_U345CCUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U345.svd + diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/generic_clock.c b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/generic_clock.c new file mode 100644 index 0000000000..54c714866f --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335CBTXQ) || defined(ARDUINO_GENERIC_U335CBUXQ) ||\ + defined(ARDUINO_GENERIC_U335CCTXQ) || defined(ARDUINO_GENERIC_U335CCUXQ) ||\ + defined(ARDUINO_GENERIC_U345CCTXQ) || defined(ARDUINO_GENERIC_U345CCUXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/variant_generic.cpp b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/variant_generic.cpp new file mode 100644 index 0000000000..ebd6578175 --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/variant_generic.cpp @@ -0,0 +1,69 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335CBTXQ) || defined(ARDUINO_GENERIC_U335CBUXQ) ||\ + defined(ARDUINO_GENERIC_U335CCTXQ) || defined(ARDUINO_GENERIC_U335CCUXQ) ||\ + defined(ARDUINO_GENERIC_U345CCTXQ) || defined(ARDUINO_GENERIC_U345CCUXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_3, // D18 + PB_4, // D19 + PB_5, // D20 + PB_6, // D21 + PB_7, // D22 + PB_8, // D23 + PB_13, // D24 + PB_14, // D25 + PB_15, // D26 + PC_13, // D27 + PC_14, // D28 + PC_15, // D29 + PH_0, // D30 + PH_1, // D31 + PH_3 // D32 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/variant_generic.h b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/variant_generic.h new file mode 100644 index 0000000000..c48cf143b8 --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/variant_generic.h @@ -0,0 +1,196 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 18 +#define PB4 19 +#define PB5 20 +#define PB6 21 +#define PB7 22 +#define PB8 23 +#define PB13 24 +#define PB14 25 +#define PB15 26 +#define PC13 27 +#define PC14 28 +#define PC15 29 +#define PH0 30 +#define PH1 31 +#define PH3 32 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 33 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB4 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/PeripheralPins.c b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/PeripheralPins.c new file mode 100644 index 0000000000..0589c2eb5a --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/PeripheralPins.c @@ -0,0 +1,337 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U335CBYxQ.xml, STM32U335CCYxQ.xml + * STM32U345CCYxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF8_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PC_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_13, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PC_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_6, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/PinNamesVar.h b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/PinNamesVar.h new file mode 100644 index 0000000000..14bce463bc --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/PinNamesVar.h @@ -0,0 +1,58 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/boards_entry.txt b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/boards_entry.txt new file mode 100644 index 0000000000..3a20e0589e --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U335CBYxQ +GenU3.menu.pnum.GENERIC_U335CBYXQ=Generic U335CBYxQ +GenU3.menu.pnum.GENERIC_U335CBYXQ.upload.maximum_size=131072 +GenU3.menu.pnum.GENERIC_U335CBYXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335CBYXQ.build.board=GENERIC_U335CBYXQ +GenU3.menu.pnum.GENERIC_U335CBYXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335CBYXQ.build.variant=STM32U3xx/U335C(B-C)YxQ_U345CCYxQ +GenU3.menu.pnum.GENERIC_U335CBYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335CCYxQ +GenU3.menu.pnum.GENERIC_U335CCYXQ=Generic U335CCYxQ +GenU3.menu.pnum.GENERIC_U335CCYXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U335CCYXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335CCYXQ.build.board=GENERIC_U335CCYXQ +GenU3.menu.pnum.GENERIC_U335CCYXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335CCYXQ.build.variant=STM32U3xx/U335C(B-C)YxQ_U345CCYxQ +GenU3.menu.pnum.GENERIC_U335CCYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U345CCYxQ +GenU3.menu.pnum.GENERIC_U345CCYXQ=Generic U345CCYxQ +GenU3.menu.pnum.GENERIC_U345CCYXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U345CCYXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U345CCYXQ.build.board=GENERIC_U345CCYXQ +GenU3.menu.pnum.GENERIC_U345CCYXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U345CCYXQ.build.variant=STM32U3xx/U335C(B-C)YxQ_U345CCYxQ +GenU3.menu.pnum.GENERIC_U345CCYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U345.svd + diff --git a/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/generic_clock.c b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/generic_clock.c new file mode 100644 index 0000000000..3c5865debf --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335CBYXQ) || defined(ARDUINO_GENERIC_U335CCYXQ) ||\ + defined(ARDUINO_GENERIC_U345CCYXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/variant_generic.cpp b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/variant_generic.cpp new file mode 100644 index 0000000000..a4ca085cbb --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/variant_generic.cpp @@ -0,0 +1,65 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335CBYXQ) || defined(ARDUINO_GENERIC_U335CCYXQ) ||\ + defined(ARDUINO_GENERIC_U345CCYXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_11, // D9 + PA_12, // D10 + PA_13, // D11 + PA_14, // D12 + PA_15, // D13 + PB_0, // D14/A8 + PB_1, // D15/A9 + PB_3, // D16 + PB_4, // D17 + PB_7, // D18 + PB_12, // D19 + PB_13, // D20 + PB_14, // D21 + PB_15, // D22 + PC_6, // D23 + PC_7, // D24 + PC_8, // D25 + PC_9, // D26 + PC_14, // D27 + PC_15, // D28 + PH_3 // D29 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 14, // A8, PB0 + 15 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/variant_generic.h b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/variant_generic.h new file mode 100644 index 0000000000..b6e7cc420c --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/variant_generic.h @@ -0,0 +1,184 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA11 9 +#define PA12 10 +#define PA13 11 +#define PA14 12 +#define PA15 13 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 16 +#define PB4 17 +#define PB7 18 +#define PB12 19 +#define PB13 20 +#define PB14 21 +#define PB15 22 +#define PC6 23 +#define PC7 24 +#define PC8 25 +#define PC9 26 +#define PC14 27 +#define PC15 28 +#define PH3 29 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 30 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB4 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN7_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U335K(B-C)U_U345KCU/PeripheralPins.c b/variants/STM32U3xx/U335K(B-C)U_U345KCU/PeripheralPins.c new file mode 100644 index 0000000000..95e4dfcac8 --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)U_U345KCU/PeripheralPins.c @@ -0,0 +1,333 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U335KBUx.xml, STM32U335KCUx.xml + * STM32U345KCUx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF8_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF_NONE, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF_NONE, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_13, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF_NONE)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF_NONE)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF_NONE)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U335K(B-C)U_U345KCU/PinNamesVar.h b/variants/STM32U3xx/U335K(B-C)U_U345KCU/PinNamesVar.h new file mode 100644 index 0000000000..e833388875 --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)U_U345KCU/PinNamesVar.h @@ -0,0 +1,62 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32U3xx/U335K(B-C)U_U345KCU/boards_entry.txt b/variants/STM32U3xx/U335K(B-C)U_U345KCU/boards_entry.txt new file mode 100644 index 0000000000..8918a1d311 --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)U_U345KCU/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U335KBUx +GenU3.menu.pnum.GENERIC_U335KBUX=Generic U335KBUx +GenU3.menu.pnum.GENERIC_U335KBUX.upload.maximum_size=131072 +GenU3.menu.pnum.GENERIC_U335KBUX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335KBUX.build.board=GENERIC_U335KBUX +GenU3.menu.pnum.GENERIC_U335KBUX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335KBUX.build.variant=STM32U3xx/U335K(B-C)U_U345KCU +GenU3.menu.pnum.GENERIC_U335KBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335KCUx +GenU3.menu.pnum.GENERIC_U335KCUX=Generic U335KCUx +GenU3.menu.pnum.GENERIC_U335KCUX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U335KCUX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335KCUX.build.board=GENERIC_U335KCUX +GenU3.menu.pnum.GENERIC_U335KCUX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335KCUX.build.variant=STM32U3xx/U335K(B-C)U_U345KCU +GenU3.menu.pnum.GENERIC_U335KCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U345KCUx +GenU3.menu.pnum.GENERIC_U345KCUX=Generic U345KCUx +GenU3.menu.pnum.GENERIC_U345KCUX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U345KCUX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U345KCUX.build.board=GENERIC_U345KCUX +GenU3.menu.pnum.GENERIC_U345KCUX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U345KCUX.build.variant=STM32U3xx/U335K(B-C)U_U345KCU +GenU3.menu.pnum.GENERIC_U345KCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U345.svd + diff --git a/variants/STM32U3xx/U335K(B-C)U_U345KCU/generic_clock.c b/variants/STM32U3xx/U335K(B-C)U_U345KCU/generic_clock.c new file mode 100644 index 0000000000..f094b55cc0 --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)U_U345KCU/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335KBUX) || defined(ARDUINO_GENERIC_U335KCUX) ||\ + defined(ARDUINO_GENERIC_U345KCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335K(B-C)U_U345KCU/variant_generic.cpp b/variants/STM32U3xx/U335K(B-C)U_U345KCU/variant_generic.cpp new file mode 100644 index 0000000000..dafaefd372 --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)U_U345KCU/variant_generic.cpp @@ -0,0 +1,60 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335KBUX) || defined(ARDUINO_GENERIC_U335KCUX) ||\ + defined(ARDUINO_GENERIC_U345KCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_3, // D18 + PB_4, // D19 + PB_5, // D20 + PB_6, // D21 + PB_7, // D22 + PC_14, // D23 + PC_15 // D24 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335K(B-C)U_U345KCU/variant_generic.h b/variants/STM32U3xx/U335K(B-C)U_U345KCU/variant_generic.h new file mode 100644 index 0000000000..93af42480f --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)U_U345KCU/variant_generic.h @@ -0,0 +1,181 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 18 +#define PB4 19 +#define PB5 20 +#define PB6 21 +#define PB7 22 +#define PC14 23 +#define PC15 24 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) + +#define NUM_DIGITAL_PINS 25 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB4 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN6_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/PeripheralPins.c b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/PeripheralPins.c new file mode 100644 index 0000000000..039ef3a48f --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/PeripheralPins.c @@ -0,0 +1,313 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U335KBYxQ.xml, STM32U335KCYxQ.xml + * STM32U345KCYxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF8_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_13, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/PinNamesVar.h b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/PinNamesVar.h new file mode 100644 index 0000000000..5c40d6669e --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/PinNamesVar.h @@ -0,0 +1,52 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/boards_entry.txt b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/boards_entry.txt new file mode 100644 index 0000000000..2fb72750d6 --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U335KBYxQ +GenU3.menu.pnum.GENERIC_U335KBYXQ=Generic U335KBYxQ +GenU3.menu.pnum.GENERIC_U335KBYXQ.upload.maximum_size=131072 +GenU3.menu.pnum.GENERIC_U335KBYXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335KBYXQ.build.board=GENERIC_U335KBYXQ +GenU3.menu.pnum.GENERIC_U335KBYXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335KBYXQ.build.variant=STM32U3xx/U335K(B-C)YxQ_U345KCYxQ +GenU3.menu.pnum.GENERIC_U335KBYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335KCYxQ +GenU3.menu.pnum.GENERIC_U335KCYXQ=Generic U335KCYxQ +GenU3.menu.pnum.GENERIC_U335KCYXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U335KCYXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335KCYXQ.build.board=GENERIC_U335KCYXQ +GenU3.menu.pnum.GENERIC_U335KCYXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335KCYXQ.build.variant=STM32U3xx/U335K(B-C)YxQ_U345KCYxQ +GenU3.menu.pnum.GENERIC_U335KCYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U345KCYxQ +GenU3.menu.pnum.GENERIC_U345KCYXQ=Generic U345KCYxQ +GenU3.menu.pnum.GENERIC_U345KCYXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U345KCYXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U345KCYXQ.build.board=GENERIC_U345KCYXQ +GenU3.menu.pnum.GENERIC_U345KCYXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U345KCYXQ.build.variant=STM32U3xx/U335K(B-C)YxQ_U345KCYxQ +GenU3.menu.pnum.GENERIC_U345KCYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U345.svd + diff --git a/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/generic_clock.c b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/generic_clock.c new file mode 100644 index 0000000000..e1153901a3 --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335KBYXQ) || defined(ARDUINO_GENERIC_U335KCYXQ) ||\ + defined(ARDUINO_GENERIC_U345KCYXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/variant_generic.cpp b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/variant_generic.cpp new file mode 100644 index 0000000000..81197ff1a7 --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/variant_generic.cpp @@ -0,0 +1,57 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335KBYXQ) || defined(ARDUINO_GENERIC_U335KCYXQ) ||\ + defined(ARDUINO_GENERIC_U345KCYXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_11, // D9 + PA_12, // D10 + PA_13, // D11 + PA_14, // D12 + PA_15, // D13 + PB_0, // D14/A8 + PB_1, // D15/A9 + PB_3, // D16 + PB_4, // D17 + PB_7, // D18 + PC_14, // D19 + PC_15, // D20 + PH_3 // D21 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 14, // A8, PB0 + 15 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/variant_generic.h b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/variant_generic.h new file mode 100644 index 0000000000..0817078c21 --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/variant_generic.h @@ -0,0 +1,172 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA11 9 +#define PA12 10 +#define PA13 11 +#define PA14 12 +#define PA15 13 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 16 +#define PB4 17 +#define PB7 18 +#define PC14 19 +#define PC15 20 +#define PH3 21 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) + +#define NUM_DIGITAL_PINS 22 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB4 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U335R(B-C)I_U345RCI/PeripheralPins.c b/variants/STM32U3xx/U335R(B-C)I_U345RCI/PeripheralPins.c new file mode 100644 index 0000000000..9990d07a4a --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)I_U345RCI/PeripheralPins.c @@ -0,0 +1,417 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U335RBIx.xml, STM32U335RCIx.xml + * STM32U345RCIx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_IN12 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF8_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_I3C1)}, + {PB_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_13, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_6, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U335R(B-C)I_U345RCI/PinNamesVar.h b/variants/STM32U3xx/U335R(B-C)I_U345RCI/PinNamesVar.h new file mode 100644 index 0000000000..d1838da1ff --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)I_U345RCI/PinNamesVar.h @@ -0,0 +1,87 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_2 = PC_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PB_10, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32U3xx/U335R(B-C)I_U345RCI/boards_entry.txt b/variants/STM32U3xx/U335R(B-C)I_U345RCI/boards_entry.txt new file mode 100644 index 0000000000..fa136f2144 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)I_U345RCI/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U335RBIx +GenU3.menu.pnum.GENERIC_U335RBIX=Generic U335RBIx +GenU3.menu.pnum.GENERIC_U335RBIX.upload.maximum_size=131072 +GenU3.menu.pnum.GENERIC_U335RBIX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335RBIX.build.board=GENERIC_U335RBIX +GenU3.menu.pnum.GENERIC_U335RBIX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335RBIX.build.variant=STM32U3xx/U335R(B-C)I_U345RCI +GenU3.menu.pnum.GENERIC_U335RBIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335RCIx +GenU3.menu.pnum.GENERIC_U335RCIX=Generic U335RCIx +GenU3.menu.pnum.GENERIC_U335RCIX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U335RCIX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335RCIX.build.board=GENERIC_U335RCIX +GenU3.menu.pnum.GENERIC_U335RCIX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335RCIX.build.variant=STM32U3xx/U335R(B-C)I_U345RCI +GenU3.menu.pnum.GENERIC_U335RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U345RCIx +GenU3.menu.pnum.GENERIC_U345RCIX=Generic U345RCIx +GenU3.menu.pnum.GENERIC_U345RCIX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U345RCIX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U345RCIX.build.board=GENERIC_U345RCIX +GenU3.menu.pnum.GENERIC_U345RCIX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U345RCIX.build.variant=STM32U3xx/U335R(B-C)I_U345RCI +GenU3.menu.pnum.GENERIC_U345RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U345.svd + diff --git a/variants/STM32U3xx/U335R(B-C)I_U345RCI/generic_clock.c b/variants/STM32U3xx/U335R(B-C)I_U345RCI/generic_clock.c new file mode 100644 index 0000000000..befbf1a8c8 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)I_U345RCI/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335RBIX) || defined(ARDUINO_GENERIC_U335RCIX) ||\ + defined(ARDUINO_GENERIC_U345RCIX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335R(B-C)I_U345RCI/variant_generic.cpp b/variants/STM32U3xx/U335R(B-C)I_U345RCI/variant_generic.cpp new file mode 100644 index 0000000000..f3e4dc9929 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)I_U345RCI/variant_generic.cpp @@ -0,0 +1,91 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335RBIX) || defined(ARDUINO_GENERIC_U335RCIX) ||\ + defined(ARDUINO_GENERIC_U345RCIX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33 + PC_3, // D34 + PC_4, // D35/A13 + PC_5, // D36/A14 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_2, // D47 + PH_0, // D48 + PH_1, // D49 + PH_3 // D50 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 35, // A13, PC4 + 36 // A14, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335R(B-C)I_U345RCI/variant_generic.h b/variants/STM32U3xx/U335R(B-C)I_U345RCI/variant_generic.h new file mode 100644 index 0000000000..97c017a807 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)I_U345RCI/variant_generic.h @@ -0,0 +1,220 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 33 +#define PC3 34 +#define PC4 PIN_A13 +#define PC5 PIN_A14 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD2 47 +#define PH0 48 +#define PH1 49 +#define PH3 50 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 51 +#define NUM_ANALOG_INPUTS 15 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN5_2 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/PeripheralPins.c b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/PeripheralPins.c new file mode 100644 index 0000000000..5c038d0299 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/PeripheralPins.c @@ -0,0 +1,402 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U335RBIxQ.xml, STM32U335RCIxQ.xml + * STM32U345RCIxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF8_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_13, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PC_6, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/PinNamesVar.h b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/PinNamesVar.h new file mode 100644 index 0000000000..9de24678b1 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/PinNamesVar.h @@ -0,0 +1,83 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PB_10, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/boards_entry.txt b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/boards_entry.txt new file mode 100644 index 0000000000..c425098d92 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U335RBIxQ +GenU3.menu.pnum.GENERIC_U335RBIXQ=Generic U335RBIxQ +GenU3.menu.pnum.GENERIC_U335RBIXQ.upload.maximum_size=131072 +GenU3.menu.pnum.GENERIC_U335RBIXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335RBIXQ.build.board=GENERIC_U335RBIXQ +GenU3.menu.pnum.GENERIC_U335RBIXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335RBIXQ.build.variant=STM32U3xx/U335R(B-C)IxQ_U345RCIxQ +GenU3.menu.pnum.GENERIC_U335RBIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335RCIxQ +GenU3.menu.pnum.GENERIC_U335RCIXQ=Generic U335RCIxQ +GenU3.menu.pnum.GENERIC_U335RCIXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U335RCIXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335RCIXQ.build.board=GENERIC_U335RCIXQ +GenU3.menu.pnum.GENERIC_U335RCIXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335RCIXQ.build.variant=STM32U3xx/U335R(B-C)IxQ_U345RCIxQ +GenU3.menu.pnum.GENERIC_U335RCIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U345RCIxQ +GenU3.menu.pnum.GENERIC_U345RCIXQ=Generic U345RCIxQ +GenU3.menu.pnum.GENERIC_U345RCIXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U345RCIXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U345RCIXQ.build.board=GENERIC_U345RCIXQ +GenU3.menu.pnum.GENERIC_U345RCIXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U345RCIXQ.build.variant=STM32U3xx/U335R(B-C)IxQ_U345RCIxQ +GenU3.menu.pnum.GENERIC_U345RCIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U345.svd + diff --git a/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/generic_clock.c b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/generic_clock.c new file mode 100644 index 0000000000..259fbc585e --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335RBIXQ) || defined(ARDUINO_GENERIC_U335RCIXQ) ||\ + defined(ARDUINO_GENERIC_U345RCIXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/variant_generic.cpp b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/variant_generic.cpp new file mode 100644 index 0000000000..9d30c16113 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/variant_generic.cpp @@ -0,0 +1,85 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335RBIXQ) || defined(ARDUINO_GENERIC_U335RCIXQ) ||\ + defined(ARDUINO_GENERIC_U345RCIXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_13, // D26 + PB_14, // D27 + PB_15, // D28 + PC_0, // D29/A11 + PC_1, // D30/A12 + PC_2, // D31 + PC_3, // D32 + PC_6, // D33 + PC_7, // D34 + PC_8, // D35 + PC_9, // D36 + PC_10, // D37 + PC_11, // D38 + PC_12, // D39 + PC_13, // D40 + PC_14, // D41 + PC_15, // D42 + PD_2, // D43 + PH_0, // D44 + PH_1, // D45 + PH_3 // D46 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 29, // A11, PC0 + 30 // A12, PC1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/variant_generic.h b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/variant_generic.h new file mode 100644 index 0000000000..fc540949d5 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/variant_generic.h @@ -0,0 +1,214 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB13 26 +#define PB14 27 +#define PB15 28 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 31 +#define PC3 32 +#define PC6 33 +#define PC7 34 +#define PC8 35 +#define PC9 36 +#define PC10 37 +#define PC11 38 +#define PC12 39 +#define PC13 40 +#define PC14 41 +#define PC15 42 +#define PD2 43 +#define PH0 44 +#define PH1 45 +#define PH3 46 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 47 +#define NUM_ANALOG_INPUTS 13 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U335R(B-C)T_U345RCT/PeripheralPins.c b/variants/STM32U3xx/U335R(B-C)T_U345RCT/PeripheralPins.c new file mode 100644 index 0000000000..051a8e485c --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)T_U345RCT/PeripheralPins.c @@ -0,0 +1,417 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U335RBTx.xml, STM32U335RCTx.xml + * STM32U345RCTx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_IN12 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF8_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_I3C1)}, + {PB_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_13, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_6, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U335R(B-C)T_U345RCT/PinNamesVar.h b/variants/STM32U3xx/U335R(B-C)T_U345RCT/PinNamesVar.h new file mode 100644 index 0000000000..3b19230381 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)T_U345RCT/PinNamesVar.h @@ -0,0 +1,87 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PC_5, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_2 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32U3xx/U335R(B-C)T_U345RCT/boards_entry.txt b/variants/STM32U3xx/U335R(B-C)T_U345RCT/boards_entry.txt new file mode 100644 index 0000000000..0560233411 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)T_U345RCT/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U335RBTx +GenU3.menu.pnum.GENERIC_U335RBTX=Generic U335RBTx +GenU3.menu.pnum.GENERIC_U335RBTX.upload.maximum_size=131072 +GenU3.menu.pnum.GENERIC_U335RBTX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335RBTX.build.board=GENERIC_U335RBTX +GenU3.menu.pnum.GENERIC_U335RBTX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335RBTX.build.variant=STM32U3xx/U335R(B-C)T_U345RCT +GenU3.menu.pnum.GENERIC_U335RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335RCTx +GenU3.menu.pnum.GENERIC_U335RCTX=Generic U335RCTx +GenU3.menu.pnum.GENERIC_U335RCTX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U335RCTX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335RCTX.build.board=GENERIC_U335RCTX +GenU3.menu.pnum.GENERIC_U335RCTX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335RCTX.build.variant=STM32U3xx/U335R(B-C)T_U345RCT +GenU3.menu.pnum.GENERIC_U335RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U345RCTx +GenU3.menu.pnum.GENERIC_U345RCTX=Generic U345RCTx +GenU3.menu.pnum.GENERIC_U345RCTX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U345RCTX.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U345RCTX.build.board=GENERIC_U345RCTX +GenU3.menu.pnum.GENERIC_U345RCTX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U345RCTX.build.variant=STM32U3xx/U335R(B-C)T_U345RCT +GenU3.menu.pnum.GENERIC_U345RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U345.svd + diff --git a/variants/STM32U3xx/U335R(B-C)T_U345RCT/generic_clock.c b/variants/STM32U3xx/U335R(B-C)T_U345RCT/generic_clock.c new file mode 100644 index 0000000000..e99913c268 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)T_U345RCT/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335RBTX) || defined(ARDUINO_GENERIC_U335RCTX) ||\ + defined(ARDUINO_GENERIC_U345RCTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335R(B-C)T_U345RCT/variant_generic.cpp b/variants/STM32U3xx/U335R(B-C)T_U345RCT/variant_generic.cpp new file mode 100644 index 0000000000..5434963a21 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)T_U345RCT/variant_generic.cpp @@ -0,0 +1,91 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335RBTX) || defined(ARDUINO_GENERIC_U335RCTX) ||\ + defined(ARDUINO_GENERIC_U345RCTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33 + PC_3, // D34 + PC_4, // D35/A13 + PC_5, // D36/A14 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_2, // D47 + PH_0, // D48 + PH_1, // D49 + PH_3 // D50 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 35, // A13, PC4 + 36 // A14, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335R(B-C)T_U345RCT/variant_generic.h b/variants/STM32U3xx/U335R(B-C)T_U345RCT/variant_generic.h new file mode 100644 index 0000000000..97c017a807 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)T_U345RCT/variant_generic.h @@ -0,0 +1,220 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 33 +#define PC3 34 +#define PC4 PIN_A13 +#define PC5 PIN_A14 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD2 47 +#define PH0 48 +#define PH1 49 +#define PH3 50 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 51 +#define NUM_ANALOG_INPUTS 15 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN5_2 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/PeripheralPins.c b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/PeripheralPins.c new file mode 100644 index 0000000000..d1af68a3ac --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/PeripheralPins.c @@ -0,0 +1,402 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U335RBTxQ.xml, STM32U335RCTxQ.xml + * STM32U345RCTxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF8_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF7_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_13, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_USART3)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI2)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PC_6, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {PB_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/PinNamesVar.h b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/PinNamesVar.h new file mode 100644 index 0000000000..4d8c7b1467 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/PinNamesVar.h @@ -0,0 +1,83 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/boards_entry.txt b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/boards_entry.txt new file mode 100644 index 0000000000..c964315afa --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U335RBTxQ +GenU3.menu.pnum.GENERIC_U335RBTXQ=Generic U335RBTxQ +GenU3.menu.pnum.GENERIC_U335RBTXQ.upload.maximum_size=131072 +GenU3.menu.pnum.GENERIC_U335RBTXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335RBTXQ.build.board=GENERIC_U335RBTXQ +GenU3.menu.pnum.GENERIC_U335RBTXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335RBTXQ.build.variant=STM32U3xx/U335R(B-C)TxQ_U345RCTxQ +GenU3.menu.pnum.GENERIC_U335RBTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U335RCTxQ +GenU3.menu.pnum.GENERIC_U335RCTXQ=Generic U335RCTxQ +GenU3.menu.pnum.GENERIC_U335RCTXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U335RCTXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U335RCTXQ.build.board=GENERIC_U335RCTXQ +GenU3.menu.pnum.GENERIC_U335RCTXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U335RCTXQ.build.variant=STM32U3xx/U335R(B-C)TxQ_U345RCTxQ +GenU3.menu.pnum.GENERIC_U335RCTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U335.svd + +# Generic U345RCTxQ +GenU3.menu.pnum.GENERIC_U345RCTXQ=Generic U345RCTxQ +GenU3.menu.pnum.GENERIC_U345RCTXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U345RCTXQ.upload.maximum_data_size=81920 +GenU3.menu.pnum.GENERIC_U345RCTXQ.build.board=GENERIC_U345RCTXQ +GenU3.menu.pnum.GENERIC_U345RCTXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U345RCTXQ.build.variant=STM32U3xx/U335R(B-C)TxQ_U345RCTxQ +GenU3.menu.pnum.GENERIC_U345RCTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U345.svd + diff --git a/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/generic_clock.c b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/generic_clock.c new file mode 100644 index 0000000000..f61140e569 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335RBTXQ) || defined(ARDUINO_GENERIC_U335RCTXQ) ||\ + defined(ARDUINO_GENERIC_U345RCTXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/variant_generic.cpp b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/variant_generic.cpp new file mode 100644 index 0000000000..e1e566effb --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/variant_generic.cpp @@ -0,0 +1,85 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U335RBTXQ) || defined(ARDUINO_GENERIC_U335RCTXQ) ||\ + defined(ARDUINO_GENERIC_U345RCTXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_13, // D26 + PB_14, // D27 + PB_15, // D28 + PC_0, // D29/A11 + PC_1, // D30/A12 + PC_2, // D31 + PC_3, // D32 + PC_6, // D33 + PC_7, // D34 + PC_8, // D35 + PC_9, // D36 + PC_10, // D37 + PC_11, // D38 + PC_12, // D39 + PC_13, // D40 + PC_14, // D41 + PC_15, // D42 + PD_2, // D43 + PH_0, // D44 + PH_1, // D45 + PH_3 // D46 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 29, // A11, PC0 + 30 // A12, PC1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/variant_generic.h b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/variant_generic.h new file mode 100644 index 0000000000..fc540949d5 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/variant_generic.h @@ -0,0 +1,214 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB13 26 +#define PB14 27 +#define PB15 28 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 31 +#define PC3 32 +#define PC6 33 +#define PC7 34 +#define PC8 35 +#define PC9 36 +#define PC10 37 +#define PC11 38 +#define PC12 39 +#define PC13 40 +#define PC14 41 +#define PC15 42 +#define PD2 43 +#define PH0 44 +#define PH1 45 +#define PH3 46 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 47 +#define NUM_ANALOG_INPUTS 13 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/PeripheralPins.c b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..1af4fd53ba --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/PeripheralPins.c @@ -0,0 +1,359 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356CCTx.xml, STM32U356CCUx.xml + * STM32U356CETx.xml, STM32U356CEUx.xml + * STM32U366CETx.xml, STM32U366CEUx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/PinNamesVar.h b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..af35db9676 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/PinNamesVar.h @@ -0,0 +1,84 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_NOE = PA_13, +#endif diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/boards_entry.txt b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/boards_entry.txt new file mode 100644 index 0000000000..8943d6e1bb --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/boards_entry.txt @@ -0,0 +1,59 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356CCTx +GenU3.menu.pnum.GENERIC_U356CCTX=Generic U356CCTx +GenU3.menu.pnum.GENERIC_U356CCTX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356CCTX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356CCTX.build.board=GENERIC_U356CCTX +GenU3.menu.pnum.GENERIC_U356CCTX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356CCTX.build.variant=STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U) +GenU3.menu.pnum.GENERIC_U356CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356CCUx +GenU3.menu.pnum.GENERIC_U356CCUX=Generic U356CCUx +GenU3.menu.pnum.GENERIC_U356CCUX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356CCUX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356CCUX.build.board=GENERIC_U356CCUX +GenU3.menu.pnum.GENERIC_U356CCUX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356CCUX.build.variant=STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U) +GenU3.menu.pnum.GENERIC_U356CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356CETx +GenU3.menu.pnum.GENERIC_U356CETX=Generic U356CETx +GenU3.menu.pnum.GENERIC_U356CETX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356CETX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356CETX.build.board=GENERIC_U356CETX +GenU3.menu.pnum.GENERIC_U356CETX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356CETX.build.variant=STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U) +GenU3.menu.pnum.GENERIC_U356CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356CEUx +GenU3.menu.pnum.GENERIC_U356CEUX=Generic U356CEUx +GenU3.menu.pnum.GENERIC_U356CEUX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356CEUX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356CEUX.build.board=GENERIC_U356CEUX +GenU3.menu.pnum.GENERIC_U356CEUX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356CEUX.build.variant=STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U) +GenU3.menu.pnum.GENERIC_U356CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366CETx +GenU3.menu.pnum.GENERIC_U366CETX=Generic U366CETx +GenU3.menu.pnum.GENERIC_U366CETX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366CETX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366CETX.build.board=GENERIC_U366CETX +GenU3.menu.pnum.GENERIC_U366CETX.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366CETX.build.variant=STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U) +GenU3.menu.pnum.GENERIC_U366CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + +# Generic U366CEUx +GenU3.menu.pnum.GENERIC_U366CEUX=Generic U366CEUx +GenU3.menu.pnum.GENERIC_U366CEUX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366CEUX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366CEUX.build.board=GENERIC_U366CEUX +GenU3.menu.pnum.GENERIC_U366CEUX.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366CEUX.build.variant=STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U) +GenU3.menu.pnum.GENERIC_U366CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/generic_clock.c b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/generic_clock.c new file mode 100644 index 0000000000..0939a2c52f --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356CCTX) || defined(ARDUINO_GENERIC_U356CCUX) ||\ + defined(ARDUINO_GENERIC_U356CETX) || defined(ARDUINO_GENERIC_U356CEUX) ||\ + defined(ARDUINO_GENERIC_U366CETX) || defined(ARDUINO_GENERIC_U366CEUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/variant_generic.cpp b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..ff61b117cf --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/variant_generic.cpp @@ -0,0 +1,74 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356CCTX) || defined(ARDUINO_GENERIC_U356CCUX) ||\ + defined(ARDUINO_GENERIC_U356CETX) || defined(ARDUINO_GENERIC_U356CEUX) ||\ + defined(ARDUINO_GENERIC_U366CETX) || defined(ARDUINO_GENERIC_U366CEUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_13, // D31 + PC_14, // D32 + PC_15, // D33 + PH_0, // D34 + PH_1, // D35 + PH_3 // D36 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18 // A10, PB2 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/variant_generic.h b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/variant_generic.h new file mode 100644 index 0000000000..6b87869aee --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/variant_generic.h @@ -0,0 +1,204 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC13 31 +#define PC14 32 +#define PC15 33 +#define PH0 34 +#define PH1 35 +#define PH3 36 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 37 +#define NUM_ANALOG_INPUTS 11 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/PeripheralPins.c b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/PeripheralPins.c new file mode 100644 index 0000000000..829e8939e9 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/PeripheralPins.c @@ -0,0 +1,343 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356CCTxQ.xml, STM32U356CCUxQ.xml + * STM32U356CETxQ.xml, STM32U356CEUxQ.xml + * STM32U366CETxQ.xml, STM32U366CEUxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/PinNamesVar.h b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/PinNamesVar.h new file mode 100644 index 0000000000..381bd5b050 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/PinNamesVar.h @@ -0,0 +1,77 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_NOE = PA_13, +#endif diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/boards_entry.txt b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/boards_entry.txt new file mode 100644 index 0000000000..58a3840992 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/boards_entry.txt @@ -0,0 +1,59 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356CCTxQ +GenU3.menu.pnum.GENERIC_U356CCTXQ=Generic U356CCTxQ +GenU3.menu.pnum.GENERIC_U356CCTXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356CCTXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356CCTXQ.build.board=GENERIC_U356CCTXQ +GenU3.menu.pnum.GENERIC_U356CCTXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356CCTXQ.build.variant=STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ +GenU3.menu.pnum.GENERIC_U356CCTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356CCUxQ +GenU3.menu.pnum.GENERIC_U356CCUXQ=Generic U356CCUxQ +GenU3.menu.pnum.GENERIC_U356CCUXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356CCUXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356CCUXQ.build.board=GENERIC_U356CCUXQ +GenU3.menu.pnum.GENERIC_U356CCUXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356CCUXQ.build.variant=STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ +GenU3.menu.pnum.GENERIC_U356CCUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356CETxQ +GenU3.menu.pnum.GENERIC_U356CETXQ=Generic U356CETxQ +GenU3.menu.pnum.GENERIC_U356CETXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356CETXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356CETXQ.build.board=GENERIC_U356CETXQ +GenU3.menu.pnum.GENERIC_U356CETXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356CETXQ.build.variant=STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ +GenU3.menu.pnum.GENERIC_U356CETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356CEUxQ +GenU3.menu.pnum.GENERIC_U356CEUXQ=Generic U356CEUxQ +GenU3.menu.pnum.GENERIC_U356CEUXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356CEUXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356CEUXQ.build.board=GENERIC_U356CEUXQ +GenU3.menu.pnum.GENERIC_U356CEUXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356CEUXQ.build.variant=STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ +GenU3.menu.pnum.GENERIC_U356CEUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366CETxQ +GenU3.menu.pnum.GENERIC_U366CETXQ=Generic U366CETxQ +GenU3.menu.pnum.GENERIC_U366CETXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366CETXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366CETXQ.build.board=GENERIC_U366CETXQ +GenU3.menu.pnum.GENERIC_U366CETXQ.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366CETXQ.build.variant=STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ +GenU3.menu.pnum.GENERIC_U366CETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + +# Generic U366CEUxQ +GenU3.menu.pnum.GENERIC_U366CEUXQ=Generic U366CEUxQ +GenU3.menu.pnum.GENERIC_U366CEUXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366CEUXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366CEUXQ.build.board=GENERIC_U366CEUXQ +GenU3.menu.pnum.GENERIC_U366CEUXQ.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366CEUXQ.build.variant=STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ +GenU3.menu.pnum.GENERIC_U366CEUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/generic_clock.c b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/generic_clock.c new file mode 100644 index 0000000000..a0380ebb6d --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356CCTXQ) || defined(ARDUINO_GENERIC_U356CCUXQ) ||\ + defined(ARDUINO_GENERIC_U356CETXQ) || defined(ARDUINO_GENERIC_U356CEUXQ) ||\ + defined(ARDUINO_GENERIC_U366CETXQ) || defined(ARDUINO_GENERIC_U366CEUXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/variant_generic.cpp b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/variant_generic.cpp new file mode 100644 index 0000000000..e90a94ca22 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/variant_generic.cpp @@ -0,0 +1,69 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356CCTXQ) || defined(ARDUINO_GENERIC_U356CCUXQ) ||\ + defined(ARDUINO_GENERIC_U356CETXQ) || defined(ARDUINO_GENERIC_U356CEUXQ) ||\ + defined(ARDUINO_GENERIC_U366CETXQ) || defined(ARDUINO_GENERIC_U366CEUXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_3, // D18 + PB_4, // D19 + PB_5, // D20 + PB_6, // D21 + PB_7, // D22 + PB_8, // D23 + PB_13, // D24 + PB_14, // D25 + PB_15, // D26 + PC_13, // D27 + PC_14, // D28 + PC_15, // D29 + PH_0, // D30 + PH_1, // D31 + PH_3 // D32 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/variant_generic.h b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/variant_generic.h new file mode 100644 index 0000000000..ec8fc77d66 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/variant_generic.h @@ -0,0 +1,197 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 18 +#define PB4 19 +#define PB5 20 +#define PB6 21 +#define PB7 22 +#define PB8 23 +#define PB13 24 +#define PB14 25 +#define PB15 26 +#define PC13 27 +#define PC14 28 +#define PC15 29 +#define PH0 30 +#define PH1 31 +#define PH3 32 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 33 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/PeripheralPins.c b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/PeripheralPins.c new file mode 100644 index 0000000000..af91e96265 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/PeripheralPins.c @@ -0,0 +1,338 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356CCYxQ.xml, STM32U356CEYxQ.xml + * STM32U366CEYxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/PinNamesVar.h b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/PinNamesVar.h new file mode 100644 index 0000000000..bb00aa18e1 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/PinNamesVar.h @@ -0,0 +1,74 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_NOE = PA_13, +#endif diff --git a/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/boards_entry.txt b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/boards_entry.txt new file mode 100644 index 0000000000..abaf31a2ac --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356CCYxQ +GenU3.menu.pnum.GENERIC_U356CCYXQ=Generic U356CCYxQ +GenU3.menu.pnum.GENERIC_U356CCYXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356CCYXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356CCYXQ.build.board=GENERIC_U356CCYXQ +GenU3.menu.pnum.GENERIC_U356CCYXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356CCYXQ.build.variant=STM32U3xx/U356C(C-E)YxQ_U366CEYxQ +GenU3.menu.pnum.GENERIC_U356CCYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356CEYxQ +GenU3.menu.pnum.GENERIC_U356CEYXQ=Generic U356CEYxQ +GenU3.menu.pnum.GENERIC_U356CEYXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356CEYXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356CEYXQ.build.board=GENERIC_U356CEYXQ +GenU3.menu.pnum.GENERIC_U356CEYXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356CEYXQ.build.variant=STM32U3xx/U356C(C-E)YxQ_U366CEYxQ +GenU3.menu.pnum.GENERIC_U356CEYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366CEYxQ +GenU3.menu.pnum.GENERIC_U366CEYXQ=Generic U366CEYxQ +GenU3.menu.pnum.GENERIC_U366CEYXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366CEYXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366CEYXQ.build.board=GENERIC_U366CEYXQ +GenU3.menu.pnum.GENERIC_U366CEYXQ.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366CEYXQ.build.variant=STM32U3xx/U356C(C-E)YxQ_U366CEYxQ +GenU3.menu.pnum.GENERIC_U366CEYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/generic_clock.c b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/generic_clock.c new file mode 100644 index 0000000000..fa1268dbb9 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356CCYXQ) || defined(ARDUINO_GENERIC_U356CEYXQ) ||\ + defined(ARDUINO_GENERIC_U366CEYXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/variant_generic.cpp b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/variant_generic.cpp new file mode 100644 index 0000000000..daa6f98ff1 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/variant_generic.cpp @@ -0,0 +1,67 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356CCYXQ) || defined(ARDUINO_GENERIC_U356CEYXQ) ||\ + defined(ARDUINO_GENERIC_U366CEYXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_3, // D18 + PB_4, // D19 + PB_5, // D20 + PB_6, // D21 + PB_7, // D22 + PB_8, // D23 + PB_15, // D24 + PC_10, // D25 + PC_11, // D26 + PC_14, // D27 + PC_15, // D28 + PH_0, // D29 + PH_1, // D30 + PH_3 // D31 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/variant_generic.h b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/variant_generic.h new file mode 100644 index 0000000000..c1b67ca88c --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/variant_generic.h @@ -0,0 +1,195 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 18 +#define PB4 19 +#define PB5 20 +#define PB6 21 +#define PB7 22 +#define PB8 23 +#define PB15 24 +#define PC10 25 +#define PC11 26 +#define PC14 27 +#define PC15 28 +#define PH0 29 +#define PH1 30 +#define PH3 31 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 32 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356K(C-E)U_U366KEU/PeripheralPins.c b/variants/STM32U3xx/U356K(C-E)U_U366KEU/PeripheralPins.c new file mode 100644 index 0000000000..1bf88ebe9e --- /dev/null +++ b/variants/STM32U3xx/U356K(C-E)U_U366KEU/PeripheralPins.c @@ -0,0 +1,323 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356KCUx.xml, STM32U356KEUx.xml + * STM32U366KEUx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356K(C-E)U_U366KEU/PinNamesVar.h b/variants/STM32U3xx/U356K(C-E)U_U366KEU/PinNamesVar.h new file mode 100644 index 0000000000..92daa150f6 --- /dev/null +++ b/variants/STM32U3xx/U356K(C-E)U_U366KEU/PinNamesVar.h @@ -0,0 +1,64 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_NOE = PA_13, +#endif diff --git a/variants/STM32U3xx/U356K(C-E)U_U366KEU/boards_entry.txt b/variants/STM32U3xx/U356K(C-E)U_U366KEU/boards_entry.txt new file mode 100644 index 0000000000..256e64f45c --- /dev/null +++ b/variants/STM32U3xx/U356K(C-E)U_U366KEU/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356KCUx +GenU3.menu.pnum.GENERIC_U356KCUX=Generic U356KCUx +GenU3.menu.pnum.GENERIC_U356KCUX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356KCUX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356KCUX.build.board=GENERIC_U356KCUX +GenU3.menu.pnum.GENERIC_U356KCUX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356KCUX.build.variant=STM32U3xx/U356K(C-E)U_U366KEU +GenU3.menu.pnum.GENERIC_U356KCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356KEUx +GenU3.menu.pnum.GENERIC_U356KEUX=Generic U356KEUx +GenU3.menu.pnum.GENERIC_U356KEUX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356KEUX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356KEUX.build.board=GENERIC_U356KEUX +GenU3.menu.pnum.GENERIC_U356KEUX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356KEUX.build.variant=STM32U3xx/U356K(C-E)U_U366KEU +GenU3.menu.pnum.GENERIC_U356KEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366KEUx +GenU3.menu.pnum.GENERIC_U366KEUX=Generic U366KEUx +GenU3.menu.pnum.GENERIC_U366KEUX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366KEUX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366KEUX.build.board=GENERIC_U366KEUX +GenU3.menu.pnum.GENERIC_U366KEUX.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366KEUX.build.variant=STM32U3xx/U356K(C-E)U_U366KEU +GenU3.menu.pnum.GENERIC_U366KEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356K(C-E)U_U366KEU/generic_clock.c b/variants/STM32U3xx/U356K(C-E)U_U366KEU/generic_clock.c new file mode 100644 index 0000000000..aaeb7d7871 --- /dev/null +++ b/variants/STM32U3xx/U356K(C-E)U_U366KEU/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356KCUX) || defined(ARDUINO_GENERIC_U356KEUX) ||\ + defined(ARDUINO_GENERIC_U366KEUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356K(C-E)U_U366KEU/variant_generic.cpp b/variants/STM32U3xx/U356K(C-E)U_U366KEU/variant_generic.cpp new file mode 100644 index 0000000000..a89500212c --- /dev/null +++ b/variants/STM32U3xx/U356K(C-E)U_U366KEU/variant_generic.cpp @@ -0,0 +1,60 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356KCUX) || defined(ARDUINO_GENERIC_U356KEUX) ||\ + defined(ARDUINO_GENERIC_U366KEUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_3, // D18 + PB_4, // D19 + PB_5, // D20 + PB_6, // D21 + PB_7, // D22 + PC_14, // D23 + PC_15 // D24 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356K(C-E)U_U366KEU/variant_generic.h b/variants/STM32U3xx/U356K(C-E)U_U366KEU/variant_generic.h new file mode 100644 index 0000000000..15187778f2 --- /dev/null +++ b/variants/STM32U3xx/U356K(C-E)U_U366KEU/variant_generic.h @@ -0,0 +1,182 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 18 +#define PB4 19 +#define PB5 20 +#define PB6 21 +#define PB7 22 +#define PC14 23 +#define PC15 24 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) + +#define NUM_DIGITAL_PINS 25 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN6_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356R(C-E)I_U366REI/PeripheralPins.c b/variants/STM32U3xx/U356R(C-E)I_U366REI/PeripheralPins.c new file mode 100644 index 0000000000..700dd10d70 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)I_U366REI/PeripheralPins.c @@ -0,0 +1,408 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356RCIx.xml, STM32U356REIx.xml + * STM32U366REIx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_IN12 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {PC_9, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356R(C-E)I_U366REI/PinNamesVar.h b/variants/STM32U3xx/U356R(C-E)I_U366REI/PinNamesVar.h new file mode 100644 index 0000000000..0cd26952b6 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)I_U366REI/PinNamesVar.h @@ -0,0 +1,96 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_2 = PC_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PB_10, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + #ifdef USB_NOE_PA_13 + USB_NOE = PA_13, + #endif + #ifdef USB_NOE_PC_9 + USB_NOE = PC_9, + #endif +#endif diff --git a/variants/STM32U3xx/U356R(C-E)I_U366REI/boards_entry.txt b/variants/STM32U3xx/U356R(C-E)I_U366REI/boards_entry.txt new file mode 100644 index 0000000000..71a0698711 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)I_U366REI/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356RCIx +GenU3.menu.pnum.GENERIC_U356RCIX=Generic U356RCIx +GenU3.menu.pnum.GENERIC_U356RCIX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356RCIX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356RCIX.build.board=GENERIC_U356RCIX +GenU3.menu.pnum.GENERIC_U356RCIX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356RCIX.build.variant=STM32U3xx/U356R(C-E)I_U366REI +GenU3.menu.pnum.GENERIC_U356RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356REIx +GenU3.menu.pnum.GENERIC_U356REIX=Generic U356REIx +GenU3.menu.pnum.GENERIC_U356REIX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356REIX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356REIX.build.board=GENERIC_U356REIX +GenU3.menu.pnum.GENERIC_U356REIX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356REIX.build.variant=STM32U3xx/U356R(C-E)I_U366REI +GenU3.menu.pnum.GENERIC_U356REIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366REIx +GenU3.menu.pnum.GENERIC_U366REIX=Generic U366REIx +GenU3.menu.pnum.GENERIC_U366REIX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366REIX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366REIX.build.board=GENERIC_U366REIX +GenU3.menu.pnum.GENERIC_U366REIX.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366REIX.build.variant=STM32U3xx/U356R(C-E)I_U366REI +GenU3.menu.pnum.GENERIC_U366REIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356R(C-E)I_U366REI/generic_clock.c b/variants/STM32U3xx/U356R(C-E)I_U366REI/generic_clock.c new file mode 100644 index 0000000000..b91f2b82b5 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)I_U366REI/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356RCIX) || defined(ARDUINO_GENERIC_U356REIX) ||\ + defined(ARDUINO_GENERIC_U366REIX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356R(C-E)I_U366REI/variant_generic.cpp b/variants/STM32U3xx/U356R(C-E)I_U366REI/variant_generic.cpp new file mode 100644 index 0000000000..d3f0a5a436 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)I_U366REI/variant_generic.cpp @@ -0,0 +1,93 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356RCIX) || defined(ARDUINO_GENERIC_U356REIX) ||\ + defined(ARDUINO_GENERIC_U366REIX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_2, // D47 + PH_0, // D48 + PH_1, // D49 + PH_3 // D50 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36 // A16, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356R(C-E)I_U366REI/variant_generic.h b/variants/STM32U3xx/U356R(C-E)I_U366REI/variant_generic.h new file mode 100644 index 0000000000..761c01831b --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)I_U366REI/variant_generic.h @@ -0,0 +1,223 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD2 47 +#define PH0 48 +#define PH1 49 +#define PH3 50 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 51 +#define NUM_ANALOG_INPUTS 17 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN5_2 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/PeripheralPins.c b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/PeripheralPins.c new file mode 100644 index 0000000000..95f2a2679a --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/PeripheralPins.c @@ -0,0 +1,393 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356RCIxQ.xml, STM32U356REIxQ.xml + * STM32U366REIxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {PC_9, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/PinNamesVar.h b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/PinNamesVar.h new file mode 100644 index 0000000000..63a8464a2a --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/PinNamesVar.h @@ -0,0 +1,90 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PB_10, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + #ifdef USB_NOE_PA_13 + USB_NOE = PA_13, + #endif + #ifdef USB_NOE_PC_9 + USB_NOE = PC_9, + #endif +#endif diff --git a/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/boards_entry.txt b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/boards_entry.txt new file mode 100644 index 0000000000..9dc227bd9a --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356RCIxQ +GenU3.menu.pnum.GENERIC_U356RCIXQ=Generic U356RCIxQ +GenU3.menu.pnum.GENERIC_U356RCIXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356RCIXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356RCIXQ.build.board=GENERIC_U356RCIXQ +GenU3.menu.pnum.GENERIC_U356RCIXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356RCIXQ.build.variant=STM32U3xx/U356R(C-E)IxQ_U366REIxQ +GenU3.menu.pnum.GENERIC_U356RCIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356REIxQ +GenU3.menu.pnum.GENERIC_U356REIXQ=Generic U356REIxQ +GenU3.menu.pnum.GENERIC_U356REIXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356REIXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356REIXQ.build.board=GENERIC_U356REIXQ +GenU3.menu.pnum.GENERIC_U356REIXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356REIXQ.build.variant=STM32U3xx/U356R(C-E)IxQ_U366REIxQ +GenU3.menu.pnum.GENERIC_U356REIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366REIxQ +GenU3.menu.pnum.GENERIC_U366REIXQ=Generic U366REIxQ +GenU3.menu.pnum.GENERIC_U366REIXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366REIXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366REIXQ.build.board=GENERIC_U366REIXQ +GenU3.menu.pnum.GENERIC_U366REIXQ.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366REIXQ.build.variant=STM32U3xx/U356R(C-E)IxQ_U366REIxQ +GenU3.menu.pnum.GENERIC_U366REIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/generic_clock.c b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/generic_clock.c new file mode 100644 index 0000000000..ca2650c881 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356RCIXQ) || defined(ARDUINO_GENERIC_U356REIXQ) ||\ + defined(ARDUINO_GENERIC_U366REIXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/variant_generic.cpp b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/variant_generic.cpp new file mode 100644 index 0000000000..35fc069c50 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/variant_generic.cpp @@ -0,0 +1,87 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356RCIXQ) || defined(ARDUINO_GENERIC_U356REIXQ) ||\ + defined(ARDUINO_GENERIC_U366REIXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_13, // D26 + PB_14, // D27 + PB_15, // D28 + PC_0, // D29/A11 + PC_1, // D30/A12 + PC_2, // D31/A13 + PC_3, // D32/A14 + PC_6, // D33 + PC_7, // D34 + PC_8, // D35 + PC_9, // D36 + PC_10, // D37 + PC_11, // D38 + PC_12, // D39 + PC_13, // D40 + PC_14, // D41 + PC_15, // D42 + PD_2, // D43 + PH_0, // D44 + PH_1, // D45 + PH_3 // D46 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 29, // A11, PC0 + 30, // A12, PC1 + 31, // A13, PC2 + 32 // A14, PC3 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/variant_generic.h b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/variant_generic.h new file mode 100644 index 0000000000..a52cc78e6d --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/variant_generic.h @@ -0,0 +1,215 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB13 26 +#define PB14 27 +#define PB15 28 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC6 33 +#define PC7 34 +#define PC8 35 +#define PC9 36 +#define PC10 37 +#define PC11 38 +#define PC12 39 +#define PC13 40 +#define PC14 41 +#define PC15 42 +#define PD2 43 +#define PH0 44 +#define PH1 45 +#define PH3 46 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 47 +#define NUM_ANALOG_INPUTS 15 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356R(C-E)T_U366RET/PeripheralPins.c b/variants/STM32U3xx/U356R(C-E)T_U366RET/PeripheralPins.c new file mode 100644 index 0000000000..d833963a7f --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)T_U366RET/PeripheralPins.c @@ -0,0 +1,408 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356RCTx.xml, STM32U356RETx.xml + * STM32U366RETx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_IN12 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {PC_9, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356R(C-E)T_U366RET/PinNamesVar.h b/variants/STM32U3xx/U356R(C-E)T_U366RET/PinNamesVar.h new file mode 100644 index 0000000000..6aff30ffc4 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)T_U366RET/PinNamesVar.h @@ -0,0 +1,96 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PC_5, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_2 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + #ifdef USB_NOE_PA_13 + USB_NOE = PA_13, + #endif + #ifdef USB_NOE_PC_9 + USB_NOE = PC_9, + #endif +#endif diff --git a/variants/STM32U3xx/U356R(C-E)T_U366RET/boards_entry.txt b/variants/STM32U3xx/U356R(C-E)T_U366RET/boards_entry.txt new file mode 100644 index 0000000000..4e9da488d2 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)T_U366RET/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356RCTx +GenU3.menu.pnum.GENERIC_U356RCTX=Generic U356RCTx +GenU3.menu.pnum.GENERIC_U356RCTX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356RCTX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356RCTX.build.board=GENERIC_U356RCTX +GenU3.menu.pnum.GENERIC_U356RCTX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356RCTX.build.variant=STM32U3xx/U356R(C-E)T_U366RET +GenU3.menu.pnum.GENERIC_U356RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356RETx +GenU3.menu.pnum.GENERIC_U356RETX=Generic U356RETx +GenU3.menu.pnum.GENERIC_U356RETX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356RETX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356RETX.build.board=GENERIC_U356RETX +GenU3.menu.pnum.GENERIC_U356RETX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356RETX.build.variant=STM32U3xx/U356R(C-E)T_U366RET +GenU3.menu.pnum.GENERIC_U356RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366RETx +GenU3.menu.pnum.GENERIC_U366RETX=Generic U366RETx +GenU3.menu.pnum.GENERIC_U366RETX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366RETX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366RETX.build.board=GENERIC_U366RETX +GenU3.menu.pnum.GENERIC_U366RETX.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366RETX.build.variant=STM32U3xx/U356R(C-E)T_U366RET +GenU3.menu.pnum.GENERIC_U366RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356R(C-E)T_U366RET/generic_clock.c b/variants/STM32U3xx/U356R(C-E)T_U366RET/generic_clock.c new file mode 100644 index 0000000000..39bb6d86d9 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)T_U366RET/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356RCTX) || defined(ARDUINO_GENERIC_U356RETX) ||\ + defined(ARDUINO_GENERIC_U366RETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356R(C-E)T_U366RET/variant_generic.cpp b/variants/STM32U3xx/U356R(C-E)T_U366RET/variant_generic.cpp new file mode 100644 index 0000000000..d5fd4b19f7 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)T_U366RET/variant_generic.cpp @@ -0,0 +1,93 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356RCTX) || defined(ARDUINO_GENERIC_U356RETX) ||\ + defined(ARDUINO_GENERIC_U366RETX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_2, // D47 + PH_0, // D48 + PH_1, // D49 + PH_3 // D50 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36 // A16, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356R(C-E)T_U366RET/variant_generic.h b/variants/STM32U3xx/U356R(C-E)T_U366RET/variant_generic.h new file mode 100644 index 0000000000..761c01831b --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)T_U366RET/variant_generic.h @@ -0,0 +1,223 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD2 47 +#define PH0 48 +#define PH1 49 +#define PH3 50 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 51 +#define NUM_ANALOG_INPUTS 17 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN5_2 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/PeripheralPins.c b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/PeripheralPins.c new file mode 100644 index 0000000000..f648125008 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/PeripheralPins.c @@ -0,0 +1,393 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356RCTxQ.xml, STM32U356RETxQ.xml + * STM32U366RETxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {PC_9, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/PinNamesVar.h b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/PinNamesVar.h new file mode 100644 index 0000000000..7bb5327e4f --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/PinNamesVar.h @@ -0,0 +1,90 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + #ifdef USB_NOE_PA_13 + USB_NOE = PA_13, + #endif + #ifdef USB_NOE_PC_9 + USB_NOE = PC_9, + #endif +#endif diff --git a/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/boards_entry.txt b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/boards_entry.txt new file mode 100644 index 0000000000..35bdba1297 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356RCTxQ +GenU3.menu.pnum.GENERIC_U356RCTXQ=Generic U356RCTxQ +GenU3.menu.pnum.GENERIC_U356RCTXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356RCTXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356RCTXQ.build.board=GENERIC_U356RCTXQ +GenU3.menu.pnum.GENERIC_U356RCTXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356RCTXQ.build.variant=STM32U3xx/U356R(C-E)TxQ_U366RETxQ +GenU3.menu.pnum.GENERIC_U356RCTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356RETxQ +GenU3.menu.pnum.GENERIC_U356RETXQ=Generic U356RETxQ +GenU3.menu.pnum.GENERIC_U356RETXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356RETXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356RETXQ.build.board=GENERIC_U356RETXQ +GenU3.menu.pnum.GENERIC_U356RETXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356RETXQ.build.variant=STM32U3xx/U356R(C-E)TxQ_U366RETxQ +GenU3.menu.pnum.GENERIC_U356RETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366RETxQ +GenU3.menu.pnum.GENERIC_U366RETXQ=Generic U366RETxQ +GenU3.menu.pnum.GENERIC_U366RETXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366RETXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366RETXQ.build.board=GENERIC_U366RETXQ +GenU3.menu.pnum.GENERIC_U366RETXQ.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366RETXQ.build.variant=STM32U3xx/U356R(C-E)TxQ_U366RETxQ +GenU3.menu.pnum.GENERIC_U366RETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/generic_clock.c b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/generic_clock.c new file mode 100644 index 0000000000..3dbfc691f6 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356RCTXQ) || defined(ARDUINO_GENERIC_U356RETXQ) ||\ + defined(ARDUINO_GENERIC_U366RETXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/variant_generic.cpp b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/variant_generic.cpp new file mode 100644 index 0000000000..272b9d4d12 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/variant_generic.cpp @@ -0,0 +1,87 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356RCTXQ) || defined(ARDUINO_GENERIC_U356RETXQ) ||\ + defined(ARDUINO_GENERIC_U366RETXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_13, // D26 + PB_14, // D27 + PB_15, // D28 + PC_0, // D29/A11 + PC_1, // D30/A12 + PC_2, // D31/A13 + PC_3, // D32/A14 + PC_6, // D33 + PC_7, // D34 + PC_8, // D35 + PC_9, // D36 + PC_10, // D37 + PC_11, // D38 + PC_12, // D39 + PC_13, // D40 + PC_14, // D41 + PC_15, // D42 + PD_2, // D43 + PH_0, // D44 + PH_1, // D45 + PH_3 // D46 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 29, // A11, PC0 + 30, // A12, PC1 + 31, // A13, PC2 + 32 // A14, PC3 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/variant_generic.h b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/variant_generic.h new file mode 100644 index 0000000000..a52cc78e6d --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/variant_generic.h @@ -0,0 +1,215 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB13 26 +#define PB14 27 +#define PB15 28 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC6 33 +#define PC7 34 +#define PC8 35 +#define PC9 36 +#define PC10 37 +#define PC11 38 +#define PC12 39 +#define PC13 40 +#define PC14 41 +#define PC15 42 +#define PD2 43 +#define PH0 44 +#define PH1 45 +#define PH3 46 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 47 +#define NUM_ANALOG_INPUTS 15 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/PeripheralPins.c b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/PeripheralPins.c new file mode 100644 index 0000000000..b9cb209751 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/PeripheralPins.c @@ -0,0 +1,394 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356RCYxQ.xml, STM32U356REYxQ.xml + * STM32U366REYxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {PC_9, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/PinNamesVar.h b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/PinNamesVar.h new file mode 100644 index 0000000000..3e6614ca94 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/PinNamesVar.h @@ -0,0 +1,91 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + #ifdef USB_NOE_PA_13 + USB_NOE = PA_13, + #endif + #ifdef USB_NOE_PC_9 + USB_NOE = PC_9, + #endif +#endif diff --git a/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/boards_entry.txt b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/boards_entry.txt new file mode 100644 index 0000000000..3a8b174642 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356RCYxQ +GenU3.menu.pnum.GENERIC_U356RCYXQ=Generic U356RCYxQ +GenU3.menu.pnum.GENERIC_U356RCYXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356RCYXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356RCYXQ.build.board=GENERIC_U356RCYXQ +GenU3.menu.pnum.GENERIC_U356RCYXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356RCYXQ.build.variant=STM32U3xx/U356R(C-E)YxQ_U366REYxQ +GenU3.menu.pnum.GENERIC_U356RCYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356REYxQ +GenU3.menu.pnum.GENERIC_U356REYXQ=Generic U356REYxQ +GenU3.menu.pnum.GENERIC_U356REYXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356REYXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356REYXQ.build.board=GENERIC_U356REYXQ +GenU3.menu.pnum.GENERIC_U356REYXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356REYXQ.build.variant=STM32U3xx/U356R(C-E)YxQ_U366REYxQ +GenU3.menu.pnum.GENERIC_U356REYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366REYxQ +GenU3.menu.pnum.GENERIC_U366REYXQ=Generic U366REYxQ +GenU3.menu.pnum.GENERIC_U366REYXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366REYXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366REYXQ.build.board=GENERIC_U366REYXQ +GenU3.menu.pnum.GENERIC_U366REYXQ.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366REYXQ.build.variant=STM32U3xx/U356R(C-E)YxQ_U366REYxQ +GenU3.menu.pnum.GENERIC_U366REYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/generic_clock.c b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/generic_clock.c new file mode 100644 index 0000000000..2c3ee7a790 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356RCYXQ) || defined(ARDUINO_GENERIC_U356REYXQ) ||\ + defined(ARDUINO_GENERIC_U366REYXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/variant_generic.cpp b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/variant_generic.cpp new file mode 100644 index 0000000000..47421fcc57 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/variant_generic.cpp @@ -0,0 +1,87 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356RCYXQ) || defined(ARDUINO_GENERIC_U356REYXQ) ||\ + defined(ARDUINO_GENERIC_U366REYXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_6, // D35 + PC_7, // D36 + PC_8, // D37 + PC_9, // D38 + PC_10, // D39 + PC_11, // D40 + PC_13, // D41 + PC_14, // D42 + PC_15, // D43 + PH_0, // D44 + PH_1, // D45 + PH_3 // D46 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34 // A14, PC3 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/variant_generic.h b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/variant_generic.h new file mode 100644 index 0000000000..7d49f9c802 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/variant_generic.h @@ -0,0 +1,216 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC6 35 +#define PC7 36 +#define PC8 37 +#define PC9 38 +#define PC10 39 +#define PC11 40 +#define PC13 41 +#define PC14 42 +#define PC15 43 +#define PH0 44 +#define PH1 45 +#define PH3 46 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 47 +#define NUM_ANALOG_INPUTS 15 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356V(C-E)I_U366VEI/PeripheralPins.c b/variants/STM32U3xx/U356V(C-E)I_U366VEI/PeripheralPins.c new file mode 100644 index 0000000000..edda30ce3d --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)I_U366VEI/PeripheralPins.c @@ -0,0 +1,457 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356VCIx.xml, STM32U356VEIx.xml + * STM32U366VEIx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_IN12 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PD_11, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PD_12, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PD_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_13, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_12, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PE_3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PE_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PE_13, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PE_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PE_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PE_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {PC_9, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356V(C-E)I_U366VEI/PinNamesVar.h b/variants/STM32U3xx/U356V(C-E)I_U366VEI/PinNamesVar.h new file mode 100644 index 0000000000..b0e89c9d4c --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)I_U366VEI/PinNamesVar.h @@ -0,0 +1,111 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PE_4, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_2 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PE_5, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_2 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PE_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_2 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_2 = PC_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_2 = PE_7, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_2 = PE_8, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PB_10, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PA_7, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + #ifdef USB_NOE_PA_13 + USB_NOE = PA_13, + #endif + #ifdef USB_NOE_PC_9 + USB_NOE = PC_9, + #endif +#endif diff --git a/variants/STM32U3xx/U356V(C-E)I_U366VEI/boards_entry.txt b/variants/STM32U3xx/U356V(C-E)I_U366VEI/boards_entry.txt new file mode 100644 index 0000000000..c2426e0487 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)I_U366VEI/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356VCIx +GenU3.menu.pnum.GENERIC_U356VCIX=Generic U356VCIx +GenU3.menu.pnum.GENERIC_U356VCIX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356VCIX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356VCIX.build.board=GENERIC_U356VCIX +GenU3.menu.pnum.GENERIC_U356VCIX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356VCIX.build.variant=STM32U3xx/U356V(C-E)I_U366VEI +GenU3.menu.pnum.GENERIC_U356VCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356VEIx +GenU3.menu.pnum.GENERIC_U356VEIX=Generic U356VEIx +GenU3.menu.pnum.GENERIC_U356VEIX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356VEIX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356VEIX.build.board=GENERIC_U356VEIX +GenU3.menu.pnum.GENERIC_U356VEIX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356VEIX.build.variant=STM32U3xx/U356V(C-E)I_U366VEI +GenU3.menu.pnum.GENERIC_U356VEIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366VEIx +GenU3.menu.pnum.GENERIC_U366VEIX=Generic U366VEIx +GenU3.menu.pnum.GENERIC_U366VEIX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366VEIX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366VEIX.build.board=GENERIC_U366VEIX +GenU3.menu.pnum.GENERIC_U366VEIX.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366VEIX.build.variant=STM32U3xx/U356V(C-E)I_U366VEI +GenU3.menu.pnum.GENERIC_U366VEIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356V(C-E)I_U366VEI/generic_clock.c b/variants/STM32U3xx/U356V(C-E)I_U366VEI/generic_clock.c new file mode 100644 index 0000000000..76449b5890 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)I_U366VEI/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356VCIX) || defined(ARDUINO_GENERIC_U356VEIX) ||\ + defined(ARDUINO_GENERIC_U366VEIX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356V(C-E)I_U366VEI/variant_generic.cpp b/variants/STM32U3xx/U356V(C-E)I_U366VEI/variant_generic.cpp new file mode 100644 index 0000000000..969265a512 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)I_U366VEI/variant_generic.cpp @@ -0,0 +1,127 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356VCIX) || defined(ARDUINO_GENERIC_U356VEIX) ||\ + defined(ARDUINO_GENERIC_U366VEIX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58/A17 + PD_12, // D59/A18 + PD_13, // D60/A19 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_1, // D64 + PE_2, // D65 + PE_3, // D66 + PE_4, // D67 + PE_5, // D68 + PE_6, // D69 + PE_7, // D70 + PE_8, // D71 + PE_9, // D72 + PE_10, // D73 + PE_11, // D74 + PE_12, // D75 + PE_13, // D76 + PE_14, // D77 + PE_15, // D78 + PH_0, // D79 + PH_1, // D80 + PH_3 // D81 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 58, // A17, PD11 + 59, // A18, PD12 + 60 // A19, PD13 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356V(C-E)I_U366VEI/variant_generic.h b/variants/STM32U3xx/U356V(C-E)I_U366VEI/variant_generic.h new file mode 100644 index 0000000000..3192eb0cf7 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)I_U366VEI/variant_generic.h @@ -0,0 +1,259 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 PIN_A17 +#define PD12 PIN_A18 +#define PD13 PIN_A19 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE1 64 +#define PE2 65 +#define PE3 66 +#define PE4 67 +#define PE5 68 +#define PE6 69 +#define PE7 70 +#define PE8 71 +#define PE9 72 +#define PE10 73 +#define PE11 74 +#define PE12 75 +#define PE13 76 +#define PE14 77 +#define PE15 78 +#define PH0 79 +#define PH1 80 +#define PH3 81 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 82 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE12 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN1_2 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN2_2 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN3_2 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN5_2 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN6_2 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN7_2 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/PeripheralPins.c b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/PeripheralPins.c new file mode 100644 index 0000000000..4980e8de04 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/PeripheralPins.c @@ -0,0 +1,449 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356VCIxQ.xml, STM32U356VEIxQ.xml + * STM32U366VEIxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PD_11, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PD_12, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PD_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_13, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_12, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PE_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PE_13, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PE_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PE_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PE_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {PC_9, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/PinNamesVar.h b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/PinNamesVar.h new file mode 100644 index 0000000000..61e3de4d09 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/PinNamesVar.h @@ -0,0 +1,106 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PE_4, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_2 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PE_5, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_2 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PE_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_2 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PE_7, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_2 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PE_8, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_2 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + #ifdef USB_NOE_PA_13 + USB_NOE = PA_13, + #endif + #ifdef USB_NOE_PC_9 + USB_NOE = PC_9, + #endif +#endif diff --git a/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/boards_entry.txt b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/boards_entry.txt new file mode 100644 index 0000000000..187d04d8b7 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356VCIxQ +GenU3.menu.pnum.GENERIC_U356VCIXQ=Generic U356VCIxQ +GenU3.menu.pnum.GENERIC_U356VCIXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356VCIXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356VCIXQ.build.board=GENERIC_U356VCIXQ +GenU3.menu.pnum.GENERIC_U356VCIXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356VCIXQ.build.variant=STM32U3xx/U356V(C-E)IxQ_U366VEIxQ +GenU3.menu.pnum.GENERIC_U356VCIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356VEIxQ +GenU3.menu.pnum.GENERIC_U356VEIXQ=Generic U356VEIxQ +GenU3.menu.pnum.GENERIC_U356VEIXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356VEIXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356VEIXQ.build.board=GENERIC_U356VEIXQ +GenU3.menu.pnum.GENERIC_U356VEIXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356VEIXQ.build.variant=STM32U3xx/U356V(C-E)IxQ_U366VEIxQ +GenU3.menu.pnum.GENERIC_U356VEIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366VEIxQ +GenU3.menu.pnum.GENERIC_U366VEIXQ=Generic U366VEIxQ +GenU3.menu.pnum.GENERIC_U366VEIXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366VEIXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366VEIXQ.build.board=GENERIC_U366VEIXQ +GenU3.menu.pnum.GENERIC_U366VEIXQ.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366VEIXQ.build.variant=STM32U3xx/U356V(C-E)IxQ_U366VEIxQ +GenU3.menu.pnum.GENERIC_U366VEIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/generic_clock.c b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/generic_clock.c new file mode 100644 index 0000000000..0b2ea4bf49 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356VCIXQ) || defined(ARDUINO_GENERIC_U356VEIXQ) ||\ + defined(ARDUINO_GENERIC_U366VEIXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/variant_generic.cpp b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/variant_generic.cpp new file mode 100644 index 0000000000..8730984177 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/variant_generic.cpp @@ -0,0 +1,122 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356VCIXQ) || defined(ARDUINO_GENERIC_U356VEIXQ) ||\ + defined(ARDUINO_GENERIC_U366VEIXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_6, // D35 + PC_7, // D36 + PC_8, // D37 + PC_9, // D38 + PC_10, // D39 + PC_11, // D40 + PC_12, // D41 + PC_13, // D42 + PC_14, // D43 + PC_15, // D44 + PD_0, // D45 + PD_1, // D46 + PD_2, // D47 + PD_3, // D48 + PD_4, // D49 + PD_5, // D50 + PD_6, // D51 + PD_7, // D52 + PD_8, // D53 + PD_9, // D54 + PD_10, // D55 + PD_11, // D56/A15 + PD_12, // D57/A16 + PD_13, // D58/A17 + PD_14, // D59 + PD_15, // D60 + PE_0, // D61 + PE_2, // D62 + PE_3, // D63 + PE_4, // D64 + PE_5, // D65 + PE_6, // D66 + PE_7, // D67 + PE_8, // D68 + PE_9, // D69 + PE_10, // D70 + PE_11, // D71 + PE_12, // D72 + PE_13, // D73 + PE_14, // D74 + PE_15, // D75 + PH_0, // D76 + PH_1, // D77 + PH_3 // D78 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 56, // A15, PD11 + 57, // A16, PD12 + 58 // A17, PD13 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/variant_generic.h b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/variant_generic.h new file mode 100644 index 0000000000..d1e4e17d84 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/variant_generic.h @@ -0,0 +1,253 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC6 35 +#define PC7 36 +#define PC8 37 +#define PC9 38 +#define PC10 39 +#define PC11 40 +#define PC12 41 +#define PC13 42 +#define PC14 43 +#define PC15 44 +#define PD0 45 +#define PD1 46 +#define PD2 47 +#define PD3 48 +#define PD4 49 +#define PD5 50 +#define PD6 51 +#define PD7 52 +#define PD8 53 +#define PD9 54 +#define PD10 55 +#define PD11 PIN_A15 +#define PD12 PIN_A16 +#define PD13 PIN_A17 +#define PD14 59 +#define PD15 60 +#define PE0 61 +#define PE2 62 +#define PE3 63 +#define PE4 64 +#define PE5 65 +#define PE6 66 +#define PE7 67 +#define PE8 68 +#define PE9 69 +#define PE10 70 +#define PE11 71 +#define PE12 72 +#define PE13 73 +#define PE14 74 +#define PE15 75 +#define PH0 76 +#define PH1 77 +#define PH3 78 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 79 +#define NUM_ANALOG_INPUTS 18 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE12 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN1_2 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN2_2 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN3_2 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN6_2 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN7_2 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356V(C-E)T_U366VET/PeripheralPins.c b/variants/STM32U3xx/U356V(C-E)T_U366VET/PeripheralPins.c new file mode 100644 index 0000000000..bead043bbe --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)T_U366VET/PeripheralPins.c @@ -0,0 +1,457 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356VCTx.xml, STM32U356VETx.xml + * STM32U366VETx.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_IN12 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PD_11, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PD_12, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PD_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_13, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_12, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PE_3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PE_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PE_13, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PE_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PE_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PE_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {PC_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {PC_9, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356V(C-E)T_U366VET/PinNamesVar.h b/variants/STM32U3xx/U356V(C-E)T_U366VET/PinNamesVar.h new file mode 100644 index 0000000000..516b7983af --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)T_U366VET/PinNamesVar.h @@ -0,0 +1,111 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PE_4, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_2 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PE_5, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_2 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_2 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PC_5, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_2 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PE_7, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_2 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PE_8, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_2 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + #ifdef USB_NOE_PA_13 + USB_NOE = PA_13, + #endif + #ifdef USB_NOE_PC_9 + USB_NOE = PC_9, + #endif +#endif diff --git a/variants/STM32U3xx/U356V(C-E)T_U366VET/boards_entry.txt b/variants/STM32U3xx/U356V(C-E)T_U366VET/boards_entry.txt new file mode 100644 index 0000000000..5da910307b --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)T_U366VET/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356VCTx +GenU3.menu.pnum.GENERIC_U356VCTX=Generic U356VCTx +GenU3.menu.pnum.GENERIC_U356VCTX.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356VCTX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356VCTX.build.board=GENERIC_U356VCTX +GenU3.menu.pnum.GENERIC_U356VCTX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356VCTX.build.variant=STM32U3xx/U356V(C-E)T_U366VET +GenU3.menu.pnum.GENERIC_U356VCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356VETx +GenU3.menu.pnum.GENERIC_U356VETX=Generic U356VETx +GenU3.menu.pnum.GENERIC_U356VETX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356VETX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356VETX.build.board=GENERIC_U356VETX +GenU3.menu.pnum.GENERIC_U356VETX.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356VETX.build.variant=STM32U3xx/U356V(C-E)T_U366VET +GenU3.menu.pnum.GENERIC_U356VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366VETx +GenU3.menu.pnum.GENERIC_U366VETX=Generic U366VETx +GenU3.menu.pnum.GENERIC_U366VETX.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366VETX.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366VETX.build.board=GENERIC_U366VETX +GenU3.menu.pnum.GENERIC_U366VETX.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366VETX.build.variant=STM32U3xx/U356V(C-E)T_U366VET +GenU3.menu.pnum.GENERIC_U366VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356V(C-E)T_U366VET/generic_clock.c b/variants/STM32U3xx/U356V(C-E)T_U366VET/generic_clock.c new file mode 100644 index 0000000000..3a46d01a8e --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)T_U366VET/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356VCTX) || defined(ARDUINO_GENERIC_U356VETX) ||\ + defined(ARDUINO_GENERIC_U366VETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356V(C-E)T_U366VET/variant_generic.cpp b/variants/STM32U3xx/U356V(C-E)T_U366VET/variant_generic.cpp new file mode 100644 index 0000000000..ac5e560c2d --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)T_U366VET/variant_generic.cpp @@ -0,0 +1,127 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356VCTX) || defined(ARDUINO_GENERIC_U356VETX) ||\ + defined(ARDUINO_GENERIC_U366VETX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58/A17 + PD_12, // D59/A18 + PD_13, // D60/A19 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_1, // D64 + PE_2, // D65 + PE_3, // D66 + PE_4, // D67 + PE_5, // D68 + PE_6, // D69 + PE_7, // D70 + PE_8, // D71 + PE_9, // D72 + PE_10, // D73 + PE_11, // D74 + PE_12, // D75 + PE_13, // D76 + PE_14, // D77 + PE_15, // D78 + PH_0, // D79 + PH_1, // D80 + PH_3 // D81 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 58, // A17, PD11 + 59, // A18, PD12 + 60 // A19, PD13 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356V(C-E)T_U366VET/variant_generic.h b/variants/STM32U3xx/U356V(C-E)T_U366VET/variant_generic.h new file mode 100644 index 0000000000..3192eb0cf7 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)T_U366VET/variant_generic.h @@ -0,0 +1,259 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 PIN_A17 +#define PD12 PIN_A18 +#define PD13 PIN_A19 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE1 64 +#define PE2 65 +#define PE3 66 +#define PE4 67 +#define PE5 68 +#define PE6 69 +#define PE7 70 +#define PE8 71 +#define PE9 72 +#define PE10 73 +#define PE11 74 +#define PE12 75 +#define PE13 76 +#define PE14 77 +#define PE15 78 +#define PH0 79 +#define PH1 80 +#define PH3 81 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 82 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE12 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN1_2 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN2_2 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN3_2 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN5_2 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN6_2 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN7_2 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/PeripheralPins.c b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/PeripheralPins.c new file mode 100644 index 0000000000..d72b4da971 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/PeripheralPins.c @@ -0,0 +1,449 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32U356VCTxQ.xml, STM32U356VETxQ.xml + * STM32U366VETxQ.xml + * CubeMX DB release 6.0.180 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PD_11, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PD_12, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PD_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_13, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF3_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {PD_12, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PA_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PC_1, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PH_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_2, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF5_I3C1)}, + {PB_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF6_I3C1)}, + {PB_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PH_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_4, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_UART5)}, + {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PE_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_SPI2)}, + {PE_13, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PE_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {PE_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {PE_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PD_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {PE_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PB_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_DP + {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {PC_9, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_USB)}, // USB_NOE + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/PinNamesVar.h b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/PinNamesVar.h new file mode 100644 index 0000000000..1cda72163c --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/PinNamesVar.h @@ -0,0 +1,106 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1 = PE_4, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_1 = PA_0, +#endif +#ifdef PWR_WAKEUP_LINE1 + SYS_WKUP1_2 = PB_2, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2 = PE_5, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_1 = PC_13, +#endif +#ifdef PWR_WAKEUP_LINE2 + SYS_WKUP2_2 = PA_4, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_LINE3 + SYS_WKUP3_2 = PB_6, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_LINE4 + SYS_WKUP4_2 = PB_7, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_LINE5 + SYS_WKUP5_1 = PB_8, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_1 = PE_7, +#endif +#ifdef PWR_WAKEUP_LINE6 + SYS_WKUP6_2 = PB_5, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_1 = PE_8, +#endif +#ifdef PWR_WAKEUP_LINE7 + SYS_WKUP7_2 = PB_15, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_LINE8 + SYS_WKUP8_1 = PB_10, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + #ifdef USB_NOE_PA_13 + USB_NOE = PA_13, + #endif + #ifdef USB_NOE_PC_9 + USB_NOE = PC_9, + #endif +#endif diff --git a/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/boards_entry.txt b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/boards_entry.txt new file mode 100644 index 0000000000..f3eed13972 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic U356VCTxQ +GenU3.menu.pnum.GENERIC_U356VCTXQ=Generic U356VCTxQ +GenU3.menu.pnum.GENERIC_U356VCTXQ.upload.maximum_size=262144 +GenU3.menu.pnum.GENERIC_U356VCTXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356VCTXQ.build.board=GENERIC_U356VCTXQ +GenU3.menu.pnum.GENERIC_U356VCTXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356VCTXQ.build.variant=STM32U3xx/U356V(C-E)TxQ_U366VETxQ +GenU3.menu.pnum.GENERIC_U356VCTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U356VETxQ +GenU3.menu.pnum.GENERIC_U356VETXQ=Generic U356VETxQ +GenU3.menu.pnum.GENERIC_U356VETXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U356VETXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U356VETXQ.build.board=GENERIC_U356VETXQ +GenU3.menu.pnum.GENERIC_U356VETXQ.build.product_line=STM32U356xx +GenU3.menu.pnum.GENERIC_U356VETXQ.build.variant=STM32U3xx/U356V(C-E)TxQ_U366VETxQ +GenU3.menu.pnum.GENERIC_U356VETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U356.svd + +# Generic U366VETxQ +GenU3.menu.pnum.GENERIC_U366VETXQ=Generic U366VETxQ +GenU3.menu.pnum.GENERIC_U366VETXQ.upload.maximum_size=524288 +GenU3.menu.pnum.GENERIC_U366VETXQ.upload.maximum_data_size=196608 +GenU3.menu.pnum.GENERIC_U366VETXQ.build.board=GENERIC_U366VETXQ +GenU3.menu.pnum.GENERIC_U366VETXQ.build.product_line=STM32U366xx +GenU3.menu.pnum.GENERIC_U366VETXQ.build.variant=STM32U3xx/U356V(C-E)TxQ_U366VETxQ +GenU3.menu.pnum.GENERIC_U366VETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U366.svd + diff --git a/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/generic_clock.c b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/generic_clock.c new file mode 100644 index 0000000000..d9aa0a47ba --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356VCTXQ) || defined(ARDUINO_GENERIC_U356VETXQ) ||\ + defined(ARDUINO_GENERIC_U366VETXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/variant_generic.cpp b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/variant_generic.cpp new file mode 100644 index 0000000000..f587850827 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/variant_generic.cpp @@ -0,0 +1,122 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_U356VCTXQ) || defined(ARDUINO_GENERIC_U356VETXQ) ||\ + defined(ARDUINO_GENERIC_U366VETXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_6, // D35 + PC_7, // D36 + PC_8, // D37 + PC_9, // D38 + PC_10, // D39 + PC_11, // D40 + PC_12, // D41 + PC_13, // D42 + PC_14, // D43 + PC_15, // D44 + PD_0, // D45 + PD_1, // D46 + PD_2, // D47 + PD_3, // D48 + PD_4, // D49 + PD_5, // D50 + PD_6, // D51 + PD_7, // D52 + PD_8, // D53 + PD_9, // D54 + PD_10, // D55 + PD_11, // D56/A15 + PD_12, // D57/A16 + PD_13, // D58/A17 + PD_14, // D59 + PD_15, // D60 + PE_0, // D61 + PE_2, // D62 + PE_3, // D63 + PE_4, // D64 + PE_5, // D65 + PE_6, // D66 + PE_7, // D67 + PE_8, // D68 + PE_9, // D69 + PE_10, // D70 + PE_11, // D71 + PE_12, // D72 + PE_13, // D73 + PE_14, // D74 + PE_15, // D75 + PH_0, // D76 + PH_1, // D77 + PH_3 // D78 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 56, // A15, PD11 + 57, // A16, PD12 + 58 // A17, PD13 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/variant_generic.h b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/variant_generic.h new file mode 100644 index 0000000000..d1e4e17d84 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/variant_generic.h @@ -0,0 +1,253 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC6 35 +#define PC7 36 +#define PC8 37 +#define PC9 38 +#define PC10 39 +#define PC11 40 +#define PC12 41 +#define PC13 42 +#define PC14 43 +#define PC15 44 +#define PD0 45 +#define PD1 46 +#define PD2 47 +#define PD3 48 +#define PD4 49 +#define PD5 50 +#define PD6 51 +#define PD7 52 +#define PD8 53 +#define PD9 54 +#define PD10 55 +#define PD11 PIN_A15 +#define PD12 PIN_A16 +#define PD13 PIN_A17 +#define PD14 59 +#define PD15 60 +#define PE0 61 +#define PE2 62 +#define PE3 63 +#define PE4 64 +#define PE5 65 +#define PE6 66 +#define PE7 67 +#define PE8 68 +#define PE9 69 +#define PE10 70 +#define PE11 71 +#define PE12 72 +#define PE13 73 +#define PE14 74 +#define PE15 75 +#define PH0 76 +#define PH1 77 +#define PH3 78 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 79 +#define NUM_ANALOG_INPUTS 18 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB0 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE12 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB2 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA1 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA7 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define HAL_I3C_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN1_2 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN2_2 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN3_2 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN4_2 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN6_2 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN7_2 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/PeripheralPins.c b/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/PeripheralPins.c index c0ddd2e4a5..c8baac730c 100644 --- a/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/PeripheralPins.c +++ b/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U375CETx.xml, STM32U375CEUx.xml * STM32U375CGTx.xml, STM32U375CGUx.xml * STM32U385CGTx.xml, STM32U385CGUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/PeripheralPins.c b/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/PeripheralPins.c index 61611ec765..a2388f1ca9 100644 --- a/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U375CETxQ.xml, STM32U375CEUxQ.xml * STM32U375CGTxQ.xml, STM32U375CGUxQ.xml * STM32U385CGTxQ.xml, STM32U385CGUxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/PeripheralPins.c b/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/PeripheralPins.c index a90ed380f8..574635361d 100644 --- a/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375CEYxQ.xml, STM32U375CGYxQ.xml * STM32U385CGYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375K(E-G)U_U385KGU/PeripheralPins.c b/variants/STM32U3xx/U375K(E-G)U_U385KGU/PeripheralPins.c index 6307ad8de4..65f5532489 100644 --- a/variants/STM32U3xx/U375K(E-G)U_U385KGU/PeripheralPins.c +++ b/variants/STM32U3xx/U375K(E-G)U_U385KGU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375KEUx.xml, STM32U375KGUx.xml * STM32U385KGUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)I_U385RGI/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)I_U385RGI/PeripheralPins.c index d4002217b3..07e22dd0ef 100644 --- a/variants/STM32U3xx/U375R(E-G)I_U385RGI/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)I_U385RGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375REIx.xml, STM32U375RGIx.xml * STM32U385RGIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/PeripheralPins.c index 78cd5c0722..71814e2b9f 100644 --- a/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375REIxQ.xml, STM32U375RGIxQ.xml * STM32U385RGIxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)T_U385RGT/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)T_U385RGT/PeripheralPins.c index 225e504bfe..9545313061 100644 --- a/variants/STM32U3xx/U375R(E-G)T_U385RGT/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)T_U385RGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375RETx.xml, STM32U375RGTx.xml * STM32U385RGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/PeripheralPins.c index b58087d029..ca6d26b22c 100644 --- a/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375RETxQ.xml, STM32U375RGTxQ.xml * STM32U385RGTxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/PeripheralPins.c index f32fac6418..52cfcb4d75 100644 --- a/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375REYxG.xml, STM32U375RGYxG.xml * STM32U385RGYxG.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/PeripheralPins.c index a089d7c638..41e3851e4c 100644 --- a/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375REYxQ.xml, STM32U375RGYxQ.xml * STM32U385RGYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375V(E-G)I_U385VGI/PeripheralPins.c b/variants/STM32U3xx/U375V(E-G)I_U385VGI/PeripheralPins.c index cd422d40d3..226691cd1b 100644 --- a/variants/STM32U3xx/U375V(E-G)I_U385VGI/PeripheralPins.c +++ b/variants/STM32U3xx/U375V(E-G)I_U385VGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375VEIx.xml, STM32U375VGIx.xml * STM32U385VGIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/PeripheralPins.c b/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/PeripheralPins.c index 0235e2273f..e9bd1b8cbd 100644 --- a/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375VEIxQ.xml, STM32U375VGIxQ.xml * STM32U385VGIxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375V(E-G)T_U385VGT/PeripheralPins.c b/variants/STM32U3xx/U375V(E-G)T_U385VGT/PeripheralPins.c index 50065929d7..74b472a620 100644 --- a/variants/STM32U3xx/U375V(E-G)T_U385VGT/PeripheralPins.c +++ b/variants/STM32U3xx/U375V(E-G)T_U385VGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375VETx.xml, STM32U375VGTx.xml * STM32U385VGTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/PeripheralPins.c b/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/PeripheralPins.c index a7a7b3f686..0beebe2e99 100644 --- a/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375VETxQ.xml, STM32U375VGTxQ.xml * STM32U385VGTxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5C(G-I)(T-U)_U3C5CI(T-U)/PeripheralPins.c b/variants/STM32U3xx/U3B5C(G-I)(T-U)_U3C5CI(T-U)/PeripheralPins.c index f31cb8854b..23dae080e9 100644 --- a/variants/STM32U3xx/U3B5C(G-I)(T-U)_U3C5CI(T-U)/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5C(G-I)(T-U)_U3C5CI(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U3B5CGTx.xml, STM32U3B5CGUx.xml * STM32U3B5CITx.xml, STM32U3B5CIUx.xml * STM32U3C5CITx.xml, STM32U3C5CIUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5C(G-I)(T-U)xQ_U3C5CI(T-U)xQ/PeripheralPins.c b/variants/STM32U3xx/U3B5C(G-I)(T-U)xQ_U3C5CI(T-U)xQ/PeripheralPins.c index 62bcb0da23..2b8500d899 100644 --- a/variants/STM32U3xx/U3B5C(G-I)(T-U)xQ_U3C5CI(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5C(G-I)(T-U)xQ_U3C5CI(T-U)xQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U3B5CGTxQ.xml, STM32U3B5CGUxQ.xml * STM32U3B5CITxQ.xml, STM32U3B5CIUxQ.xml * STM32U3C5CITxQ.xml, STM32U3C5CIUxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5J(G-I)YxQ_U3C5JIYxQ/PeripheralPins.c b/variants/STM32U3xx/U3B5J(G-I)YxQ_U3C5JIYxQ/PeripheralPins.c index 280970012d..b59d40697b 100644 --- a/variants/STM32U3xx/U3B5J(G-I)YxQ_U3C5JIYxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5J(G-I)YxQ_U3C5JIYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U3B5JGYxQ.xml, STM32U3B5JIYxQ.xml * STM32U3C5JIYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5Q(G-I)I_U3C5QII/PeripheralPins.c b/variants/STM32U3xx/U3B5Q(G-I)I_U3C5QII/PeripheralPins.c index 89b5297f3f..e65a85f9fc 100644 --- a/variants/STM32U3xx/U3B5Q(G-I)I_U3C5QII/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5Q(G-I)I_U3C5QII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U3B5QGIx.xml, STM32U3B5QIIx.xml * STM32U3C5QIIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5Q(G-I)IxQ_U3C5QIIxQ/PeripheralPins.c b/variants/STM32U3xx/U3B5Q(G-I)IxQ_U3C5QIIxQ/PeripheralPins.c index 4d835a86bf..9c591fbca5 100644 --- a/variants/STM32U3xx/U3B5Q(G-I)IxQ_U3C5QIIxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5Q(G-I)IxQ_U3C5QIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U3B5QGIxQ.xml, STM32U3B5QIIxQ.xml * STM32U3C5QIIxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5R(G-I)T_U3C5RIT/PeripheralPins.c b/variants/STM32U3xx/U3B5R(G-I)T_U3C5RIT/PeripheralPins.c index ff21678dae..d42e4e30ee 100644 --- a/variants/STM32U3xx/U3B5R(G-I)T_U3C5RIT/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5R(G-I)T_U3C5RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U3B5RGTx.xml, STM32U3B5RITx.xml * STM32U3C5RITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5R(G-I)TxQ_U3C5RITxQ/PeripheralPins.c b/variants/STM32U3xx/U3B5R(G-I)TxQ_U3C5RITxQ/PeripheralPins.c index 6b4be3b58e..2e3721fb15 100644 --- a/variants/STM32U3xx/U3B5R(G-I)TxQ_U3C5RITxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5R(G-I)TxQ_U3C5RITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U3B5RGTxQ.xml, STM32U3B5RITxQ.xml * STM32U3C5RITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5V(G-I)T_U3C5VIT/PeripheralPins.c b/variants/STM32U3xx/U3B5V(G-I)T_U3C5VIT/PeripheralPins.c index b7243ace88..532cb3143f 100644 --- a/variants/STM32U3xx/U3B5V(G-I)T_U3C5VIT/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5V(G-I)T_U3C5VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U3B5VGTx.xml, STM32U3B5VITx.xml * STM32U3C5VITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5V(G-I)TxQ_U3C5VITxQ/PeripheralPins.c b/variants/STM32U3xx/U3B5V(G-I)TxQ_U3C5VITxQ/PeripheralPins.c index 430a0d12b6..9803f0a476 100644 --- a/variants/STM32U3xx/U3B5V(G-I)TxQ_U3C5VITxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5V(G-I)TxQ_U3C5VITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U3B5VGTxQ.xml, STM32U3B5VITxQ.xml * STM32U3C5VITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5V(G-I)YxQ_U3C5VIYxQ/PeripheralPins.c b/variants/STM32U3xx/U3B5V(G-I)YxQ_U3C5VIYxQ/PeripheralPins.c index 4c28835579..565d691569 100644 --- a/variants/STM32U3xx/U3B5V(G-I)YxQ_U3C5VIYxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5V(G-I)YxQ_U3C5VIYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U3B5VGYxQ.xml, STM32U3B5VIYxQ.xml * STM32U3C5VIYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5W(G-I)YxQ_U3C5WIYxQ/PeripheralPins.c b/variants/STM32U3xx/U3B5W(G-I)YxQ_U3C5WIYxQ/PeripheralPins.c index 8b69ac1a25..c73feb1354 100644 --- a/variants/STM32U3xx/U3B5W(G-I)YxQ_U3C5WIYxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5W(G-I)YxQ_U3C5WIYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U3B5WGYxQ.xml, STM32U3B5WIYxQ.xml * STM32U3C5WIYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5Z(G-I)T_U3C5ZIT/PeripheralPins.c b/variants/STM32U3xx/U3B5Z(G-I)T_U3C5ZIT/PeripheralPins.c index 3124be7f3c..9e1b79c5de 100644 --- a/variants/STM32U3xx/U3B5Z(G-I)T_U3C5ZIT/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5Z(G-I)T_U3C5ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U3B5ZGTx.xml, STM32U3B5ZITx.xml * STM32U3C5ZITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U3B5Z(G-I)TxQ_U3C5ZITxQ/PeripheralPins.c b/variants/STM32U3xx/U3B5Z(G-I)TxQ_U3C5ZITxQ/PeripheralPins.c index 75470bc476..0c5e74a5dc 100644 --- a/variants/STM32U3xx/U3B5Z(G-I)TxQ_U3C5ZITxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U3B5Z(G-I)TxQ_U3C5ZITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U3B5ZGTxQ.xml, STM32U3B5ZITxQ.xml * STM32U3C5ZITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c b/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c index 05221a5ebf..2e75f6d05e 100644 --- a/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c +++ b/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U535CCTx.xml, STM32U535CCUx.xml * STM32U535CETx.xml, STM32U535CEUx.xml * STM32U545CETx.xml, STM32U545CEUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c b/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c index 44509104e1..b77ff419c5 100644 --- a/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U535CCTxQ.xml, STM32U535CCUxQ.xml * STM32U535CETxQ.xml, STM32U535CEUxQ.xml * STM32U545CETxQ.xml, STM32U545CEUxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c b/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c index b422401d8a..a5e45eb726 100644 --- a/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U535JEYxQ.xml, STM32U545JEYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c b/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c index d096ed9a87..fe9c534e21 100644 --- a/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535NCYxQ.xml, STM32U535NEYxQ.xml * STM32U545NEYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c index 5841857802..4da1fe7918 100644 --- a/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBIx.xml, STM32U535RCIx.xml * STM32U535REIx.xml, STM32U545REIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c index 3871e6b835..a8da1656ed 100644 --- a/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBIxQ.xml, STM32U535RCIxQ.xml * STM32U535REIxQ.xml, STM32U545REIxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c index dae1fb5a8d..b556b888ab 100644 --- a/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBTx.xml, STM32U535RCTx.xml * STM32U535RETx.xml, STM32U545RETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c index 8dfabc786f..0e893c1a1c 100644 --- a/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBTxQ.xml, STM32U535RCTxQ.xml * STM32U535RETxQ.xml, STM32U545RETxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c index 0d690e91dd..dac95f6963 100644 --- a/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCIx.xml, STM32U535VEIx.xml * STM32U545VEIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c index ee6fb0b27c..cce5393b99 100644 --- a/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCIxQ.xml, STM32U535VEIxQ.xml * STM32U545VEIxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c index 97e8cd3f69..fa0eed16cc 100644 --- a/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCTx.xml, STM32U535VETx.xml * STM32U545VETx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c index 3650dcd1e0..d45b2032e9 100644 --- a/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCTxQ.xml, STM32U535VETxQ.xml * STM32U545VETxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c b/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c index 34f58c31aa..65e408ed58 100644 --- a/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c +++ b/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575AGIx.xml, STM32U575AIIx.xml * STM32U585AIIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c b/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c index 66d5c05444..f289902849 100644 --- a/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575AGIxQ.xml, STM32U575AIIxQ.xml * STM32U585AIIxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c index f4c155acae..e99b841f70 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U575CGTx.xml, STM32U575CGUx.xml * STM32U575CITx.xml, STM32U575CIUx.xml * STM32U585CITx.xml, STM32U585CIUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c b/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c index e6517d22b3..6f569c979d 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U575CGTxQ.xml, STM32U575CGUxQ.xml * STM32U575CITxQ.xml, STM32U575CIUxQ.xml * STM32U585CITxQ.xml, STM32U585CIUxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c b/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c index 9457594078..8ddd74ded5 100644 --- a/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575OGYxQ.xml, STM32U575OIYxQ.xml * STM32U585OIYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c b/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c index b28a351b1e..9ef2329135 100644 --- a/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c +++ b/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575QGIx.xml, STM32U575QIIx.xml * STM32U585QIIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c b/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c index 396665cff3..40eb023faf 100644 --- a/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575QGIxQ.xml, STM32U575QIIxQ.xml * STM32U585QIIxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c b/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c index 3e9a24902c..d07602fed6 100644 --- a/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575RGTx.xml, STM32U575RITx.xml * STM32U585RITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c b/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c index 15b7558cb5..9b7f8fa435 100644 --- a/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575RGTxQ.xml, STM32U575RITxQ.xml * STM32U585RITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c b/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c index bd1286e4e1..558c845c4b 100644 --- a/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575VGTx.xml, STM32U575VITx.xml * STM32U585VITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c b/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c index b619b99162..4ed4ba5793 100644 --- a/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575VGTxQ.xml, STM32U575VITxQ.xml * STM32U585VITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c b/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c index 3d44c03b63..f101ce2a09 100644 --- a/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575ZGTx.xml, STM32U575ZITx.xml * STM32U585ZITx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c b/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c index 923255dc88..820a7ec68d 100644 --- a/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575ZGTxQ.xml, STM32U575ZITxQ.xml * STM32U585ZITxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c b/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c index e1a6e4ca7c..aab630ab3c 100644 --- a/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c +++ b/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595AIHx.xml, STM32U595AJHx.xml * STM32U5A5AJHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c b/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c index 7b36d47b91..b9fe4f72eb 100644 --- a/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595AIHxQ.xml, STM32U595AJHxQ.xml * STM32U5A5AJHxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c b/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c index 65300672f3..b96d5f2eb2 100644 --- a/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c +++ b/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595QIIx.xml, STM32U595QJIx.xml * STM32U5A5QJIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c index 191230d6a5..ce7ab2660a 100644 --- a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595QIIxQ.xml, STM32U595QJIxQ.xml * STM32U5A5QIIxQ.xml, STM32U5A5QJIxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c b/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c index de9fed219c..04fc36df6a 100644 --- a/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595RITx.xml, STM32U595RJTx.xml * STM32U5A5RJTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c index 00d907dd41..88bf873673 100644 --- a/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595RITxQ.xml, STM32U595RJTxQ.xml * STM32U5A5RJTxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c b/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c index 51e853827a..0e5d9b0d53 100644 --- a/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595VITx.xml, STM32U595VJTx.xml * STM32U599VJTx.xml, STM32U5A5VJTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c index 79ed2bac48..5f859089a4 100644 --- a/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U595VITxQ.xml, STM32U595VJTxQ.xml * STM32U599VITxQ.xml, STM32U599VJTxQ.xml * STM32U5A5VJTxQ.xml, STM32U5A9VJTxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c index d007388c5d..6d265a03b8 100644 --- a/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595ZITx.xml, STM32U595ZJTx.xml * STM32U5A5ZJTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c index 7e584c8731..88e8f3c098 100644 --- a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U595ZITxQ.xml, STM32U595ZJTxQ.xml * STM32U599ZITxQ.xml, STM32U599ZJTxQ.xml * STM32U5A5ZJTxQ.xml, STM32U5A9ZJTxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c index 8052d8db10..0324dd4d44 100644 --- a/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595ZIYxQ.xml, STM32U595ZJYxQ.xml * STM32U5A5ZJYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c b/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c index 4b460dc352..cc82ee5659 100644 --- a/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U599BJYxQ.xml, STM32U5A9BJYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c index 377a297e4e..7663ed060b 100644 --- a/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U599NIHxQ.xml, STM32U599NJHxQ.xml * STM32U5A9NJHxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c b/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c index 1273c83c7c..0a9332843d 100644 --- a/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U599ZIYxQ.xml, STM32U599ZJYxQ.xml * STM32U5A9ZJYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c b/variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c index ae8c4a942d..ee4b007d17 100644 --- a/variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c +++ b/variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F7VITx.xml, STM32U5F7VJTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c b/variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c index 78ffb20596..e56a6a678d 100644 --- a/variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F7VITxQ.xml, STM32U5F7VJTxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c index 1cdeac0287..ccd4b30deb 100644 --- a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9BJYxQ.xml, STM32U5G9BJYxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c index a7b90b433e..d416905e94 100644 --- a/variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9NJHxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c index 4a86e4448c..60c3fff00d 100644 --- a/variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9VITxQ.xml, STM32U5F9VJTxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c index 1c031f46ba..4132db038f 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9ZIJxQ.xml, STM32U5F9ZJJxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c index fc9a81acd9..0a5b2d54cf 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9ZITxQ.xml, STM32U5F9ZJTxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G7VJT/PeripheralPins.c b/variants/STM32U5xx/U5G7VJT/PeripheralPins.c index 1c28e86828..f3b0a35732 100644 --- a/variants/STM32U5xx/U5G7VJT/PeripheralPins.c +++ b/variants/STM32U5xx/U5G7VJT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G7VJTx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c index 561a9dcfb9..8828362d70 100644 --- a/variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G7VJTxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c index 5faf2286c5..e5d1d70489 100644 --- a/variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G9NJHxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c index f6ecadfafb..45d5d2bd03 100644 --- a/variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G9VJTxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c index 9b62dbdeef..50836ab776 100644 --- a/variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G9ZJJxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c index 2471bcb301..e7d15b082d 100644 --- a/variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G9ZJTxQ.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WB0x/WB05KZV_WB05TZF_WB09KEV_WB09TEF/PeripheralPins.c b/variants/STM32WB0x/WB05KZV_WB05TZF_WB09KEV_WB09TEF/PeripheralPins.c index 43eac26e5f..9f9838284c 100644 --- a/variants/STM32WB0x/WB05KZV_WB05TZF_WB09KEV_WB09TEF/PeripheralPins.c +++ b/variants/STM32WB0x/WB05KZV_WB05TZF_WB09KEV_WB09TEF/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WB05KZVx.xml, STM32WB05TZFx.xml * STM32WB09KEVx.xml, STM32WB09TEFx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WB0x/WB06CCF_WB07CCF/PeripheralPins.c b/variants/STM32WB0x/WB06CCF_WB07CCF/PeripheralPins.c index fd6ea0ef4c..1a0d3cc78d 100644 --- a/variants/STM32WB0x/WB06CCF_WB07CCF/PeripheralPins.c +++ b/variants/STM32WB0x/WB06CCF_WB07CCF/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB06CCFx.xml, STM32WB07CCFx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WB0x/WB06CCV_WB07CCV/PeripheralPins.c b/variants/STM32WB0x/WB06CCV_WB07CCV/PeripheralPins.c index 6444e369ce..0e16ce402b 100644 --- a/variants/STM32WB0x/WB06CCV_WB07CCV/PeripheralPins.c +++ b/variants/STM32WB0x/WB06CCV_WB07CCV/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB06CCVx.xml, STM32WB07CCVx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WB0x/WB06KCV_WB07KCV/PeripheralPins.c b/variants/STM32WB0x/WB06KCV_WB07KCV/PeripheralPins.c index f45900a723..990f37a5df 100644 --- a/variants/STM32WB0x/WB06KCV_WB07KCV/PeripheralPins.c +++ b/variants/STM32WB0x/WB06KCV_WB07KCV/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB06KCVx.xml, STM32WB07KCVx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA23CEU/PeripheralPins.c b/variants/STM32WBAxx/WBA23CEU/PeripheralPins.c index 55d9da2c5d..e9d69586a3 100644 --- a/variants/STM32WBAxx/WBA23CEU/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA23CEU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA23CEUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA23KEU/PeripheralPins.c b/variants/STM32WBAxx/WBA23KEU/PeripheralPins.c index 9ffc8426c5..c0dc798d25 100644 --- a/variants/STM32WBAxx/WBA23KEU/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA23KEU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA23KEUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA25CEU/PeripheralPins.c b/variants/STM32WBAxx/WBA25CEU/PeripheralPins.c index 3d5bf15bd6..545d8b5a07 100644 --- a/variants/STM32WBAxx/WBA25CEU/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA25CEU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA25CEUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA25HEF/PeripheralPins.c b/variants/STM32WBAxx/WBA25HEF/PeripheralPins.c index d1fa71f064..4dfeeeaac7 100644 --- a/variants/STM32WBAxx/WBA25HEF/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA25HEF/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA25HEFx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA50KGU/PeripheralPins.c b/variants/STM32WBAxx/WBA50KGU/PeripheralPins.c index f2a3b7ee96..a729c83449 100644 --- a/variants/STM32WBAxx/WBA50KGU/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA50KGU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA50KGUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U/PeripheralPins.c b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U/PeripheralPins.c index 7b65f2207a..474fc1c423 100644 --- a/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WBA52CEUx.xml, STM32WBA52CGUx.xml * STM32WBA54CEUx.xml, STM32WBA54CGUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c index 539001d8ef..88459d7d73 100644 --- a/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WBA52KEUx.xml, STM32WBA52KGUx.xml * STM32WBA54KEUx.xml, STM32WBA54KGUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c b/variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c index eff845e5a0..5b67eb05cf 100644 --- a/variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA55CEUx.xml, STM32WBA55CGUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA55H(E-G)F/PeripheralPins.c b/variants/STM32WBAxx/WBA55H(E-G)F/PeripheralPins.c index 1a4055ddac..0647ec56ed 100644 --- a/variants/STM32WBAxx/WBA55H(E-G)F/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA55H(E-G)F/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA55HEFx.xml, STM32WBA55HGFx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA55H(E-G)F/boards_entry.txt b/variants/STM32WBAxx/WBA55H(E-G)F/boards_entry.txt index 59fc8463d4..f745a7c759 100644 --- a/variants/STM32WBAxx/WBA55H(E-G)F/boards_entry.txt +++ b/variants/STM32WBAxx/WBA55H(E-G)F/boards_entry.txt @@ -10,7 +10,6 @@ GenWBA.menu.pnum.GENERIC_WBA55HEFX.upload.maximum_data_size=98304 GenWBA.menu.pnum.GENERIC_WBA55HEFX.build.board=GENERIC_WBA55HEFX GenWBA.menu.pnum.GENERIC_WBA55HEFX.build.product_line=STM32WBA55xx GenWBA.menu.pnum.GENERIC_WBA55HEFX.build.variant=STM32WBAxx/WBA55H(E-G)F -GenWBA.menu.pnum.GENERIC_WBA55HEFX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBAxx/STM32WBA55.svd # Generic WBA55HGFx GenWBA.menu.pnum.GENERIC_WBA55HGFX=Generic WBA55HGFx diff --git a/variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c b/variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c index 6f6a77b390..b0a8c65d7e 100644 --- a/variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA55UEIx.xml, STM32WBA55UGIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA5MMGH/PeripheralPins.c b/variants/STM32WBAxx/WBA5MMGH/PeripheralPins.c index 119b5d26ce..02622de9e0 100644 --- a/variants/STM32WBAxx/WBA5MMGH/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA5MMGH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA5MMGHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA62C(G-I)U_WBA64C(G-I)U/PeripheralPins.c b/variants/STM32WBAxx/WBA62C(G-I)U_WBA64C(G-I)U/PeripheralPins.c index 5f7fc8b1b5..eed13323f2 100644 --- a/variants/STM32WBAxx/WBA62C(G-I)U_WBA64C(G-I)U/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA62C(G-I)U_WBA64C(G-I)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WBA62CGUx.xml, STM32WBA62CIUx.xml * STM32WBA64CGUx.xml, STM32WBA64CIUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA62M(G-I)F_WBA65M(G-I)F/PeripheralPins.c b/variants/STM32WBAxx/WBA62M(G-I)F_WBA65M(G-I)F/PeripheralPins.c index 66d16bc7c4..94b9f90403 100644 --- a/variants/STM32WBAxx/WBA62M(G-I)F_WBA65M(G-I)F/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA62M(G-I)F_WBA65M(G-I)F/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WBA62MGFx.xml, STM32WBA62MIFx.xml * STM32WBA65MGFx.xml, STM32WBA65MIFx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA62P(G-I)I_WBA65P(G-I)I/PeripheralPins.c b/variants/STM32WBAxx/WBA62P(G-I)I_WBA65P(G-I)I/PeripheralPins.c index 356344ede8..6ecaa01814 100644 --- a/variants/STM32WBAxx/WBA62P(G-I)I_WBA65P(G-I)I/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA62P(G-I)I_WBA65P(G-I)I/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WBA62PGIx.xml, STM32WBA62PIIx.xml * STM32WBA65PGIx.xml, STM32WBA65PIIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA63C(G-I)U/PeripheralPins.c b/variants/STM32WBAxx/WBA63C(G-I)U/PeripheralPins.c index e491dbd4b8..72f8630a9c 100644 --- a/variants/STM32WBAxx/WBA63C(G-I)U/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA63C(G-I)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA63CGUx.xml, STM32WBA63CIUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA65C(G-I)U/PeripheralPins.c b/variants/STM32WBAxx/WBA65C(G-I)U/PeripheralPins.c index 822fde2938..a529cc6161 100644 --- a/variants/STM32WBAxx/WBA65C(G-I)U/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA65C(G-I)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA65CGUx.xml, STM32WBA65CIUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA65R(G-I)V/PeripheralPins.c b/variants/STM32WBAxx/WBA65R(G-I)V/PeripheralPins.c index 3b8aa61e04..851a2cc38a 100644 --- a/variants/STM32WBAxx/WBA65R(G-I)V/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA65R(G-I)V/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA65RGVx.xml, STM32WBA65RIVx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA6MOIH/PeripheralPins.c b/variants/STM32WBAxx/WBA6MOIH/PeripheralPins.c index 0cf8530fe4..0e3ad4abcf 100644 --- a/variants/STM32WBAxx/WBA6MOIH/PeripheralPins.c +++ b/variants/STM32WBAxx/WBA6MOIH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WBA6MOIHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB10CCU/PeripheralPins.c b/variants/STM32WBxx/WB10CCU/PeripheralPins.c index 7f760f9461..1d986ffa69 100644 --- a/variants/STM32WBxx/WB10CCU/PeripheralPins.c +++ b/variants/STM32WBxx/WB10CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB10CCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCU/PeripheralPins.c b/variants/STM32WBxx/WB15CCU/PeripheralPins.c index 295466441a..9f904cd53d 100644 --- a/variants/STM32WBxx/WB15CCU/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c b/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c index 21e852b710..bbe3fa7cef 100644 --- a/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCUxE.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCY/PeripheralPins.c b/variants/STM32WBxx/WB15CCY/PeripheralPins.c index 11e7c34bc5..a716049172 100644 --- a/variants/STM32WBxx/WB15CCY/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB1MMCH/PeripheralPins.c b/variants/STM32WBxx/WB1MMCH/PeripheralPins.c index 0222fa4d6b..924adecb5f 100644 --- a/variants/STM32WBxx/WB1MMCH/PeripheralPins.c +++ b/variants/STM32WBxx/WB1MMCH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB1MMCHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c index 3f7cd47f21..3dc0a8cbcc 100644 --- a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c +++ b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB30CEUxA.xml, STM32WB50CGUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c index 775acd1ea1..1d01b6c233 100644 --- a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c +++ b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WB35C(C-E)UxA.xml, STM32WB55CCUx.xml * STM32WB55CEUx.xml, STM32WB55CGUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c b/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c index 41f27b6894..511f1e618c 100644 --- a/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c +++ b/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WB55RCVx.xml, STM32WB55REVx.xml * STM32WB55RGVx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c index 259fff573c..e415bd7801 100644 --- a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c +++ b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WB55VEQx.xml, STM32WB55VEYx.xml * STM32WB55VGQx.xml, STM32WB55VGYx.xml * STM32WB55VYYx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB5MMGH/PeripheralPins.c b/variants/STM32WBxx/WB5MMGH/PeripheralPins.c index be3a3fe2be..0a6c144912 100644 --- a/variants/STM32WBxx/WB5MMGH/PeripheralPins.c +++ b/variants/STM32WBxx/WB5MMGH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB5MMGHx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WL3x/WL30K(8-B)V/PeripheralPins.c b/variants/STM32WL3x/WL30K(8-B)V/PeripheralPins.c index 9ee38edd5e..b61ddcbcd0 100644 --- a/variants/STM32WL3x/WL30K(8-B)V/PeripheralPins.c +++ b/variants/STM32WL3x/WL30K(8-B)V/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WL30K8Vx.xml, STM32WL30KBVx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WL3x/WL31C(8-B)V/PeripheralPins.c b/variants/STM32WL3x/WL31C(8-B)V/PeripheralPins.c index 41476e1dc4..5f11b50dfa 100644 --- a/variants/STM32WL3x/WL31C(8-B)V/PeripheralPins.c +++ b/variants/STM32WL3x/WL31C(8-B)V/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WL31C8Vx.xml, STM32WL31CBVx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X)/PeripheralPins.c b/variants/STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X)/PeripheralPins.c index d56c2b838e..e861079533 100644 --- a/variants/STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X)/PeripheralPins.c +++ b/variants/STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WL33K8Vx.xml, STM32WL33K8VxX.xml * STM32WL33KBVx.xml, STM32WL33KBVxX.xml * STM32WL33KCVx.xml, STM32WL33KCVxX.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/PeripheralPins.c b/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/PeripheralPins.c index 714972362d..05f53b8efc 100644 --- a/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/PeripheralPins.c +++ b/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32WL33C8Vx.xml, STM32WL33C8VxX.xml * STM32WL33CBVx.xml, STM32WL33CBVxX.xml * STM32WL33CCVx.xml, STM32WL33CCVxX.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WL3x/WL3RK(8-B)Vx(X)/PeripheralPins.c b/variants/STM32WL3x/WL3RK(8-B)Vx(X)/PeripheralPins.c index 4bc7bb6053..303c5a27f6 100644 --- a/variants/STM32WL3x/WL3RK(8-B)Vx(X)/PeripheralPins.c +++ b/variants/STM32WL3x/WL3RK(8-B)Vx(X)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WL3RK8Vx.xml, STM32WL3RK8VxX.xml * STM32WL3RKBVx.xml, STM32WL3RKBVxX.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c index 233d2633f4..c3fa69e2ca 100644 --- a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c +++ b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WLE4C8Ux.xml, STM32WLE4CBUx.xml * STM32WLE4CCUx.xml, STM32WLE5C8Ux.xml * STM32WLE5CBUx.xml, STM32WLE5CCUx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c b/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c index a95a8d0a77..297ea8899c 100644 --- a/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c +++ b/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WLE4J8Ix.xml, STM32WLE4JBIx.xml * STM32WLE4JCIx.xml, STM32WLE5J8Ix.xml * STM32WLE5JBIx.xml, STM32WLE5JCIx.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL5MOCHx(S)/PeripheralPins.c b/variants/STM32WLxx/WL5MOCHx(S)/PeripheralPins.c index a8e180aa3f..fff6ebbc7a 100644 --- a/variants/STM32WLxx/WL5MOCHx(S)/PeripheralPins.c +++ b/variants/STM32WLxx/WL5MOCHx(S)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WL5MOCHx.xml, STM32WL5MOCHxS.xml - * CubeMX DB release 6.0.170 + * CubeMX DB release 6.0.180 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" From 6c824022002a53770863b1afcea12a1438506c5e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jul 2026 09:30:13 +0200 Subject: [PATCH 2/2] chore(cmake): update database Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 24 ++++++-------- libraries/I3C/CMakeLists.txt | 1 + .../CMakeLists.txt | 1 + .../CMakeLists.txt | 31 +++++++++++++++++++ .../H543R(E-G)T_H553RGT/CMakeLists.txt | 31 +++++++++++++++++++ .../STM32H5xx/H543UGY_H553UGY/CMakeLists.txt | 31 +++++++++++++++++++ .../CMakeLists.txt | 31 +++++++++++++++++++ .../CMakeLists.txt | 31 +++++++++++++++++++ variants/STM32L4xx/L4P5R(G-E)T/CMakeLists.txt | 31 +++++++++++++++++++ variants/STM32L4xx/L4Q5RGT/CMakeLists.txt | 31 +++++++++++++++++++ .../CMakeLists.txt | 31 +++++++++++++++++++ .../CMakeLists.txt | 31 +++++++++++++++++++ .../U335C(B-C)YxQ_U345CCYxQ/CMakeLists.txt | 31 +++++++++++++++++++ .../U335K(B-C)U_U345KCU/CMakeLists.txt | 31 +++++++++++++++++++ .../U335K(B-C)YxQ_U345KCYxQ/CMakeLists.txt | 31 +++++++++++++++++++ .../U335R(B-C)I_U345RCI/CMakeLists.txt | 31 +++++++++++++++++++ .../U335R(B-C)IxQ_U345RCIxQ/CMakeLists.txt | 31 +++++++++++++++++++ .../U335R(B-C)T_U345RCT/CMakeLists.txt | 31 +++++++++++++++++++ .../U335R(B-C)TxQ_U345RCTxQ/CMakeLists.txt | 31 +++++++++++++++++++ .../CMakeLists.txt | 31 +++++++++++++++++++ .../CMakeLists.txt | 31 +++++++++++++++++++ .../U356C(C-E)YxQ_U366CEYxQ/CMakeLists.txt | 31 +++++++++++++++++++ .../U356K(C-E)U_U366KEU/CMakeLists.txt | 31 +++++++++++++++++++ .../U356R(C-E)I_U366REI/CMakeLists.txt | 31 +++++++++++++++++++ .../U356R(C-E)IxQ_U366REIxQ/CMakeLists.txt | 31 +++++++++++++++++++ .../U356R(C-E)T_U366RET/CMakeLists.txt | 31 +++++++++++++++++++ .../U356R(C-E)TxQ_U366RETxQ/CMakeLists.txt | 31 +++++++++++++++++++ .../U356R(C-E)YxQ_U366REYxQ/CMakeLists.txt | 31 +++++++++++++++++++ .../U356V(C-E)I_U366VEI/CMakeLists.txt | 31 +++++++++++++++++++ .../U356V(C-E)IxQ_U366VEIxQ/CMakeLists.txt | 31 +++++++++++++++++++ .../U356V(C-E)T_U366VET/CMakeLists.txt | 31 +++++++++++++++++++ .../U356V(C-E)TxQ_U366VETxQ/CMakeLists.txt | 31 +++++++++++++++++++ 32 files changed, 910 insertions(+), 15 deletions(-) create mode 100644 variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/CMakeLists.txt create mode 100644 variants/STM32H5xx/H543R(E-G)T_H553RGT/CMakeLists.txt create mode 100644 variants/STM32H5xx/H543UGY_H553UGY/CMakeLists.txt create mode 100644 variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/CMakeLists.txt create mode 100644 variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/CMakeLists.txt create mode 100644 variants/STM32L4xx/L4P5R(G-E)T/CMakeLists.txt create mode 100644 variants/STM32L4xx/L4Q5RGT/CMakeLists.txt create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/CMakeLists.txt create mode 100644 variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/CMakeLists.txt create mode 100644 variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/CMakeLists.txt create mode 100644 variants/STM32U3xx/U335K(B-C)U_U345KCU/CMakeLists.txt create mode 100644 variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/CMakeLists.txt create mode 100644 variants/STM32U3xx/U335R(B-C)I_U345RCI/CMakeLists.txt create mode 100644 variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/CMakeLists.txt create mode 100644 variants/STM32U3xx/U335R(B-C)T_U345RCT/CMakeLists.txt create mode 100644 variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356K(C-E)U_U366KEU/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356R(C-E)I_U366REI/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356R(C-E)T_U366RET/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356V(C-E)I_U366VEI/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356V(C-E)T_U366VET/CMakeLists.txt create mode 100644 variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/CMakeLists.txt diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 2887ddf4e6..0d2f341044 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -101413,16 +101413,12 @@ set(HERON_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575O(G- set(HERON_MAXSIZE 2097152) set(HERON_MAXDATASIZE 786432) set(HERON_MCU cortex-m33) -set(HERON_FPU_CONF "fpv5-sp-d16") -set(HERON_FPU_ABI "hard") -set(HERON_FPCONF "${HERON_FPU_CONF}-${HERON_FPU_ABI}") -set(HERON_PID 0x0004) +set(HERON_FPCONF "fpv5-sp-d16-hard") add_library(HERON INTERFACE) target_compile_options(HERON INTERFACE "SHELL:-DSTM32U575xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" - "SHELL:" - "SHELL:-mfpu=${HERON_FPU_CONF} -mfloat-abi=${HERON_FPU_ABI}" + "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${HERON_MCU} ) target_compile_definitions(HERON INTERFACE @@ -101444,15 +101440,14 @@ target_include_directories(HERON INTERFACE target_link_options(HERON INTERFACE "LINKER:--default-script=${HERON_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" - "LINKER:--defsym=LD_MAX_SIZE=${HERON_MAXSIZE}" - "LINKER:--defsym=LD_MAX_DATA_SIZE=${HERON_MAXDATASIZE}" - "SHELL:-mfpu=${HERON_FPU_CONF} -mfloat-abi=${HERON_FPU_ABI}" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=786432" + "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${HERON_MCU} ) add_library(HERON_serial_disabled INTERFACE) target_compile_options(HERON_serial_disabled INTERFACE - "SHELL:" ) add_library(HERON_serial_generic INTERFACE) target_compile_options(HERON_serial_generic INTERFACE @@ -101464,23 +101459,21 @@ target_compile_options(HERON_serial_none INTERFACE ) add_library(HERON_usb_CDC INTERFACE) target_compile_options(HERON_usb_CDC INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0x30A4 -DUSBD_PID=${HERON_PID} -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" + "SHELL:-DUSBCON -DUSBD_VID=0x30A4 -DUSBD_PID=0x0004 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" ) add_library(HERON_usb_CDCgen INTERFACE) target_compile_options(HERON_usb_CDCgen INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0x30A4 -DUSBD_PID=${HERON_PID} -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" + "SHELL:-DUSBCON -DUSBD_VID=0x30A4 -DUSBD_PID=0x0004 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" ) add_library(HERON_usb_HID INTERFACE) target_compile_options(HERON_usb_HID INTERFACE - "SHELL:-DUSBCON -DUSBD_VID=0x30A4 -DUSBD_PID=${HERON_PID} -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" + "SHELL:-DUSBCON -DUSBD_VID=0x30A4 -DUSBD_PID=0x0004 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" ) add_library(HERON_usb_none INTERFACE) target_compile_options(HERON_usb_none INTERFACE - "SHELL:" ) add_library(HERON_xusb_FS INTERFACE) target_compile_options(HERON_xusb_FS INTERFACE - "SHELL:" ) add_library(HERON_xusb_HS INTERFACE) target_compile_options(HERON_xusb_HS INTERFACE @@ -104285,6 +104278,7 @@ set(NUCLEO_F746ZG_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_F746ZG INTERFACE) target_compile_options(NUCLEO_F746ZG INTERFACE "SHELL:-DSTM32F746xx" + "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F746ZG_MCU} ) diff --git a/libraries/I3C/CMakeLists.txt b/libraries/I3C/CMakeLists.txt index 5a1abeb768..49ed8dbc59 100644 --- a/libraries/I3C/CMakeLists.txt +++ b/libraries/I3C/CMakeLists.txt @@ -28,3 +28,4 @@ target_link_libraries(I3C INTERFACE I3C_bin $ ) + diff --git a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/CMakeLists.txt b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/CMakeLists.txt index c40bd132e0..a0fc49797e 100644 --- a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/CMakeLists.txt +++ b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/CMakeLists.txt @@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c PeripheralPins_ETHERCAT_DUINO.c + PeripheralPins_F7x6ZG.c variant_ETHERCAT_DUINO.cpp variant_generic.cpp variant_NUCLEO_F7x6ZG.cpp diff --git a/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/CMakeLists.txt b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H543C(E-G)(T-U)_H553CG(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H543R(E-G)T_H553RGT/CMakeLists.txt b/variants/STM32H5xx/H543R(E-G)T_H553RGT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H543R(E-G)T_H553RGT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H543UGY_H553UGY/CMakeLists.txt b/variants/STM32H5xx/H543UGY_H553UGY/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H543UGY_H553UGY/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/CMakeLists.txt b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H543V(E-G)(I-T-Z)_H553VG(I-T-Z)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/CMakeLists.txt b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H543Z(E-G)(J-T-Z)_H553ZG(J-T-Z)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32L4xx/L4P5R(G-E)T/CMakeLists.txt b/variants/STM32L4xx/L4P5R(G-E)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32L4xx/L4P5R(G-E)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32L4xx/L4Q5RGT/CMakeLists.txt b/variants/STM32L4xx/L4Q5RGT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32L4xx/L4Q5RGT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/CMakeLists.txt b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)_U345CC(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/CMakeLists.txt b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)(T-U)xQ_U345CC(T-U)xQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/CMakeLists.txt b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U335C(B-C)YxQ_U345CCYxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U335K(B-C)U_U345KCU/CMakeLists.txt b/variants/STM32U3xx/U335K(B-C)U_U345KCU/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)U_U345KCU/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/CMakeLists.txt b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U335K(B-C)YxQ_U345KCYxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U335R(B-C)I_U345RCI/CMakeLists.txt b/variants/STM32U3xx/U335R(B-C)I_U345RCI/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)I_U345RCI/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/CMakeLists.txt b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)IxQ_U345RCIxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U335R(B-C)T_U345RCT/CMakeLists.txt b/variants/STM32U3xx/U335R(B-C)T_U345RCT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)T_U345RCT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/CMakeLists.txt b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U335R(B-C)TxQ_U345RCTxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/CMakeLists.txt b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)_U366CE(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/CMakeLists.txt b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)(T-U)xQ_U366CE(T-U)xQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/CMakeLists.txt b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356C(C-E)YxQ_U366CEYxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356K(C-E)U_U366KEU/CMakeLists.txt b/variants/STM32U3xx/U356K(C-E)U_U366KEU/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356K(C-E)U_U366KEU/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356R(C-E)I_U366REI/CMakeLists.txt b/variants/STM32U3xx/U356R(C-E)I_U366REI/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)I_U366REI/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/CMakeLists.txt b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)IxQ_U366REIxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356R(C-E)T_U366RET/CMakeLists.txt b/variants/STM32U3xx/U356R(C-E)T_U366RET/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)T_U366RET/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/CMakeLists.txt b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)TxQ_U366RETxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/CMakeLists.txt b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356R(C-E)YxQ_U366REYxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356V(C-E)I_U366VEI/CMakeLists.txt b/variants/STM32U3xx/U356V(C-E)I_U366VEI/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)I_U366VEI/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/CMakeLists.txt b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)IxQ_U366VEIxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356V(C-E)T_U366VET/CMakeLists.txt b/variants/STM32U3xx/U356V(C-E)T_U366VET/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)T_U366VET/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/CMakeLists.txt b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32U3xx/U356V(C-E)TxQ_U366VETxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) +