Wire.begin() and USB peripheral clock conflict

[zfields]

This simple sketch reveals a bug in the Cygnet:

#include <Wire.h>

void setup() {
  pinMode(LED_BUILTIN, OUTPUT);

  for (int i = 0; i < 5; i++) {
    digitalWrite(LED_BUILTIN, HIGH);
    delay(500);
    digitalWrite(LED_BUILTIN, LOW);
    delay(500);
  }

  Wire.begin();
}

void loop() {
  digitalWrite(LED_BUILTIN, HIGH);
  delay(1000);
  digitalWrite(LED_BUILTIN, LOW);
  delay(1000);
}

Describe the bug
The sketch will indefinitely hang at Wire.begin(); until the USB is plugged in. If the USB is plugged in at the beginning of the sketch, the whole sketch will run without interruption.

To Reproduce

Flash the sketch above using SWD when the device is powered by battery, and the Cygnet will blink 5 times quickly, but never transition to the slower blinks.

Plug in the USB and it will continue to the slower blinks.

Expected behavior
Continuous Blinking

Desktop (please complete the following information):

• OS: Linux
• Arduino IDE version: 2.3.8
• STM32 core version: 2.12.0
• Tools menu settings if not the default: n/a
• Upload method: SWD

Board (please complete the following information):

• Name: Blues Cygnet
• Hardware Revision: 1.2
• Extra hardware used if any: n/a

Additional context

I've tested several modifications to the initialization routines, and I was able to narrow it down to the following change in the WEAK void SystemClock_Config(void) function:

From (reproducing):

  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB;
  PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
    Error_Handler();
  }

To (no repro):

  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
    Error_Handler();
  }

When I stepped through the debugger, this is the exact place it hangs in the code:

twi.c:

#if defined(I2C3_BASE)
  if (i2c == I2C3) {
#if defined(RCC_PERIPHCLK_I2C3) || defined(RCC_PERIPHCLK_I2C35)
#ifdef RCC_PERIPHCLK_I2C3
    clkSrcFreq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2C3);
#else
    clkSrcFreq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2C35);
#endif
    if (clkSrcFreq == 0)
#endif
    {
#if defined(__HAL_RCC_GET_I2C3_SOURCE)
      switch (__HAL_RCC_GET_I2C3_SOURCE()) {
#ifdef RCC_I2C3CLKSOURCE_HSI
        case RCC_I2C3CLKSOURCE_HSI:
          clkSrcFreq = HSI_VALUE;
          break;
#endif
#ifdef RCC_I2C3CLKSOURCE_SYSCLK
        case RCC_I2C3CLKSOURCE_SYSCLK:
          clkSrcFreq = SystemCoreClock;
          break;
#endif
#if defined(RCC_I2C3CLKSOURCE_PCLK1) || defined(RCC_I2C3CLKSOURCE_D2PCLK1)
#ifdef RCC_I2C3CLKSOURCE_PCLK1
        case RCC_I2C3CLKSOURCE_PCLK1:
#endif
#ifdef RCC_I2C3CLKSOURCE_D2PCLK1
        case RCC_I2C3CLKSOURCE_D2PCLK1:
#endif
          clkSrcFreq = HAL_RCC_GetPCLK1Freq();
          break;
#endif
#ifdef RCC_I2C3CLKSOURCE_CSI
        case RCC_I2C3CLKSOURCE_CSI:
          clkSrcFreq = CSI_VALUE;
          break;
#endif
#ifdef RCC_I2C3CLKSOURCE_PLL3
        case RCC_I2C3CLKSOURCE_PLL3:
          HAL_RCCEx_GetPLL3ClockFreq(&PLL3_Clocks);
          clkSrcFreq = PLL3_Clocks.PLL3_R_Frequency;
          break;
#endif
        default:
          Error_Handler();
      }
#else
      /* STM32 G0 I2C3 has no independent clock */
      clkSrcFreq = HAL_RCC_GetPCLK1Freq();
#endif
    }
  }
#endif // I2C3_BASE

I don't understand the relationship between the USB and the I2C peripherals.

[fpistm]

Hi @zfields
Quickl look at the clock config, it seems something is not correct:

Arduino_Core_STM32/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.cpp

Line 152 in 734f525

PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_MSI;

STM32L433CC has no SDMMC.

Else I saw nothing which can explain this as you simplu set the USB clock source. Is USB enabled in the menu?

[fpistm]

Going deeper, it seems even if STM32L433CC have no SDMM1C, I wonder why there is no build error.
In fact even if no SDMM1C it is defined in the CMSIS device header and so available in the RCC_PeriphCLKInitTypeDef

#if defined(SDMMC1)

uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */

#endif /* SDMMC1 */

But in that case it is initialised by the HAL_RCCEx_PeriphCLKConfig which probably doing weird things.

[zfields]

Is USB enabled in the menu?

Yes. I have tried it both enabled and disabled. It reproduces only when USB is enabled.

STM32L433CC has no SDMM1C,

Yes, I noticed the SDMMC1 mistake and removed it during one of my iterations. It made no difference.

---

Here are the functions I was testing when I provided the bug report...

WEAK void initVariant(void)
{
  /* All pins set to high-Z (floating) initially */
  /* DS11449 Rev 8, Section 3.9.5 - Reset Mode: */
  /* In order to improve the consumption under reset, the I/Os state under and after reset is
   * “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
   * deactivated when the reset source is internal.
   */

  /* Turn on the 3V3 regulator */
  __HAL_RCC_GPIOH_CLK_ENABLE();
  GPIO_InitTypeDef  GPIO_InitStruct;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1;
  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); /* PH0 is ENABLE_3V3, PH1 is DISCHARGE_3V3 */
  HAL_GPIO_WritePin(GPIOH, GPIO_InitStruct.Pin, GPIO_PIN_SET); /* Enable 3V3 regulator and disable discharging */
}

/**
  * @brief  System Clock Configuration
  * @param  None
  * @retval None
  */
WEAK void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {};

  /** Enable PWR peripheral clock
  *
  * RM0394 §5.1.2: PWR registers are on APB1. PWREN (RCC_APB1ENR1 bit 28)
  * resets to 1, so this is defensive rather than strictly necessary, but
  * required for correctness if PWREN has been cleared by prior code.
  * CubeMX generates this unconditionally for all STM32L4 projects.
  */
  __HAL_RCC_PWR_CLK_ENABLE();

  /** Configure the main internal regulator output voltage
  */
  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
    Error_Handler();
  }

  /** Configure LSE Drive Capability
  *
  * Use MEDIUMLOW (not LOW): RCC_LSEDRIVE_LOW risks marginal LSE startup
  * on units near the crystal ESR tolerance limit and degrades MSI PLL mode
  * (MSIPLLEN) lock quality. ST recommends MEDIUMLOW as the minimum when
  * MSIPLLEN is in use.
  *
  * Backup domain access must be enabled before configuring LSE or selecting
  * the RTC clock source, as those registers (RCC->BDCR) are write-protected
  * after reset and silently ignore writes until the lock is cleared.
  */
  HAL_PWR_EnableBkUpAccess();
  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW);

  /** Enable MSI Auto calibration
  *
  * Set MSIPLLEN before calling HAL_RCC_OscConfig(). Hardware protection
  * prevents MSIPLLEN from taking effect until LSERDY=1, so setting it here
  * is safe. When HAL_RCC_OscConfig() enables LSE and LSERDY asserts, MSIPLL
  * mode activates automatically: MSI briefly deasserts MSIRDY while it
  * re-locks to LSE, then reasserts it. This transient happens inside the
  * remaining execution of HAL_RCC_OscConfig(), so by the time that function
  * returns, MSIRDY is already stable — no separate wait needed.
  */
  HAL_RCCEx_EnableMSIPLLMode();

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE
                                     | RCC_OSCILLATORTYPE_MSI
                                     | RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
  /* HSI is not used as SYSCLK source, PLL input, or USB/MSIPLLEN reference.
   * Disabling it saves ~200-300 µA. The HAL will reject this if HSI is
   * currently driving SYSCLK or the PLL, providing a safe guard. */
  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
  /* Blocks until LSERDY is set. Once LSERDY asserts, MSIPLL activates and
   * MSI re-locks. MSIRDY is stable again before this function returns. */
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
  // RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
    Error_Handler();
  }

  /** Initializes the Peripheral clocks
  *
  * RCC_CCIPR.CLK48SEL (USB clock source) lives in the VDD domain and is
  * safe to write unconditionally regardless of VBUS state. USB will be
  * correctly configured whether present at boot or hot-plugged later.
  */
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB;
  PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
    Error_Handler();
  }

  /** Ensure that MSI is wake-up system clock
  */
  HAL_RCCEx_WakeUpStopCLKConfig(RCC_STOP_WAKEUPCLOCK_MSI);
#pragma message("Compiled using local Arduino_Core_STM32: 2.13.0-dev.")
}

[zfields]

I tested the Nucleo L432KC, and referenced its clock configuration; it appears to map well to the Cygnet.

Based on the Nucleo config, here is a working config for the Cygnet.

WEAK void initVariant(void)
{
  /* All pins set to high-Z (floating) initially */
  /* DS11449 Rev 8, Section 3.9.5 - Reset Mode: */
  /* In order to improve the consumption under reset, the I/Os state under and after reset is
   * “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
   * deactivated when the reset source is internal.
   */

  /* Turn on the 3V3 regulator */
  __HAL_RCC_GPIOH_CLK_ENABLE();
  GPIO_InitTypeDef  GPIO_InitStruct;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1;
  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); /* PH0 is ENABLE_3V3, PH1 is DISCHARGE_3V3 */
  HAL_GPIO_WritePin(GPIOH, GPIO_InitStruct.Pin, GPIO_PIN_SET); /* Enable 3V3 regulator and disable discharging */
}

/**
  * @brief  System Clock Configuration
  * @param  None
  * @retval None
  */
WEAK void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {};

  /** Enable PWR peripheral clock
  *
  * RM0394 §5.1.2: PWR registers are on APB1. PWREN (RCC_APB1ENR1 bit 28)
  * resets to 1, so this is defensive rather than strictly necessary, but
  * required for correctness if PWREN has been cleared by prior code.
  * CubeMX generates this unconditionally for all STM32L4 projects.
  */
  __HAL_RCC_PWR_CLK_ENABLE();

  /** Configure the main internal regulator output voltage
  */
  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
    Error_Handler();
  }

  /** Configure LSE Drive Capability
  *
  * Use MEDIUMLOW (not LOW): RCC_LSEDRIVE_LOW risks marginal LSE startup
  * on units near the crystal ESR tolerance limit and degrades MSI PLL mode
  * (MSIPLLEN) lock quality. ST recommends MEDIUMLOW as the minimum when
  * MSIPLLEN is in use.
  *
  * Backup domain access must be enabled before configuring LSE or selecting
  * the RTC clock source, as those registers (RCC->BDCR) are write-protected
  * after reset and silently ignore writes until the lock is cleared.
  */
  HAL_PWR_EnableBkUpAccess();
  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW);

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  *
  * EXPERIMENT: Mirror the Nucleo L432KC clock architecture to test whether
  * its immunity to the USB-init-without-VBUS hang stems from:
  *   (a) SYSCLK derived from PLL (not MSI), so SysTick / HAL_GetTick() are
  *       immune to any MSIPLLEN-induced MSIRDY transient, and
  *   (b) USB clock sourced from PLLSAI1 (independent PLL), so the HAL
  *       waits for PLLSAI1RDY — which it can do reliably because SysTick
  *       is PLL-based — rather than handing the USB peripheral a live MSI
  *       clock immediately via a plain register write.
  *
  * Key differences from the previous Cygnet config:
  *   - MSI: MSIRANGE_11 (48 MHz) → MSIRANGE_6 (4 MHz) — used as PLL input
  *   - HSI: remains OFF — nothing in this config uses it
  *   - PLL: NONE → ON  (MSI 4 MHz × PLLN=40 / PLLR=2 → SYSCLK = 80 MHz)
  *   - SYSCLK: MSI (48 MHz) → PLLCLK (80 MHz)
  *   - USB clock: removed from PeriphCLKConfig (MSI) → PLLSAI1 (48 MHz)
  *   - HAL_RCCEx_EnableMSIPLLMode(): moved to AFTER PeriphCLKConfig,
  *     exactly as the Nucleo does — MSIRDY transient can no longer stall
  *     SysTick because SYSCLK = PLL, not MSI.
  *   - FLASH_LATENCY: 2 → 4  (required for 80 MHz / VOS1 per RM0394 §3.3)
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE
                                     | RCC_OSCILLATORTYPE_MSI;
  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
  /* HSI is not used as SYSCLK source, PLL/PLLSAI1 input, or any peripheral
   * clock reference. Disabling it saves ~200-300 µA. */
  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
  /* MSIRANGE_6 = 4 MHz — same as Nucleo. Low-frequency reference fed into
   * the main PLL (×40/÷2 = 80 MHz) and PLLSAI1 (×24/÷2 = 48 MHz). */
  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
  RCC_OscInitStruct.PLL.PLLM = 1;
  RCC_OscInitStruct.PLL.PLLN = 40;
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;  /* 4 × 40 / 2 = 80 MHz */
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  *
  * SYSCLK = PLLCLK (80 MHz). SysTick and HAL_GetTick() are now driven by
  * the PLL output, completely decoupled from MSI. Any subsequent MSIRDY
  * transient (from HAL_RCCEx_EnableMSIPLLMode below) cannot stall SysTick.
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  /* FLASH_LATENCY_4: required for HCLK > 64 MHz at VOS1 (RM0394 §3.3.3) */
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
    Error_Handler();
  }

  /** Initializes the Peripheral clocks
  *
  * USB clock: PLLSAI1 (MSI 4 MHz × PLLSAI1N=24 / PLLSAI1Q=2 = 48 MHz).
  * This mirrors the Nucleo L432KC exactly. RCCEx_PLLSAI1_Config() waits
  * for PLLSAI1RDY using HAL_GetTick(). Because SYSCLK is now PLL-based,
  * HAL_GetTick() is immune to MSI transients — the wait is reliable.
  * PLLSAI1 and the main PLL share the same source (MSI) and M divider (1),
  * which the HAL enforces; both are configured consistently here.
  *
  * HAL_RCCEx_PeriphCLKConfig writes CLK48SEL first (pointing at PLLSAI1
  * before it is running), then enables PLLSAI1 and waits for its RDY flag.
  * During that brief window the USB peripheral has no 48 MHz clock and
  * stays quiescent — avoiding the race where a live MSI clock is handed
  * to USB before the peripheral is ready to handle the absence of VBUS.
  */
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC;
  PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
  PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
  PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
  PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
  PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
  PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;  /* 4 × 24 / 2 = 48 MHz */
  PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
  PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
    Error_Handler();
  }

  /** Enable MSI Auto calibration
  *
  * Called AFTER PeriphCLKConfig, matching the Nucleo's ordering exactly.
  * MSIPLLEN causes MSI to transiently lose MSIRDY while it re-locks to
  * LSE — but SYSCLK is now PLLCLK (80 MHz), so SysTick is unaffected.
  * The transient cannot stall HAL_GetTick() or deadlock any timeout loop.
  */
  HAL_RCCEx_EnableMSIPLLMode();

  /** Ensure that MSI is wake-up system clock
  *
  * After STOP mode, the PLL is not automatically re-enabled. MSI is used
  * as the initial wake-up clock; firmware must re-lock the PLL manually
  * if 80 MHz is required after wake. This is the same behaviour as any
  * PLL-based design on STM32L4.
  */
  HAL_RCCEx_WakeUpStopCLKConfig(RCC_STOP_WAKEUPCLOCK_MSI);
#pragma message("Compiled using local Arduino_Core_STM32: 2.13.0-dev.")
}

[zfields]

AI Summary

What changed

	Old config	New config
SYSCLK source	MSI (48 MHz, MSIRANGE_11)	PLL (80 MHz, MSI 4 MHz × 40 / 2)
USB clock (CLK48SEL)	MSI — already running when written	PLLSAI1 (48 MHz) — not yet running when written
EnableMSIPLLMode position	After PeriphCLKConfig	After PeriphCLKConfig (same, but now safe for a different reason)
Flash latency	2	4 (required for >64 MHz / VOS1)

───

Why the old config failed

The root cause is two problems that compound each other.

Problem 1 — live USB clock on battery power.

When PeriphCLKConfig ran with RCC_USBCLKSOURCE_MSI, it wrote CLK48SEL while MSI was already running at 48 MHz. The USB peripheral immediately received a valid clock and started its hardware state machine. On battery power with no VBUS, this put the USB peripheral into an error state that corrupted subsequent initialization.

Problem 2 — SYSCLK=MSI makes HAL_GetTick() unreliable during EnableMSIPLLMode.

When EnableMSIPLLMode() was called, it set MSIPLLEN, causing MSI to briefly deassert MSIRDY while re-locking to LSE. Because SYSCLK was also MSI, SysTick stalled during the transient. Any HAL timeout loop running during or just after that window could deadlock. The watchdog eventually fired, and after a reset or two the I2C peripheral was left in a corrupted state that caused Wire.begin() to hang permanently.

NOTE: I ran an HSI48 experiment that confirmed switching the USB clock source didn't help — the SYSCLK=MSI problem persisted regardless of which 48 MHz source was selected.

───

Why the new config works

Fix 1 — PLLSAI1 for USB.

RCCEx_PLLSAI1_Config (called inside PeriphCLKConfig) writes CLK48SEL to point at PLLSAI1 before enabling it. During that brief window the USB peripheral has no clock and stays quiescent. There is no race with VBUS state.

Fix 2 — SYSCLK=PLL decouples SysTick from MSI.

The main PLL (80 MHz) provides SYSCLK. SysTick and HAL_GetTick() are completely isolated from any MSI transient. When EnableMSIPLLMode() sets MSIPLLEN after PeriphCLKConfig, the MSIRDY re-lock transient is harmless — SysTick never stalls, no timeout loop can deadlock.

Fix 3 — ordering protects the PLLSAI1 MSIRDY guard.

RCCEx_PLLSAI1_Config explicitly checks if(MSIRDY == 0) return HAL_ERROR before enabling PLLSAI1. Calling EnableMSIPLLMode() after PeriphCLKConfig ensures PLLSAI1 is fully configured before the MSIRDY transient can occur.

[zfields]

The AI summary was generated after several iterations of testing with an AI side-kick; I cannot speak to it's accuracy.

@fpistm, I am happy to test any curiosities you may have, in case you suspect a different root cause than the machine has offered.

[fpistm]

See nothing related in the errata sheet.
Maybe something linked to VddUSB.
Looking at the reference manual, found this but MSI seems usable as direct source.

When configured in PLL-mode, the MSI automatically calibrates itself thanks to the LSE.
This mode is available for all MSI frequency ranges. At 48 MHz, the MSI in PLL-mode can
be used for the USB FS device, saving the need of an external high-speed crystal.

Guess point 1 is valid but not an expert.