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WORKAROUND: arm64: dts: qcom: monaco-evk: enable ethernet on the QPS615 switch
Enable the 10GbE and 2.5GbE ethernet ports of the QPS615 PCIE switch. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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&eeprom1 {
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nvmem-layout {
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mac_addr1: mac-addr@0 {
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reg = <0x0 0x6>;
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};
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mac_addr2: mac-addr@6 {
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reg = <0x6 0x6>;
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};
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};
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};
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&pcieport0 {
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pcie@0,0 {
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pcie@3,0 {
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pci@0,0 {
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nvmem-cells = <&mac_addr1>;
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nvmem-cell-names = "mac-address";
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pinctrl-names = "default";
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pinctrl-0 = <&aqr_intn_wol_sig>;
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phy-rst-som-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
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interrupts-extended = <&tlmm 40 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "wol_irq";
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qcom,always-on-supply;
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qcom,phy-rst-delay-us = <221000>;
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qcom,iommu-group = <&eth0_pci_iommu_group>;
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eth0_pci_iommu_group: eth0_pci_iommu_group {
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qcom,iommu-dma = "atomic";
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};
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};
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pci@0,1 {
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nvmem-cells = <&mac_addr2>;
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nvmem-cell-names = "mac-address";
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pinctrl-names = "default";
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pinctrl-0 = <&napa_intn_wol_sig>;
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phy-rst-som-gpios = <&expander5 0 GPIO_ACTIVE_HIGH>;
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interrupts-extended = <&tlmm 39 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "wol_irq";
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qcom,always-on-supply;
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qcom,phy-rst-delay-us = <20000>;
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qcom,iommu-group = <&eth1_pci_iommu_group>;
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eth1_pci_iommu_group: eth1_pci_iommu_group {
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qcom,iommu-dma = "atomic";
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};
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};
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};
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};
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};
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&tlmm {
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qps615_intn_wol {
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aqr_intn_wol_sig: aqr-intn-wol-sig {
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pins = "gpio40";
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function = "gpio";
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input-enable;
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bias-disable;
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};
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napa_intn_wol_sig: napa-intn-wol-sig {
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pins = "gpio39";
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function = "gpio";
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input-enable;
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bias-disable;
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};
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};
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};

arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso

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output-high;
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};
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};
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#include "monaco-evk-ifp-mezzanine-qps615.dtsi"

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