From f7a558e8f0a158981223f0531587e5d9b1d7dee5 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:15:32 +0530 Subject: [PATCH 01/21] QCLINUX: revert "dt-bindings: crypto: qcom,ice: Require power-domain and iface clk" This reverts commit ee496ca417bc706043f5ab1aeec7ab8681d16385. Signed-off-by: Abhinaba Rakshit --- .../bindings/crypto/qcom,inline-crypto-engine.yaml | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index 1078de779c16e..061ff718b23d6 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -29,20 +29,12 @@ properties: maxItems: 1 clocks: - maxItems: 2 - - clock-names: - maxItems: 2 - - power-domains: maxItems: 1 required: - compatible - reg - clocks - - clock-names - - power-domains additionalProperties: false @@ -54,10 +46,6 @@ examples: compatible = "qcom,sm8550-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x01d88000 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; ... From cea5cfb5c16524004f60350de37de02b41d108e9 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:25:49 +0530 Subject: [PATCH 02/21] QCLINUX: revert "arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node" This reverts commit 6675f5595d7b963f5c41503f77518bb8501c4992. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/lemans.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 4473aa8bd5f43..808827b83553d 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2758,11 +2758,7 @@ compatible = "qcom,sa8775p-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; cryptobam: dma-controller@1dc4000 { From 0f0e5523b384c279ee375cb18e084936c47de948 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:26:58 +0530 Subject: [PATCH 03/21] QCLINUX: revert "arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node" This reverts commit 4622e9a502a5df34252112e3a8b687fb46f7bd27. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index d4e05f9acdb5d..0366a05f83176 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2725,11 +2725,7 @@ compatible = "qcom,qcs8300-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc GCC_UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; crypto: crypto@1dfa000 { From 08fad310e47eefffe224bb1a70fb3931064eda3a Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:27:54 +0530 Subject: [PATCH 04/21] QCLINUX: revert "arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node" This reverts commit 1434fd89cc2ed123641f449e9dbaa028ba79c3e4. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 74eb895cf4da7..45b9864e3304b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1605,11 +1605,7 @@ compatible = "qcom,sc7180-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d90000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; ipa: ipa@1e40000 { From 8520848dee030d58e68305545f8ec7fc79e8b686 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:28:41 +0530 Subject: [PATCH 05/21] QCLINUX: revert "arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node" This reverts commit a1310e6297b5e40e9e8e3fc99512fa607ad9a764. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 6bdc932021229..7ee7e787d3c8c 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2588,11 +2588,7 @@ compatible = "qcom,sc7280-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc GCC_UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; cryptobam: dma-controller@1dc4000 { From 8fb8176971d27bbae490c1b859f502773849b9e4 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:30:27 +0530 Subject: [PATCH 06/21] QCLINUX: revert "arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node" This reverts commit e86738a3345b16d7383edf2ea980f5bfc9779a57. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 3d243e757fa1a..920a2d1c04d0c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5374,11 +5374,7 @@ compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; cryptobam: dma-controller@1dc4000 { From 5014acdc2ed4708a089e94f8ce7a943b033e6681 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:31:01 +0530 Subject: [PATCH 07/21] QCLINUX: revert "arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node" This reverts commit e670e835c548d3a1d5e1ebf2b30bd16314a1e548. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index b6c8c76429ba9..e3f93f4f412de 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2449,11 +2449,7 @@ "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; tcsr_mutex: hwlock@1f40000 { From fbe9152ba39c9416bd099e6fb33257d52d1dde8d Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:31:29 +0530 Subject: [PATCH 08/21] QCLINUX: revert "arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node" This reverts commit 4e48c910cc9100f1de2860c11ac9a1db4ea30376. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index c32a817efdb47..357e43b907405 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4081,11 +4081,7 @@ "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; cryptobam: dma-controller@1dc4000 { From 4650e26f3613df1d9358bdbdd56f25c40df8149f Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:33:38 +0530 Subject: [PATCH 09/21] QCLINUX: revert "arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node" This reverts commit a207c39dbba7250e613cc8b8886292d59332a478. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index e870bdf2528c2..f56b1f889b857 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2083,11 +2083,7 @@ "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc GCC_UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; cryptobam: dma-controller@1dc4000 { From cab76452130ffee97202f30aac11a72b13ad6587 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:34:39 +0530 Subject: [PATCH 10/21] QCLINUX: revert "soc: qcom: ice: Add explicit power-domain and clock voting calls for ICE" This reverts commit 725a9c8705f2171bd0f08d3f12276acb9321e83e. Signed-off-by: Abhinaba Rakshit --- drivers/soc/qcom/ice.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index 4b50d05ca02a3..b203bc685cadd 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,8 +16,6 @@ #include #include #include -#include -#include #include @@ -110,7 +108,6 @@ struct qcom_ice { void __iomem *base; struct clk *core_clk; - struct clk *iface_clk; bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; @@ -313,20 +310,12 @@ int qcom_ice_resume(struct qcom_ice *ice) struct device *dev = ice->dev; int err; - pm_runtime_get_sync(dev); err = clk_prepare_enable(ice->core_clk); if (err) { dev_err(dev, "failed to enable core clock (%d)\n", err); return err; } - - err = clk_prepare_enable(ice->iface_clk); - if (err) { - dev_err(dev, "failed to enable iface clock (%d)\n", - err); - return err; - } qcom_ice_hwkm_init(ice); return qcom_ice_wait_bist_status(ice); } @@ -334,9 +323,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume); int qcom_ice_suspend(struct qcom_ice *ice) { - clk_disable_unprepare(ice->iface_clk); clk_disable_unprepare(ice->core_clk); - pm_runtime_put_sync(ice->dev); ice->hwkm_init_complete = false; return 0; @@ -597,10 +584,6 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, if (IS_ERR(engine->core_clk)) return ERR_CAST(engine->core_clk); - engine->iface_clk = devm_clk_get_enabled(dev, "iface_clk"); - if (IS_ERR(engine->iface_clk)) - return ERR_CAST(engine->iface_clk); - if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); @@ -742,9 +725,6 @@ static int qcom_ice_probe(struct platform_device *pdev) return PTR_ERR(base); } - devm_pm_runtime_enable(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); - engine = qcom_ice_create(&pdev->dev, base); if (IS_ERR(engine)) return PTR_ERR(engine); From 69d8e87fd14aa002de5b23595ff671bff2b695b1 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 00:46:58 +0530 Subject: [PATCH 11/21] FROMLIST: dt-bindings: crypto: qcom,ice: Fix missing power-domain and iface clk The DT bindings for inline-crypto engine do not specify the UFS_PHY_GDSC power-domain and iface clock. Without enabling the iface clock and the associated power-domain the ICE hardware cannot function correctly and leads to unclocked hardware accesses being observed during probe. Fix the DT bindings for inline-crypto engine to require the UFS_PHY_GDSC power-domain and iface clock for new devices (Eliza and Milos) introduced in the current release (7.0) with yet-to-stabilize ABI, while preserving backward compatibility for older devices. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-1-e36044bbdfe9@oss.qualcomm.com/ Fixes: 618195a7ac3df ("dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE") Fixes: 85faec1e85555 ("dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE") Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- .../crypto/qcom,inline-crypto-engine.yaml | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index 061ff718b23d6..45c39be16e96d 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -29,6 +29,16 @@ properties: maxItems: 1 clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: core + - const: iface + + power-domains: maxItems: 1 required: @@ -38,6 +48,25 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-inline-crypto-engine + - qcom,milos-inline-crypto-engine + + then: + required: + - power-domains + - clock-names + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + examples: - | #include @@ -46,6 +75,10 @@ examples: compatible = "qcom,sm8550-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x01d88000 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; ... From 4d6d4a7c30381c37eaee8832af1566ce5c387820 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:00:33 +0530 Subject: [PATCH 12/21] FROMLIST: soc: qcom: ice: Allow explicit votes on 'iface' clock for ICE Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver de-coupled from the QCOM UFS driver, it explicitly votes for its required clocks during probe. For scenarios where the 'clk_ignore_unused' flag is not passed on the kernel command line, to avoid potential unclocked ICE hardware register access during probe the ICE driver should additionally vote on the 'iface' clock. Also update the suspend and resume callbacks to handle un-voting and voting on the 'iface' clock. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-2-e36044bbdfe9@oss.qualcomm.com/ Fixes: 2afbf43a4aec6 ("soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver") Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- drivers/soc/qcom/ice.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index b203bc685cadd..bf4ab2d9e5c03 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -108,6 +108,7 @@ struct qcom_ice { void __iomem *base; struct clk *core_clk; + struct clk *iface_clk; bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; @@ -312,8 +313,13 @@ int qcom_ice_resume(struct qcom_ice *ice) err = clk_prepare_enable(ice->core_clk); if (err) { - dev_err(dev, "failed to enable core clock (%d)\n", - err); + dev_err(dev, "Failed to enable core clock: %d\n", err); + return err; + } + + err = clk_prepare_enable(ice->iface_clk); + if (err) { + dev_err(dev, "Failed to enable iface clock: %d\n", err); return err; } qcom_ice_hwkm_init(ice); @@ -323,6 +329,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume); int qcom_ice_suspend(struct qcom_ice *ice) { + clk_disable_unprepare(ice->iface_clk); clk_disable_unprepare(ice->core_clk); ice->hwkm_init_complete = false; @@ -579,11 +586,17 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk"); if (!engine->core_clk) engine->core_clk = devm_clk_get_optional_enabled(dev, "ice"); + if (!engine->core_clk) + engine->core_clk = devm_clk_get_optional_enabled(dev, "core"); if (!engine->core_clk) engine->core_clk = devm_clk_get_enabled(dev, NULL); if (IS_ERR(engine->core_clk)) return ERR_CAST(engine->core_clk); + engine->iface_clk = devm_clk_get_optional_enabled(dev, "iface"); + if (IS_ERR(engine->iface_clk)) + return ERR_CAST(engine->iface_clk); + if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); From 14577746635a0663559724fedd3f1ef411fc0551 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:06:44 +0530 Subject: [PATCH 13/21] FROMLIST: arm64: dts: qcom: kaanapali: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kaanapali. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-3-e36044bbdfe9@oss.qualcomm.com/ Fixes: 2eeb5767d53f4 ("arm64: dts: qcom: Introduce Kaanapali SoC") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 9ef57ad0ca71d..52af56e091689 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -868,7 +868,11 @@ "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From c377d0f5be5f2939c8d35f0abcba6ddfd845329b Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:08:24 +0530 Subject: [PATCH 14/21] FROMLIST: arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for lemans. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-4-e36044bbdfe9@oss.qualcomm.com/ Fixes: 96272ba7103d4 ("arm64: dts: qcom: sa8775p: enable the inline crypto engine") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/lemans.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 808827b83553d..6b8c81ceddee5 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2758,7 +2758,11 @@ compatible = "qcom,sa8775p-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From af215af7608c4052344fe8a3a635433a0eaee2fa Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:09:30 +0530 Subject: [PATCH 15/21] FROMLIST: arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for monaco. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-5-e36044bbdfe9@oss.qualcomm.com/ Fixes: cc9d29aad876d ("arm64: dts: qcom: qcs8300: enable the inline crypto engine") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 0366a05f83176..0339ba653a09e 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2725,7 +2725,11 @@ compatible = "qcom,qcs8300-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; crypto: crypto@1dfa000 { From 28b09aa08c1a06ade1afa520de9b38e1a7555b7f Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:10:51 +0530 Subject: [PATCH 16/21] FROMLIST: arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sc7180. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-6-e36044bbdfe9@oss.qualcomm.com/ Fixes: 858536d9dc946 ("arm64: dts: qcom: sc7180: Add UFS nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 45b9864e3304b..d6e01aca4c5a1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1605,7 +1605,11 @@ compatible = "qcom,sc7180-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d90000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; ipa: ipa@1e40000 { From 6a849b41f46fce2336647e3acb9453cbb6ec2363 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:12:08 +0530 Subject: [PATCH 17/21] FROMLIST: arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kodiak. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-7-e36044bbdfe9@oss.qualcomm.com/ Fixes: dfd5ee7b34bb7 ("arm64: dts: qcom: sc7280: Add inline crypto engine") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 7ee7e787d3c8c..e48af314a9487 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2588,7 +2588,11 @@ compatible = "qcom,sc7280-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From d8d7b00a63666c3656d57b2c7f63998352229640 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:14:52 +0530 Subject: [PATCH 18/21] FROMLIST: arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8450. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-8-e36044bbdfe9@oss.qualcomm.com/ Fixes: 86b0aef435851 ("arm64: dts: qcom: sm8450: Use standalone ICE node for UFS") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 920a2d1c04d0c..d763f7205641b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5374,7 +5374,11 @@ compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 9bf79b456f7493887eb250b7e9a053cd901ecbce Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:15:46 +0530 Subject: [PATCH 19/21] FROMLIST: arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8550. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-9-e36044bbdfe9@oss.qualcomm.com/ Fixes: b8630c48b43fc ("arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index e3f93f4f412de..473fb47480361 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2449,7 +2449,11 @@ "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From e4125cbf00ebd5b996b13ecf897f0c6ffabf1566 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:17:12 +0530 Subject: [PATCH 20/21] FROMLIST: arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8650. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-10-e36044bbdfe9@oss.qualcomm.com/ Fixes: 10e0246712951 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 357e43b907405..d211bd94fb413 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4081,7 +4081,11 @@ "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From f3f53c07cdd90749a91e99692480a1812b2a10a2 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:18:33 +0530 Subject: [PATCH 21/21] FROMLIST: arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8750. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-11-e36044bbdfe9@oss.qualcomm.com/ Fixes: b1dac789c650a ("arm64: dts: qcom: sm8750: Add ICE nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index f56b1f889b857..8c33bc3620ef0 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2083,7 +2083,11 @@ "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 {