diff --git a/backends/webgpu/test/ops/test_quantized_linear.py b/backends/webgpu/test/ops/test_quantized_linear.py index b1a033502b3..14fef6be33c 100644 --- a/backends/webgpu/test/ops/test_quantized_linear.py +++ b/backends/webgpu/test/ops/test_quantized_linear.py @@ -63,6 +63,13 @@ class Q4gswConfig: # (e.g. lvp); else shmem (K>=4096 or N>=2048) or register-tiled (SwiftShader # caps at 128). Same fp64 golden regardless of which kernel runs. Q4gswConfig("steel", 96, 2048, 256), # steel-isolating (K<4096, N<2048) + # Same shape as "steel"; the .pte is dtype-independent, so this fixture feeds + # the f16-multiply steel kernel in a -DWGPU_BACKEND_STEEL_F16 build (goldened + # at a looser f16 tol in the native test). The default f32 build ignores it. + Q4gswConfig("steel_f16", 96, 2048, 256), # f16-multiply steel (opt-in build) + # Partial M and N steel tiles under the f16 kernel; exercises f16 boundary + # masking (the exact-N "steel_f16" shape does not). N%8==0, steel-isolating. + Q4gswConfig("steel_f16_edge", 70, 1024, 136), # f16 partial-tile (opt-in) Q4gswConfig("gate_proj_pf", 128, 2048, 8192), # gate/up prefill (shmem via N) Q4gswConfig("down_proj_pf", 128, 8192, 2048), # down prefill (shmem via K) Q4gswConfig("shmem_edge", 130, 4096, 2056), # partial 32-tile bounds diff --git a/backends/webgpu/test/test_webgpu_native.cpp b/backends/webgpu/test/test_webgpu_native.cpp index dea4f26ff20..1e8034d0e1e 100644 --- a/backends/webgpu/test/test_webgpu_native.cpp +++ b/backends/webgpu/test/test_webgpu_native.cpp @@ -277,6 +277,14 @@ const Q4gswConfig kQ4gswConfigs[] = { // general-N robustness). // M>1: steel GEMM on a >=256-invocation device (K%16==0), else shmem/tiled. {"steel", 96, 2048, 256, 1e-4f, 1e-3f, true, false}, // steel-isolating +#ifdef WGPU_BACKEND_STEEL_F16 + // Same shape as "steel" run under the f16-multiply steel kernel; the f16 + // rounding floor (~2.3e-4, uniform in K -- not an accumulate bug) needs a + // looser abs gate than the strict f32 1e-4. Opt-in build only. + {"steel_f16", 96, 2048, 256, 2.3e-4f, 1e-3f, true, false}, + // Partial M and N steel tiles under the f16 kernel (f16 boundary masking). + {"steel_f16_edge", 70, 1024, 136, 2.3e-4f, 1e-3f, true, false}, +#endif {"gate_proj_pf", 128, 2048, 8192, 1e-4f, 1e-3f, true, false}, // shmem via N {"down_proj_pf", 128, 8192, 2048, 1e-3f, 1e-2f, true, false}, // shmem via K {"shmem_edge", 130, 4096, 2056, 1e-4f, 1e-3f, true, false}, // partial tiles