From 40f1e7a86ac43fb34bb3bd23e4f5cd378c4ab349 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Sun, 10 May 2026 18:21:13 +0000 Subject: [PATCH 01/23] Update dynarec_arm64_00.c --- src/dynarec/arm64/dynarec_arm64_00.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/dynarec/arm64/dynarec_arm64_00.c b/src/dynarec/arm64/dynarec_arm64_00.c index 200cf20c65..c94094dda5 100644 --- a/src/dynarec/arm64/dynarec_arm64_00.c +++ b/src/dynarec/arm64/dynarec_arm64_00.c @@ -950,7 +950,26 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin break; case 0x62: nextop = F8; - if(rex.is32bits && !MODREG) { + if(!rex.is32bits) { + vex_t vex = {0}; + u8 = F8; + u16 = F8; + if(FillVEXFromEVEX(&vex, rex, nextop, u8, u16)) { + INST_NAME("EVEX"); + addr = dynarec64_AVX(dyn, addr, ip, ninst, vex, ok, need_epilog); + } else { + INST_NAME("Illegal 62"); + if(BOX64DRENV(dynarec_safeflags)>1) { + READFLAGS(X_PEND); + } else { + SETFLAGS(X_ALL, SF_SET_NODF); // Hack to set flags in "don't care" state + } + GETIP(ip); + UDF(0); + *need_epilog = 1; + *ok = 0; + } + } else if(!MODREG) { INST_NAME("BOUND Gd, Ed"); addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0); LDRxw_U12(x2, wback, 0); From bbeaf5b21b639f0aaecf5e9930934d8fa0808ce1 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Sun, 10 May 2026 18:21:58 +0000 Subject: [PATCH 02/23] Update dynarec_arm64_avx.c --- src/dynarec/arm64/dynarec_arm64_avx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/dynarec/arm64/dynarec_arm64_avx.c b/src/dynarec/arm64/dynarec_arm64_avx.c index 5f0eda17ed..7d97b7a9ef 100644 --- a/src/dynarec/arm64/dynarec_arm64_avx.c +++ b/src/dynarec/arm64/dynarec_arm64_avx.c @@ -71,7 +71,8 @@ uintptr_t dynarec64_AVX(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ni if((*ok==-1) && (BOX64ENV(dynarec_log)>=LOG_INFO || dyn->need_dump || BOX64ENV(dynarec_missing))) if(!dyn->size || BOX64ENV(dynarec_log)>LOG_INFO || dyn->need_dump) { - dynarec_log(LOG_NONE, " Dynarec unimplemented VEX opcode size %d prefix %s map %s opcode %02X\n", 128< Date: Sun, 10 May 2026 18:23:43 +0000 Subject: [PATCH 03/23] Update x64run_private.h --- src/emu/x64run_private.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/src/emu/x64run_private.h b/src/emu/x64run_private.h index 46bc052494..bc920b6ec5 100644 --- a/src/emu/x64run_private.h +++ b/src/emu/x64run_private.h @@ -42,8 +42,43 @@ typedef struct vex_s { uint16_t p:2; //0: none, 1: 0x66, 2:0xF3, 3: 0xF2 uint16_t v:4; // src register uint16_t m:5; // opcode map + uint16_t evex:1; // was decoded from an EVEX prefix } vex_t; +static inline int FillVEXFromEVEX(vex_t* vex, rex_t rex, uint8_t p0, uint8_t p1, uint8_t p2) +{ + uint8_t m = p0 & 0x0f; + uint8_t l = (p2 >> 5) & 0x03; + + if(rex.is32bits || rex.is66 || rex.isf0 || rex.rep) + return 0; + if(!(p1 & 0x04)) // EVEX P1 bit 2 is reserved and must be 1 + return 0; + if(m != VEX_M_0F && m != VEX_M_0F38 && m != VEX_M_0F3A) + return 0; + if(l > 1) // no ZMM state yet + return 0; + if(!(p0 & 0x10)) // no high-16 destination register state yet + return 0; + if(!(p2 & 0x08)) // no high-16 NDS/VIDX register state yet + return 0; + if(p2 & 0x97) // z, b and aaa need opmask/broadcast/SAE handling + return 0; + + *vex = (vex_t){0}; + vex->rex = rex; + vex->rex.b = (p0 & 0x20) ? 0 : 1; + vex->rex.x = (p0 & 0x40) ? 0 : 1; + vex->rex.r = (p0 & 0x80) ? 0 : 1; + vex->rex.w = (p1 >> 7) & 1; + vex->p = p1 & 0x03; + vex->l = l; + vex->v = ((~p1) >> 3) & 0x0f; + vex->m = m; + vex->evex = 1; + return 1; +} + // the op code definition can be found here: http://ref.x86asm.net/geek32.html reg64_t* GetECommon(x64emu_t* emu, uintptr_t* addr, rex_t rex, uint8_t m, uint8_t delta); From 563912f1500432d37a949ef78c275f308d671c6d Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Sun, 10 May 2026 18:24:32 +0000 Subject: [PATCH 04/23] Update x64run.c --- src/emu/x64run.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/src/emu/x64run.c b/src/emu/x64run.c index da8b6ae149..f32e0ab5d1 100644 --- a/src/emu/x64run.c +++ b/src/emu/x64run.c @@ -504,9 +504,29 @@ int Run(x64emu_t *emu, int step) goto fini; } break; - case 0x62: /* BOUND Gd, Ed */ + case 0x62: /* EVEX prefix / BOUND Gd, Ed */ nextop = F8; - if(rex.is32bits && !MODREG) { + if(!rex.is32bits) { + vex_t vex = {0}; + tmp8u = F8; + tmp8u2 = F8; + if(!FillVEXFromEVEX(&vex, rex, nextop, tmp8u, tmp8u2)) { + unimp = 1; + goto fini; + } + #ifdef TEST_INTERPRETER + if(!(addr = TestAVX(test, vex, addr, &step))) + unimp = 1; + #else + if(!(addr = RunAVX(emu, vex, addr, &step))) { + unimp = 1; + goto fini; + } + if(step==2) { + STEP2; + } + #endif + } else if(!MODREG) { GETGD; int* bounds = (int*)GETEA(0); if((GD->sdword[0]sdword[0]>bounds[1])) From 11565707d439fea2a3ea35a768215471307982f2 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Sun, 10 May 2026 18:25:17 +0000 Subject: [PATCH 05/23] Update x64runavx.c --- src/emu/x64runavx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/emu/x64runavx.c b/src/emu/x64runavx.c index 6a39e5a960..ac0f8638e4 100644 --- a/src/emu/x64runavx.c +++ b/src/emu/x64runavx.c @@ -106,7 +106,8 @@ uintptr_t RunAVX(x64emu_t *emu, vex_t vex, uintptr_t addr, int *step) else addr = 0; if(!addr) - printf_log(LOG_INFO, "Unimplemented AVX opcode size %d prefix %s map %s opcode %02X ", 128< Date: Tue, 12 May 2026 15:45:23 +0000 Subject: [PATCH 06/23] Update dynarec_arm64_avx.c --- src/dynarec/arm64/dynarec_arm64_avx.c | 46 +++++++++++++++------------ 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/src/dynarec/arm64/dynarec_arm64_avx.c b/src/dynarec/arm64/dynarec_arm64_avx.c index 7d97b7a9ef..18de7fd727 100644 --- a/src/dynarec/arm64/dynarec_arm64_avx.c +++ b/src/dynarec/arm64/dynarec_arm64_avx.c @@ -40,34 +40,38 @@ static const char* avx_map_string(uint16_t m) } } +typedef uintptr_t (*dynarec64_avx_f)(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog); + uintptr_t dynarec64_AVX(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog) { (void)ip; (void)need_epilog; uint8_t opcode = PK(0); rex_t rex = vex.rex; + static const dynarec64_avx_f avx_dispatch[4][4] = { + [VEX_M_0F] = { + [VEX_P_NONE] = dynarec64_AVX_0F, + [VEX_P_66] = dynarec64_AVX_66_0F, + [VEX_P_F3] = dynarec64_AVX_F3_0F, + [VEX_P_F2] = dynarec64_AVX_F2_0F, + }, + [VEX_M_0F38] = { + [VEX_P_NONE] = dynarec64_AVX_0F38, + [VEX_P_66] = dynarec64_AVX_66_0F38, + [VEX_P_F3] = dynarec64_AVX_F3_0F38, + [VEX_P_F2] = dynarec64_AVX_F2_0F38, + }, + [VEX_M_0F3A] = { + [VEX_P_66] = dynarec64_AVX_66_0F3A, + [VEX_P_F2] = dynarec64_AVX_F2_0F3A, + }, + }; - if( (vex.m==VEX_M_0F) && (vex.p==VEX_P_NONE)) - addr = dynarec64_AVX_0F(dyn, addr, ip, ninst, vex, ok, need_epilog); - else if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_NONE)) - addr = dynarec64_AVX_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog); - else if( (vex.m==VEX_M_0F) && (vex.p==VEX_P_66)) - addr = dynarec64_AVX_66_0F(dyn, addr, ip, ninst, vex, ok, need_epilog); - else if( (vex.m==VEX_M_0F) && (vex.p==VEX_P_F2)) - addr = dynarec64_AVX_F2_0F(dyn, addr, ip, ninst, vex, ok, need_epilog); - else if( (vex.m==VEX_M_0F) && (vex.p==VEX_P_F3)) - addr = dynarec64_AVX_F3_0F(dyn, addr, ip, ninst, vex, ok, need_epilog); - else if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_66)) - addr = dynarec64_AVX_66_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog); - else if( (vex.m==VEX_M_0F3A) && (vex.p==VEX_P_66)) - addr = dynarec64_AVX_66_0F3A(dyn, addr, ip, ninst, vex, ok, need_epilog); - else if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_F2)) - addr = dynarec64_AVX_F2_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog); - else if( (vex.m==VEX_M_0F3A) && (vex.p==VEX_P_F2)) - addr = dynarec64_AVX_F2_0F3A(dyn, addr, ip, ninst, vex, ok, need_epilog); - else if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_F3)) - addr = dynarec64_AVX_F3_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog); - else {DEFAULT;} + if(vex.m < 4 && vex.p < 4 && avx_dispatch[vex.m][vex.p]) + addr = avx_dispatch[vex.m][vex.p](dyn, addr, ip, ninst, vex, ok, need_epilog); + else { + DEFAULT; + } if((*ok==-1) && (BOX64ENV(dynarec_log)>=LOG_INFO || dyn->need_dump || BOX64ENV(dynarec_missing))) if(!dyn->size || BOX64ENV(dynarec_log)>LOG_INFO || dyn->need_dump) { From 7a50b8a7bdf855efba809d89a35ef6d0b70804ca Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Tue, 12 May 2026 15:46:19 +0000 Subject: [PATCH 07/23] Update dynarec_arm64_functions.c --- src/dynarec/arm64/dynarec_arm64_functions.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/src/dynarec/arm64/dynarec_arm64_functions.c b/src/dynarec/arm64/dynarec_arm64_functions.c index cd76f88a48..b0177a4867 100644 --- a/src/dynarec/arm64/dynarec_arm64_functions.c +++ b/src/dynarec/arm64/dynarec_arm64_functions.c @@ -448,13 +448,12 @@ int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst) { if((dyn->insts[i2].x64.barrier&BARRIER_FLOAT)) // if the barrier as already been apply, no transform needed return ((dyn->insts[ninst].x64.barrier&BARRIER_FLOAT))?0:(isCacheEmpty(dyn, ninst)?0:1); - int ret = 0; if(!i2) { // just purge if(dyn->insts[ninst].n.stack_next) return 1; if(dyn->insts[ninst].ymm0_out) return 1; - for(int i=0; i<32 && !ret; ++i) + for(int i=0; i<32; ++i) if(dyn->insts[ninst].n.neoncache[i].v) { // there is something at ninst for i int t = dyn->insts[ninst].n.neoncache[i].t; int n = dyn->insts[ninst].n.neoncache[i].n; @@ -463,15 +462,15 @@ int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst) { || t==NEON_CACHE_ST_D || t==NEON_CACHE_ST_I64) && ninsts[ninst].n.stack_pop)) - ret = 1; + return 1; } - return ret; + return 0; } // Check if ninst can be compatible to i2 if(dyn->insts[ninst].n.stack_next != dyn->insts[i2].n.stack-dyn->insts[i2].n.stack_push) { return 1; } - if(dyn->insts[ninst].ymm0_out && (dyn->insts[ninst].ymm0_out&~dyn->insts[i2].ymm0_in)) + if(dyn->insts[ninst].ymm0_out && (dyn->insts[ninst].ymm0_out&~dyn->insts[i2].ymm0_in&~dyn->insts[i2].n.ymm_unneeded)) return 1; neoncache_t cache_i2 = dyn->insts[i2].n; neoncacheUnwind(&cache_i2); @@ -484,22 +483,22 @@ int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst) { if(((t==NEON_CACHE_XMMR) || (t==NEON_CACHE_XMMW)) && (cache_i2.xmm_unneeded&(1<insts[ninst].n.neoncache[i].v!=cache_i2.neoncache[i].v) { // there is something different if(n!=cache_i2.neoncache[i].n) { // not the same x64 reg - ret = 1; + return 1; } else if((t == NEON_CACHE_XMMR) && cache_i2.neoncache[i].t == NEON_CACHE_XMMW) {/* nothing */ } else if((t == NEON_CACHE_YMMR) && cache_i2.neoncache[i].t == NEON_CACHE_YMMW) {/* nothing */ } else - ret = 1; + return 1; } } else if(cache_i2.neoncache[i].v) - ret = 1; + return 1; } - return ret; + return 0; } void neoncacheUnwind(neoncache_t* cache) @@ -1588,4 +1587,4 @@ void addSSEPreload(dynarec_arm_t* dyn, int ninst, int i2, uint32_t preload) dyn->insts[i2].preload_from = ninst; dyn->insts[i2].n.xmm_unneeded |= preload&0xffff; dyn->insts[i2].n.ymm_unneeded |= ymm_mask; -} \ No newline at end of file +} From 6c1a89558d0780bc02e209cf1e0c8cbcf661aed0 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Tue, 12 May 2026 15:47:10 +0000 Subject: [PATCH 08/23] Update dynarec_arm64_helper.c --- src/dynarec/arm64/dynarec_arm64_helper.c | 62 ++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 5 deletions(-) diff --git a/src/dynarec/arm64/dynarec_arm64_helper.c b/src/dynarec/arm64/dynarec_arm64_helper.c index 5ddd7e623d..7bb1f41d21 100644 --- a/src/dynarec/arm64/dynarec_arm64_helper.c +++ b/src/dynarec/arm64/dynarec_arm64_helper.c @@ -1886,6 +1886,55 @@ static int findCacheSlot(dynarec_arm_t* dyn, int ninst, int t, int n, neoncache_ return -1; } +static void buildCacheMasks(neoncache_t* cache, uint8_t* st, uint8_t* mm, uint16_t* xmm, uint16_t* ymm) +{ + *st = *mm = 0; + *xmm = *ymm = 0; + for(int i=0; i<32; ++i) { + if(!cache->neoncache[i].v) + continue; + int n = cache->neoncache[i].n; + switch(cache->neoncache[i].t) { + case NEON_CACHE_ST_F: + case NEON_CACHE_ST_D: + case NEON_CACHE_ST_I64: + *st |= 1<insts[i2].n; neoncacheUnwind(&cache_i2); + uint8_t cache_i2_st, cache_i2_mm; + uint16_t cache_i2_xmm, cache_i2_ymm; + buildCacheMasks(&cache_i2, &cache_i2_st, &cache_i2_mm, &cache_i2_xmm, &cache_i2_ymm); if(!cache_i2.stack) { int purge = 0; // default to purge if there is any regs that are not needed at jump @@ -2143,22 +2195,22 @@ static void fpuCacheTransform(dynarec_arm_t* dyn, int ninst, int s1, int s2, int // check SSE first, than MMX, in order, to optimize successive memory write for(int i=0; i<16; ++i) { int j=findCacheSlot(dyn, ninst, NEON_CACHE_XMMW, i, &cache); - if(j>=0 && findCacheSlot(dyn, ninst, NEON_CACHE_XMMW, i, &cache_i2)==-1) + if(j>=0 && !(cache_i2_xmm&(1<=0 && findCacheSlot(dyn, ninst, NEON_CACHE_YMMW, i, &cache_i2)==-1) + if(j>=0 && !(cache_i2_ymm&(1<=0 && findCacheSlot(dyn, ninst, NEON_CACHE_MM, i, &cache_i2)==-1) + if(j>=0 && !(cache_i2_mm&(1< Date: Tue, 12 May 2026 15:48:57 +0000 Subject: [PATCH 09/23] Update dynarec_native_functions.c From 51c9034c85a4b05cf04147abb3a351bcd2b60351 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Tue, 12 May 2026 15:49:57 +0000 Subject: [PATCH 10/23] Update x64runavx.c From 52a7cf44ee1b19f42da4fd56f385bd21a7fe0932 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 11:01:39 +0000 Subject: [PATCH 11/23] Update dynarec_arm64_arch.c --- src/dynarec/arm64/dynarec_arm64_arch.c | 98 +++++++++++++------------- 1 file changed, 50 insertions(+), 48 deletions(-) diff --git a/src/dynarec/arm64/dynarec_arm64_arch.c b/src/dynarec/arm64/dynarec_arm64_arch.c index ff3faf3aae..54641e52cc 100644 --- a/src/dynarec/arm64/dynarec_arm64_arch.c +++ b/src/dynarec/arm64/dynarec_arm64_arch.c @@ -103,59 +103,61 @@ static int arch_build(dynarec_arm_t* dyn, int ninst, arch_build_t* arch, int noa arch->unaligned = dyn->insts[ninst].unaligned; if(!noarch) { // got through all naoncache to gather regs assignments - int idx; - for(int i=0; i<32; ++i) - if(dyn->insts[ninst].n.neoncache[i].v) - switch(dyn->insts[ninst].n.neoncache[i].t) { - case NEON_CACHE_XMMW: - arch->sse = 1; - arch->sse_.sse |= 1<insts[ninst].n.neoncache[i].n; - break; - case NEON_CACHE_MM: - arch->mmx = 1; - arch->mmx_.mmx |= 1<insts[ninst].n.neoncache[i].n; - break; - case NEON_CACHE_YMMW: - arch->ymm = 1; - arch->ymm_.ymm |= 1<insts[ninst].n.neoncache[i].n; - idx = i; - if(idx>=EMM0 && idx<=EMM0+8) - idx-=EMM0; - else - idx-=SCRATCH0-8; - arch->ymm_.ymm_pos |= idx<<(dyn->insts[ninst].n.neoncache[i].n*4); - break; - case NEON_CACHE_ST_D: - arch->x87 = 1; - arch->x87_.x87 |= 1<insts[ninst].n.neoncache[i].n; - arch->x87_.x87_pos = (i-EMM0)<<(dyn->insts[ninst].n.neoncache[i].n*4); - arch->x87_.x87_type = (X87_ST_D)<<(dyn->insts[ninst].n.neoncache[i].n*2); - break; - case NEON_CACHE_ST_F: - arch->x87 = 1; - arch->x87_.x87 |= 1<insts[ninst].n.neoncache[i].n; - arch->x87_.x87_pos = (i-EMM0)<<(dyn->insts[ninst].n.neoncache[i].n*4); - arch->x87_.x87_type = (X87_ST_F)<<(dyn->insts[ninst].n.neoncache[i].n*2); - break; - case NEON_CACHE_ST_I64: - arch->x87 = 1; - arch->x87_.x87 |= 1<insts[ninst].n.neoncache[i].n; - arch->x87_.x87_pos = (i-EMM0)<<(dyn->insts[ninst].n.neoncache[i].n*4); - arch->x87_.x87_type = (X87_ST_I64)<<(dyn->insts[ninst].n.neoncache[i].n*2); - break; - case NEON_CACHE_XMMR: - case NEON_CACHE_YMMR: - default: - // doing nothing, it's just a value read in memory - break; - } + if(dyn->use_x87 || dyn->use_mmx || dyn->use_xmm || dyn->use_ymm) { + int idx; + for(int i=0; i<32; ++i) + if(dyn->insts[ninst].n.neoncache[i].v) + switch(dyn->insts[ninst].n.neoncache[i].t) { + case NEON_CACHE_XMMW: + arch->sse = 1; + arch->sse_.sse |= 1<insts[ninst].n.neoncache[i].n; + break; + case NEON_CACHE_MM: + arch->mmx = 1; + arch->mmx_.mmx |= 1<insts[ninst].n.neoncache[i].n; + break; + case NEON_CACHE_YMMW: + arch->ymm = 1; + arch->ymm_.ymm |= 1<insts[ninst].n.neoncache[i].n; + idx = i; + if(idx>=EMM0 && idx<=EMM0+8) + idx-=EMM0; + else + idx-=SCRATCH0-8; + arch->ymm_.ymm_pos |= idx<<(dyn->insts[ninst].n.neoncache[i].n*4); + break; + case NEON_CACHE_ST_D: + arch->x87 = 1; + arch->x87_.x87 |= 1<insts[ninst].n.neoncache[i].n; + arch->x87_.x87_pos = (i-EMM0)<<(dyn->insts[ninst].n.neoncache[i].n*4); + arch->x87_.x87_type = (X87_ST_D)<<(dyn->insts[ninst].n.neoncache[i].n*2); + break; + case NEON_CACHE_ST_F: + arch->x87 = 1; + arch->x87_.x87 |= 1<insts[ninst].n.neoncache[i].n; + arch->x87_.x87_pos = (i-EMM0)<<(dyn->insts[ninst].n.neoncache[i].n*4); + arch->x87_.x87_type = (X87_ST_F)<<(dyn->insts[ninst].n.neoncache[i].n*2); + break; + case NEON_CACHE_ST_I64: + arch->x87 = 1; + arch->x87_.x87 |= 1<insts[ninst].n.neoncache[i].n; + arch->x87_.x87_pos = (i-EMM0)<<(dyn->insts[ninst].n.neoncache[i].n*4); + arch->x87_.x87_type = (X87_ST_I64)<<(dyn->insts[ninst].n.neoncache[i].n*2); + break; + case NEON_CACHE_XMMR: + case NEON_CACHE_YMMR: + default: + // doing nothing, it's just a value read in memory + break; + } + } // ymm0 - if(dyn->insts[ninst].ymm0_out) { + if(dyn->use_ymm && dyn->insts[ninst].ymm0_out) { arch->ymm = 1; arch->ymm_.ymm0 = dyn->insts[ninst].ymm0_out; } // x87 top - if(dyn->insts[ninst].n.x87stack) { + if((dyn->use_x87 || dyn->insts[ninst].x87_used) && dyn->insts[ninst].n.x87stack) { arch->x87 = 1; arch->x87_.delta = dyn->insts[ninst].n.x87stack; } From 2da30a4306f158abe3f5314ce4fede609e453e69 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 11:02:50 +0000 Subject: [PATCH 12/23] Update dynarec_arm64_functions.c --- src/dynarec/arm64/dynarec_arm64_functions.c | 38 +++++++++++---------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/src/dynarec/arm64/dynarec_arm64_functions.c b/src/dynarec/arm64/dynarec_arm64_functions.c index b0177a4867..5e97f8c2e4 100644 --- a/src/dynarec/arm64/dynarec_arm64_functions.c +++ b/src/dynarec/arm64/dynarec_arm64_functions.c @@ -98,22 +98,23 @@ int fpu_get_reg_x87(dynarec_arm_t* dyn, int ninst, int t, int n) void fpu_free_reg(dynarec_arm_t* dyn, int reg) { // TODO: check upper limit? + int t = dyn->n.neoncache[reg].t; + int n = dyn->n.neoncache[reg].n; dyn->n.fpuused[reg] = 0; - if(dyn->n.neoncache[reg].t==NEON_CACHE_YMMR || dyn->n.neoncache[reg].t==NEON_CACHE_YMMW) { - dyn->n.ymm_removed |= 1<n.neoncache[reg].n; - if(dyn->n.neoncache[reg].t==NEON_CACHE_YMMW) - dyn->n.ymm_write |= 1<n.neoncache[reg].n; + if(t==NEON_CACHE_XMMR || t==NEON_CACHE_XMMW) { + dyn->n.xmm_removed |= 1<n.xmm_write |= 1<n.ymm_removed |= 1<n.ymm_write |= 1<SCRATCH0) - dyn->n.ymm_regs |= (8LL+reg-SCRATCH0)<<(dyn->n.neoncache[reg].n*4); + dyn->n.ymm_regs |= (8LL+reg-SCRATCH0)<<(n*4); else - dyn->n.ymm_regs |= ((uint64_t)(reg-EMM0))<<(dyn->n.neoncache[reg].n*4); + dyn->n.ymm_regs |= ((uint64_t)(reg-EMM0))<<(n*4); } - if(dyn->n.neoncache[reg].t==NEON_CACHE_XMMR || dyn->n.neoncache[reg].t==NEON_CACHE_XMMW) { - dyn->n.xmm_removed |= 1<n.neoncache[reg].n; - if(dyn->n.neoncache[reg].t==NEON_CACHE_XMMW) - dyn->n.xmm_write |= 1<n.neoncache[reg].n; - } - if(dyn->n.neoncache[reg].t!=NEON_CACHE_ST_F && dyn->n.neoncache[reg].t!=NEON_CACHE_ST_D && dyn->n.neoncache[reg].t!=NEON_CACHE_ST_I64) + if(t!=NEON_CACHE_ST_F && t!=NEON_CACHE_ST_D && t!=NEON_CACHE_ST_I64) dyn->n.neoncache[reg].v = 0; if(dyn->n.fpu_scratch && reg==SCRATCH0+dyn->n.fpu_scratch-1) --dyn->n.fpu_scratch; @@ -941,20 +942,21 @@ static void mmx_reset(neoncache_t* n) n->mmxcache[i] = -1; } -static void sse_reset(neoncache_t* n) +static void sse_reset(neoncache_t* n, int use_ymm) { for (int i=0; i<16; ++i) n->ssecache[i].v = -1; - for (int i=0; i<32; ++i) - if(n->neoncache[i].t==NEON_CACHE_YMMR || n->neoncache[i].t==NEON_CACHE_YMMW) - n->neoncache[i].v = 0; + if(use_ymm) + for (int i=0; i<32; ++i) + if(n->neoncache[i].t==NEON_CACHE_YMMR || n->neoncache[i].t==NEON_CACHE_YMMW) + n->neoncache[i].v = 0; } void fpu_reset(dynarec_native_t* dyn) { x87_reset(&dyn->n); mmx_reset(&dyn->n); - sse_reset(&dyn->n); + sse_reset(&dyn->n, dyn->use_ymm); fpu_reset_reg(dyn); dyn->ymm_zero = 0; } @@ -963,7 +965,7 @@ void fpu_reset_ninst(dynarec_native_t* dyn, int ninst) { x87_reset(&dyn->insts[ninst].n); mmx_reset(&dyn->insts[ninst].n); - sse_reset(&dyn->insts[ninst].n); + sse_reset(&dyn->insts[ninst].n, dyn->use_ymm); fpu_reset_reg_neoncache(&dyn->insts[ninst].n); } From 60a3fe4ef5e0c69a1d3eaac7b3a6b42e553dd462 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 11:04:05 +0000 Subject: [PATCH 13/23] Update dynarec_arm64_helper.c --- src/dynarec/arm64/dynarec_arm64_helper.c | 30 ++++++++++++++---------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/src/dynarec/arm64/dynarec_arm64_helper.c b/src/dynarec/arm64/dynarec_arm64_helper.c index 7bb1f41d21..d98afb034e 100644 --- a/src/dynarec/arm64/dynarec_arm64_helper.c +++ b/src/dynarec/arm64/dynarec_arm64_helper.c @@ -1781,9 +1781,10 @@ void fpu_pushcache(dynarec_arm_t* dyn, int ninst, int s1, int not07) if((dyn->n.ssecache[i].v!=-1) && (dyn->n.ssecache[i].write)) ++n; } - for(int i=0; i<32; ++i) - if(dyn->n.neoncache[i].t==NEON_CACHE_YMMW) - ++n; + if(dyn->use_ymm) + for(int i=0; i<32; ++i) + if(dyn->n.neoncache[i].t==NEON_CACHE_YMMW) + ++n; if(!n) return; MESSAGE(LOG_DUMP, "\tPush XMM Cache (%d)------\n", n); @@ -1793,10 +1794,11 @@ void fpu_pushcache(dynarec_arm_t* dyn, int ninst, int s1, int not07) } } // push the YMM values - for(int i=0; i<32; ++i) { - if(dyn->n.neoncache[i].t==NEON_CACHE_YMMW) - VSTR128_U12(i, xEmu, offsetof(x64emu_t, ymm[dyn->n.neoncache[i].n])); - } + if(dyn->use_ymm) + for(int i=0; i<32; ++i) { + if(dyn->n.neoncache[i].t==NEON_CACHE_YMMW) + VSTR128_U12(i, xEmu, offsetof(x64emu_t, ymm[dyn->n.neoncache[i].n])); + } MESSAGE(LOG_DUMP, "\t------- Push XMM Cache (%d)\n", n); } @@ -1808,9 +1810,10 @@ void fpu_popcache(dynarec_arm_t* dyn, int ninst, int s1, int not07) for (int i=start; i<16; i++) if(dyn->n.ssecache[i].v!=-1) ++n; - for(int i=0; i<32; ++i) - if(dyn->n.neoncache[i].t==NEON_CACHE_YMMW || dyn->n.neoncache[i].t==NEON_CACHE_YMMR) - ++n; + if(dyn->use_ymm) + for(int i=0; i<32; ++i) + if(dyn->n.neoncache[i].t==NEON_CACHE_YMMW || dyn->n.neoncache[i].t==NEON_CACHE_YMMR) + ++n; if(!n) return; MESSAGE(LOG_DUMP, "\tPop XMM Cache (%d)------\n", n); @@ -1820,9 +1823,10 @@ void fpu_popcache(dynarec_arm_t* dyn, int ninst, int s1, int not07) /*dyn->n.ssecache[i].write = 0; // OPTIM: it's sync, so not write anymore dyn->n.neoncache[dyn->n.ssecache[i].reg].t = NEON_CACHE_XMMR;*/ } - for(int i=0; i<32; ++i) - if(dyn->n.neoncache[i].t==NEON_CACHE_YMMW || dyn->n.neoncache[i].t==NEON_CACHE_YMMR) - VLDR128_U12(i, xEmu, offsetof(x64emu_t, ymm[dyn->n.neoncache[i].n])); + if(dyn->use_ymm) + for(int i=0; i<32; ++i) + if(dyn->n.neoncache[i].t==NEON_CACHE_YMMW || dyn->n.neoncache[i].t==NEON_CACHE_YMMR) + VLDR128_U12(i, xEmu, offsetof(x64emu_t, ymm[dyn->n.neoncache[i].n])); MESSAGE(LOG_DUMP, "\t------- Pop XMM Cache (%d)\n", n); } From 91cc38f284d7925f485f54d519be5ed870df585a Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 11:05:07 +0000 Subject: [PATCH 14/23] Update dynarec_arm64_helper.h --- src/dynarec/arm64/dynarec_arm64_helper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/dynarec/arm64/dynarec_arm64_helper.h b/src/dynarec/arm64/dynarec_arm64_helper.h index 092a8f50b1..51959fc8fa 100644 --- a/src/dynarec/arm64/dynarec_arm64_helper.h +++ b/src/dynarec/arm64/dynarec_arm64_helper.h @@ -1872,7 +1872,7 @@ uintptr_t dynarec64_AVX_F3_0F38(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip #define PURGE_YMM() \ do { \ - if ((ok > 0) && reset_n == -1 && dyn->insts[ninst + 1].purge_ymm) \ + if (dyn->use_ymm && (ok > 0) && reset_n == -1 && dyn->insts[ninst + 1].purge_ymm) \ avx_purge_ymm(dyn, ninst, dyn->insts[ninst + 1].purge_ymm, x1); \ } while (0) From 492dfc0ff7c55acbacdc7bf1b47d68f13e86a1b1 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 11:05:53 +0000 Subject: [PATCH 15/23] Update dynarec_native_pass.c --- src/dynarec/dynarec_native_pass.c | 71 +++++++++++++++++++++++-------- 1 file changed, 53 insertions(+), 18 deletions(-) diff --git a/src/dynarec/dynarec_native_pass.c b/src/dynarec/dynarec_native_pass.c index db8a2bba4f..e13a316f22 100644 --- a/src/dynarec/dynarec_native_pass.c +++ b/src/dynarec/dynarec_native_pass.c @@ -54,6 +54,46 @@ static int dynarec_can_read_window(uintptr_t addr, uintptr_t size) } #endif +#define X64_PREFIX_LOCK 1 +#define X64_PREFIX_REP_F2 2 +#define X64_PREFIX_REP_F3 3 +#define X64_PREFIX_SEG0 4 +#define X64_PREFIX_FS 5 +#define X64_PREFIX_GS 6 +#define X64_PREFIX_66 7 +#define X64_PREFIX_67 8 +#define X64_PREFIX_REX 9 + +static const uint8_t x64_prefix_kind[256] = { + [0x26] = X64_PREFIX_SEG0, + [0x2e] = X64_PREFIX_SEG0, + [0x36] = X64_PREFIX_SEG0, + [0x3e] = X64_PREFIX_SEG0, + [0x40] = X64_PREFIX_REX, + [0x41] = X64_PREFIX_REX, + [0x42] = X64_PREFIX_REX, + [0x43] = X64_PREFIX_REX, + [0x44] = X64_PREFIX_REX, + [0x45] = X64_PREFIX_REX, + [0x46] = X64_PREFIX_REX, + [0x47] = X64_PREFIX_REX, + [0x48] = X64_PREFIX_REX, + [0x49] = X64_PREFIX_REX, + [0x4a] = X64_PREFIX_REX, + [0x4b] = X64_PREFIX_REX, + [0x4c] = X64_PREFIX_REX, + [0x4d] = X64_PREFIX_REX, + [0x4e] = X64_PREFIX_REX, + [0x4f] = X64_PREFIX_REX, + [0x64] = X64_PREFIX_FS, + [0x65] = X64_PREFIX_GS, + [0x66] = X64_PREFIX_66, + [0x67] = X64_PREFIX_67, + [0xf0] = X64_PREFIX_LOCK, + [0xf2] = X64_PREFIX_REP_F2, + [0xf3] = X64_PREFIX_REP_F3, +}; + uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int is32bits, int inst_max) { int ok = 1; @@ -235,27 +275,22 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int rex.is67 = 0; rex.isf0 = 0; rex.rep = 0; - while((pk==0xF2) || (pk==0xF3) || (pk==0xf0) - || (pk==0x3E) || (pk==0x26) || (pk==0x2e) || (pk==0x36) - || (pk==0x64) || (pk==0x65) || (pk==0x66) || (pk==0x67) - || (!is32bits && (pk>=0x40 && pk<=0x4f))) { - switch (pk) { - case 0xF0: rex.isf0 = 1; rex.rex = 0; break; - case 0xF2: rex.rep = 1; rex.rex = 0; break; - case 0xF3: rex.rep = 2; rex.rex = 0; break; - case 0x26: /* ES: */ - case 0x2E: /* CS: */ - case 0x36: /* SS; */ - case 0x3E: /* DS; */ - rex.seg = 0; rex.rex = 0; break; - case 0x64: rex.seg = _FS; rex.rex = 0; break; - case 0x65: rex.seg = _GS; rex.rex = 0; break; - case 0x66: rex.is66 = 1; rex.rex = 0; break; - case 0x67: rex.is67 = 1; rex.rex = 0; break; - case 0x40 ... 0x4F: rex.rex = pk; break; + uint8_t prefix = x64_prefix_kind[pk]; + while(prefix && (prefix!=X64_PREFIX_REX || !is32bits)) { + switch (prefix) { + case X64_PREFIX_LOCK: rex.isf0 = 1; rex.rex = 0; break; + case X64_PREFIX_REP_F2: rex.rep = 1; rex.rex = 0; break; + case X64_PREFIX_REP_F3: rex.rep = 2; rex.rex = 0; break; + case X64_PREFIX_SEG0: rex.seg = 0; rex.rex = 0; break; + case X64_PREFIX_FS: rex.seg = _FS; rex.rex = 0; break; + case X64_PREFIX_GS: rex.seg = _GS; rex.rex = 0; break; + case X64_PREFIX_66: rex.is66 = 1; rex.rex = 0; break; + case X64_PREFIX_67: rex.is67 = 1; rex.rex = 0; break; + case X64_PREFIX_REX: rex.rex = pk; break; } ++addr; pk = PK(0); + prefix = x64_prefix_kind[pk]; } if(rex.isf0) { if(rex.is66 && !rex.w) From 07e2df1c1bbce285fc594c31e12c461ba5900d29 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 13:02:01 +0000 Subject: [PATCH 16/23] Update dynarec_native_pass.c --- src/dynarec/dynarec_native_pass.c | 40 ------------------------------- 1 file changed, 40 deletions(-) diff --git a/src/dynarec/dynarec_native_pass.c b/src/dynarec/dynarec_native_pass.c index e13a316f22..562940799d 100644 --- a/src/dynarec/dynarec_native_pass.c +++ b/src/dynarec/dynarec_native_pass.c @@ -54,46 +54,6 @@ static int dynarec_can_read_window(uintptr_t addr, uintptr_t size) } #endif -#define X64_PREFIX_LOCK 1 -#define X64_PREFIX_REP_F2 2 -#define X64_PREFIX_REP_F3 3 -#define X64_PREFIX_SEG0 4 -#define X64_PREFIX_FS 5 -#define X64_PREFIX_GS 6 -#define X64_PREFIX_66 7 -#define X64_PREFIX_67 8 -#define X64_PREFIX_REX 9 - -static const uint8_t x64_prefix_kind[256] = { - [0x26] = X64_PREFIX_SEG0, - [0x2e] = X64_PREFIX_SEG0, - [0x36] = X64_PREFIX_SEG0, - [0x3e] = X64_PREFIX_SEG0, - [0x40] = X64_PREFIX_REX, - [0x41] = X64_PREFIX_REX, - [0x42] = X64_PREFIX_REX, - [0x43] = X64_PREFIX_REX, - [0x44] = X64_PREFIX_REX, - [0x45] = X64_PREFIX_REX, - [0x46] = X64_PREFIX_REX, - [0x47] = X64_PREFIX_REX, - [0x48] = X64_PREFIX_REX, - [0x49] = X64_PREFIX_REX, - [0x4a] = X64_PREFIX_REX, - [0x4b] = X64_PREFIX_REX, - [0x4c] = X64_PREFIX_REX, - [0x4d] = X64_PREFIX_REX, - [0x4e] = X64_PREFIX_REX, - [0x4f] = X64_PREFIX_REX, - [0x64] = X64_PREFIX_FS, - [0x65] = X64_PREFIX_GS, - [0x66] = X64_PREFIX_66, - [0x67] = X64_PREFIX_67, - [0xf0] = X64_PREFIX_LOCK, - [0xf2] = X64_PREFIX_REP_F2, - [0xf3] = X64_PREFIX_REP_F3, -}; - uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int is32bits, int inst_max) { int ok = 1; From d123c3ef5e4858c5f46a3ec8228178452cd404cb Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 13:03:08 +0000 Subject: [PATCH 17/23] Update x64run_private.c --- src/emu/x64run_private.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/emu/x64run_private.c b/src/emu/x64run_private.c index cc31ff2e36..2b7e156658 100644 --- a/src/emu/x64run_private.c +++ b/src/emu/x64run_private.c @@ -30,6 +30,36 @@ #define from_ptrv(A) ((void*)(uintptr_t)(A)) #endif +const uint8_t x64_prefix_kind[256] = { + [0x26] = X64_PREFIX_SEG0, + [0x2e] = X64_PREFIX_SEG0, + [0x36] = X64_PREFIX_SEG0, + [0x3e] = X64_PREFIX_SEG0, + [0x40] = X64_PREFIX_REX, + [0x41] = X64_PREFIX_REX, + [0x42] = X64_PREFIX_REX, + [0x43] = X64_PREFIX_REX, + [0x44] = X64_PREFIX_REX, + [0x45] = X64_PREFIX_REX, + [0x46] = X64_PREFIX_REX, + [0x47] = X64_PREFIX_REX, + [0x48] = X64_PREFIX_REX, + [0x49] = X64_PREFIX_REX, + [0x4a] = X64_PREFIX_REX, + [0x4b] = X64_PREFIX_REX, + [0x4c] = X64_PREFIX_REX, + [0x4d] = X64_PREFIX_REX, + [0x4e] = X64_PREFIX_REX, + [0x4f] = X64_PREFIX_REX, + [0x64] = X64_PREFIX_FS, + [0x65] = X64_PREFIX_GS, + [0x66] = X64_PREFIX_66, + [0x67] = X64_PREFIX_67, + [0xf0] = X64_PREFIX_LOCK, + [0xf2] = X64_PREFIX_REP_F2, + [0xf3] = X64_PREFIX_REP_F3, +}; + #ifdef HAVE_TRACE #define PK(a) (*(uint8_t*)(ip+a)) From 320f3b625cad29e99467b3fd2466809cbdb550e8 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 13:04:00 +0000 Subject: [PATCH 18/23] Update x64run_private.h --- src/emu/x64run_private.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/emu/x64run_private.h b/src/emu/x64run_private.h index bc920b6ec5..5ba3d20543 100644 --- a/src/emu/x64run_private.h +++ b/src/emu/x64run_private.h @@ -8,6 +8,20 @@ #include "symbolfuncs.h" #include "x64emu.h" +enum { + X64_PREFIX_LOCK = 1, + X64_PREFIX_REP_F2, + X64_PREFIX_REP_F3, + X64_PREFIX_SEG0, + X64_PREFIX_FS, + X64_PREFIX_GS, + X64_PREFIX_66, + X64_PREFIX_67, + X64_PREFIX_REX, +}; + +extern const uint8_t x64_prefix_kind[256]; + typedef struct rex_s { union { uint8_t rex; From ac44ac6e0734e3a90061a0ed1a570b6d557b9a8f Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 13:04:40 +0000 Subject: [PATCH 19/23] Update x64run.c --- src/emu/x64run.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/src/emu/x64run.c b/src/emu/x64run.c index f32e0ab5d1..0e2e7ec291 100644 --- a/src/emu/x64run.c +++ b/src/emu/x64run.c @@ -108,26 +108,21 @@ int Run(x64emu_t *emu, int step) rex.is67 = 0; rex.isf0 = 0; rex.rep = 0; - while((opcode==0xF2) || (opcode==0xF3) || (opcode==0xF0) - || (opcode==0x3E) || (opcode==0x26) || (opcode==0x2e) || (opcode==0x36) - || (opcode==0x64) || (opcode==0x65) || (opcode==0x66) || (opcode==0x67) - || (!is32bits && (opcode>=0x40 && opcode<=0x4f))) { - switch (opcode) { - case 0xF0: rex.isf0 = 1; rex.rex = 0; break; - case 0xF2: rex.rep = 1; rex.rex = 0; break; - case 0xF3: rex.rep = 2; rex.rex = 0; break; - case 0x26: /* ES: */ - case 0x2E: /* CS: */ - case 0x36: /* SS; */ - case 0x3E: /* DS; */ - rex.seg = 0; rex.rex = 0; break; - case 0x64: rex.seg = _FS; rex.rex = 0; break; - case 0x65: rex.seg = _GS; rex.rex = 0; break; - case 0x66: rex.is66 = 1; rex.rex = 0; break; - case 0x67: rex.is67 = 1; rex.rex = 0; break; - case 0x40 ... 0x4F: rex.rex = opcode; break; + uint8_t prefix = x64_prefix_kind[opcode]; + while(prefix && (prefix!=X64_PREFIX_REX || !is32bits)) { + switch (prefix) { + case X64_PREFIX_LOCK: rex.isf0 = 1; rex.rex = 0; break; + case X64_PREFIX_REP_F2: rex.rep = 1; rex.rex = 0; break; + case X64_PREFIX_REP_F3: rex.rep = 2; rex.rex = 0; break; + case X64_PREFIX_SEG0: rex.seg = 0; rex.rex = 0; break; + case X64_PREFIX_FS: rex.seg = _FS; rex.rex = 0; break; + case X64_PREFIX_GS: rex.seg = _GS; rex.rex = 0; break; + case X64_PREFIX_66: rex.is66 = 1; rex.rex = 0; break; + case X64_PREFIX_67: rex.is67 = 1; rex.rex = 0; break; + case X64_PREFIX_REX: rex.rex = opcode; break; } opcode = F8; + prefix = x64_prefix_kind[opcode]; } if(rex.seg) From 004ec392f9d90c5a2e9d8f51b4ca3589ca4503d4 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 13:17:20 +0000 Subject: [PATCH 20/23] Update dynarec_native_pass.c --- src/dynarec/dynarec_native_pass.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/dynarec/dynarec_native_pass.c b/src/dynarec/dynarec_native_pass.c index 562940799d..5c17fa9564 100644 --- a/src/dynarec/dynarec_native_pass.c +++ b/src/dynarec/dynarec_native_pass.c @@ -235,7 +235,7 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int rex.is67 = 0; rex.isf0 = 0; rex.rep = 0; - uint8_t prefix = x64_prefix_kind[pk]; + uint8_t prefix = x64_prefix_kind_table[pk]; while(prefix && (prefix!=X64_PREFIX_REX || !is32bits)) { switch (prefix) { case X64_PREFIX_LOCK: rex.isf0 = 1; rex.rex = 0; break; @@ -250,7 +250,7 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int } ++addr; pk = PK(0); - prefix = x64_prefix_kind[pk]; + prefix = x64_prefix_kind_table[pk]; } if(rex.isf0) { if(rex.is66 && !rex.w) From 4336763f322c19c72876665c5a384d33fcf7b041 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 13:18:25 +0000 Subject: [PATCH 21/23] Update x64run_private.c --- src/emu/x64run_private.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/emu/x64run_private.c b/src/emu/x64run_private.c index 2b7e156658..a37a6c8f2a 100644 --- a/src/emu/x64run_private.c +++ b/src/emu/x64run_private.c @@ -30,7 +30,7 @@ #define from_ptrv(A) ((void*)(uintptr_t)(A)) #endif -const uint8_t x64_prefix_kind[256] = { +const uint8_t x64_prefix_kind_table[256] = { [0x26] = X64_PREFIX_SEG0, [0x2e] = X64_PREFIX_SEG0, [0x36] = X64_PREFIX_SEG0, From 2a7722ec5304ea5f11a6fb76d630227252d1294e Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 13:18:59 +0000 Subject: [PATCH 22/23] Update x64run_private.h --- src/emu/x64run_private.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/emu/x64run_private.h b/src/emu/x64run_private.h index 5ba3d20543..f1b99c3787 100644 --- a/src/emu/x64run_private.h +++ b/src/emu/x64run_private.h @@ -20,7 +20,7 @@ enum { X64_PREFIX_REX, }; -extern const uint8_t x64_prefix_kind[256]; +extern const uint8_t x64_prefix_kind_table[256]; typedef struct rex_s { union { From a967ee568f1bfbf78c959ab9f768b3035419f772 Mon Sep 17 00:00:00 2001 From: Makhi Burroughs Date: Wed, 13 May 2026 13:19:38 +0000 Subject: [PATCH 23/23] Update x64run.c --- src/emu/x64run.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/emu/x64run.c b/src/emu/x64run.c index 0e2e7ec291..0522eed6d5 100644 --- a/src/emu/x64run.c +++ b/src/emu/x64run.c @@ -108,7 +108,7 @@ int Run(x64emu_t *emu, int step) rex.is67 = 0; rex.isf0 = 0; rex.rep = 0; - uint8_t prefix = x64_prefix_kind[opcode]; + uint8_t prefix = x64_prefix_kind_table[opcode]; while(prefix && (prefix!=X64_PREFIX_REX || !is32bits)) { switch (prefix) { case X64_PREFIX_LOCK: rex.isf0 = 1; rex.rex = 0; break; @@ -122,7 +122,7 @@ int Run(x64emu_t *emu, int step) case X64_PREFIX_REX: rex.rex = opcode; break; } opcode = F8; - prefix = x64_prefix_kind[opcode]; + prefix = x64_prefix_kind_table[opcode]; } if(rex.seg)