diff --git a/bsp_sedi/soc/intel_ish/pm/aon/include/ish_registers.h b/bsp_sedi/soc/intel_ish/pm/aon/include/ish_registers.h
index 4a9a96e46c7..586a9e84dd5 100644
--- a/bsp_sedi/soc/intel_ish/pm/aon/include/ish_registers.h
+++ b/bsp_sedi/soc/intel_ish/pm/aon/include/ish_registers.h
@@ -63,7 +63,6 @@
 #define PMU_RST_PREP			(SEDI_REG_BASE(PMU) + 0x5c)
 #define PMU_RST_PREP_GET		BIT(0)
 #define PMU_RST_PREP_AVAIL		BIT(1)
-#define PMU_RST_PREP_RESET_TYPE		0x3FC
 #define PMU_RST_PREP_INT_MASK		BIT(31)
 
 #define VNN_ID_DMA0			4
diff --git a/bsp_sedi/soc/intel_ish/pm/aon/ish_aontask.c b/bsp_sedi/soc/intel_ish/pm/aon/ish_aontask.c
index 9b01fb5668a..921be502e0f 100644
--- a/bsp_sedi/soc/intel_ish/pm/aon/ish_aontask.c
+++ b/bsp_sedi/soc/intel_ish/pm/aon/ish_aontask.c
@@ -18,7 +18,6 @@
 #define AON_IDT_ENTRY_VEC_FIRST		SEDI_VEC_RESET_PREP
 #define AON_IDT_ENTRY_VEC_LAST		SEDI_VEC_PMU2IOAPIC
 
-#define PMU_RST_AP_REBOOT 0x40
 static void handle_reset(enum ish_pm_state pm_state);
 
 /* ISR for PMU wakeup interrupt */
@@ -653,8 +652,6 @@ static void sram_exit_sleep_mode(void)
 
 static void handle_d0i2(void)
 {
-	uint32_t reg_val;
-
 	ish_pg_exit_save_ctx();
 	aon_share.pg_exit = 0;
 
@@ -701,9 +698,7 @@ static void handle_d0i2(void)
 		continue;
 #endif
 
-	reg_val = read32(PMU_RST_PREP);
-	if ((reg_val & PMU_RST_PREP_AVAIL) ||
-		((reg_val & PMU_RST_PREP_RESET_TYPE) == PMU_RST_AP_REBOOT)) {
+	if (read32(PMU_RST_PREP) & PMU_RST_PREP_AVAIL) {
 		handle_reset(ISH_PM_STATE_RESET_PREP);
 	}
 
@@ -715,7 +710,6 @@ static void handle_d0i2(void)
 static void handle_d0i3(void)
 {
 	int ret;
-	uint32_t reg_val;
 
 	ish_pg_exit_save_ctx();
 	aon_share.pg_exit = 0;
@@ -749,9 +743,7 @@ static void handle_d0i3(void)
 
 	clear_vnnred_aoncg();
 
-	reg_val = read32(PMU_RST_PREP);
-	if ((reg_val & PMU_RST_PREP_AVAIL) ||
-		((reg_val & PMU_RST_PREP_RESET_TYPE) == PMU_RST_AP_REBOOT)) {
+	if (read32(PMU_RST_PREP) & PMU_RST_PREP_AVAIL) {
 		handle_reset(ISH_PM_STATE_RESET_PREP);
 	}