diff --git a/ports/cortex_a12/ac6/src/tx_thread_system_return.S b/ports/cortex_a12/ac6/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a12/ac6/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a12/gnu/src/tx_thread_system_return.S b/ports/cortex_a12/gnu/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a12/gnu/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a15/ac6/src/tx_thread_system_return.S b/ports/cortex_a15/ac6/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a15/ac6/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a15/gnu/src/tx_thread_system_return.S b/ports/cortex_a15/gnu/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a15/gnu/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a17/ac6/src/tx_thread_system_return.S b/ports/cortex_a17/ac6/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a17/ac6/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a17/gnu/src/tx_thread_system_return.S b/ports/cortex_a17/gnu/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a17/gnu/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a5/ac6/src/tx_thread_system_return.S b/ports/cortex_a5/ac6/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a5/ac6/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a5/gnu/src/tx_thread_system_return.S b/ports/cortex_a5/gnu/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a5/gnu/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a7/ac6/src/tx_thread_system_return.S b/ports/cortex_a7/ac6/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a7/ac6/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a7/gnu/src/tx_thread_system_return.S b/ports/cortex_a7/gnu/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a7/gnu/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a8/ac6/src/tx_thread_system_return.S b/ports/cortex_a8/ac6/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a8/ac6/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a8/gnu/src/tx_thread_system_return.S b/ports/cortex_a8/gnu/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a8/gnu/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a9/ac6/src/tx_thread_system_return.S b/ports/cortex_a9/ac6/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a9/ac6/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports/cortex_a9/gnu/src/tx_thread_system_return.S b/ports/cortex_a9/gnu/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a9/gnu/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S index 1a17446bc..9aa7e0e50 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -121,7 +122,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.S index fd8de2273..fae8a96a2 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.S @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -117,7 +118,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice // Pickup address of time slice LDR r1, [r2] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread control block. The + scheduler runs on the banked SVC mode stack that the startup code + set up, so there is no stack switch to perform. */ STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s index f22ca01c5..dd041adc0 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -8,6 +9,7 @@ ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; +; // Some portions generated by Copilot (Opus 5). ; ;/**************************************************************************/ ;/**************************************************************************/ @@ -113,7 +115,9 @@ _tx_skip_solicited_vfp_save: LDR r2, =_tx_timer_time_slice ; Pickup address of time slice LDR r1, [r2] ; Pickup current time slice -; /* Save current stack and switch to system stack. */ +; /* Save the current stack pointer in the thread control block. The +; scheduler runs on the banked SVC mode stack that the startup code +; set up, so there is no stack switch to perform. */ STR sp, [r0, #8] ; Save thread stack pointer diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s index 330478930..e3e0290e6 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -8,6 +9,7 @@ ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; +; // Some portions generated by Copilot (Opus 5). ; ;/**************************************************************************/ ;/**************************************************************************/ @@ -145,11 +147,11 @@ __tx_thread_not_nested_save BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; -; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -; -; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; /* This routine runs in IRQ mode on this core's banked IRQ stack, which +; serves as the system stack on this architecture, so there is no stack +; switch to perform here. The thread's stack pointer is saved in its +; control block by _tx_thread_context_restore, and only when the +; interrupt results in preemption. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s index da21d7c16..cb527029f 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -8,6 +9,7 @@ ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; +; // Some portions generated by Copilot (Opus 5). ; ;/**************************************************************************/ ;/**************************************************************************/ @@ -132,9 +134,10 @@ _tx_skip_solicited_vfp_save ADD r2, r2, r12 ; Build index into time-slice array LDR r1, [r2, #0] ; Pickup current time slice ; -; /* Save current stack and switch to system stack. */ +; /* Save the current stack pointer in the thread's control block. The +; scheduler runs on this core's banked SVC mode stack, which the startup +; code set up, so there is no stack switch to perform. */ ; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -; sp = _tx_thread_system_stack_ptr[core]; ; STR sp, [r0, #8] ; Save thread stack pointer ; diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s index 69a226939..586be818f 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -8,6 +9,7 @@ ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; +; // Some portions generated by Copilot (Opus 5). ; ;/**************************************************************************/ ;/**************************************************************************/ @@ -143,11 +145,11 @@ __tx_thread_not_nested_save ; ; /* Note: Minimal context of interrupted thread is already saved. */ ; -; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -; -; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr[core]; +; /* This routine runs in IRQ mode on this core's banked IRQ stack, which +; serves as the system stack on this architecture, so there is no stack +; switch to perform here. The thread's stack pointer is saved in its +; control block by _tx_thread_context_restore, and only when the +; interrupt results in preemption. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_save.S index 3148c0f5c..0da2af21b 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_save.S @@ -1,5 +1,6 @@ @/*************************************************************************** @ * Copyright (c) 2024 Microsoft Corporation +@ * Copyright (c) 2026-present Eclipse ThreadX contributors @ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @@ -8,6 +9,7 @@ @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ +@ // Some portions generated by Copilot (Opus 5). @ @/**************************************************************************/ @/**************************************************************************/ @@ -147,11 +149,11 @@ __tx_thread_not_nested_save: BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ -@ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -@ -@ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr; +@ /* This routine runs in IRQ mode on this core's banked IRQ stack, which +@ serves as the system stack on this architecture, so there is no stack +@ switch to perform here. The thread's stack pointer is saved in its +@ control block by _tx_thread_context_restore, and only when the +@ interrupt results in preemption. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_system_return.S index f49d8324c..33d1760eb 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_system_return.S @@ -1,5 +1,6 @@ @/*************************************************************************** @ * Copyright (c) 2024 Microsoft Corporation +@ * Copyright (c) 2026-present Eclipse ThreadX contributors @ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @@ -8,6 +9,7 @@ @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ +@ // Some portions generated by Copilot (Opus 5). @ @/**************************************************************************/ @/**************************************************************************/ @@ -134,9 +136,10 @@ _tx_skip_solicited_vfp_save: ADD r2, r2, r12 @ Build index into time-slice array LDR r1, [r2, #0] @ Pickup current time slice @ -@ /* Save current stack and switch to system stack. */ +@ /* Save the current stack pointer in the thread's control block. The +@ scheduler runs on this core's banked SVC mode stack, which the startup +@ code set up, so there is no stack switch to perform. */ @ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -@ sp = _tx_thread_system_stack_ptr[core]; @ STR sp, [r0, #8] @ Save thread stack pointer @ diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_vectored_context_save.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_vectored_context_save.S index aed336ada..8a3eb6685 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_vectored_context_save.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_vectored_context_save.S @@ -1,5 +1,6 @@ @/*************************************************************************** @ * Copyright (c) 2024 Microsoft Corporation +@ * Copyright (c) 2026-present Eclipse ThreadX contributors @ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @@ -8,6 +9,7 @@ @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ +@ // Some portions generated by Copilot (Opus 5). @ @/**************************************************************************/ @/**************************************************************************/ @@ -145,11 +147,11 @@ __tx_thread_not_nested_save: @ @ /* Note: Minimal context of interrupted thread is already saved. */ @ -@ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -@ -@ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr[core]; +@ /* This routine runs in IRQ mode on this core's banked IRQ stack, which +@ serves as the system stack on this architecture, so there is no stack +@ switch to perform here. The thread's stack pointer is saved in its +@ control block by _tx_thread_context_restore, and only when the +@ interrupt results in preemption. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s index acc2de11c..8c45f4a97 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -8,6 +9,7 @@ ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; +; // Some portions generated by Copilot (Opus 5). ; ;/**************************************************************************/ ;/**************************************************************************/ @@ -145,11 +147,11 @@ __tx_thread_not_nested_save BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; -; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -; -; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; /* This routine runs in IRQ mode on this core's banked IRQ stack, which +; serves as the system stack on this architecture, so there is no stack +; switch to perform here. The thread's stack pointer is saved in its +; control block by _tx_thread_context_restore, and only when the +; interrupt results in preemption. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s index ebd80ae25..75bea71e5 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -8,6 +9,7 @@ ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; +; // Some portions generated by Copilot (Opus 5). ; ;/**************************************************************************/ ;/**************************************************************************/ @@ -132,9 +134,10 @@ _tx_skip_solicited_vfp_save ADD r2, r2, r12 ; Build index into time-slice array LDR r1, [r2, #0] ; Pickup current time slice ; -; /* Save current stack and switch to system stack. */ +; /* Save the current stack pointer in the thread's control block. The +; scheduler runs on this core's banked SVC mode stack, which the startup +; code set up, so there is no stack switch to perform. */ ; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -; sp = _tx_thread_system_stack_ptr[core]; ; STR sp, [r0, #8] ; Save thread stack pointer ; diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s index 86145e1e6..a46578ece 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -8,6 +9,7 @@ ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; +; // Some portions generated by Copilot (Opus 5). ; ;/**************************************************************************/ ;/**************************************************************************/ @@ -143,11 +145,11 @@ __tx_thread_not_nested_save ; ; /* Note: Minimal context of interrupted thread is already saved. */ ; -; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -; -; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr[core]; +; /* This routine runs in IRQ mode on this core's banked IRQ stack, which +; serves as the system stack on this architecture, so there is no stack +; switch to perform here. The thread's stack pointer is saved in its +; control block by _tx_thread_context_restore, and only when the +; interrupt results in preemption. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S index 448b3a5af..6deb2371d 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S @@ -1,5 +1,6 @@ @/*************************************************************************** @ * Copyright (c) 2024 Microsoft Corporation +@ * Copyright (c) 2026-present Eclipse ThreadX contributors @ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @@ -8,6 +9,7 @@ @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ +@ // Some portions generated by Copilot (Opus 5). @ @/**************************************************************************/ @/**************************************************************************/ @@ -150,11 +152,11 @@ __tx_thread_not_nested_save: BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ -@ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -@ -@ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr; +@ /* This routine runs in IRQ mode on this core's banked IRQ stack, which +@ serves as the system stack on this architecture, so there is no stack +@ switch to perform here. The thread's stack pointer is saved in its +@ control block by _tx_thread_context_restore, and only when the +@ interrupt results in preemption. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S index 98e64ad1c..565390fce 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S @@ -1,5 +1,6 @@ @/*************************************************************************** @ * Copyright (c) 2024 Microsoft Corporation +@ * Copyright (c) 2026-present Eclipse ThreadX contributors @ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @@ -8,6 +9,7 @@ @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ +@ // Some portions generated by Copilot (Opus 5). @ @/**************************************************************************/ @/**************************************************************************/ @@ -134,9 +136,10 @@ _tx_skip_solicited_vfp_save: ADD r2, r2, r12 @ Build index into time-slice array LDR r1, [r2, #0] @ Pickup current time slice @ -@ /* Save current stack and switch to system stack. */ +@ /* Save the current stack pointer in the thread's control block. The +@ scheduler runs on this core's banked SVC mode stack, which the startup +@ code set up, so there is no stack switch to perform. */ @ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -@ sp = _tx_thread_system_stack_ptr[core]; @ STR sp, [r0, #8] @ Save thread stack pointer @ diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S index 0d8aab556..a656be78b 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S @@ -1,5 +1,6 @@ @/*************************************************************************** @ * Copyright (c) 2024 Microsoft Corporation +@ * Copyright (c) 2026-present Eclipse ThreadX contributors @ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @@ -8,6 +9,7 @@ @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ +@ // Some portions generated by Copilot (Opus 5). @ @/**************************************************************************/ @/**************************************************************************/ @@ -145,11 +147,11 @@ __tx_thread_not_nested_save: @ @ /* Note: Minimal context of interrupted thread is already saved. */ @ -@ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -@ -@ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr[core]; +@ /* This routine runs in IRQ mode on this core's banked IRQ stack, which +@ serves as the system stack on this architecture, so there is no stack +@ switch to perform here. The thread's stack pointer is saved in its +@ control block by _tx_thread_context_restore, and only when the +@ interrupt results in preemption. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s index a0e2a5e6c..948748287 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -8,6 +9,7 @@ ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; +; // Some portions generated by Copilot (Opus 5). ; ;/**************************************************************************/ ;/**************************************************************************/ @@ -145,11 +147,11 @@ __tx_thread_not_nested_save BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; -; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -; -; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; /* This routine runs in IRQ mode on this core's banked IRQ stack, which +; serves as the system stack on this architecture, so there is no stack +; switch to perform here. The thread's stack pointer is saved in its +; control block by _tx_thread_context_restore, and only when the +; interrupt results in preemption. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s index f03fc6fe4..4b8b56ce0 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -8,6 +9,7 @@ ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; +; // Some portions generated by Copilot (Opus 5). ; ;/**************************************************************************/ ;/**************************************************************************/ @@ -132,9 +134,10 @@ _tx_skip_solicited_vfp_save ADD r2, r2, r12 ; Build index into time-slice array LDR r1, [r2, #0] ; Pickup current time slice ; -; /* Save current stack and switch to system stack. */ +; /* Save the current stack pointer in the thread's control block. The +; scheduler runs on this core's banked SVC mode stack, which the startup +; code set up, so there is no stack switch to perform. */ ; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -; sp = _tx_thread_system_stack_ptr[core]; ; STR sp, [r0, #8] ; Save thread stack pointer ; diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s index 8102e78bf..8bd7dc61d 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -8,6 +9,7 @@ ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; +; // Some portions generated by Copilot (Opus 5). ; ;/**************************************************************************/ ;/**************************************************************************/ @@ -143,11 +145,11 @@ __tx_thread_not_nested_save ; ; /* Note: Minimal context of interrupted thread is already saved. */ ; -; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -; -; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr[core]; +; /* This routine runs in IRQ mode on this core's banked IRQ stack, which +; serves as the system stack on this architecture, so there is no stack +; switch to perform here. The thread's stack pointer is saved in its +; control block by _tx_thread_context_restore, and only when the +; interrupt results in preemption. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S index ae4065c41..32a78bc8d 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S @@ -1,5 +1,6 @@ @/*************************************************************************** @ * Copyright (c) 2024 Microsoft Corporation +@ * Copyright (c) 2026-present Eclipse ThreadX contributors @ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @@ -8,6 +9,7 @@ @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ +@ // Some portions generated by Copilot (Opus 5). @ @/**************************************************************************/ @/**************************************************************************/ @@ -147,11 +149,11 @@ __tx_thread_not_nested_save: BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ -@ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -@ -@ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr; +@ /* This routine runs in IRQ mode on this core's banked IRQ stack, which +@ serves as the system stack on this architecture, so there is no stack +@ switch to perform here. The thread's stack pointer is saved in its +@ control block by _tx_thread_context_restore, and only when the +@ interrupt results in preemption. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S index 6feec05b6..7c0ba3d3b 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S @@ -1,5 +1,6 @@ @/*************************************************************************** @ * Copyright (c) 2024 Microsoft Corporation +@ * Copyright (c) 2026-present Eclipse ThreadX contributors @ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @@ -8,6 +9,7 @@ @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ +@ // Some portions generated by Copilot (Opus 5). @ @/**************************************************************************/ @/**************************************************************************/ @@ -134,9 +136,10 @@ _tx_skip_solicited_vfp_save: ADD r2, r2, r12 @ Build index into time-slice array LDR r1, [r2, #0] @ Pickup current time slice @ -@ /* Save current stack and switch to system stack. */ +@ /* Save the current stack pointer in the thread's control block. The +@ scheduler runs on this core's banked SVC mode stack, which the startup +@ code set up, so there is no stack switch to perform. */ @ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -@ sp = _tx_thread_system_stack_ptr[core]; @ STR sp, [r0, #8] @ Save thread stack pointer @ diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S index 5991c4707..8c85ddbd0 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S @@ -1,5 +1,6 @@ @/*************************************************************************** @ * Copyright (c) 2024 Microsoft Corporation +@ * Copyright (c) 2026-present Eclipse ThreadX contributors @ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @@ -8,6 +9,7 @@ @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ +@ // Some portions generated by Copilot (Opus 5). @ @/**************************************************************************/ @/**************************************************************************/ @@ -145,11 +147,11 @@ __tx_thread_not_nested_save: @ @ /* Note: Minimal context of interrupted thread is already saved. */ @ -@ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; -@ -@ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr[core]; +@ /* This routine runs in IRQ mode on this core's banked IRQ stack, which +@ serves as the system stack on this architecture, so there is no stack +@ switch to perform here. The thread's stack pointer is saved in its +@ control block by _tx_thread_context_restore, and only when the +@ interrupt results in preemption. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_save.s index 780a6b0ae..f506f4e42 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_save.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_save.s @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -134,11 +135,11 @@ __tx_thread_not_nested_save BEQ __tx_thread_idle_system_save // If so, interrupt occurred in // scheduling loop - nothing needs saving! - /* Save the current stack pointer in the thread's control block. */ - // _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; - - /* Switch to the system stack. */ - // sp = _tx_thread_system_stack_ptr; + /* This routine runs in IRQ mode on this core's banked IRQ stack, which + serves as the system stack on this architecture, so there is no stack + switch to perform here. The thread's stack pointer is saved in its + control block by _tx_thread_context_restore, and only when the + interrupt results in preemption. */ MOV r10, #0 // Clear stack limit diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_system_return.s index 2280a3518..fc1b59ed8 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_system_return.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_system_return.s @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -120,9 +121,10 @@ _tx_skip_solicited_vfp_save ADD r2, r2, r12 // Build index into time-slice array LDR r1, [r2, #0] // Pickup current time slice - /* Save current stack and switch to system stack. */ + /* Save the current stack pointer in the thread's control block. The + scheduler runs on this core's banked SVC mode stack, which the startup + code set up, so there is no stack switch to perform. */ // _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; - // sp = _tx_thread_system_stack_ptr[core]; STR sp, [r0, #8] // Save thread stack pointer diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_vectored_context_save.s index c62297e85..9e82773c0 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_vectored_context_save.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_vectored_context_save.s @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Copilot (Opus 5). /**************************************************************************/ /**************************************************************************/ @@ -132,11 +133,11 @@ __tx_thread_not_nested_save /* Note: Minimal context of interrupted thread is already saved. */ - /* Save the current stack pointer in the thread's control block. */ - // _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; - - /* Switch to the system stack. */ - // sp = _tx_thread_system_stack_ptr[core]; + /* This routine runs in IRQ mode on this core's banked IRQ stack, which + serves as the system stack on this architecture, so there is no stack + switch to perform here. The thread's stack pointer is saved in its + control block by _tx_thread_context_restore, and only when the + interrupt results in preemption. */ MOV r10, #0 // Clear stack limit