From 0f8e8abfd62a96e7fd24463c18026bf49b9bd418 Mon Sep 17 00:00:00 2001
From: Afonso Bordado <afonsobordado@az8.co>
Date: Sat, 18 Jul 2026 09:57:42 +0100
Subject: [PATCH] riscv64: Add support for `vconst.f16`

---
 .../codegen/src/isa/riscv64/inst_vector.isle  |  3 ++
 .../filetests/isa/riscv64/simd-const-f16.clif | 35 +++++++++++++++++++
 .../filetests/runtests/simd-vconst-f16.clif   | 18 ++++++++++
 cranelift/reader/src/parser.rs                |  1 +
 4 files changed, 57 insertions(+)
 create mode 100644 cranelift/filetests/filetests/isa/riscv64/simd-const-f16.clif
 create mode 100644 cranelift/filetests/filetests/runtests/simd-vconst-f16.clif

diff --git a/cranelift/codegen/src/isa/riscv64/inst_vector.isle b/cranelift/codegen/src/isa/riscv64/inst_vector.isle
index 4ed04a81bf83..6e276dc963ac 100644
--- a/cranelift/codegen/src/isa/riscv64/inst_vector.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst_vector.isle
@@ -350,6 +350,9 @@
 (rule (element_width_from_type ty)
   (if-let $I8 (lane_type ty))
   (VecElementWidth.E8))
+(rule (element_width_from_type ty)
+  (if-let $F16 (lane_type ty))
+  (VecElementWidth.E16))
 (rule (element_width_from_type ty)
   (if-let $I16 (lane_type ty))
   (VecElementWidth.E16))
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-const-f16.clif b/cranelift/filetests/filetests/isa/riscv64/simd-const-f16.clif
new file mode 100644
index 000000000000..2419d83ac4c2
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-const-f16.clif
@@ -0,0 +1,35 @@
+test compile precise-output
+set enable_multi_ret_implicit_sret
+set unwind_info=false
+target riscv64 has_v has_zvfh
+
+
+function %const_f16x8() -> f16x8 {
+    const0 = 0xf9d45846788bf825707b7b78faa77803
+
+block0:
+    v1 = vconst.f16x8 const0
+    return v1
+}
+
+; VCode:
+; block0:
+;   vle16.v v8,[const(0)] #avl=8, #vtype=(e16, m1, ta, ma)
+;   vse8.v v8,0(a0) #avl=16, #vtype=(e8, m1, ta, ma)
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x57, 0x70, 0x84, 0xcc
+;   auipc t6, 0
+;   addi t6, t6, 0x1c
+;   .byte 0x07, 0xd4, 0x0f, 0x02
+;   .byte 0x57, 0x70, 0x08, 0xcc
+;   .byte 0x27, 0x04, 0x05, 0x02
+;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x03, 0x78, 0xa7, 0xfa
+;   .byte 0x78, 0x7b, 0x7b, 0x70
+;   .byte 0x25, 0xf8, 0x8b, 0x78
+;   .byte 0x46, 0x58, 0xd4, 0xf9
+
diff --git a/cranelift/filetests/filetests/runtests/simd-vconst-f16.clif b/cranelift/filetests/filetests/runtests/simd-vconst-f16.clif
new file mode 100644
index 000000000000..7a306fa6cff0
--- /dev/null
+++ b/cranelift/filetests/filetests/runtests/simd-vconst-f16.clif
@@ -0,0 +1,18 @@
+test run
+set enable_multi_ret_implicit_sret
+target riscv64 has_v has_zvfh
+target riscv64 has_v has_zvfh has_c has_zcb
+
+function %vconst_zeroes_f16x8() -> f16x8 {
+block0:
+    v0 = vconst.f16x8 [0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0]
+    return v0
+}
+; run: %vconst_zeroes_f16x8() == [0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0]
+
+function %vconst_varied_f16x8() -> f16x8 {
+block0:
+    v0 = vconst.f16x8 [0x1.0 -0x1.0 0.0 Inf -Inf 0x1.554p-2 -0x1.554p-2 0x1.92p1]
+    return v0
+}
+; run: %vconst_varied_f16x8() == [0x1.0 -0x1.0 0.0 Inf -Inf 0x1.554p-2 -0x1.554p-2 0x1.92p1]
diff --git a/cranelift/reader/src/parser.rs b/cranelift/reader/src/parser.rs
index 2e8489b08a0f..ffede91ddd4a 100644
--- a/cranelift/reader/src/parser.rs
+++ b/cranelift/reader/src/parser.rs
@@ -1005,6 +1005,7 @@ impl<'a> Parser<'a> {
                 I16 => consume!(ty, self.match_imm16("Expected a 16-bit integer")?),
                 I32 => consume!(ty, self.match_imm32("Expected a 32-bit integer")?),
                 I64 => consume!(ty, self.match_imm64("Expected a 64-bit integer")?),
+                F16 => consume!(ty, self.match_ieee16("Expected a 16-bit float")?),
                 F32 => consume!(ty, self.match_ieee32("Expected a 32-bit float")?),
                 F64 => consume!(ty, self.match_ieee64("Expected a 64-bit float")?),
                 _ => return err!(self.loc, "Expected a type of: float, int, bool"),