-e top module: test
-e top file : FASTPATH_SUBMIT_MP.bsv
-e print simulation log to: /dev/stdout
-e
-e bsc -verilog -g test -u FASTPATH_SUBMIT_MP.bsv
checking package dependencies
Error: "FASTPATH_SUBMIT_MP.bsv", line 11, column 8: (S0000)
Cannot find package `TLM2'
Error: "FASTPATH_SUBMIT_MP.bsv", line 12, column 8: (S0000)
Cannot find package `Axi'
Error: "FASTPATH_SUBMIT_MP.bsv", line 13, column 8: (S0000)
Cannot find package `AXI32_GDefines'
Error: "FASTPATH_SUBMIT_MP.bsv", line 14, column 8: (S0000)
Cannot find package `Zynq_AXI32'
Error: "FASTPATH_SUBMIT_MP.bsv", line 15, column 8: (S0000)
Cannot find package `ACPDefines'
Error: "FASTPATH_SUBMIT_MP.bsv", line 16, column 8: (S0000)
Cannot find package `Zynq_ACP'
Error: "FASTPATH_SUBMIT_MP.bsv", line 18, column 8: (S0000)
Cannot find package `BusRange'
-e Error: failed to generate Verilog !
I tried running
bsvbuild.sh - vs test FASTPATH_SUBMIT_maP.bsvbut the terminal encountered an error:
How can this problem be solved?