From 662cfc098de5ed3f95cc442dda2849bd8581363c Mon Sep 17 00:00:00 2001 From: "Ahmed R. Mohamed" Date: Fri, 13 Mar 2026 19:48:47 +0000 Subject: [PATCH 1/3] odb: impl 3dblox verilog writer Signed-off-by: Ahmed R. Mohamed --- include/ord/OpenRoad.hh | 4 +- src/OpenRoad.cc | 7 +- src/OpenRoad.i | 7 + src/OpenRoad.tcl | 9 + src/odb/include/odb/3dblox.h | 1 + src/odb/src/3dblox/3dblox.cpp | 14 ++ src/odb/src/3dblox/CMakeLists.txt | 1 + src/odb/src/3dblox/dbxWriter.cpp | 2 + src/odb/src/3dblox/verilogWriter.cpp | 121 ++++++++++++ src/odb/src/3dblox/verilogWriter.h | 24 +++ src/odb/test/BUILD | 6 + src/odb/test/CMakeLists.txt | 2 + src/odb/test/cpp/BUILD | 1 + src/odb/test/cpp/CMakeLists.txt | 2 +- src/odb/test/cpp/Test3DBloxVerilogWriter.cpp | 186 +++++++++++++++++++ src/odb/test/data/example_nets.3dbv | 36 ++++ src/odb/test/data/example_nets.3dbx | 45 +++++ src/odb/test/data/example_nets.bmap | 2 + src/odb/test/data/top_nets.v | 12 ++ src/odb/test/write_3dblox_verilog.ok | 9 + src/odb/test/write_3dblox_verilog.tcl | 10 + src/odb/test/write_3dblox_verilog.vok | 6 + src/odb/test/write_3dblox_verilog_nets.ok | 10 + src/odb/test/write_3dblox_verilog_nets.tcl | 10 + src/odb/test/write_3dblox_verilog_nets.vok | 12 ++ src/odb/test/write_3dbx.3dbxok | 2 + 26 files changed, 537 insertions(+), 4 deletions(-) create mode 100644 src/odb/src/3dblox/verilogWriter.cpp create mode 100644 src/odb/src/3dblox/verilogWriter.h create mode 100644 src/odb/test/cpp/Test3DBloxVerilogWriter.cpp create mode 100644 src/odb/test/data/example_nets.3dbv create mode 100644 src/odb/test/data/example_nets.3dbx create mode 100644 src/odb/test/data/example_nets.bmap create mode 100644 src/odb/test/data/top_nets.v create mode 100644 src/odb/test/write_3dblox_verilog.ok create mode 100644 src/odb/test/write_3dblox_verilog.tcl create mode 100644 src/odb/test/write_3dblox_verilog.vok create mode 100644 src/odb/test/write_3dblox_verilog_nets.ok create mode 100644 src/odb/test/write_3dblox_verilog_nets.tcl create mode 100644 src/odb/test/write_3dblox_verilog_nets.vok diff --git a/include/ord/OpenRoad.hh b/include/ord/OpenRoad.hh index 546d4803432..aa6ddfcb41c 100644 --- a/include/ord/OpenRoad.hh +++ b/include/ord/OpenRoad.hh @@ -3,8 +3,7 @@ #pragma once -#include -#include +#include #include #include @@ -231,6 +230,7 @@ class OpenRoad void read3Dbx(const std::string& filename); void write3Dbv(const std::string& filename); void write3Dbx(const std::string& filename); + void write3DbloxVerilog(const std::string& filename); void read3DBloxBMap(const std::string& filename); void check3DBlox(); diff --git a/src/OpenRoad.cc b/src/OpenRoad.cc index 0922c026b61..7cd214538ba 100644 --- a/src/OpenRoad.cc +++ b/src/OpenRoad.cc @@ -79,7 +79,6 @@ #include "rsz/MakeResizer.hh" #include "rsz/Resizer.hh" #include "sta/VerilogReader.hh" -#include "sta/VerilogWriter.hh" #include "stt/MakeSteinerTreeBuilder.h" #include "tap/MakeTapcell.h" #include "tap/tapcell.h" @@ -536,6 +535,12 @@ void OpenRoad::write3Dbx(const std::string& filename) writer.writeDbx(filename, db_->getChip()); } +void OpenRoad::write3DbloxVerilog(const std::string& filename) +{ + odb::ThreeDBlox writer(logger_, db_, sta_); + writer.writeVerilog(filename, db_->getChip()); +} + // TODO: bool hierarchy should be removed in the future. // It is retained for a while for backward compatibility. void OpenRoad::readDb(const char* filename, bool hierarchy) diff --git a/src/OpenRoad.i b/src/OpenRoad.i index b105f0cbc40..93543a153ac 100644 --- a/src/OpenRoad.i +++ b/src/OpenRoad.i @@ -404,6 +404,13 @@ write_3dbx_cmd(const char *filename) ord->write3Dbx(filename); } +void +write_3dblox_verilog_cmd(const char *filename) +{ + OpenRoad *ord = getOpenRoad(); + ord->write3DbloxVerilog(filename); +} + void read_db_cmd(const char *filename, bool hierarchy) { diff --git a/src/OpenRoad.tcl b/src/OpenRoad.tcl index 205d07ab125..4651056b62d 100644 --- a/src/OpenRoad.tcl +++ b/src/OpenRoad.tcl @@ -198,6 +198,15 @@ proc write_3dbx { args } { ord::write_3dbx_cmd $filename } +sta::define_cmd_args "write_3dblox_verilog" {filename} + +proc write_3dblox_verilog { args } { + sta::parse_key_args "write_3dblox_verilog" args keys {} flags {} + sta::check_argc_eq1 "write_3dblox_verilog" $args + set filename [file nativename [lindex $args 0]] + ord::write_3dblox_verilog_cmd $filename +} + sta::define_cmd_args "read_3dbx" {filename} proc read_3dbx { args } { diff --git a/src/odb/include/odb/3dblox.h b/src/odb/include/odb/3dblox.h index 61873bb8aa4..b6e07ff5626 100644 --- a/src/odb/include/odb/3dblox.h +++ b/src/odb/include/odb/3dblox.h @@ -46,6 +46,7 @@ class ThreeDBlox void writeDbv(const std::string& dbv_file, odb::dbChip* chip); void writeDbx(const std::string& dbx_file, odb::dbChip* chip); void writeBMap(const std::string& bmap_file, odb::dbChipRegion* region); + void writeVerilog(const std::string& verilog_file, odb::dbChip* chip); private: void createChiplet(const ChipletDef& chiplet); diff --git a/src/odb/src/3dblox/3dblox.cpp b/src/odb/src/3dblox/3dblox.cpp index 11c34ddb602..7fac6ab5ac1 100644 --- a/src/odb/src/3dblox/3dblox.cpp +++ b/src/odb/src/3dblox/3dblox.cpp @@ -37,6 +37,7 @@ #include "sta/VerilogReader.hh" #include "utl/Logger.h" #include "utl/ScopedTemporaryFile.h" +#include "verilogWriter.h" namespace odb { static std::map dup_orient_map @@ -301,10 +302,23 @@ void ThreeDBlox::writeDbx(const std::string& dbx_file, odb::dbChip* chip) writeDbv(current_dir_path + chip->getName() + ".3dbv", chip); + // Write the Verilog connectivity file for this HIER chiplet. + writeVerilog(current_dir_path + chip->getName() + ".v", chip); + DbxWriter writer(logger_, db_); writer.writeChiplet(dbx_file, chip); } +void ThreeDBlox::writeVerilog(const std::string& verilog_file, + odb::dbChip* chip) +{ + if (chip == nullptr) { + return; + } + VerilogWriter writer(logger_); + writer.writeChiplet(verilog_file, chip); +} + void ThreeDBlox::writeBMap(const std::string& bmap_file, odb::dbChipRegion* region) { diff --git a/src/odb/src/3dblox/CMakeLists.txt b/src/odb/src/3dblox/CMakeLists.txt index b6423b687de..dde022f4aa3 100644 --- a/src/odb/src/3dblox/CMakeLists.txt +++ b/src/odb/src/3dblox/CMakeLists.txt @@ -12,6 +12,7 @@ add_library(3dblox bmapWriter.cpp dbvWriter.cpp dbxWriter.cpp + verilogWriter.cpp 3dblox.cpp checker.cpp ) diff --git a/src/odb/src/3dblox/dbxWriter.cpp b/src/odb/src/3dblox/dbxWriter.cpp index c777e5a41cc..39684afd5f8 100644 --- a/src/odb/src/3dblox/dbxWriter.cpp +++ b/src/odb/src/3dblox/dbxWriter.cpp @@ -49,6 +49,8 @@ void DbxWriter::writeYamlContent(YAML::Node& root, odb::dbChip* chiplet) void DbxWriter::writeDesign(YAML::Node& design_node, odb::dbChip* chiplet) { design_node["name"] = chiplet->getName(); + YAML::Node external_node = design_node["external"]; + external_node["verilog_file"] = std::string(chiplet->getName()) + ".v"; } void DbxWriter::writeChipletInsts(YAML::Node& instances_node, diff --git a/src/odb/src/3dblox/verilogWriter.cpp b/src/odb/src/3dblox/verilogWriter.cpp new file mode 100644 index 00000000000..9b86c8eec5d --- /dev/null +++ b/src/odb/src/3dblox/verilogWriter.cpp @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2019-2025, The OpenROAD Authors + +#include "verilogWriter.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "odb/db.h" +#include "utl/Logger.h" + +namespace odb { + +VerilogWriter::VerilogWriter(utl::Logger* logger) : logger_(logger) +{ +} + +void VerilogWriter::writeChiplet(const std::string& filename, odb::dbChip* chip) +{ + std::ofstream verilog_file(filename); + if (!verilog_file.is_open()) { + logger_->error( + utl::ODB, 563, "Unable to open Verilog file for writing: {}", filename); + return; + } + + // chip_inst -> list of (port_name, net_name) + std::map>> + inst_connections; + + for (dbChipNet* net : chip->getChipNets()) { + const std::string net_name = net->getName(); + const uint32_t num_bumps = net->getNumBumpInsts(); + for (uint32_t i = 0; i < num_bumps; i++) { + std::vector path; + dbChipBumpInst* bump_inst = net->getBumpInst(i, path); + if (bump_inst == nullptr || path.size() != 1) { + continue; + } + // Only handle direct children (path length 1) — "single bump + // connections". + dbChipInst* chip_inst = path[0]; + dbChipBump* bump = bump_inst->getChipBump(); + if (bump == nullptr) { + continue; + } + dbBTerm* bterm = bump->getBTerm(); + if (bterm == nullptr) { + continue; + } + inst_connections[chip_inst].emplace_back(bterm->getName(), net_name); + } + } + + // Sort each instance's port connections alphabetically by port name. + for (std::pair>>& entry : + inst_connections) { + std::ranges::sort(entry.second); + } + + // Write module header. + fmt::print(verilog_file, "module {} ();\n", chip->getName()); + + // Collect and sort net names alphabetically for deterministic wire order. + std::vector net_names; + for (dbChipNet* net : chip->getChipNets()) { + net_names.push_back(net->getName()); + } + std::ranges::sort(net_names); + + // Write wire declarations in sorted order. + for (const std::string& name : net_names) { + fmt::print(verilog_file, " wire {};\n", name); + } + + // Collect and sort instances alphabetically by instance name. + std::vector chip_insts; + for (dbChipInst* chip_inst : chip->getChipInsts()) { + chip_insts.push_back(chip_inst); + } + std::ranges::sort(chip_insts, [](dbChipInst* a, dbChipInst* b) { + return a->getName() < b->getName(); + }); + + // Write instance declarations in sorted order. + for (dbChipInst* chip_inst : chip_insts) { + fmt::print(verilog_file, + " {} {} (\n", + chip_inst->getMasterChip()->getName(), + chip_inst->getName()); + const std::map< + dbChipInst*, + std::vector>>::const_iterator it + = inst_connections.find(chip_inst); + if (it != inst_connections.end()) { + const std::vector>& conns + = it->second; + for (size_t j = 0; j < conns.size(); j++) { + const bool is_last = (j + 1 == conns.size()); + fmt::print(verilog_file, + " .{}({}){}\n", + conns[j].first, + conns[j].second, + is_last ? "" : ","); + } + } + fmt::print(verilog_file, " );\n"); + } + + fmt::print(verilog_file, "endmodule\n"); + verilog_file.close(); +} + +} // namespace odb diff --git a/src/odb/src/3dblox/verilogWriter.h b/src/odb/src/3dblox/verilogWriter.h new file mode 100644 index 00000000000..73fe78bb5b2 --- /dev/null +++ b/src/odb/src/3dblox/verilogWriter.h @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2019-2025, The OpenROAD Authors + +#pragma once + +#include + +namespace utl { +class Logger; +} +namespace odb { +class dbChip; + +class VerilogWriter +{ + public: + VerilogWriter(utl::Logger* logger); + void writeChiplet(const std::string& filename, odb::dbChip* chip); + + private: + utl::Logger* logger_ = nullptr; +}; + +} // namespace odb diff --git a/src/odb/test/BUILD b/src/odb/test/BUILD index 74ba226a62a..ec89f70221e 100644 --- a/src/odb/test/BUILD +++ b/src/odb/test/BUILD @@ -208,6 +208,8 @@ COMPULSORY_TESTS = [ "write_cdl", "write_3dbv", "write_3dbx", + "write_3dblox_verilog", + "write_3dblox_verilog_nets", "write_def58", "write_def58_gzip", "write_lef_and_def", @@ -288,6 +290,9 @@ filegroup( "data/example2.bmap", "data/example3.bmap", "data/example4.bmap", + "data/example_nets.3dbv", + "data/example_nets.3dbx", + "data/example_nets.bmap", "data/floorplan_initialize.def", "data/floorplan_initialize.v", "data/floorplan_initialize2.def", @@ -309,6 +314,7 @@ filegroup( "data/rounding.def", "data/sky130_fd_sc_hd__inv_1.gds", "data/sky130hd_multi_patterned.def", + "data/top_nets.v", "dump_netlists.tcl", "dump_netlists_withfill.tcl", "fake_macros.def", diff --git a/src/odb/test/CMakeLists.txt b/src/odb/test/CMakeLists.txt index dd1ceda26d6..e2ef5355453 100644 --- a/src/odb/test/CMakeLists.txt +++ b/src/odb/test/CMakeLists.txt @@ -64,6 +64,8 @@ or_integration_tests( write_cdl write_3dbv write_3dbx + write_3dblox_verilog + write_3dblox_verilog_nets write_def58 write_def58_gzip write_lef_and_def diff --git a/src/odb/test/cpp/BUILD b/src/odb/test/cpp/BUILD index 979ebaf1e3e..8570130a7a5 100644 --- a/src/odb/test/cpp/BUILD +++ b/src/odb/test/cpp/BUILD @@ -257,6 +257,7 @@ cc_test( name = "Test3DBloxParser", srcs = [ "Test3DBloxParser.cpp", + "Test3DBloxVerilogWriter.cpp", ], data = [ "//src/odb/test:regression_resources", diff --git a/src/odb/test/cpp/CMakeLists.txt b/src/odb/test/cpp/CMakeLists.txt index 2b16ec39287..71bceadd96b 100644 --- a/src/odb/test/cpp/CMakeLists.txt +++ b/src/odb/test/cpp/CMakeLists.txt @@ -35,7 +35,7 @@ add_executable(TestNetTrack TestNetTrack.cpp) add_executable(TestMaster TestMaster.cpp) add_executable(TestGDSIn TestGDSIn.cpp) add_executable(TestChips TestChips.cpp) -add_executable(Test3DBloxParser Test3DBloxParser.cpp) +add_executable(Test3DBloxParser Test3DBloxParser.cpp Test3DBloxVerilogWriter.cpp) add_executable(Test3DBloxChecker Test3DBloxChecker.cpp Test3DBloxCheckerLogicalConn.cpp Test3DBloxCheckerBumps.cpp) add_executable(TestSwapMaster TestSwapMaster.cpp) add_executable(TestSwapMasterUnusedPort TestSwapMasterUnusedPort.cpp) diff --git a/src/odb/test/cpp/Test3DBloxVerilogWriter.cpp b/src/odb/test/cpp/Test3DBloxVerilogWriter.cpp new file mode 100644 index 00000000000..63190891478 --- /dev/null +++ b/src/odb/test/cpp/Test3DBloxVerilogWriter.cpp @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2023-2026, The OpenROAD Authors +// +// Tests for VerilogWriter path-length filtering: +// - bumps with path.size() == 1 (direct child) must appear in output +// - bumps with path.size() > 1 (nested child) must be silently skipped + +#include +#include +#include + +#include "gtest/gtest.h" +#include "odb/3dblox.h" +#include "odb/db.h" +#include "odb/geom.h" +#include "tst/fixture.h" + +namespace odb { +namespace { + +// Helper to read an entire file into a string. +static std::string readFileContent(const std::string& path) +{ + std::ifstream file(path); + return std::string(std::istreambuf_iterator(file), + std::istreambuf_iterator()); +} + +class VerilogWriterFixture : public tst::Fixture +{ + protected: + VerilogWriterFixture() + { + tech_ = dbTech::create(db_.get(), "tech"); + dbTechLayer::create(tech_, "layer1", dbTechLayerType::ROUTING); + + // HIER top chip (the module being written). + top_chip_ + = dbChip::create(db_.get(), nullptr, "TopChip", dbChip::ChipType::HIER); + + // DIE chip used as the master for instances. + chip1_ = dbChip::create(db_.get(), tech_, "Chip1", dbChip::ChipType::DIE); + chip1_->setWidth(2000); + chip1_->setHeight(2000); + chip1_->setThickness(500); + dbBlock::create(chip1_, "block1"); + + // A second DIE chip, only needed to form multi-element path vectors. + chip2_ = dbChip::create(db_.get(), tech_, "Chip2", dbChip::ChipType::DIE); + chip2_->setWidth(1500); + chip2_->setHeight(1500); + chip2_->setThickness(500); + dbBlock::create(chip2_, "block2"); + + // Front region on chip1 where bumps will be placed. + dbChipRegion* r1_fr = dbChipRegion::create( + chip1_, "r1_fr", dbChipRegion::Side::FRONT, nullptr); + r1_fr->setBox(Rect(0, 0, 2000, 2000)); + + // Shared bump master for physical bump cells. + lib_ = dbLib::create(db_.get(), "bump_lib", tech_, ','); + bump_master_ = dbMaster::create(lib_, "bump_pad"); + bump_master_->setWidth(100); + bump_master_->setHeight(100); + bump_master_->setType(dbMasterType::CORE); + dbMTerm::create(bump_master_, "pad", dbIoType::INOUT, dbSigType::SIGNAL); + bump_master_->setFrozen(); + } + + // Create a bump on a chip region and attach a named BTerm (Verilog port). + // Must be called BEFORE creating any dbChipInst that uses this chip, + // so the bump inst is propagated into the region inst at create time. + dbChipBump* createBump(dbChip* chip, + dbChipRegion* region, + const char* bump_name, + int x, + int y) + { + dbBlock* block = chip->getBlock(); + dbTechLayer* layer = tech_->findLayer("layer1"); + + // Physical placement cell for the bump. + dbInst* inst = dbInst::create(block, bump_master_, bump_name); + inst->setOrigin(x, y); + inst->setPlacementStatus(dbPlacementStatus::PLACED); + + // Chip-level bump object. + dbChipBump* chip_bump = dbChipBump::create(region, inst); + + // Net + BTerm — the BTerm name becomes the Verilog port name. + const std::string net_name = std::string(bump_name) + "_net"; + dbNet* net = dbNet::create(block, net_name.c_str()); + dbBTerm* bterm = dbBTerm::create(net, bump_name); + bterm->setIoType(dbIoType::INOUT); + + // BPin geometry required for placement checks. + dbBPin* bpin = dbBPin::create(bterm); + bpin->setPlacementStatus(dbPlacementStatus::PLACED); + dbBox::create(bpin, layer, x, y, x + 100, y + 100); + + chip_bump->setNet(net); + chip_bump->setBTerm(bterm); + return chip_bump; + } + + // Write the top chip's Verilog to a fixed temp file and return the path. + std::string writeVerilog() + { + const std::string filename = "/tmp/odb_test_verilog_writer.v"; + ThreeDBlox writer(&logger_, db_.get()); + writer.writeVerilog(filename, top_chip_); + return filename; + } + + dbTech* tech_; + dbChip* top_chip_; + dbChip* chip1_; + dbChip* chip2_; + dbLib* lib_; + dbMaster* bump_master_; +}; + +// A bump registered with path.size() == 1 (direct child of the HIER chip) +// must produce a port connection in the Verilog output. +TEST_F(VerilogWriterFixture, test_direct_child_written) +{ + // Create bump BEFORE the chip inst so it is propagated into the region inst. + dbChipRegion* r1_fr = chip1_->findChipRegion("r1_fr"); + createBump(chip1_, r1_fr, "port_a", 100, 100); + + dbChipInst* inst1 = dbChipInst::create(top_chip_, chip1_, "inst1"); + inst1->setLoc(Point3D(0, 0, 0)); + inst1->setOrient(dbOrientType3D(dbOrientType::R0, false)); + + // Retrieve the bump inst auto-created on the region inst. + dbChipRegionInst* ri1 = inst1->findChipRegionInst("r1_fr"); + ASSERT_NE(ri1, nullptr); + dbChipBumpInst* bump_inst = *ri1->getChipBumpInsts().begin(); + ASSERT_NE(bump_inst, nullptr); + + // Wire the bump to a net via a direct (path length 1) path. + dbChipNet* chip_net = dbChipNet::create(top_chip_, "net_signal"); + chip_net->addBumpInst(bump_inst, {inst1}); + + const std::string filename = writeVerilog(); + const std::string content = readFileContent(filename); + + // The port connection must appear in the output. + EXPECT_NE(content.find(".port_a(net_signal)"), std::string::npos); +} + +// A bump registered with path.size() > 1 (nested child) must be silently +// skipped; no port connection should appear in the Verilog output. +TEST_F(VerilogWriterFixture, test_nested_child_skipped) +{ + // Create bump BEFORE the chip inst so it is propagated into the region inst. + dbChipRegion* r1_fr = chip1_->findChipRegion("r1_fr"); + createBump(chip1_, r1_fr, "port_b", 200, 200); + + dbChipInst* inst1 = dbChipInst::create(top_chip_, chip1_, "inst1"); + inst1->setLoc(Point3D(0, 0, 0)); + inst1->setOrient(dbOrientType3D(dbOrientType::R0, false)); + + // inst2 is used only to form a path vector of length 2. + dbChipInst* inst2 = dbChipInst::create(top_chip_, chip2_, "inst2"); + inst2->setLoc(Point3D(0, 0, 500)); + inst2->setOrient(dbOrientType3D(dbOrientType::R0, false)); + + dbChipRegionInst* ri1 = inst1->findChipRegionInst("r1_fr"); + ASSERT_NE(ri1, nullptr); + dbChipBumpInst* bump_inst = *ri1->getChipBumpInsts().begin(); + ASSERT_NE(bump_inst, nullptr); + + // Path of length 2 — nested child; writer must skip this bump. + dbChipNet* chip_net = dbChipNet::create(top_chip_, "net_deep"); + chip_net->addBumpInst(bump_inst, {inst1, inst2}); + + const std::string filename = writeVerilog(); + const std::string content = readFileContent(filename); + + // No port connection should appear for the skipped bump. + EXPECT_EQ(content.find(".port_b"), std::string::npos); +} + +} // namespace +} // namespace odb diff --git a/src/odb/test/data/example_nets.3dbv b/src/odb/test/data/example_nets.3dbv new file mode 100644 index 00000000000..8d1eaa485ee --- /dev/null +++ b/src/odb/test/data/example_nets.3dbv @@ -0,0 +1,36 @@ + +#!define NG45_PATH ../Nangate45 + +Header: + version: 2.5 + unit: micron + precision: 2000 + +ChipletDef: + SoC: + type: die + design_area: [955, 1082] + shrink: 1 + tsv: false + thickness: 300 + offset: [0, 0] + cad_layer: + 108;101: + type: design_area + regions: + front_reg: + side: front + back_reg: + side: back + coords: + - [0, 0] + - [955, 0] + - [955, 1082] + - [0, 1082] + bmap: example_nets.bmap + layer: metal1 + external: + APR_tech_file: [NG45_PATH/*_tech.lef] + liberty_file: [NG45_PATH/fake_macros.lib] + LEF_file: [NG45_PATH/fake_macros.lef, NG45_PATH/fake_bumps.lef] + DEF_file: ../fake_macros.def diff --git a/src/odb/test/data/example_nets.3dbx b/src/odb/test/data/example_nets.3dbx new file mode 100644 index 00000000000..603721403ec --- /dev/null +++ b/src/odb/test/data/example_nets.3dbx @@ -0,0 +1,45 @@ +Header: + version: "1.0" + unit: "micron" + precision: 2000 + include: + - example_nets.3dbv + +Design: + name: "TopDesign" + external: + verilog_file: "top_nets.v" + +ChipletInst: + soc_inst: + reference: SoC + external: + verilog_file: "soc.v" + sdc_file: "/path/to/soc.sdc" + def_file: "/path/to/soc.def" + soc_inst_duplicate: + reference: SoC + external: + verilog_file: "soc.v" + sdc_file: "/path/to/soc.sdc" + def_file: "/path/to/soc.def" + +Stack: + soc_inst: + loc: [100.0, 200.0] + z: 0.0 + orient: R0 + soc_inst_duplicate: + loc: [100.0, 200.0] + z: 300.0 + orient: MZ + +Connection: + soc_to_soc: + top: soc_inst_duplicate.regions.front_reg + bot: soc_inst.regions.front_reg + thickness: 0.0 + soc_to_virtual: + top: soc_inst.regions.back_reg + bot: ~ + thickness: 0.0 diff --git a/src/odb/test/data/example_nets.bmap b/src/odb/test/data/example_nets.bmap new file mode 100644 index 00000000000..a8d88425fc7 --- /dev/null +++ b/src/odb/test/data/example_nets.bmap @@ -0,0 +1,2 @@ +bump1 BUMP 100.0 200.0 clk clk +bump2 BUMP 150.0 200.0 data data diff --git a/src/odb/test/data/top_nets.v b/src/odb/test/data/top_nets.v new file mode 100644 index 00000000000..209e4e2cb6e --- /dev/null +++ b/src/odb/test/data/top_nets.v @@ -0,0 +1,12 @@ +module TopDesign (); + wire clk; + wire data; + SoC soc_inst ( + .clk(clk), + .data(data) + ); + SoC soc_inst_duplicate ( + .clk(clk), + .data(data) + ); +endmodule diff --git a/src/odb/test/write_3dblox_verilog.ok b/src/odb/test/write_3dblox_verilog.ok new file mode 100644 index 00000000000..356d528d0e1 --- /dev/null +++ b/src/odb/test/write_3dblox_verilog.ok @@ -0,0 +1,9 @@ +[INFO ODB-0227] LEF file: data/../Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias +[INFO ODB-0227] LEF file: data/../Nangate45/fake_macros.lef, created 10 library cells +[INFO ODB-0227] LEF file: data/../Nangate45/fake_bumps.lef, created 1 library cells +[WARNING STA-1171] data/../Nangate45/fake_macros.lib line 32, default_max_transition is 0.0. +[INFO ODB-0128] Design: fake_macros +[INFO ODB-0131] Created 10 components and 32 component-terminals. +[INFO ODB-0133] Created 12 nets and 24 connections. +No differences found. +pass diff --git a/src/odb/test/write_3dblox_verilog.tcl b/src/odb/test/write_3dblox_verilog.tcl new file mode 100644 index 00000000000..0ebf16fcff2 --- /dev/null +++ b/src/odb/test/write_3dblox_verilog.tcl @@ -0,0 +1,10 @@ +source "helpers.tcl" + +read_3dbx "data/example.3dbx" +set out_v [make_result_file "write_3dblox_verilog/out.v"] +write_3dblox_verilog $out_v + +diff_files $out_v "write_3dblox_verilog.vok" + +puts "pass" +exit 0 diff --git a/src/odb/test/write_3dblox_verilog.vok b/src/odb/test/write_3dblox_verilog.vok new file mode 100644 index 00000000000..d2627dc811c --- /dev/null +++ b/src/odb/test/write_3dblox_verilog.vok @@ -0,0 +1,6 @@ +module TopDesign (); + SoC soc_inst ( + ); + SoC soc_inst_duplicate ( + ); +endmodule diff --git a/src/odb/test/write_3dblox_verilog_nets.ok b/src/odb/test/write_3dblox_verilog_nets.ok new file mode 100644 index 00000000000..07cc7b0213f --- /dev/null +++ b/src/odb/test/write_3dblox_verilog_nets.ok @@ -0,0 +1,10 @@ +[INFO ODB-0227] LEF file: data/../Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias +[INFO ODB-0227] LEF file: data/../Nangate45/fake_macros.lef, created 10 library cells +[INFO ODB-0227] LEF file: data/../Nangate45/fake_bumps.lef, created 1 library cells +[WARNING STA-1171] data/../Nangate45/fake_macros.lib line 32, default_max_transition is 0.0. +[INFO ODB-0128] Design: fake_macros +[INFO ODB-0131] Created 10 components and 32 component-terminals. +[INFO ODB-0133] Created 12 nets and 24 connections. +[WARNING STA-0198] data/top_nets.v line 4, module SoC not found. Creating black box for soc_inst. +No differences found. +pass diff --git a/src/odb/test/write_3dblox_verilog_nets.tcl b/src/odb/test/write_3dblox_verilog_nets.tcl new file mode 100644 index 00000000000..47e7956de8f --- /dev/null +++ b/src/odb/test/write_3dblox_verilog_nets.tcl @@ -0,0 +1,10 @@ +source "helpers.tcl" + +read_3dbx "data/example_nets.3dbx" +set out_v [make_result_file "write_3dblox_verilog_nets/out.v"] +write_3dblox_verilog $out_v + +diff_files $out_v "write_3dblox_verilog_nets.vok" + +puts "pass" +exit 0 diff --git a/src/odb/test/write_3dblox_verilog_nets.vok b/src/odb/test/write_3dblox_verilog_nets.vok new file mode 100644 index 00000000000..209e4e2cb6e --- /dev/null +++ b/src/odb/test/write_3dblox_verilog_nets.vok @@ -0,0 +1,12 @@ +module TopDesign (); + wire clk; + wire data; + SoC soc_inst ( + .clk(clk), + .data(data) + ); + SoC soc_inst_duplicate ( + .clk(clk), + .data(data) + ); +endmodule diff --git a/src/odb/test/write_3dbx.3dbxok b/src/odb/test/write_3dbx.3dbxok index 89a2e28b8d7..f3725612e82 100644 --- a/src/odb/test/write_3dbx.3dbxok +++ b/src/odb/test/write_3dbx.3dbxok @@ -6,6 +6,8 @@ Header: - TopDesign.3dbv Design: name: TopDesign + external: + verilog_file: TopDesign.v ChipletInst: soc_inst_duplicate: reference: SoC From 9eab18a5e2bf33bfa5b639eb2d6afaf50417a4fb Mon Sep 17 00:00:00 2001 From: "Ahmed R. Mohamed" Date: Mon, 23 Mar 2026 17:31:40 +0000 Subject: [PATCH 2/3] odb: fix 3dblox verilog writer PR comments Signed-off-by: Ahmed R. Mohamed --- include/ord/OpenRoad.hh | 1 - src/odb/src/3dblox/verilogWriter.cpp | 5 +---- src/odb/test/cpp/BUILD | 20 +++++++++++++++++++- src/odb/test/cpp/CMakeLists.txt | 5 ++++- 4 files changed, 24 insertions(+), 7 deletions(-) diff --git a/include/ord/OpenRoad.hh b/include/ord/OpenRoad.hh index aa6ddfcb41c..fde9766d50a 100644 --- a/include/ord/OpenRoad.hh +++ b/include/ord/OpenRoad.hh @@ -3,7 +3,6 @@ #pragma once -#include #include #include diff --git a/src/odb/src/3dblox/verilogWriter.cpp b/src/odb/src/3dblox/verilogWriter.cpp index 9b86c8eec5d..e2e183e1913 100644 --- a/src/odb/src/3dblox/verilogWriter.cpp +++ b/src/odb/src/3dblox/verilogWriter.cpp @@ -95,10 +95,7 @@ void VerilogWriter::writeChiplet(const std::string& filename, odb::dbChip* chip) " {} {} (\n", chip_inst->getMasterChip()->getName(), chip_inst->getName()); - const std::map< - dbChipInst*, - std::vector>>::const_iterator it - = inst_connections.find(chip_inst); + auto it = inst_connections.find(chip_inst); if (it != inst_connections.end()) { const std::vector>& conns = it->second; diff --git a/src/odb/test/cpp/BUILD b/src/odb/test/cpp/BUILD index 8570130a7a5..6d5fa2e2bdc 100644 --- a/src/odb/test/cpp/BUILD +++ b/src/odb/test/cpp/BUILD @@ -257,7 +257,6 @@ cc_test( name = "Test3DBloxParser", srcs = [ "Test3DBloxParser.cpp", - "Test3DBloxVerilogWriter.cpp", ], data = [ "//src/odb/test:regression_resources", @@ -294,6 +293,25 @@ cc_test( ], ) +cc_test( + name = "Test3DBloxVerilogWriter", + srcs = [ + "Test3DBloxVerilogWriter.cpp", + ], + data = [ + "//src/odb/test:regression_resources", + ], + deps = [ + "//src/odb", + "//src/odb/test/cpp/helper", + "//src/tst", + "//src/tst:nangate45_fixture", + "//src/utl", + "@googletest//:gtest", + "@googletest//:gtest_main", + ], +) + cc_test( name = "TestWriteReadDbHier", srcs = [ diff --git a/src/odb/test/cpp/CMakeLists.txt b/src/odb/test/cpp/CMakeLists.txt index 71bceadd96b..f4f9c231aac 100644 --- a/src/odb/test/cpp/CMakeLists.txt +++ b/src/odb/test/cpp/CMakeLists.txt @@ -35,8 +35,9 @@ add_executable(TestNetTrack TestNetTrack.cpp) add_executable(TestMaster TestMaster.cpp) add_executable(TestGDSIn TestGDSIn.cpp) add_executable(TestChips TestChips.cpp) -add_executable(Test3DBloxParser Test3DBloxParser.cpp Test3DBloxVerilogWriter.cpp) +add_executable(Test3DBloxParser Test3DBloxParser.cpp) add_executable(Test3DBloxChecker Test3DBloxChecker.cpp Test3DBloxCheckerLogicalConn.cpp Test3DBloxCheckerBumps.cpp) +add_executable(Test3DBloxVerilogWriter Test3DBloxVerilogWriter.cpp) add_executable(TestSwapMaster TestSwapMaster.cpp) add_executable(TestSwapMasterUnusedPort TestSwapMasterUnusedPort.cpp) add_executable(TestWriteReadDbHier TestWriteReadDbHier.cpp) @@ -58,6 +59,7 @@ target_link_libraries(TestGDSIn ${TEST_LIBS}) target_link_libraries(TestChips ${TEST_LIBS}) target_link_libraries(Test3DBloxParser ${TEST_LIBS}) target_link_libraries(Test3DBloxChecker ${TEST_LIBS}) +target_link_libraries(Test3DBloxVerilogWriter ${TEST_LIBS}) target_link_libraries(TestSwapMaster ${TEST_LIBS}) target_link_libraries(TestSwapMasterUnusedPort ${TEST_LIBS}) target_link_libraries(TestWriteReadDbHier ${TEST_LIBS}) @@ -87,6 +89,7 @@ add_dependencies(build_and_test TestChips Test3DBloxParser Test3DBloxChecker + Test3DBloxVerilogWriter TestSwapMaster TestSwapMasterUnusedPort TestWriteReadDbHier From ac2e2abb035afc104332c70e6b76d3f7dff2e313 Mon Sep 17 00:00:00 2001 From: "Ahmed R. Mohamed" Date: Thu, 26 Mar 2026 19:36:17 +0000 Subject: [PATCH 3/3] odb: fix 3dblox verilog writer PR comments Remove standalone tcl command Signed-off-by: Ahmed R. Mohamed --- include/ord/OpenRoad.hh | 1 - src/OpenRoad.cc | 6 --- src/OpenRoad.i | 7 ---- src/OpenRoad.tcl | 9 ----- src/odb/test/BUILD | 6 --- src/odb/test/CMakeLists.txt | 2 - src/odb/test/data/example_nets.3dbv | 36 ----------------- src/odb/test/data/example_nets.3dbx | 45 ---------------------- src/odb/test/data/example_nets.bmap | 2 - src/odb/test/data/top_nets.v | 12 ------ src/odb/test/write_3dblox_verilog.ok | 9 ----- src/odb/test/write_3dblox_verilog.tcl | 10 ----- src/odb/test/write_3dblox_verilog.vok | 6 --- src/odb/test/write_3dblox_verilog_nets.ok | 10 ----- src/odb/test/write_3dblox_verilog_nets.tcl | 10 ----- src/odb/test/write_3dblox_verilog_nets.vok | 12 ------ 16 files changed, 183 deletions(-) delete mode 100644 src/odb/test/data/example_nets.3dbv delete mode 100644 src/odb/test/data/example_nets.3dbx delete mode 100644 src/odb/test/data/example_nets.bmap delete mode 100644 src/odb/test/data/top_nets.v delete mode 100644 src/odb/test/write_3dblox_verilog.ok delete mode 100644 src/odb/test/write_3dblox_verilog.tcl delete mode 100644 src/odb/test/write_3dblox_verilog.vok delete mode 100644 src/odb/test/write_3dblox_verilog_nets.ok delete mode 100644 src/odb/test/write_3dblox_verilog_nets.tcl delete mode 100644 src/odb/test/write_3dblox_verilog_nets.vok diff --git a/include/ord/OpenRoad.hh b/include/ord/OpenRoad.hh index fde9766d50a..35b6ad067a1 100644 --- a/include/ord/OpenRoad.hh +++ b/include/ord/OpenRoad.hh @@ -229,7 +229,6 @@ class OpenRoad void read3Dbx(const std::string& filename); void write3Dbv(const std::string& filename); void write3Dbx(const std::string& filename); - void write3DbloxVerilog(const std::string& filename); void read3DBloxBMap(const std::string& filename); void check3DBlox(); diff --git a/src/OpenRoad.cc b/src/OpenRoad.cc index 7cd214538ba..eef476375e0 100644 --- a/src/OpenRoad.cc +++ b/src/OpenRoad.cc @@ -535,12 +535,6 @@ void OpenRoad::write3Dbx(const std::string& filename) writer.writeDbx(filename, db_->getChip()); } -void OpenRoad::write3DbloxVerilog(const std::string& filename) -{ - odb::ThreeDBlox writer(logger_, db_, sta_); - writer.writeVerilog(filename, db_->getChip()); -} - // TODO: bool hierarchy should be removed in the future. // It is retained for a while for backward compatibility. void OpenRoad::readDb(const char* filename, bool hierarchy) diff --git a/src/OpenRoad.i b/src/OpenRoad.i index 93543a153ac..b105f0cbc40 100644 --- a/src/OpenRoad.i +++ b/src/OpenRoad.i @@ -404,13 +404,6 @@ write_3dbx_cmd(const char *filename) ord->write3Dbx(filename); } -void -write_3dblox_verilog_cmd(const char *filename) -{ - OpenRoad *ord = getOpenRoad(); - ord->write3DbloxVerilog(filename); -} - void read_db_cmd(const char *filename, bool hierarchy) { diff --git a/src/OpenRoad.tcl b/src/OpenRoad.tcl index 4651056b62d..205d07ab125 100644 --- a/src/OpenRoad.tcl +++ b/src/OpenRoad.tcl @@ -198,15 +198,6 @@ proc write_3dbx { args } { ord::write_3dbx_cmd $filename } -sta::define_cmd_args "write_3dblox_verilog" {filename} - -proc write_3dblox_verilog { args } { - sta::parse_key_args "write_3dblox_verilog" args keys {} flags {} - sta::check_argc_eq1 "write_3dblox_verilog" $args - set filename [file nativename [lindex $args 0]] - ord::write_3dblox_verilog_cmd $filename -} - sta::define_cmd_args "read_3dbx" {filename} proc read_3dbx { args } { diff --git a/src/odb/test/BUILD b/src/odb/test/BUILD index ec89f70221e..74ba226a62a 100644 --- a/src/odb/test/BUILD +++ b/src/odb/test/BUILD @@ -208,8 +208,6 @@ COMPULSORY_TESTS = [ "write_cdl", "write_3dbv", "write_3dbx", - "write_3dblox_verilog", - "write_3dblox_verilog_nets", "write_def58", "write_def58_gzip", "write_lef_and_def", @@ -290,9 +288,6 @@ filegroup( "data/example2.bmap", "data/example3.bmap", "data/example4.bmap", - "data/example_nets.3dbv", - "data/example_nets.3dbx", - "data/example_nets.bmap", "data/floorplan_initialize.def", "data/floorplan_initialize.v", "data/floorplan_initialize2.def", @@ -314,7 +309,6 @@ filegroup( "data/rounding.def", "data/sky130_fd_sc_hd__inv_1.gds", "data/sky130hd_multi_patterned.def", - "data/top_nets.v", "dump_netlists.tcl", "dump_netlists_withfill.tcl", "fake_macros.def", diff --git a/src/odb/test/CMakeLists.txt b/src/odb/test/CMakeLists.txt index e2ef5355453..dd1ceda26d6 100644 --- a/src/odb/test/CMakeLists.txt +++ b/src/odb/test/CMakeLists.txt @@ -64,8 +64,6 @@ or_integration_tests( write_cdl write_3dbv write_3dbx - write_3dblox_verilog - write_3dblox_verilog_nets write_def58 write_def58_gzip write_lef_and_def diff --git a/src/odb/test/data/example_nets.3dbv b/src/odb/test/data/example_nets.3dbv deleted file mode 100644 index 8d1eaa485ee..00000000000 --- a/src/odb/test/data/example_nets.3dbv +++ /dev/null @@ -1,36 +0,0 @@ - -#!define NG45_PATH ../Nangate45 - -Header: - version: 2.5 - unit: micron - precision: 2000 - -ChipletDef: - SoC: - type: die - design_area: [955, 1082] - shrink: 1 - tsv: false - thickness: 300 - offset: [0, 0] - cad_layer: - 108;101: - type: design_area - regions: - front_reg: - side: front - back_reg: - side: back - coords: - - [0, 0] - - [955, 0] - - [955, 1082] - - [0, 1082] - bmap: example_nets.bmap - layer: metal1 - external: - APR_tech_file: [NG45_PATH/*_tech.lef] - liberty_file: [NG45_PATH/fake_macros.lib] - LEF_file: [NG45_PATH/fake_macros.lef, NG45_PATH/fake_bumps.lef] - DEF_file: ../fake_macros.def diff --git a/src/odb/test/data/example_nets.3dbx b/src/odb/test/data/example_nets.3dbx deleted file mode 100644 index 603721403ec..00000000000 --- a/src/odb/test/data/example_nets.3dbx +++ /dev/null @@ -1,45 +0,0 @@ -Header: - version: "1.0" - unit: "micron" - precision: 2000 - include: - - example_nets.3dbv - -Design: - name: "TopDesign" - external: - verilog_file: "top_nets.v" - -ChipletInst: - soc_inst: - reference: SoC - external: - verilog_file: "soc.v" - sdc_file: "/path/to/soc.sdc" - def_file: "/path/to/soc.def" - soc_inst_duplicate: - reference: SoC - external: - verilog_file: "soc.v" - sdc_file: "/path/to/soc.sdc" - def_file: "/path/to/soc.def" - -Stack: - soc_inst: - loc: [100.0, 200.0] - z: 0.0 - orient: R0 - soc_inst_duplicate: - loc: [100.0, 200.0] - z: 300.0 - orient: MZ - -Connection: - soc_to_soc: - top: soc_inst_duplicate.regions.front_reg - bot: soc_inst.regions.front_reg - thickness: 0.0 - soc_to_virtual: - top: soc_inst.regions.back_reg - bot: ~ - thickness: 0.0 diff --git a/src/odb/test/data/example_nets.bmap b/src/odb/test/data/example_nets.bmap deleted file mode 100644 index a8d88425fc7..00000000000 --- a/src/odb/test/data/example_nets.bmap +++ /dev/null @@ -1,2 +0,0 @@ -bump1 BUMP 100.0 200.0 clk clk -bump2 BUMP 150.0 200.0 data data diff --git a/src/odb/test/data/top_nets.v b/src/odb/test/data/top_nets.v deleted file mode 100644 index 209e4e2cb6e..00000000000 --- a/src/odb/test/data/top_nets.v +++ /dev/null @@ -1,12 +0,0 @@ -module TopDesign (); - wire clk; - wire data; - SoC soc_inst ( - .clk(clk), - .data(data) - ); - SoC soc_inst_duplicate ( - .clk(clk), - .data(data) - ); -endmodule diff --git a/src/odb/test/write_3dblox_verilog.ok b/src/odb/test/write_3dblox_verilog.ok deleted file mode 100644 index 356d528d0e1..00000000000 --- a/src/odb/test/write_3dblox_verilog.ok +++ /dev/null @@ -1,9 +0,0 @@ -[INFO ODB-0227] LEF file: data/../Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias -[INFO ODB-0227] LEF file: data/../Nangate45/fake_macros.lef, created 10 library cells -[INFO ODB-0227] LEF file: data/../Nangate45/fake_bumps.lef, created 1 library cells -[WARNING STA-1171] data/../Nangate45/fake_macros.lib line 32, default_max_transition is 0.0. -[INFO ODB-0128] Design: fake_macros -[INFO ODB-0131] Created 10 components and 32 component-terminals. -[INFO ODB-0133] Created 12 nets and 24 connections. -No differences found. -pass diff --git a/src/odb/test/write_3dblox_verilog.tcl b/src/odb/test/write_3dblox_verilog.tcl deleted file mode 100644 index 0ebf16fcff2..00000000000 --- a/src/odb/test/write_3dblox_verilog.tcl +++ /dev/null @@ -1,10 +0,0 @@ -source "helpers.tcl" - -read_3dbx "data/example.3dbx" -set out_v [make_result_file "write_3dblox_verilog/out.v"] -write_3dblox_verilog $out_v - -diff_files $out_v "write_3dblox_verilog.vok" - -puts "pass" -exit 0 diff --git a/src/odb/test/write_3dblox_verilog.vok b/src/odb/test/write_3dblox_verilog.vok deleted file mode 100644 index d2627dc811c..00000000000 --- a/src/odb/test/write_3dblox_verilog.vok +++ /dev/null @@ -1,6 +0,0 @@ -module TopDesign (); - SoC soc_inst ( - ); - SoC soc_inst_duplicate ( - ); -endmodule diff --git a/src/odb/test/write_3dblox_verilog_nets.ok b/src/odb/test/write_3dblox_verilog_nets.ok deleted file mode 100644 index 07cc7b0213f..00000000000 --- a/src/odb/test/write_3dblox_verilog_nets.ok +++ /dev/null @@ -1,10 +0,0 @@ -[INFO ODB-0227] LEF file: data/../Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias -[INFO ODB-0227] LEF file: data/../Nangate45/fake_macros.lef, created 10 library cells -[INFO ODB-0227] LEF file: data/../Nangate45/fake_bumps.lef, created 1 library cells -[WARNING STA-1171] data/../Nangate45/fake_macros.lib line 32, default_max_transition is 0.0. -[INFO ODB-0128] Design: fake_macros -[INFO ODB-0131] Created 10 components and 32 component-terminals. -[INFO ODB-0133] Created 12 nets and 24 connections. -[WARNING STA-0198] data/top_nets.v line 4, module SoC not found. Creating black box for soc_inst. -No differences found. -pass diff --git a/src/odb/test/write_3dblox_verilog_nets.tcl b/src/odb/test/write_3dblox_verilog_nets.tcl deleted file mode 100644 index 47e7956de8f..00000000000 --- a/src/odb/test/write_3dblox_verilog_nets.tcl +++ /dev/null @@ -1,10 +0,0 @@ -source "helpers.tcl" - -read_3dbx "data/example_nets.3dbx" -set out_v [make_result_file "write_3dblox_verilog_nets/out.v"] -write_3dblox_verilog $out_v - -diff_files $out_v "write_3dblox_verilog_nets.vok" - -puts "pass" -exit 0 diff --git a/src/odb/test/write_3dblox_verilog_nets.vok b/src/odb/test/write_3dblox_verilog_nets.vok deleted file mode 100644 index 209e4e2cb6e..00000000000 --- a/src/odb/test/write_3dblox_verilog_nets.vok +++ /dev/null @@ -1,12 +0,0 @@ -module TopDesign (); - wire clk; - wire data; - SoC soc_inst ( - .clk(clk), - .data(data) - ); - SoC soc_inst_duplicate ( - .clk(clk), - .data(data) - ); -endmodule