The ram module currently does not support column muxing, which is very useful for both 1) changing the aspect ratio of the generated RAM and 2) optimizing the timing of the circuit when words >> bits.
This feature should add a new optional flag -column_mux_ratio to generate_ram. If the flag is not specified, the column/mux ratio should be 1, which results in the current behavior.
The valid values for the ratio should be any power of 2, as long as it is less than the total number of words. In practice, only 1, 2, 4, and maybe 8 would typically be used. It is fine to mark larger ratios as unsupported.
Muxes should be constructed using as few standard cells as possible, likely using an AOI gate and inverters (see e.g. page 13 on these slides)
The muxes should be added to the top row(s) of the ram near the Q outputs. 2:1 muxes should be simple. For each pair of columns, there should be a single AOI and an inverter to mux the output. There will also need to be a single inverter for the whole array to create the inverted select signal for all muxes.
The ram module currently does not support column muxing, which is very useful for both 1) changing the aspect ratio of the generated RAM and 2) optimizing the timing of the circuit when words >> bits.
This feature should add a new optional flag
-column_mux_ratiotogenerate_ram. If the flag is not specified, the column/mux ratio should be 1, which results in the current behavior.The valid values for the ratio should be any power of 2, as long as it is less than the total number of words. In practice, only 1, 2, 4, and maybe 8 would typically be used. It is fine to mark larger ratios as unsupported.
Muxes should be constructed using as few standard cells as possible, likely using an AOI gate and inverters (see e.g. page 13 on these slides)
The muxes should be added to the top row(s) of the ram near the Q outputs. 2:1 muxes should be simple. For each pair of columns, there should be a single AOI and an inverter to mux the output. There will also need to be a single inverter for the whole array to create the inverted select signal for all muxes.