From 6127dd05f4a2eadb12685db1cd0f12f11729bfc8 Mon Sep 17 00:00:00 2001 From: Cam Quilici Date: Thu, 18 Jun 2026 17:21:31 -0500 Subject: [PATCH 1/5] chore: update MiniMax M3 B200 image --- .github/configs/nvidia-master.yaml | 4 ++-- benchmarks/single_node/fixed_seq_len/minimaxm3_fp8_b200.sh | 5 ++++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/.github/configs/nvidia-master.yaml b/.github/configs/nvidia-master.yaml index 521ba6636..d9dbffc7f 100644 --- a/.github/configs/nvidia-master.yaml +++ b/.github/configs/nvidia-master.yaml @@ -12948,13 +12948,13 @@ minimaxm3-fp8-b300-vllm: # 427B total / 26B active MoE with MSA sparse attention; MXFP8 checkpoint # (MiniMaxAI/MiniMax-M3-MXFP8, ~444 GB) quantized by NVIDIA — native MX tensor # cores on Blackwell. M3 support has not shipped in a stable vLLM release; -# the dedicated vllm/vllm-openai:minimax-m3 image is built from the m3_release +# the dedicated vllm/vllm-openai:minimax-m3-0618 image is built from the m3_release # branch (vllm-project/vllm#45381). --block-size 128 is mandatory (MSA # sparse/index cache alignment). Weights are NOT SRE-staged: b200-dgxc reads # /lustre/fsw/gharunners/models/MiniMax-M3-MXFP8 (pre-downloaded, see # launch_b200-dgxc.sh). minimaxm3-fp8-b200-vllm: - image: vllm/vllm-openai:minimax-m3 + image: vllm/vllm-openai:minimax-m3-0618 model: MiniMaxAI/MiniMax-M3-MXFP8 model-prefix: minimaxm3 runner: b200-dgxc diff --git a/benchmarks/single_node/fixed_seq_len/minimaxm3_fp8_b200.sh b/benchmarks/single_node/fixed_seq_len/minimaxm3_fp8_b200.sh index 16041a2ea..9c901a9bd 100755 --- a/benchmarks/single_node/fixed_seq_len/minimaxm3_fp8_b200.sh +++ b/benchmarks/single_node/fixed_seq_len/minimaxm3_fp8_b200.sh @@ -45,7 +45,7 @@ if [ "${DP_ATTENTION}" = "true" ]; then elif [ "$EP_SIZE" -gt 1 ]; then PARALLEL_ARGS="--tensor-parallel-size=$TP --enable-expert-parallel" else - PARALLEL_ARGS="--tensor-parallel-size=$TP --moe-backend marlin" + PARALLEL_ARGS="--tensor-parallel-size=$TP" fi if [ "${EVAL_ONLY}" = "true" ]; then @@ -61,6 +61,9 @@ $PARALLEL_ARGS \ --gpu-memory-utilization 0.90 \ --max-model-len $MAX_MODEL_LEN \ --block-size 128 \ +--attention-config '{"backend": "FLASHINFER", "use_trtllm_attention": true}' \ +--attention-config.indexer_kv_dtype "fp8" \ +--kv-cache-dtype fp8 \ --language-model-only \ --max-cudagraph-capture-size 2048 \ --max-num-batched-tokens "$((ISL * 2 ))" \ From 25fd1ba660a8ae33065bd3a5c09eb782493d28f0 Mon Sep 17 00:00:00 2001 From: Cam Quilici Date: Thu, 18 Jun 2026 17:22:29 -0500 Subject: [PATCH 2/5] chore: register MiniMax M3 image bump --- perf-changelog.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/perf-changelog.yaml b/perf-changelog.yaml index 06a81eaf1..251ff6c44 100644 --- a/perf-changelog.yaml +++ b/perf-changelog.yaml @@ -3950,3 +3950,11 @@ - "Update ISL=8192 search-space: TP8-only from conc=4-64, DPA from conc=128-1024 (previously conc=1-64 and DPA conc=64-512)" - "Update Applied TBO on high concurrencies" pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/1717 + +- config-keys: + - minimaxm3-fp8-b200-vllm + description: + - "Update the MiniMax-M3 B200 single-node image to vllm/vllm-openai:minimax-m3-0618." + - "Enable FlashInfer TRT-LLM attention with FP8 indexer KV and KV cache." + - "Switch TP-only configurations from explicit Marlin MoE to the new image's default FlashInfer TRT-LLM MoE backend." + pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/1833 From e38b4da58ba9039ff358b37dcd8e24b53ee71341 Mon Sep 17 00:00:00 2001 From: Oseltamivir <58582368+Oseltamivir@users.noreply.github.com> Date: Fri, 19 Jun 2026 07:38:05 +0800 Subject: [PATCH 3/5] chore: use cu130 MiniMax M3 image --- .github/configs/nvidia-master.yaml | 6 +++--- perf-changelog.yaml | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/configs/nvidia-master.yaml b/.github/configs/nvidia-master.yaml index d9dbffc7f..05dc6343b 100644 --- a/.github/configs/nvidia-master.yaml +++ b/.github/configs/nvidia-master.yaml @@ -12948,13 +12948,13 @@ minimaxm3-fp8-b300-vllm: # 427B total / 26B active MoE with MSA sparse attention; MXFP8 checkpoint # (MiniMaxAI/MiniMax-M3-MXFP8, ~444 GB) quantized by NVIDIA — native MX tensor # cores on Blackwell. M3 support has not shipped in a stable vLLM release; -# the dedicated vllm/vllm-openai:minimax-m3-0618 image is built from the m3_release -# branch (vllm-project/vllm#45381). --block-size 128 is mandatory (MSA +# the dedicated vllm/vllm-openai:minimax-m3-0618-x86_64-cu130 image is built +# from the m3_release branch (vllm-project/vllm#45381). --block-size 128 is mandatory (MSA # sparse/index cache alignment). Weights are NOT SRE-staged: b200-dgxc reads # /lustre/fsw/gharunners/models/MiniMax-M3-MXFP8 (pre-downloaded, see # launch_b200-dgxc.sh). minimaxm3-fp8-b200-vllm: - image: vllm/vllm-openai:minimax-m3-0618 + image: vllm/vllm-openai:minimax-m3-0618-x86_64-cu130 model: MiniMaxAI/MiniMax-M3-MXFP8 model-prefix: minimaxm3 runner: b200-dgxc diff --git a/perf-changelog.yaml b/perf-changelog.yaml index 251ff6c44..eab26906a 100644 --- a/perf-changelog.yaml +++ b/perf-changelog.yaml @@ -3954,7 +3954,7 @@ - config-keys: - minimaxm3-fp8-b200-vllm description: - - "Update the MiniMax-M3 B200 single-node image to vllm/vllm-openai:minimax-m3-0618." + - "Update the MiniMax-M3 B200 single-node image to vllm/vllm-openai:minimax-m3-0618-x86_64-cu130." - "Enable FlashInfer TRT-LLM attention with FP8 indexer KV and KV cache." - "Switch TP-only configurations from explicit Marlin MoE to the new image's default FlashInfer TRT-LLM MoE backend." pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/1833 From 6c0791f0fde4383b2f8c8df1fb1168c26a831c9e Mon Sep 17 00:00:00 2001 From: Oseltamivir <58582368+Oseltamivir@users.noreply.github.com> Date: Fri, 19 Jun 2026 07:41:59 +0800 Subject: [PATCH 4/5] chore: retrigger benchmark sweeps From 5cbb51e1dfae0d51d37c4625b7692272fea82b6a Mon Sep 17 00:00:00 2001 From: Oseltamivir <58582368+Oseltamivir@users.noreply.github.com> Date: Fri, 19 Jun 2026 11:33:00 +0800 Subject: [PATCH 5/5] fix(vllm): materialize MiniMax M3 MSA top-k slice --- .../fixed_seq_len/minimaxm3_fp8_b200.sh | 33 +++++++++++++++++++ perf-changelog.yaml | 1 + 2 files changed, 34 insertions(+) diff --git a/benchmarks/single_node/fixed_seq_len/minimaxm3_fp8_b200.sh b/benchmarks/single_node/fixed_seq_len/minimaxm3_fp8_b200.sh index 9c901a9bd..7ac314a09 100755 --- a/benchmarks/single_node/fixed_seq_len/minimaxm3_fp8_b200.sh +++ b/benchmarks/single_node/fixed_seq_len/minimaxm3_fp8_b200.sh @@ -22,6 +22,39 @@ check_env_vars \ RANDOM_RANGE_RATIO \ RESULT_FILENAME +# The 0618 image keeps MiniMax M3 top-k indices in a persistent +# [head_kv, max_tokens, topK] buffer for CUDA graphs. Slicing that buffer to +# the actual prefill length is non-contiguous when TP leaves multiple local KV +# heads, and the MSA CSR builder rejects it. Materialize the slice until the +# image includes this fix. +python3 - <<'PYEOF' || { echo "MiniMax M3 MSA contiguity patch failed" >&2; exit 1; } +import importlib.util +import pathlib + +spec = importlib.util.find_spec("vllm") +if spec is None or not spec.submodule_search_locations: + raise RuntimeError("Could not locate the installed vllm package") + +target = ( + pathlib.Path(next(iter(spec.submodule_search_locations))) + / "models" + / "minimax_m3" + / "nvidia" + / "sparse_attention_msa.py" +) +src = target.read_text() +old = " prefill_topk = topk[:, nd:num_tokens, :]\n" +new = " prefill_topk = topk[:, nd:num_tokens, :].contiguous()\n" + +if new in src: + print(f"[minimax-m3-msa-patch] already applied: {target}") +elif src.count(old) == 1: + target.write_text(src.replace(old, new, 1)) + print(f"[minimax-m3-msa-patch] patched: {target}") +else: + raise RuntimeError(f"Expected exactly one patch anchor in {target}") +PYEOF + if [[ -n "$SLURM_JOB_ID" ]]; then echo "JOB $SLURM_JOB_ID running on $SLURMD_NODENAME" fi diff --git a/perf-changelog.yaml b/perf-changelog.yaml index eab26906a..8c0169fcc 100644 --- a/perf-changelog.yaml +++ b/perf-changelog.yaml @@ -3957,4 +3957,5 @@ - "Update the MiniMax-M3 B200 single-node image to vllm/vllm-openai:minimax-m3-0618-x86_64-cu130." - "Enable FlashInfer TRT-LLM attention with FP8 indexer KV and KV cache." - "Switch TP-only configurations from explicit Marlin MoE to the new image's default FlashInfer TRT-LLM MoE backend." + - "Patch the image's MiniMax M3 MSA prefill path to materialize sliced top-k indices before CSR construction." pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/1833