diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 090b7c012905..c8de15e8b579 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -495,6 +495,13 @@ "ESP/ESP32_C3" ] }, + { + "RTT_BSP": "ESP32S3", + "RTT_TOOL_CHAIN": "sourcery-xtensa-esp32s3", + "SUB_RTT_BSP": [ + "ESP/ESP32_S3" + ] + }, { "RTT_BSP": "ESP32C6", "RTT_TOOL_CHAIN": "sourcery-riscv32-esp32", diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index 0792d9fdf31d..70a4ebd02762 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -293,6 +293,15 @@ jobs: pip3 install esptool echo "RTT_EXEC_PATH=/opt/riscv32-esp-elf/bin" >> $GITHUB_ENV + - name: Install xtensa-esp32s3-elf ToolChains + if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-xtensa-esp32s3' && success() }} + run: | + wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz + sudo tar xf xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz -C /opt + /opt/xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-gcc --version + pip3 install esptool + echo "RTT_EXEC_PATH=/opt/xtensa-esp32s3-elf/bin" >> $GITHUB_ENV + - name: Install Arm Musl ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && matrix.legs.RTT_SMART_TOOL_CHAIN == 'arm-linux-musleabi' && success() }} shell: bash diff --git a/.github/workflows/manual_bsp_build.yml b/.github/workflows/manual_bsp_build.yml index 421eb976c1ab..2e8cd02900d9 100644 --- a/.github/workflows/manual_bsp_build.yml +++ b/.github/workflows/manual_bsp_build.yml @@ -45,6 +45,7 @@ on: - "sourcery-riscv64-unknown-elf" - "gcc" - "sourcery-riscv32-esp32" + - "sourcery-xtensa-esp32s3" permissions: contents: read # to fetch code (actions/checkout) @@ -134,6 +135,15 @@ jobs: pip3 install esptool echo "RTT_EXEC_PATH=/opt/riscv32-esp-elf/bin" >> $GITHUB_ENV + - name: Install xtensa-esp32s3-elf ToolChains + if: ${{ github.event.inputs.bsp_tool_chain == 'sourcery-xtensa-esp32s3' && success() }} + run: | + wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz + sudo tar xf xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz -C /opt + /opt/xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-gcc --version + pip3 install esptool + echo "RTT_EXEC_PATH=/opt/xtensa-esp32s3-elf/bin" >> $GITHUB_ENV + - name: Install GCC Tools if: ${{ github.event.inputs.bsp_tool_chain == 'gcc' && success() }} run: | diff --git a/.github/workflows/manual_dist.yml b/.github/workflows/manual_dist.yml index 2f64a734967f..4b35d823bf18 100644 --- a/.github/workflows/manual_dist.yml +++ b/.github/workflows/manual_dist.yml @@ -35,6 +35,7 @@ on: - "sourcery-riscv64-unknown-elf" - "gcc" - "sourcery-riscv32-esp32" + - "sourcery-xtensa-esp32s3" - "i686-x86-newlib" - "i686-x86-picolib" bsp_config: @@ -125,6 +126,13 @@ jobs: echo "RTT_EXEC_PATH=/opt/riscv32-esp-elf-gcc/bin" >> $GITHUB_ENV pip3 install esptool + - name: Install xtensa-esp32s3-elf ToolChains + if: ${{ github.event.inputs.bsp_tool_chain == 'sourcery-xtensa-esp32s3' && success() }} + run: | + source tools/ci/toolchain.sh xtensa-esp32s3-elf-gcc + echo "RTT_EXEC_PATH=/opt/xtensa-esp32s3-elf-gcc/bin" >> $GITHUB_ENV + pip3 install esptool + - name: Install GCC Tools if: ${{ github.event.inputs.bsp_tool_chain == 'gcc' && success() }} run: | diff --git a/.github/workflows/manual_trigger_scons_except_STM32_all.yml b/.github/workflows/manual_trigger_scons_except_STM32_all.yml index 85ab16cb4999..a79de570f865 100644 --- a/.github/workflows/manual_trigger_scons_except_STM32_all.yml +++ b/.github/workflows/manual_trigger_scons_except_STM32_all.yml @@ -90,7 +90,8 @@ jobs: - {RTT_BSP_NAME: "dm365", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "dm365"} - {RTT_BSP_NAME: "efm32", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "efm32"} - {RTT_BSP_NAME: "ESP32_C3", RTT_TOOL_CHAIN: "sourcery-riscv32-esp32", RTT_BSP: "ESP32_C3"} - - {RTT_BSP_NAME: "ESP32_C6", RTT_TOOL_CHAIN: "sourcery-riscv32-esp32", RTT_BSP: "ESP32_C6"} + - {RTT_BSP_NAME: "ESP32_S3", RTT_TOOL_CHAIN: "sourcery-xtensa-esp32s3", RTT_BSP: "ESP/ESP32_S3"} + - {RTT_BSP_NAME: "ESP32_C6", RTT_TOOL_CHAIN: "sourcery-riscv32-esp32", RTT_BSP: "ESP32_C6"} - {RTT_BSP_NAME: "essemi_es32f0654", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "essemi/es32f0654"} - {RTT_BSP_NAME: "essemi_es32f365x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "essemi/es32f365x"} - {RTT_BSP_NAME: "essemi_es32f369x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "essemi/es32f369x"} @@ -365,6 +366,15 @@ jobs: /opt/riscv32-esp-elf/bin/riscv32-esp-elf-gcc --version pip3 install esptool echo "RTT_EXEC_PATH=/opt/riscv32-esp-elf/bin" >> $GITHUB_ENV + + - name: Install xtensa-esp32s3-elf ToolChains + if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-xtensa-esp32s3' && success() }} + run: | + wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz + sudo tar xf xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz -C /opt + /opt/xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-gcc --version + pip3 install esptool + echo "RTT_EXEC_PATH=/opt/xtensa-esp32s3-elf/bin" >> $GITHUB_ENV - name: Bsp Scons Compile if: ${{ success() }} diff --git a/.github/workflows/manual_trigger_update_all.yml b/.github/workflows/manual_trigger_update_all.yml index 16d0d03fa15c..81aa1d1c21fb 100644 --- a/.github/workflows/manual_trigger_update_all.yml +++ b/.github/workflows/manual_trigger_update_all.yml @@ -34,6 +34,7 @@ on: - "sourcery-riscv64-unknown-elf" - "gcc" - "sourcery-riscv32-esp32" + - "sourcery-xtensa-esp32s3" permissions: contents: read # to fetch code (actions/checkout) @@ -123,6 +124,15 @@ jobs: pip3 install esptool echo "RTT_EXEC_PATH=/opt/riscv32-esp-elf/bin" >> $GITHUB_ENV + - name: Install xtensa-esp32s3-elf ToolChains + if: ${{ github.event.inputs.bsp_tool_chain == 'sourcery-xtensa-esp32s3' && success() }} + run: | + wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz + sudo tar xf xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz -C /opt + /opt/xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-gcc --version + pip3 install esptool + echo "RTT_EXEC_PATH=/opt/xtensa-esp32s3-elf/bin" >> $GITHUB_ENV + - name: Install GCC Tools if: ${{ github.event.inputs.bsp_tool_chain == 'gcc' && success() }} run: | diff --git a/bsp/ESP/ESP32_S3/.config b/bsp/ESP/ESP32_S3/.config new file mode 100644 index 000000000000..205f9a1da7ab --- /dev/null +++ b/bsp/ESP/ESP32_S3/.config @@ -0,0 +1,1430 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +# CONFIG_RT_USING_OVERFLOW_CHECK is not set +# CONFIG_RT_USING_HOOK is not set +# CONFIG_RT_USING_HOOKLIST is not set +# CONFIG_RT_USING_IDLE_HOOK is not set +CONFIG_IDLE_THREAD_STACK_SIZE=2048 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_VER_NUM=0x50301 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +CONFIG_PKG_USING_FREERTOS_WRAPPER=y +CONFIG_PKG_FREERTOS_WRAPPER_PATH="/packages/system/FreeRTOS_Wrapper" +CONFIG_PKG_FREERTOS_USING_CONFIG_H=y +# CONFIG_PKG_FREERTOS_USING_MEMMANG is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER_V100 is not set +CONFIG_PKG_USING_FREERTOS_WRAPPER_LATEST_VERSION=y +CONFIG_PKG_FREERTOS_WRAPPER_VER="latest" +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +CONFIG_PKG_USING_ESP_IDF=y +CONFIG_PKG_ESP_IDF_PATH="/packages/peripherals/hal-sdk/ESP-IDF" +CONFIG_PKG_USING_ESP_IDF_LATEST_VERSION=y +CONFIG_PKG_ESP_IDF_VER="latest" + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_ESPRESSIF=y +# CONFIG_SOC_ESP32_C3 is not set +CONFIG_SOC_ESP32_S3=y + +# +# Hardware Drivers Config +# +# CONFIG_BSP_BOARD_LUATOS_ESP32C3 is not set +CONFIG_BSP_BOARD_ESP32S3_DEVKITM1=y +# CONFIG_BSP_BOARD_HX_EXP32C3 is not set + +# +# Onboard Peripheral Drivers +# +CONFIG_RT_BSP_UART_PORT=0 +CONFIG_RT_BSP_UART_TX_PIN=43 +CONFIG_RT_BSP_UART_RX_PIN=44 +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_WIFI is not set +# CONFIG_BSP_USING_BLE is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_PWM is not set +# end of On-chip Peripheral Drivers + +# CONFIG_BSP_ENABLE_GDBSTUB is not set +# end of Hardware Drivers Config diff --git a/bsp/ESP/ESP32_S3/Kconfig b/bsp/ESP/ESP32_S3/Kconfig new file mode 100644 index 000000000000..98d353037c48 --- /dev/null +++ b/bsp/ESP/ESP32_S3/Kconfig @@ -0,0 +1,11 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/drivers/Kconfig" diff --git a/bsp/ESP/ESP32_S3/README.md b/bsp/ESP/ESP32_S3/README.md new file mode 100644 index 000000000000..798aa9e9fb6b --- /dev/null +++ b/bsp/ESP/ESP32_S3/README.md @@ -0,0 +1,82 @@ +# ESP32-S3-DevKitM-1 BSP 说明 + +## 1 开发板简介 + +ESP32-S3-DevKitM-1 是乐鑫推出的一款基于 Xtensa LX7 的开发板，模组为 ESP32-S3-MINI-1。本板读到的芯片是 QFN56，revision v0.2。这颗不是 RISC-V，不能用 ESP32-C3 / C6 的工具链，也不能搬它们的中断接法。 + +**基本特性：** + +- MCU：ESP32-S3，本 BSP 以单核模式运行，主频 160MHz，Flash 8MB，DIO +- 晶振：40MHz +- 片内 PSRAM 8MB，本版没有启用 +- USB：标着 UART 的口是 CP210x，接到 UART0（TX GPIO43，RX GPIO44） +- 不用 WCH-Link + +更多信息请访问 [ESP32-S3-DevKitM-1](https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitm-1/user_guide.html) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :----------- | :----------: | :------- | +| UART | 支持 | UART0，TX GPIO43，RX GPIO44。115200，能进 msh | +| GPIO | 待支持 | `help` 里有 `pin`，还没在板上做电平输入 | +| I2C | 待支持 | | +| SPI | 待支持 | | +| ADC | 待支持 | | +| PWM | 待支持 | | +| Wi-Fi | 待支持 | | +| BLE | 待支持 | | +| 板载 LED | 待支持 | | +| PSRAM | 待支持 | 8MB 未启用，堆来自片内 SRAM | +| FPU / AI 指令 | 部分支持 | 单精度浮点（FPU, CP0）已启用：应用可以做 `float` 运算，工具链会编译成 FPU 指令（lsi/ssi/madd.s 等），每次中断和线程切换时自动保存恢复 FP 状态。AI/SIMD（CP3）仍不支持，使用会触发 `CoprocessorDisabled` 异常。`double` 走软件实现，不受影响 | + +### IO 在板级支持包中的映射情况 + +| IO | 板级包中的定义 | +| ------ | -------------- | +| GPIO43 | UART0_TX | +| GPIO44 | UART0_RX | + +## 2 编译说明 + +板级包使用乐鑫 Xtensa GCC，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| ---------- | ---------- | +| GCC | Espressif xtensa-esp32s3-elf GCC 12.2.0（esp-12.2.0_20230208） | + +不要用 `riscv32-esp-elf`。 + +## 3 使用说明 + +> 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果。 + +### 3.1 使用 Env 编译 BSP + +1. 下载 [xtensa-esp32s3-elf GCC 12.2.0](https://github.com/espressif/crosstool-NG/releases/tag/esp-12.2.0_20230208)。Windows 用该标签下的 mingw 包，Linux 用同版本的 linux 包。 +2. 下载 Env 工具 [最新版本](https://github.com/RT-Thread/env-windows/releases) +3. 在当前 BSP 目录执行 `pkgs --update`，拉官方 `RT-Thread-packages/esp-idf`。这份包的 SConscript 只编 ESP32-C3；S3 的源文件由本目录 `idf_components/SConscript` 从包里挑出来编。 +4. 在当前 BSP 目录下执行 `scons --exec-path=工具链的bin目录`。改过 `idf_port/ld/sections.ld` 之后先删掉 `rtthread.elf` 再编，scons 不跟踪链接脚本。 +5. 编译完成之后会生成 **rtthread.bin** 文件。默认打开 GPIO 和 UART0。GPIO 还没在板上做电平测试。 + +### 3.2 硬件连接 + +串口用板上标着 UART 的 USB 口。不用杜邦线，也不用 WCH-Link。 + +### 3.3 下载 + +bootloader 和分区表在 `builtin_imgs`。必须是这份 ESP32-S3 的，不能用 ESP32-C3 的。 + +```sh +esptool.py --chip esp32s3 -p COMx -b 460800 --before default_reset --after hard_reset write_flash --flash_mode dio --flash_size 8MB --flash_freq 80m 0x0 builtin_imgs/bootloader.bin 0x8000 builtin_imgs/partition-table.bin 0x10000 rtthread.bin +``` + +### 3.4 运行结果 + +在终端工具里打开串口（115200-8-1-N），先打开串口再复位，可以看到 RT-Thread 的输出信息、`Hello! RT-Thread on ESP32-S3-DevKitM-1` 和 `msh >`。`help`、`version`、`ps`、`free` 有回应。隔开再执行 `ps`，`left tick` 会变。 + +中断看门狗默认关掉。IDF 用自己的向量去喂 TG1WDT，这份 BSP 换了向量（`libcpu/xtensa/esp32s3/context_gcc.S`）。不关的话，启动大约 300 ms 后复位，原因是 `rst:0x8 (TG1WDT_SYS_RST)`。 + +本 BSP 只服务 level-1 中断。注册中断时要带 `ESP_INTR_FLAG_LEVEL1`。 diff --git a/bsp/ESP/ESP32_S3/SConscript b/bsp/ESP/ESP32_S3/SConscript new file mode 100644 index 000000000000..fafbdf46fe93 --- /dev/null +++ b/bsp/ESP/ESP32_S3/SConscript @@ -0,0 +1,29 @@ +# for module compiling +import os +Import('RTT_ROOT') +from env_package import find_package_path + +cwd = str(Dir('#')) +objs = [] + +# BSP-owned groups, in dependency-free order. +for d in ('main', 'idf_port', 'idf_components'): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +# The FreeRTOS->RT-Thread shim is target independent and is walked directly. +# packages/SConscript (the pkgs-generated aggregator) is NOT used: the ESP-IDF +# package's own SConscript only defines source lists for C3/C6 and would abort +# on this target; the esp-idf file set lives in idf_components/SConscript. +# pkgs --update-force names the shim FreeRTOS_Wrapper-latest. A manual clone +# of the same repo may be FreeRTOS-Wrapper-latest. +wrapper = None +for name in ('FreeRTOS_Wrapper-latest', 'FreeRTOS-Wrapper-latest'): + path = find_package_path(cwd, name, marker='SConscript') + if os.path.isfile(os.path.join(path, 'SConscript')): + wrapper = path + break +if wrapper is None: + wrapper = os.path.join(cwd, 'packages', 'FreeRTOS_Wrapper-latest') +objs = objs + SConscript(os.path.join(wrapper, 'SConscript')) + +Return('objs') diff --git a/bsp/ESP/ESP32_S3/SConstruct b/bsp/ESP/ESP32_S3/SConstruct new file mode 100644 index 000000000000..bc297ea36d22 --- /dev/null +++ b/bsp/ESP/ESP32_S3/SConstruct @@ -0,0 +1,80 @@ +import os +import sys +from esptool.bin_image import ELFFile, ImageSegment, LoadFirmwareImage +from esptool.targets import CHIP_DEFS, CHIP_LIST, ROM_LIST + +def elf2image(target, source, env): + e = ELFFile("rtthread.elf") + + print("Creating esp32s3 image...") + + image = CHIP_DEFS["esp32s3"].BOOTLOADER_IMAGE() + # ESP32-S3 has no silicon revisions that gate feature bits in esptool's + # v1 image header for our use; 0 matches IDF 5.1 default app images. + image.min_rev = 0 + image.entrypoint = e.entrypoint + image.flash_mode = 2 # flash_mode: dio + + # ELFSection is a subclass of ImageSegment, so can use interchangeably + image.segments = e.sections + # 8MB quad flash @80MHz, matching the bootloader/partition table built + # from the same settings (see builtin_imgs + README). + image.flash_size_freq = image.ROM_LOADER.parse_flash_size_arg("8MB") + image.flash_size_freq += image.ROM_LOADER.parse_flash_freq_arg("80m") + + image.elf_sha256 = e.sha256() + image.elf_sha256_offset = 0xb0 + + before = len(image.segments) + image.merge_adjacent_segments() + if len(image.segments) != before: + delta = before - len(image.segments) + print("Merged %d ELF section%s" % (delta, "s" if delta > 1 else "")) + + image.verify() + + image.save("rtthread.bin") + + print("Successfully created esp32s3 image.") + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +import rtconfig +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, remove_components = ['libc']) + +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +# make a building +DoBuilding(TARGET, objs) + +# turn the ELF into an ESP32-S3 app image right after linking +env.AddPostAction(TARGET, elf2image) diff --git a/bsp/ESP/ESP32_S3/builtin_imgs/.gitignore b/bsp/ESP/ESP32_S3/builtin_imgs/.gitignore new file mode 100644 index 000000000000..0aff3fa14504 --- /dev/null +++ b/bsp/ESP/ESP32_S3/builtin_imgs/.gitignore @@ -0,0 +1,4 @@ +* +!.gitignore +!bootloader.bin +!partition-table.bin diff --git a/bsp/ESP/ESP32_S3/builtin_imgs/bootloader.bin b/bsp/ESP/ESP32_S3/builtin_imgs/bootloader.bin new file mode 100644 index 000000000000..fed79d6c0033 Binary files /dev/null and b/bsp/ESP/ESP32_S3/builtin_imgs/bootloader.bin differ diff --git a/bsp/ESP/ESP32_S3/builtin_imgs/partition-table.bin b/bsp/ESP/ESP32_S3/builtin_imgs/partition-table.bin new file mode 100644 index 000000000000..0dc4a341ac77 Binary files /dev/null and b/bsp/ESP/ESP32_S3/builtin_imgs/partition-table.bin differ diff --git a/bsp/ESP/ESP32_S3/idf_components/SConscript b/bsp/ESP/ESP32_S3/idf_components/SConscript new file mode 100644 index 000000000000..077131f2904a --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_components/SConscript @@ -0,0 +1,390 @@ +# ESP-IDF component selection for the ESP32-S3 BSP. +# +# The ESP-IDF package (packages/ESP-IDF-latest) ships a SConscript that only +# knows the ESP32-C3 (and, in newer forks, C6) file sets; for the S3 target it +# raises NameError because no branch defines its source list. Rather than +# patching the vendored package, the BSP declares its own esp-idf group here: +# the file list is the C3 set with every esp32c3 path renamed to its existing +# esp32s3 counterpart (checked against the package at authoring time), with +# these deliberate differences: +# - Wi-Fi / BT / wpa / lwip / netif / vfs / nvs / esp_phy / esp_event groups: +# not compiled (v1 console-only BSP, matching the BSP's Kconfig defaults) +# - components/cxx, esp_pm, app_update, efuse, pthread: kept exactly as C3 so +# IDF startup code sees the same symbol set (unused pieces drop out via +# --gc-sections) +# - RISC-V arch files (components/riscv/*, esp_system arch/riscv) replaced +# by their esp_system/port/arch/xtensa counterparts plus the target- +# independent components/xtensa interrupt plumbing, and linked against +# xtensa/esp32s3/libxt_hal.a (xthal_save_extra_nw / window spill / cp regs) +# - adc / sha / aes / ds / brownout-only HALs and the S3 peripheral files +# with no RT-Thread driver behind them are left out. +# - Left out of the xtensa arch set deliberately: esp_ipc_isr* (dual-core IPI, +# CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE makes esp_ipc.c call handlers +# directly), expression_with_stack* (indexes the real FreeRTOS TCB, which +# the RT-Thread wrapper does not provide), bootloader_sha/secure_boot/ +# flash_encrypt (need mbedtls / secure boot, both off), and +# esp_hw_support/sleep_modes.c (deep sleep, needs the excluded +# driver/touch_sensor.h; no esp_sleep API is offered by this BSP v1). +# - Added on top of the C3 set: spi_flash/spi_flash_timing_tuning.c and +# spi_flash/spi_flash_hpm_enable.c. The xtensa cpu_start.c/rtc_init.c call +# spi_timing_flash_tuning() and spi_flash_enable_high_performance_mode(); +# on C3 those call sites are RISC-V-guarded out, so the C3 list has none. + +import os +from building import * +from env_package import find_package_path + +cwd = GetCurrentDir() +bsp_root = os.path.normpath(os.path.join(cwd, '..')) +# pkgs --update-force may place this under bsp/ESP/libraries rather than +# this BSP's packages directory. +PKG = find_package_path(bsp_root, 'ESP-IDF-latest', + marker='components/xtensa/esp32s3/include') + +_rel_src = Split(""" +components/esp_app_format/esp_app_desc.c +components/esp_ringbuf/ringbuf.c +components/esp_pm/pm_trace.c +components/esp_pm/pm_locks.c +components/esp_pm/pm_impl.c +components/cxx/cxx_exception_stubs.cpp +components/cxx/cxx_guards.cpp +components/app_update/esp_ota_app_desc.c +components/app_update/esp_ota_ops.c +components/esp_common/src/esp_err_to_name.c + +components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +components/bootloader_support/src/esp32s3/bootloader_soc.c +components/bootloader_support/src/bootloader_init.c +components/bootloader_support/src/bootloader_console.c +components/bootloader_support/src/bootloader_random_esp32s3.c +components/bootloader_support/src/bootloader_mem.c +components/bootloader_support/src/bootloader_common.c +components/bootloader_support/src/bootloader_clock_init.c +components/bootloader_support/src/bootloader_random.c +components/bootloader_support/src/bootloader_common_loader.c +components/bootloader_support/src/flash_partitions.c +components/bootloader_support/bootloader_flash/src/bootloader_flash.c +components/bootloader_support/src/bootloader_efuse.c +components/bootloader_support/src/bootloader_utility.c +components/bootloader_support/src/esp_image_format.c +components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c +components/bootloader_support/bootloader_flash/src/flash_qio_mode.c + +components/esp_system/int_wdt.c +components/esp_system/esp_err.c +components/esp_system/esp_ipc.c +components/esp_system/crosscore_int.c +components/esp_system/port/soc/esp32s3/reset_reason.c +components/esp_system/esp_system.c +components/esp_system/freertos_hooks.c +components/esp_system/port/brownout.c +components/esp_system/stack_check.c +components/esp_system/panic.c +components/esp_system/system_time.c +components/esp_system/task_wdt.c +components/esp_system/debug_stubs.c +components/esp_system/startup.c +components/esp_system/ubsan.c +components/esp_system/xt_wdt.c +components/esp_system/port/soc/esp32s3/cache_err_int.c +components/esp_system/port/cpu_start.c +components/esp_system/port/soc/esp32s3/apb_backup_dma.c +components/esp_system/port/panic_handler.c +components/esp_system/port/soc/esp32s3/system_internal.c +components/esp_system/port/soc/esp32s3/clk.c +components/esp_system/eh_frame_parser.c + +components/esp_system/port/arch/xtensa/panic_arch.c +components/esp_system/port/arch/xtensa/panic_handler_asm.S +components/esp_system/port/arch/xtensa/debug_stubs.c +components/esp_system/port/arch/xtensa/debug_helpers.c +components/esp_system/port/arch/xtensa/debug_helpers_asm.S + +components/xtensa/xtensa_intr.c +components/xtensa/xtensa_intr_asm.S +components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_context.S + +components/esp_rom/patches/esp_rom_sys.c +components/esp_rom/patches/esp_rom_crc.c +components/esp_rom/patches/esp_rom_uart.c +components/esp_rom/patches/esp_rom_spiflash.c +components/esp_rom/patches/esp_rom_regi2c.c +components/esp_rom/patches/esp_rom_systimer.c +components/esp_rom/patches/esp_rom_efuse.c + +components/heap/port/esp32s3/memory_layout.c +components/heap/multi_heap.c +components/heap/port/memory_layout_utils.c +components/heap/heap_caps_init.c +components/heap/heap_caps.c +components/heap/tlsf/tlsf.c + +components/spi_flash/flash_brownout_hook.c +components/spi_flash/spi_flash_chip_drivers.c +components/spi_flash/spi_flash_chip_issi.c +components/spi_flash/partition_target.c +components/spi_flash/partition.c +components/spi_flash/spi_flash_chip_gd.c +components/spi_flash/spi_flash_chip_mxic.c +components/spi_flash/spi_flash_chip_boya.c +components/spi_flash/spi_flash_chip_winbond.c +components/spi_flash/spi_flash_chip_generic.c +components/spi_flash/spi_flash_chip_th.c +components/spi_flash/spi_flash_chip_mxic_opi.c +components/spi_flash/memspi_host_driver.c +components/spi_flash/cache_utils.c +components/spi_flash/spi_flash_os_func_app.c +components/spi_flash/esp32s3/flash_ops_esp32s3.c +components/spi_flash/esp32s3/spi_timing_config.c +components/spi_flash/spi_flash_timing_tuning.c +components/spi_flash/spi_flash_hpm_enable.c +components/spi_flash/flash_ops.c +components/spi_flash/flash_mmap.c +components/spi_flash/spi_flash_os_func_noos.c +components/spi_flash/esp_flash_spi_init.c +components/spi_flash/esp_flash_api.c + +components/newlib/heap.c +components/newlib/assert.c +components/newlib/pthread.c +components/newlib/abort.c +components/newlib/poll.c +components/newlib/newlib_init.c +components/newlib/termios.c +components/newlib/random.c +components/newlib/locks.c +components/newlib/reent_init.c +components/newlib/syscalls.c +components/newlib/sysconf.c +components/newlib/port/esp_time_impl.c +components/newlib/realpath.c +components/newlib/time.c +components/newlib/stdatomic.c + +components/log/log.c +components/log/log_buffers.c +components/log/log_freertos.c + +components/driver/gpio/dedic_gpio.c +components/driver/spi_bus_lock.c +components/driver/gpio/rtc_io.c +components/driver/gptimer.c +components/driver/spi_master.c +components/driver/gpio/gpio.c +components/driver/spi_slave.c +components/driver/uart.c +components/driver/i2c.c +components/driver/spi_common.c +components/driver/sdm.c +components/driver/rmt/rmt_common.c +components/driver/rmt/rmt_encoder.c +components/driver/rmt/rmt_rx.c +components/driver/rmt/rmt_tx.c +components/driver/i2s/i2s_std.c +components/driver/temperature_sensor.c +components/driver/i2s/i2s_common.c +components/driver/i2s/i2s_tdm.c +components/driver/usb_serial_jtag.c +components/driver/spi_slave_hd.c +components/driver/i2s/i2s_pdm.c +components/driver/twai.c +components/driver/ledc.c +components/driver/sdspi_crc.c +components/driver/sdspi_transaction.c +components/driver/sdspi_host.c + +components/pthread/pthread_local_storage.c +components/pthread/pthread_cond_var.c +components/pthread/pthread_rwlock.c +components/pthread/pthread.c + +components/efuse/esp32s3/esp_efuse_table.c +components/efuse/esp32s3/esp_efuse_utility.c +components/efuse/esp32s3/esp_efuse_fields.c +components/efuse/src/esp_efuse_utility.c +components/efuse/esp32s3/esp_efuse_rtc_calib.c +components/efuse/src/esp_efuse_api.c +components/efuse/src/esp_efuse_fields.c +components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c + +components/esp_timer/src/esp_timer_impl_systimer.c +components/esp_timer/src/system_time.c +components/esp_timer/src/esp_timer.c +components/esp_timer/src/ets_timer_legacy.c + +components/hal/xt_wdt_hal.c +components/hal/mpu_hal.c +components/hal/efuse_hal.c +components/hal/rtc_io_hal.c +components/hal/esp32s3/efuse_hal.c +components/hal/mmu_hal.c +components/hal/wdt_hal_iram.c +components/hal/cache_hal.c +components/hal/spi_hal_iram.c +components/hal/timer_hal.c +components/hal/timer_hal_iram.c +components/hal/spi_slave_hal.c +components/hal/spi_hal.c +components/hal/spi_slave_hal_iram.c +components/hal/ledc_hal.c +components/hal/i2c_hal.c +components/hal/gpio_hal.c +components/hal/i2c_hal_iram.c +components/hal/ledc_hal_iram.c +components/hal/uart_hal_iram.c +components/hal/uart_hal.c +components/hal/spi_flash_encrypt_hal_iram.c +components/hal/spi_flash_hal.c +components/hal/systimer_hal.c +components/hal/adc_oneshot_hal.c +components/hal/rmt_hal.c +components/hal/sdm_hal.c +components/hal/adc_hal_common.c +components/hal/spi_flash_hal_iram.c +components/hal/twai_hal_iram.c +components/hal/gdma_hal.c +components/hal/twai_hal.c +components/hal/esp32s3/brownout_hal.c +components/hal/i2s_hal.c +components/hal/spi_flash_hal_gpspi.c +components/hal/esp32s3/rtc_cntl_hal.c +components/hal/adc_hal.c +components/hal/esp32s3/hmac_hal.c +components/hal/spi_slave_hd_hal.c + +components/soc/lldesc.c +components/soc/dport_access_common.c +components/soc/esp32s3/gpio_periph.c +components/soc/esp32s3/sdm_periph.c +components/soc/esp32s3/interrupts.c +components/soc/esp32s3/rmt_periph.c +components/soc/esp32s3/ledc_periph.c +components/soc/esp32s3/i2s_periph.c +components/soc/esp32s3/dedic_gpio_periph.c +components/soc/esp32s3/adc_periph.c +components/soc/esp32s3/gdma_periph.c +components/soc/esp32s3/i2c_periph.c +components/soc/esp32s3/spi_periph.c +components/soc/esp32s3/temperature_sensor_periph.c +components/soc/esp32s3/uart_periph.c +components/soc/esp32s3/timer_periph.c +components/soc/esp32s3/rtc_io_periph.c + +components/esp_hw_support/esp_memory_utils.c +components/esp_hw_support/hw_random.c +components/esp_hw_support/clk_ctrl_os.c +components/esp_hw_support/esp_clk.c +components/esp_hw_support/cpu.c +components/esp_hw_support/mac_addr.c +components/esp_hw_support/sleep_mac_bb.c +components/esp_hw_support/periph_ctrl.c +components/esp_hw_support/sleep_gpio.c +components/esp_hw_support/rtc_module.c +components/esp_hw_support/intr_alloc.c +components/esp_hw_support/regi2c_ctrl.c +components/esp_hw_support/port/esp32s3/systimer.c +components/esp_hw_support/sleep_retention.c +components/esp_hw_support/adc_share_hw_ctrl.c +components/esp_hw_support/port/async_memcpy_impl_gdma.c +components/esp_hw_support/port/esp32s3/rtc_clk_init.c +components/esp_hw_support/port/esp32s3/rtc_pm.c +components/esp_hw_support/esp_async_memcpy.c +components/esp_hw_support/port/esp32s3/rtc_sleep.c +components/esp_hw_support/gdma.c +components/esp_hw_support/port/esp32s3/rtc_init.c +components/esp_hw_support/port/esp32s3/rtc_time.c +components/esp_hw_support/port/esp32s3/chip_info.c +components/esp_hw_support/port/esp32s3/rtc_clk.c +components/esp_hw_support/port/esp32s3/esp_hmac.c +components/esp_hw_support/port/esp32s3/esp_crypto_lock.c +components/esp_hw_support/port/esp_memprot_conv.c +components/esp_hw_support/port/esp32s3/esp_ds.c +components/esp_hw_support/port/esp32s3/esp_memprot.c +""") + +src = [PKG + '/' + s for s in _rel_src] + +path = [ + # Prepended so include_compat wraps package headers via #include_next + # (bootloader_flash_priv.h for flash_qio_mode.c, bootloader_flash.h for + # flash_ops_esp32s3.c; see those files' comments). + cwd + '/include_compat', + PKG + '/components/hal/esp32s3/include', + PKG + '/components/hal/include', + PKG + '/components/soc/esp32s3/include', + PKG + '/components/soc/include', + PKG + '/components/hal/platform_port/include', + PKG + '/components/esp_system/include', + PKG + '/components/esp_hw_support/include', + PKG + '/components/esp_hw_support/include/soc', + PKG + '/components/esp_hw_support/include/soc/esp32s3', + PKG + '/components/esp_hw_support/port/include', + PKG + '/components/esp_hw_support/include/esp_private', + PKG + '/components/esp_common/include', + PKG + '/components/driver/include', + PKG + '/components/driver/deprecated', + PKG + '/components/esp_rom/include', + PKG + '/components/esp_rom/esp32s3/include', + PKG + '/components/xtensa/include', + PKG + '/components/xtensa/esp32s3/include', + PKG + '/components/freertos/FreeRTOS-Kernel/portable/xtensa', + PKG + '/components/freertos/FreeRTOS-Kernel/portable/xtensa/include', + PKG + '/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos', + PKG + '/components/heap/include', + PKG + '/components/heap/tlsf', + PKG + '/components/newlib/platform_include', + PKG + '/components/newlib/priv_include', + PKG + '/components/esp_ringbuf/include', + PKG + '/components/log/include', + PKG + '/components/spi_flash/include', + PKG + '/components/spi_flash/include/spi_flash', + PKG + '/components/app_update/include', + PKG + '/components/esp_system/port/include', + PKG + '/components/esp_system/port/include/private', + PKG + '/components/bootloader_support/include', + PKG + '/components/bootloader_support/bootloader_flash/include', + PKG + '/components/bootloader_support/private_include', + PKG + '/components/efuse/include', + PKG + '/components/efuse/esp32s3/include', + PKG + '/components/efuse/private_include', + PKG + '/components/efuse/esp32s3/private_include', + PKG + '/components/esp_pm/include', + PKG + '/components/esp_timer/include', + PKG + '/components/esp_timer/private_include', + PKG + '/components/pthread/include', + PKG + '/components/esp_app_format/include', + PKG + '/components/esp_rom/esp32s3', + PKG + '/components/soc/esp32s3', +] + +# libxt_hal.a supplies xthal_save/restore_extra_nw, xthal_window_spill_nw and +# the coprocessor save/restore used by libcpu/xtensa and xtensa_context.S. +LIB_PATH = [PKG + '/components/xtensa/esp32s3'] +LIB = ['xt_hal'] + +CPPDEFINES = [ + 'IDF_VER=\\"999\\"', + 'PROJECT_VER=\\"999\\"', + '_GNU_SOURCE', + 'MULTI_HEAP_FREERTOS', + 'ESP_PLATFORM=1', + 'IDF_TARGET=esp32s3', + '_POSIX_READER_WRITER_LOCKS', + 'PROJECT_NAME=\\"rtthread\\"', + '__ets__', + # The fork's spi_flash_defs.h predates the ESP32-S3 cache-wrap feature and + # does not define CMD_WRAP, but the (newer) bootloader_flash.c uses it + # under #if SOC_CACHE_SUPPORT_WRAP. Value per ESP-IDF v5.1.4's + # spi_flash/spi_flash_defs.h:0x77. Harmless for C3-only files. + 'CMD_WRAP=0x77', +] + +# Force-feed ATOMIC_VAR_INIT for toolchains whose dropped it. +LOCAL_CFLAGS = ' -include ' + cwd + '/include_compat/atomic_var_init.h' + +group = DefineGroup('esp-idf', src, depend = ['PKG_USING_ESP_IDF'], + CPPPATH = path, LIBS = LIB, LIBPATH = LIB_PATH, + CPPDEFINES = CPPDEFINES, LOCAL_CFLAGS = LOCAL_CFLAGS) + +Return('group') diff --git a/bsp/ESP/ESP32_S3/idf_components/include_compat/atomic_var_init.h b/bsp/ESP/ESP32_S3/idf_components/include_compat/atomic_var_init.h new file mode 100644 index 000000000000..1f43bde9b790 --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_components/include_compat/atomic_var_init.h @@ -0,0 +1,9 @@ +/* + * ATOMIC_VAR_INIT was removed from in C17. Newer Xtensa + * toolchains (GCC 15+) default to a mode where the macro is gone, while + * the vendored ESP-IDF still uses it in driver/spi_common.c. Provide the + * historical expansion so both GCC 12 (CI) and GCC 15 (local) build. + */ +#ifndef ATOMIC_VAR_INIT +#define ATOMIC_VAR_INIT(value) (value) +#endif diff --git a/bsp/ESP/ESP32_S3/idf_components/include_compat/bootloader_flash.h b/bsp/ESP/ESP32_S3/idf_components/include_compat/bootloader_flash.h new file mode 100644 index 000000000000..bddbd2e49fee --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_components/include_compat/bootloader_flash.h @@ -0,0 +1,31 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Compatibility shim for the vendored ESP-IDF fork on ESP32-S3. + * + * flash_ops_esp32s3.c includes bootloader_flash.h (not the priv header) and + * calls bootloader_flash_wrap_set under SOC_CACHE_SUPPORT_WRAP. The fork + * implements that symbol in bootloader_flash.c but never declares it in + * bootloader_flash.h, so the call is an implicit declaration. The priv-header + * shim covers flash_qio_mode.c; this one covers the spi_flash call site. + * + * Change Logs: + * Date Author Notes + * 2026-10-10 seteiro declare bootloader_flash_wrap_set for S3 + */ +#pragma once + +#include_next +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if SOC_CACHE_SUPPORT_WRAP +esp_err_t bootloader_flash_wrap_set(spi_flash_wrap_mode_t mode); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/bsp/ESP/ESP32_S3/idf_components/include_compat/bootloader_flash_priv.h b/bsp/ESP/ESP32_S3/idf_components/include_compat/bootloader_flash_priv.h new file mode 100644 index 000000000000..320e103c8c19 --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_components/include_compat/bootloader_flash_priv.h @@ -0,0 +1,36 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Compatibility shim for the vendored ESP-IDF fork on ESP32-S3. + * + * bootloader_flash.c implements bootloader_flash_wrap_set() under + * #if SOC_CACHE_SUPPORT_WRAP (true on S3 via soc_caps.h), and + * flash_qio_mode.c calls it under the same guard. The fork never declares + * the prototype in any header, so -Werror=implicit-function-declaration + * fails scons. C3 is unaffected: its soc_caps leave SOC_CACHE_SUPPORT_WRAP + * unset, so both the call and the body are compiled out. + * + * This directory is prepended to the esp-idf group's CPPPATH so the + * include_next below reaches the real bootloader_flash_priv.h in the + * package. Delete this shim if the package grows a matching declaration. + * + * Change Logs: + * Date Author Notes + * 2026-10-10 seteiro declare bootloader_flash_wrap_set for S3 + */ + +#pragma once + +#include_next + +#ifdef __cplusplus +extern "C" { +#endif + +#if SOC_CACHE_SUPPORT_WRAP +esp_err_t bootloader_flash_wrap_set(spi_flash_wrap_mode_t mode); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/bsp/ESP/ESP32_S3/idf_port/SConscript b/bsp/ESP/ESP32_S3/idf_port/SConscript new file mode 100644 index 000000000000..643f4a4c2c9d --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_port/SConscript @@ -0,0 +1,39 @@ +import os +from building import * +from env_package import find_package_path + +Import('rtconfig') + +cwd = GetCurrentDir() +bsp_root = os.path.normpath(os.path.join(cwd, '..')) +# pkgs --update-force may place this under bsp/ESP/libraries rather than +# this BSP's packages directory. +PKG_IDF = find_package_path(bsp_root, 'ESP-IDF-latest', + marker='components/xtensa/esp32s3/include') + +src = Split(""" + src/rt-thread_balance_stub.c + src/port.c + src/port_common.c +""") + +# The Xtensa vector/context building blocks stay in libcpu/xtensa; here we +# only add the include dirs the ESP-IDF Xtensa port headers expect: +# portable/xtensa -> xt_asm_utils.h +# portable/xtensa/include/freertos -> xtensa_rtos.h / xtensa_context.h shim +# components/xtensa/include -> generic headers +# components/xtensa/esp32s3/include -> per-SoC config +CPPPATH = [ + cwd + '/include', + cwd + '/include/freertos', + PKG_IDF + '/components/driver/include', + PKG_IDF + '/components/esp_common/include', + PKG_IDF + '/components/freertos/FreeRTOS-Kernel/portable/xtensa', + PKG_IDF + '/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos', + PKG_IDF + '/components/xtensa/include', + PKG_IDF + '/components/xtensa/esp32s3/include', +] + +group = DefineGroup('idf_port', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/ESP/ESP32_S3/idf_port/include/freertos/FreeRTOSConfig.h b/bsp/ESP/ESP32_S3/idf_port/include/freertos/FreeRTOSConfig.h new file mode 100644 index 000000000000..6881496f31ac --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_port/include/freertos/FreeRTOSConfig.h @@ -0,0 +1,277 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "sdkconfig.h" + +/* +This file get's pulled into assembly sources. Therefore, some includes need to be wrapped in #ifndef __ASSEMBLER__ +*/ + +#ifndef __ASSEMBLER__ +#include //For configASSERT() +#endif /* def __ASSEMBLER__ */ + +#ifdef CONFIG_FREERTOS_SMP + +// Pull in the SMP configuration +#include "freertos/FreeRTOSConfig_smp.h" + +#else // CONFIG_FREERTOS_SMP + +// The arch-specific FreeRTOSConfig_arch.h in port//include. +#include "freertos/FreeRTOSConfig_arch.h" + +#if !(defined(FREERTOS_CONFIG_XTENSA_H) || defined(FREERTOS_CONFIG_RISCV_H) || defined(FREERTOS_CONFIG_LINUX_H)) +#error "Needs architecture-speific FreeRTOSConfig.h!" +#endif + +/* ----------------------------------------------------- Helpers ------------------------------------------------------- + * - Macros that the FreeRTOS configuration macros depend on + * ------------------------------------------------------------------------------------------------------------------ */ + +/* Higher stack checker modes cause overhead on each function call */ +#if CONFIG_STACK_CHECK_ALL || CONFIG_STACK_CHECK_STRONG +#define STACK_OVERHEAD_CHECKER 256 +#else +#define STACK_OVERHEAD_CHECKER 0 +#endif + +/* with optimizations disabled, scheduler uses additional stack */ +#if CONFIG_COMPILER_OPTIMIZATION_NONE +#define STACK_OVERHEAD_OPTIMIZATION 320 +#else +#define STACK_OVERHEAD_OPTIMIZATION 0 +#endif + +/* apptrace mdule increases minimum stack usage */ +#if CONFIG_APPTRACE_ENABLE +#define STACK_OVERHEAD_APPTRACE 1280 +#else +#define STACK_OVERHEAD_APPTRACE 0 +#endif + +/* Stack watchpoint decreases minimum usable stack size by up to 60 bytes. + See FreeRTOS FREERTOS_WATCHPOINT_END_OF_STACK option in Kconfig. */ +#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK +#define STACK_OVERHEAD_WATCHPOINT 60 +#else +#define STACK_OVERHEAD_WATCHPOINT 0 +#endif + +#define configSTACK_OVERHEAD_TOTAL ( \ + STACK_OVERHEAD_CHECKER + \ + STACK_OVERHEAD_OPTIMIZATION + \ + STACK_OVERHEAD_APPTRACE + \ + STACK_OVERHEAD_WATCHPOINT) + +/* ------------------------------------------------- FreeRTOS Config --------------------------------------------------- + * - All Vanilla FreeRTOS configuration goes into this section + * - Keep this section in-sync with the corresponding version of single-core upstream version of FreeRTOS + * - Don't put any SMP or ESP-IDF exclusive FreeRTOS configurations here. Those go into the next section + * - Not all FreeRTOS configuration are listed. Some configurations have default values set in FreeRTOS.h thus don't + * need to be explicitly defined. + * ------------------------------------------------------------------------------------------------------------------ */ + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +// ------------------ Scheduler Related -------------------- + +// #define configUSE_PREEMPTION 1 +// #define configUSE_TICKLESS_IDLE CONFIG_FREERTOS_USE_TICKLESS_IDLE +#if configUSE_TICKLESS_IDLE +#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP +#endif // configUSE_TICKLESS_IDLE +#define configCPU_CLOCK_HZ (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000) +// #define configTICK_RATE_HZ CONFIG_FREERTOS_HZ +// #define configMAX_PRIORITIES ( 25 ) //This has impact on speed of search for highest priority +// #define configMINIMAL_STACK_SIZE ( 768 + configSTACK_OVERHEAD_TOTAL ) +// #define configUSE_TIME_SLICING 1 +// #define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configKERNEL_INTERRUPT_PRIORITY 1 // Todo: This currently isn't used anywhere + +// ------------- Synchronization Primitives ---------------- + +// #define configUSE_MUTEXES 1 +// #define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +// #define configUSE_QUEUE_SETS 1 +// #define configQUEUE_REGISTRY_SIZE CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE +#define configUSE_TASK_NOTIFICATIONS 1 +// #define configTASK_NOTIFICATION_ARRAY_ENTRIES 1 + +// ----------------------- System -------------------------- + +// #define configMAX_TASK_NAME_LEN CONFIG_FREERTOS_MAX_TASK_NAME_LEN +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS +#ifndef CONFIG_IDF_TARGET_LINUX +#define configSTACK_DEPTH_TYPE uint32_t +#define configUSE_NEWLIB_REENTRANT 1 +#endif +#if CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#else +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#endif +// #define configASSERT(a) assert(a) +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +// ----------------------- Memory ------------------------- + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +// We define the heap to span all of the non-statically-allocated shared RAM. ToDo: Make sure there +// is some space left for the app and main cpu when running outside of a thread. +// #define configTOTAL_HEAP_SIZE (&_heap_end - &_heap_start)//( ( size_t ) (64 * 1024) ) +// #define configAPPLICATION_ALLOCATED_HEAP 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +// ------------------------ Hooks -------------------------- + +// #define configUSE_IDLE_HOOK CONFIG_FREERTOS_USE_IDLE_HOOK +// #define configUSE_TICK_HOOK CONFIG_FREERTOS_USE_TICK_HOOK + +// configCHECK_FOR_STACK_OVERFLOW is deliberately NOT mapped here. +// +// The FreeRTOS_Wrapper package hard-codes it to 0 unconditionally in +// FreeRTOS.h:118 ("Hook functions are not supported by RT-Thread"), and that +// line runs *after* this header is pulled in (FreeRTOS.h:63). Any value defined +// here is therefore discarded, and sdkconfig_s3.h selects +// CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY, so the mapping only ever produced +// a "configCHECK_FOR_STACK_OVERFLOW redefined" warning -- one per translation +// unit that touches FreeRTOS.h (84 occurrences in a full build). +// +// The wrapper's own guarded default (FreeRTOS.h:459) supplies 0, so leaving this +// out changes nothing: stack overflow checking stays off, as it already was. +// +// Note for whoever picks this up: enabling the canary mode needs the +// FreeRTOS_Wrapper package to stop forcing 0, or this BSP to vendor its own +// copy of that header. It cannot be turned on from here. +#define configRECORD_STACK_HIGH_ADDRESS 1 + +// ------------------- Run-time Stats ---------------------- + +#ifdef CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS +#define configGENERATE_RUN_TIME_STATS 1 /* Used by vTaskGetRunTimeStats() */ +#endif +#ifdef CONFIG_FREERTOS_USE_TRACE_FACILITY +#define configUSE_TRACE_FACILITY 1 /* Used by uxTaskGetSystemState(), and other trace facility functions */ +#endif +#ifdef CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 /* Used by vTaskList() */ +#endif + +// -------------------- Co-routines ----------------------- + +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +// ------------------- Software Timer ---------------------- + +// #define configUSE_TIMERS 1 +// #define configTIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY +// #define configTIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH +// #define configTIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH + +// -------------------- API Includes ----------------------- + +#if CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#else +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#endif + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_xTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_uxTaskGetStackHighWaterMark2 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 1 +// #define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +// Unlisted +#define INCLUDE_pxTaskGetStackStart 1 + +// -------------------- Trace Macros ----------------------- + +/* +For trace macros. +Note: Include trace macros here and not above as trace macros are dependent on some of the FreeRTOS configs +*/ +#ifndef __ASSEMBLER__ +#if CONFIG_SYSVIEW_ENABLE +#include "SEGGER_SYSVIEW_FreeRTOS.h" +#undef INLINE // to avoid redefinition +#endif // CONFIG_SYSVIEW_ENABLE +#endif /* def __ASSEMBLER__ */ + +/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- + * - All FreeRTOS related configurations no part of Vanilla FreeRTOS goes into this section + * - FreeRTOS configurations related to SMP and ESP-IDF additions go into this section + * ------------------------------------------------------------------------------------------------------------------ */ + +// ------------------------- SMP --------------------------- + +#ifndef CONFIG_FREERTOS_UNICORE +#define portNUM_PROCESSORS 2 +#else +#define portNUM_PROCESSORS 1 +#endif +#define configNUM_CORES portNUM_PROCESSORS +#ifdef CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID +#define configTASKLIST_INCLUDE_COREID 1 +#endif + +// ---------------------- Features ------------------------- + +#define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1 +#ifndef configIDLE_TASK_STACK_SIZE +#define configIDLE_TASK_STACK_SIZE CONFIG_FREERTOS_IDLE_TASK_STACKSIZE +#endif + +#if CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER +#define configCHECK_MUTEX_GIVEN_BY_OWNER 1 +#else +#define configCHECK_MUTEX_GIVEN_BY_OWNER 0 +#endif + +#ifndef __ASSEMBLER__ +#if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP +extern void vPortCleanUpTCB(void *pxTCB); +#define portCLEAN_UP_TCB(pxTCB) vPortCleanUpTCB(pxTCB) +#endif +#endif + +// -------------------- Compatibility ---------------------- + +// backward compatibility for 4.4 +#define xTaskRemoveFromUnorderedEventList vTaskRemoveFromUnorderedEventList + +#endif // CONFIG_FREERTOS_SMP + +#endif /* FREERTOS_CONFIG_H */ diff --git a/bsp/ESP/ESP32_S3/idf_port/include/freertos/FreeRTOSConfig_arch.h b/bsp/ESP/ESP32_S3/idf_port/include/freertos/FreeRTOSConfig_arch.h new file mode 100644 index 000000000000..6be035cb860f --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_port/include/freertos/FreeRTOSConfig_arch.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef FREERTOS_CONFIG_XTENSA_H +#define FREERTOS_CONFIG_XTENSA_H + +//Xtensa Archiecture specific configuration. This file is included in the common FreeRTOSConfig.h. + +#include "sdkconfig.h" + +/* Required for configuration-dependent settings. */ +#include "xtensa_config.h" + +/* -------------------------------------------- Xtensa Additional Config ---------------------------------------------- + * - Provide Xtensa definitions usually given by -D option when building with xt-make (see readme_xtensa.txt) + * - xtensa_rtos.h and xtensa_timer.h will default some of these values + * - XT_SIMULATOR configXT_SIMULATOR + * - XT_BOARD configXT_BOARD + * - XT_CLOCK_FREQ Should not be defined as we are using XT_BOARD mode + * - XT_TICK_PER_SEC Defaults to configTICK_RATE_HZ + * - XT_TIMER_INDEX Defaults to configXT_TIMER_INDEX + * - XT_INTEXC_HOOKS Defaults to configXT_INTEXC_HOOKS + * - XT_USE_OVLY We don't define this (unused) + * - XT_USE_SWPRI We don't define this (unused) + * ------------------------------------------------------------------------------------------------------------------ */ + +#define configXT_SIMULATOR 0 +#define configXT_BOARD 1 /* Board mode */ +#if CONFIG_FREERTOS_CORETIMER_0 +#define configXT_TIMER_INDEX 0 +#elif CONFIG_FREERTOS_CORETIMER_1 +#define configXT_TIMER_INDEX 1 +#endif +#define configXT_INTEXC_HOOKS 0 + +#define configBENCHMARK 0 + +/* ------------------------------------------------- FreeRTOS Config --------------------------------------------------- + * - All Vanilla FreeRTOS configuration goes into this section + * ------------------------------------------------------------------------------------------------------------------ */ + +// ------------------ Scheduler Related -------------------- + +#ifdef CONFIG_FREERTOS_OPTIMIZED_SCHEDULER +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#else +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif +#define configMAX_API_CALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL + +/* ------------------------------------------------ ESP-IDF Additions -------------------------------------------------- + * + * ------------------------------------------------------------------------------------------------------------------ */ + +/* The Xtensa port uses a separate interrupt stack. Adjust the stack size + * to suit the needs of your specific application. + * Size needs to be aligned to the stack increment, since the location of + * the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE. + */ +#define configSTACK_ALIGNMENT 16 +#ifndef configISR_STACK_SIZE +#define configISR_STACK_SIZE ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1))) +#endif + +#endif // FREERTOS_CONFIG_XTENSA_H diff --git a/bsp/ESP/ESP32_S3/idf_port/include/freertos/freertos_tasks_c_additions.h b/bsp/ESP/ESP32_S3/idf_port/include/freertos/freertos_tasks_c_additions.h new file mode 100644 index 000000000000..cfcaafd4b5da --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_port/include/freertos/freertos_tasks_c_additions.h @@ -0,0 +1,434 @@ +/* + * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "sdkconfig.h" + +/** + * This file will be included in `tasks.c` file, thus, it must NOT be included + * by any (other) file. + * The functions below only consist in getters for the static variables in + * `tasks.c` file. + * The only source files that should call these functions are the ones in + * `/additions` directory. + */ + +/* ----------------------------------------------------- Newlib -------------------------------------------------------- + * + * ------------------------------------------------------------------------------------------------------------------ */ + +#if (configUSE_NEWLIB_REENTRANT == 1) +/** + * @brief Get reentrancy structure of the current task + * + * - This funciton is required by newlib (when __DYNAMIC_REENT__ is enabled) + * - It will return a pointer to the current task's reent struct + * - If FreeRTOS is not running, it will return the global reent struct + * + * @return Pointer to a the (current taks's)/(globa) reent struct + */ +struct _reent *__getreent(void) +{ + // No lock needed because if this changes, we won't be running anymore. + struct _reent *ret; +#if !defined CONFIG_IDF_RTOS_RTTHREAD + TCB_t *pxCurTask = xTaskGetCurrentTaskHandle(); + if (pxCurTask == NULL) + { + // No task running. Return global struct. + ret = _GLOBAL_REENT; + } + else + { + // We have a task; return its reentrant struct. + ret = &pxCurTask->xNewLib_reent; + } +#else + ret = _GLOBAL_REENT; +#endif + return ret; +} +#endif // configUSE_NEWLIB_REENTRANT == 1 + +/* -------------------------------------------------- Task Snapshot ---------------------------------------------------- + * + * ------------------------------------------------------------------------------------------------------------------ */ + +#if CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT + +#include "task_snapshot.h" + +/** + * @brief List of all task lists in FreeRTOS + * + * @note There are currently differing number of task list between SMP FreeRTOS and ESP-IDF FreeRTOS + */ +static List_t *non_ready_task_lists[] = { +#ifdef CONFIG_FREERTOS_SMP + &xPendingReadyList, +#else + &xPendingReadyList[0], +#ifndef CONFIG_FREERTOS_UNICORE + &xPendingReadyList[1], +#endif // CONFIG_FREERTOS_UNICORE +#endif //CONFIG_FREERTOS_SMP + &xDelayedTaskList1, + &xDelayedTaskList2, +#if (INCLUDE_vTaskDelete == 1) + &xTasksWaitingTermination, +#endif +#if (INCLUDE_vTaskSuspend == 1) + &xSuspendedTaskList, +#endif +}; + +/** + * @brief Get the next task list to traverse + * + * - Given a particular task list, this function returns the next task to traverse. + * - The task lists are returned in the following precedence + * - Ready lists (highest to lowers priority) + * - Pending ready list(s) + * - Delayed list 1 + * - Delayed list 2 + * - Waiting termination list + * - Suspended list + * + * @param pxCurTaskList Previously traversed task list (or NULL if obtaining the first task list) + * @return List_t* The next task list to traverse (or NULL of all task lists have been traversed) + */ +static List_t *pxGetNextTaskList(List_t *pxCurTaskList) +{ + List_t *pxNextTaskList = NULL; + + // No Current List. Start from the highest priority ready task list + if (pxCurTaskList == NULL) + { + pxNextTaskList = &pxReadyTasksLists[configMAX_PRIORITIES - 1]; + } + // Current list is one of the ready task lists. Find the current priority, and return the next lower priority ready task list + else if (pxCurTaskList >= &pxReadyTasksLists[0] && pxCurTaskList <= &pxReadyTasksLists[configMAX_PRIORITIES - 1]) + { + // Find the current priority + int cur_priority; + for (cur_priority = configMAX_PRIORITIES - 1; cur_priority >= 0; cur_priority--) + { + if (pxCurTaskList == &pxReadyTasksLists[cur_priority]) + { + break; + } + } + // Return the ready task list at (cur_priority - 1), or the pending ready task list + if (cur_priority > 0) + { + pxNextTaskList = &pxReadyTasksLists[cur_priority - 1]; + } + // We've reached the end of the Ready Task Lists. We get the next list from the non-ready task lists + else if (cur_priority == 0) + { + pxNextTaskList = non_ready_task_lists[0]; + } + else + { + abort(); // This should never occur + } + } + + // Current list is one of the non-ready task lists. Fetch the next non-ready task list + if (pxNextTaskList == NULL) + { + int cur_list_idx; + const int num_non_ready_task_lists = (sizeof(non_ready_task_lists) / sizeof(List_t *)); + // Note: - 1 so that if the current list is the last on non_ready_task_lists[], the next list will return NULL + for (cur_list_idx = 0; cur_list_idx < num_non_ready_task_lists - 1; cur_list_idx++) + { + if (pxCurTaskList == non_ready_task_lists[cur_list_idx]) + { + pxNextTaskList = non_ready_task_lists[cur_list_idx + 1]; + break; + } + } + } + + return pxNextTaskList; +} + +TaskHandle_t pxTaskGetNext(TaskHandle_t pxTask) +{ + TCB_t *pxTCB = (TCB_t *)pxTask; + // Check current task is valid + if (pxTCB != NULL && !portVALID_TCB_MEM(pxTCB)) + { + return NULL; + } + + List_t *pxCurTaskList; + const ListItem_t *pxCurListItem; + if (pxTCB == NULL) + { + // Starting traversal for the first time + pxCurTaskList = pxGetNextTaskList(NULL); + pxCurListItem = listGET_END_MARKER(pxCurTaskList); + } + else + { + // Continuing traversal + pxCurTaskList = listLIST_ITEM_CONTAINER(&pxTCB->xStateListItem); + pxCurListItem = &pxTCB->xStateListItem; + } + + ListItem_t *pxNextListItem = NULL; + if (pxCurListItem->pxNext == listGET_END_MARKER(pxCurTaskList)) + { + List_t *pxNextTaskList = pxGetNextTaskList(pxCurTaskList); + while (pxNextTaskList != NULL) + { + if (!listLIST_IS_EMPTY(pxNextTaskList)) + { + // Get the first item in the next task list + pxNextListItem = listGET_HEAD_ENTRY(pxNextTaskList); + break; + } + // Task list is empty. Get the next task list + pxNextTaskList = pxGetNextTaskList(pxNextTaskList); + } + } + else + { + //There are still more items in the current task list. Get the next item + pxNextListItem = listGET_NEXT(pxCurListItem); + } + + TCB_t *pxNextTCB; + if (pxNextListItem == NULL) + { + pxNextTCB = NULL; + } + else + { + pxNextTCB = (TCB_t *)listGET_LIST_ITEM_OWNER(pxNextListItem); + } + + return pxNextTCB; +} + +BaseType_t vTaskGetSnapshot(TaskHandle_t pxTask, TaskSnapshot_t *pxTaskSnapshot) +{ + if (portVALID_TCB_MEM(pxTask) == false || pxTaskSnapshot == NULL) + { + return pdFALSE; + } + + TCB_t *pxTCB = (TCB_t *)pxTask; + pxTaskSnapshot->pxTCB = pxTCB; + pxTaskSnapshot->pxTopOfStack = (StackType_t *)pxTCB->pxTopOfStack; + pxTaskSnapshot->pxEndOfStack = (StackType_t *)pxTCB->pxEndOfStack; + return pdTRUE; +} + +UBaseType_t uxTaskGetSnapshotAll(TaskSnapshot_t * const pxTaskSnapshotArray, const UBaseType_t uxArrayLength, UBaseType_t * const pxTCBSize) +{ + UBaseType_t uxArrayNumFilled = 0; + + //Traverse all of the tasks lists + List_t *pxCurTaskList = pxGetNextTaskList(NULL); //Get the first task list + while (pxCurTaskList != NULL && uxArrayNumFilled < uxArrayLength) + { + if (!listLIST_IS_EMPTY(pxCurTaskList)) + { + const ListItem_t *pxCurListItem; + //Walk each task on the current task list + pxCurListItem = listGET_HEAD_ENTRY(pxCurTaskList); + while (pxCurListItem != listGET_END_MARKER(pxCurTaskList)) + { + TCB_t *pxTCB = (TCB_t *)listGET_LIST_ITEM_OWNER(pxCurListItem); + vTaskGetSnapshot((TaskHandle_t)pxTCB, &pxTaskSnapshotArray[uxArrayNumFilled]); + uxArrayNumFilled++; + if (!(uxArrayNumFilled < uxArrayLength)) + { + break; + } + pxCurListItem = listGET_NEXT(pxCurListItem); + } + } + //Get the next task list + pxCurTaskList = pxGetNextTaskList(pxCurTaskList); + } + + *pxTCBSize = sizeof(TCB_t); + return uxArrayNumFilled; +} +#endif // CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT + +/* ----------------------------------------------------- OpenOCD ------------------------------------------------------- + * + * ------------------------------------------------------------------------------------------------------------------ */ + +#if (configENABLE_FREERTOS_DEBUG_OCDAWARE == 1) + +/** + * Debug param indexes. DO NOT change the order. OpenOCD uses the same indexes + * Entries in FreeRTOS_openocd_params must match the order of these indexes + */ +enum +{ + ESP_FREERTOS_DEBUG_TABLE_SIZE = 0, + ESP_FREERTOS_DEBUG_TABLE_VERSION, + ESP_FREERTOS_DEBUG_KERNEL_VER_MAJOR, + ESP_FREERTOS_DEBUG_KERNEL_VER_MINOR, + ESP_FREERTOS_DEBUG_KERNEL_VER_BUILD, + ESP_FREERTOS_DEBUG_UX_TOP_USED_PIORITY, + ESP_FREERTOS_DEBUG_PX_TOP_OF_STACK, + ESP_FREERTOS_DEBUG_PC_TASK_NAME, + /* New entries must be inserted here */ + ESP_FREERTOS_DEBUG_TABLE_END, +}; + +const DRAM_ATTR uint8_t FreeRTOS_openocd_params[ESP_FREERTOS_DEBUG_TABLE_END] = { + ESP_FREERTOS_DEBUG_TABLE_END, /* table size */ + 1, /* table version */ + tskKERNEL_VERSION_MAJOR, + tskKERNEL_VERSION_MINOR, + tskKERNEL_VERSION_BUILD, + configMAX_PRIORITIES - 1, /* uxTopUsedPriority */ + offsetof(TCB_t, pxTopOfStack), /* thread_stack_offset; */ + offsetof(TCB_t, pcTaskName), /* thread_name_offset; */ +}; + +#endif // configENABLE_FREERTOS_DEBUG_OCDAWARE == 1 + +/* -------------------------------------------- FreeRTOS IDF API Additions --------------------------------------------- + * FreeRTOS related API that were added by IDF + * ------------------------------------------------------------------------------------------------------------------ */ + +#if CONFIG_FREERTOS_SMP +_Static_assert(tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "CONFIG_FREERTOS_NO_AFFINITY must be the same as tskNO_AFFINITY"); + +BaseType_t xTaskCreatePinnedToCore(TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + const BaseType_t xCoreID) +{ + BaseType_t ret; +#if ((configUSE_CORE_AFFINITY == 1) && (configNUM_CORES > 1)) + { + // Convert xCoreID into an affinity mask + UBaseType_t uxCoreAffinityMask; + if (xCoreID == tskNO_AFFINITY) + { + uxCoreAffinityMask = tskNO_AFFINITY; + } + else + { + uxCoreAffinityMask = (1 << xCoreID); + } + ret = xTaskCreateAffinitySet(pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask); + } +#else /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUM_CORES > 1 ) ) */ + { + ret = xTaskCreate(pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask); + } +#endif /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUM_CORES > 1 ) ) */ + return ret; +} + +#if (configSUPPORT_STATIC_ALLOCATION == 1) +TaskHandle_t xTaskCreateStaticPinnedToCore(TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + const BaseType_t xCoreID) +{ + TaskHandle_t ret; +#if ((configUSE_CORE_AFFINITY == 1) && (configNUM_CORES > 1)) + { + // Convert xCoreID into an affinity mask + UBaseType_t uxCoreAffinityMask; + if (xCoreID == tskNO_AFFINITY) + { + uxCoreAffinityMask = tskNO_AFFINITY; + } + else + { + uxCoreAffinityMask = (1 << xCoreID); + } + ret = xTaskCreateStaticAffinitySet(pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask); + } +#else /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUM_CORES > 1 ) ) */ + { + ret = xTaskCreateStatic(pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer); + } +#endif /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUM_CORES > 1 ) ) */ + return ret; +} +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +TaskHandle_t xTaskGetCurrentTaskHandleForCPU(BaseType_t xCoreID) +{ + TaskHandle_t xTaskHandleTemp; + assert(xCoreID >= 0 && xCoreID < configNUM_CORES); + taskENTER_CRITICAL(); + xTaskHandleTemp = (TaskHandle_t)pxCurrentTCBs[xCoreID]; + taskEXIT_CRITICAL(); + return xTaskHandleTemp; +} + +TaskHandle_t xTaskGetIdleTaskHandleForCPU(BaseType_t xCoreID) +{ + assert(xCoreID >= 0 && xCoreID < configNUM_CORES); + return (TaskHandle_t)xIdleTaskHandle[xCoreID]; +} + +BaseType_t xTaskGetAffinity(TaskHandle_t xTask) +{ + taskENTER_CRITICAL(); + UBaseType_t uxCoreAffinityMask; +#if (configUSE_CORE_AFFINITY == 1 && configNUM_CORES > 1) + TCB_t *pxTCB = prvGetTCBFromHandle(xTask); + uxCoreAffinityMask = pxTCB->uxCoreAffinityMask; +#else + uxCoreAffinityMask = tskNO_AFFINITY; +#endif + taskEXIT_CRITICAL(); + BaseType_t ret; + // If the task is not pinned to a particular core, treat it as tskNO_AFFINITY + if (uxCoreAffinityMask & (uxCoreAffinityMask - 1)) + { // If more than one bit set + ret = tskNO_AFFINITY; + } + else + { + int index_plus_one = __builtin_ffs(uxCoreAffinityMask); + assert(index_plus_one >= 1); + ret = index_plus_one - 1; + } + return ret; +} + +#if (CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS) +void vTaskSetThreadLocalStoragePointerAndDelCallback(TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue, TlsDeleteCallbackFunction_t pvDelCallback) +{ + // Verify that the offsets of pvThreadLocalStoragePointers and pvDummy15 match. + // pvDummy15 is part of the StaticTask_t struct and is used to access the TLSPs + // while deletion. + _Static_assert(offsetof(StaticTask_t, pvDummy15) == offsetof(TCB_t, pvThreadLocalStoragePointers), "Offset of pvDummy15 must match the offset of pvThreadLocalStoragePointers"); + + //Set the local storage pointer first + vTaskSetThreadLocalStoragePointer(xTaskToSet, xIndex, pvValue); + + //Set the deletion callback at an offset of configNUM_THREAD_LOCAL_STORAGE_POINTERS/2 + vTaskSetThreadLocalStoragePointer(xTaskToSet, (xIndex + (configNUM_THREAD_LOCAL_STORAGE_POINTERS / 2)), pvDelCallback); +} +#endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS + +#endif // CONFIG_FREERTOS_SMP diff --git a/bsp/ESP/ESP32_S3/idf_port/include/freertos/portmacro.h b/bsp/ESP/ESP32_S3/idf_port/include/freertos/portmacro.h new file mode 100644 index 000000000000..8d220b7669a4 --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_port/include/freertos/portmacro.h @@ -0,0 +1,370 @@ +/* + * SPDX-FileCopyrightText: 2020 Amazon.com, Inc. or its affiliates + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifndef __ASSEMBLER__ + +#include "sdkconfig.h" +#include +#include +#include +#include +#include "spinlock.h" +#include "soc/interrupt_core0_reg.h" +#include "esp_macros.h" +#include "esp_attr.h" +#include "esp_cpu.h" +#include "esp_rom_sys.h" +#include "esp_heap_caps.h" +#include "esp_system.h" /* required by esp_get_...() functions in portable.h. [refactor-todo] Update portable.h */ +#include "esp_newlib.h" +#include "rtthread.h" + +/* [refactor-todo] These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */ +#include + +/* [refactor-todo] introduce a port wrapper function to avoid including esp_timer.h into the public header */ +#if CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER +#include "esp_timer.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* --------------------------------------------------- Port Types ------------------------------------------------------ + * - Port specific types. + * - The settings in this file configure FreeRTOS correctly for the given hardware and compiler. + * - These settings should not be altered. + * - The port types must come first as they are used further down in this file + * ------------------------------------------------------------------------------------------------------------------ */ + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE rt_ubase_t +#define portBASE_TYPE rt_base_t + +typedef portSTACK_TYPE StackType_t; +typedef rt_base_t BaseType_t; +typedef rt_ubase_t UBaseType_t; +typedef rt_tick_t TickType_t; +#define portMAX_DELAY (TickType_t) RT_TICK_MAX + +struct rt_semaphore_wrapper +{ + struct rt_semaphore sem; + rt_uint16_t max_value; +}; + + +/* ----------------------------------------------- Port Configurations ------------------------------------------------- + * - Configurations values supplied by each port + * - Required by FreeRTOS + * ------------------------------------------------------------------------------------------------------------------ */ + +#define portTICK_PERIOD_MS ((TickType_t)(1000 / configTICK_RATE_HZ)) +#define portBYTE_ALIGNMENT RT_ALIGN_SIZE +#define portNOP() __asm volatile(" nop ") + + +/* ---------------------------------------------- Forward Declarations ------------------------------------------------- + * - Forward declarations of all the port functions and macros need to implement the FreeRTOS porting interface + * - These must come before definition/declaration of the FreeRTOS porting interface + * ------------------------------------------------------------------------------------------------------------------ */ + +// --------------------- Interrupts ------------------------ + +/** + * @brief Checks if the current core is in an ISR context + * + * - ISR context consist of Low/Mid priority ISR, or time tick ISR + * - High priority ISRs aren't detected here, but they normally cannot call C code, so that should not be an issue anyway. + * + * @note [refactor-todo] Check if this should be inlined + * @return + * - pdTRUE if in ISR + * - pdFALSE otherwise + */ +BaseType_t xPortInIsrContext(void); + +/** + * @brief Check if in ISR context from High priority ISRs + * + * - Called from High priority ISR + * - Checks if the previous context (before high priority interrupt) was in ISR context (meaning low/med priority) + * + * @note [refactor-todo] Check if this should be inlined + * @return + * - pdTRUE if in previous in ISR context + * - pdFALSE otherwise + */ +BaseType_t xPortInterruptedFromISRContext(void); + +/* ---------------------- Spinlocks ------------------------ + - Spinlocks added to match API with SMP FreeRTOS. Single core RISC-V does not need spin locks + - Because single core does not have a primitive spinlock data type, we have to implement one here + * @note [refactor-todo] Refactor critical section API so that this is no longer required + * ------------------------------------------------------ */ + +/** + * @brief Spinlock object + * Owner: + * - Set to 0 if uninitialized + * - Set to portMUX_FREE_VAL when free + * - Set to CORE_ID_REGVAL_PRO or CORE_ID_REGVAL_AP when locked + * - Any other value indicates corruption + * Count: + * - 0 if unlocked + * - Recursive count if locked + * + * @note Not a true spinlock as single core RISC-V does not have atomic compare and set instruction + * @note Keep portMUX_INITIALIZER_UNLOCKED in sync with this struct + */ +typedef struct +{ + uint32_t owner; + uint32_t count; +} portMUX_TYPE; +/**< Spinlock initializer */ +#define portMUX_INITIALIZER_UNLOCKED { \ + .owner = portMUX_FREE_VAL, \ + .count = 0, \ +} +#define portMUX_FREE_VAL SPINLOCK_FREE /**< Spinlock is free. [refactor-todo] check if this is still required */ +#define portMUX_NO_TIMEOUT SPINLOCK_WAIT_FOREVER /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */ +#define portMUX_TRY_LOCK SPINLOCK_NO_WAIT /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */ +#define portMUX_INITIALIZE(mux) ({ \ + (mux)->owner = portMUX_FREE_VAL; \ + (mux)->count = 0; \ +}) + +// ------------------ Critical Sections -------------------- + +/** + * @brief Enter a critical section + * + * - Simply disable interrupts + * - Can be nested + */ +void vPortEnterCritical(void); + +/** + * @brief Exit a critical section + * + * - Reenables interrupts + * - Can be nested + */ +void vPortExitCritical(void); + +// ---------------------- Yielding ------------------------- + +/** + * @brief Perform a context switch from a task + * + * @note [refactor-todo] The rest of ESP-IDF should call taskYield() instead + */ +#define vPortYield(void) rt_thread_yield() + +/** + * @brief Checks if the current core can yield + * + * - A core cannot yield if its in an ISR or in a critical section + * + * @note [refactor-todo] See if this can be separated from port macro + * @note [refactor-todo] Check if this function should be renamed (due to bool return type) + * @return true Core can yield + * @return false Core cannot yield + */ +FORCE_INLINE_ATTR bool xPortCanYield(void); + +// ----------------------- System -------------------------- + +/** + * @brief Get the tick rate per second + * + * @note [refactor-todo] make this inline + * @note [refactor-todo] Check if this function should be renamed (due to uint return type) + * @return uint32_t Tick rate in Hz + */ +uint32_t xPortGetTickRateHz(void); + +/** + * @brief Set a watchpoint to watch the last 32 bytes of the stack + * + * Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack watchpoint + * around. + * + * @param pxStackStart Pointer to the start of the stack + */ +void vPortSetStackWatchpoint(void *pxStackStart); + +/** + * @brief Get the current core's ID + * + * @note Added to be compatible with SMP API + * @note [refactor-todo] IDF should call a FreeRTOS like macro instead of port function directly + * @return BaseType_t Core ID + */ +FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void) +{ + return (BaseType_t)esp_cpu_get_core_id(); +} + + +/* ------------------------------------------- FreeRTOS Porting Interface ---------------------------------------------- + * - Contains all the mappings of the macros required by FreeRTOS + * - Most come after forward declare as porting macros map to declared functions + * - Maps to forward declared functions + * ------------------------------------------------------------------------------------------------------------------ */ + +// --------------------- Interrupts ------------------------ + +#define portDISABLE_INTERRUPTS() vPortEnterCritical() +#define portENABLE_INTERRUPTS() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() rt_hw_interrupt_disable() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedStatusValue) rt_hw_interrupt_enable(uxSavedStatusValue) + +// ------------------ Critical Sections -------------------- + +#define portENTER_CRITICAL(mux) \ + { \ + (void)mux; \ + vPortEnterCritical(); \ + } +#define portEXIT_CRITICAL(mux) \ + { \ + (void)mux; \ + vPortExitCritical(); \ + } +#define portTRY_ENTER_CRITICAL(mux, timeout) ({ \ + (void)mux; \ + (void)timeout; \ + vPortEnterCritical(); \ + BaseType_t ret = pdPASS; \ + ret; \ +}) +//In single-core RISC-V, we can use the same critical section API +#define portENTER_CRITICAL_ISR(mux) portENTER_CRITICAL(mux) +#define portEXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL(mux) +#define portTRY_ENTER_CRITICAL_ISR(mux, timeout) portTRY_ENTER_CRITICAL(mux, timeout) + +/* [refactor-todo] on RISC-V, both ISR and non-ISR cases result in the same call. We can redefine this macro */ +#define portENTER_CRITICAL_SAFE(mux) ({ \ + if (xPortInIsrContext()) \ + { \ + portENTER_CRITICAL_ISR(mux); \ + } \ + else \ + { \ + portENTER_CRITICAL(mux); \ + } \ +}) +#define portEXIT_CRITICAL_SAFE(mux) ({ \ + if (xPortInIsrContext()) \ + { \ + portEXIT_CRITICAL_ISR(mux); \ + } \ + else \ + { \ + portEXIT_CRITICAL(mux); \ + } \ +}) +#define portTRY_ENTER_CRITICAL_SAFE(mux, timeout) portTRY_ENTER_CRITICAL(mux, timeout) + +// ---------------------- Yielding ------------------------- + +#define portYIELD() rt_thread_yield() +#define portYIELD_FROM_ISR_NO_ARG() rt_thread_yield() +#define portYIELD_FROM_ISR_ARG(xHigherPriorityTaskWoken) ({ \ + if (xHigherPriorityTaskWoken == pdTRUE) \ + { \ + rt_thread_yield(); \ + } \ +}) +/** + * @note The macro below could be used when passing a single argument, or without any argument, + * it was developed to support both usages of portYIELD inside of an ISR. Any other usage form + * might result in undesired behavior + */ +#if defined(__cplusplus) && (__cplusplus > 201703L) +#define portYIELD_FROM_ISR(...) CHOOSE_MACRO_VA_ARG(portYIELD_FROM_ISR_ARG, portYIELD_FROM_ISR_NO_ARG __VA_OPT__(, ) __VA_ARGS__)(__VA_ARGS__) +#else +#define portYIELD_FROM_ISR(...) CHOOSE_MACRO_VA_ARG(portYIELD_FROM_ISR_ARG, portYIELD_FROM_ISR_NO_ARG, ##__VA_ARGS__)(__VA_ARGS__) +#endif + + +/* --------------------------------------------- Inline Implementations ------------------------------------------------ + * - Implementation of inline functions of the forward declares + * - Should come after forward declare and FreeRTOS Porting interface, as implementation may use both. + * - For implementation of non-inlined functions, see port.c, port_common.c, or other assembly files + * ------------------------------------------------------------------------------------------------------------------ */ + +// --------------------- Interrupts ------------------------ + +// ---------------------- Yielding ------------------------- + +FORCE_INLINE_ATTR bool xPortCanYield(void) +{ + rt_base_t level = rt_interrupt_get_nest(); + return (level == 0); +} + +#define FREERTOS_PRIORITY_TO_RTTHREAD(priority) (configMAX_PRIORITIES - 1 - (priority)) +#define RTTHREAD_PRIORITY_TO_FREERTOS(priority) (RT_THREAD_PRIORITY_MAX - 1 - (priority)) +/* Use this macro to calculate the buffer size when allocating a queue statically + * To ensure the buffer can fit the desired number of messages + */ +#define QUEUE_BUFFER_SIZE(uxQueueLength, uxItemSize) ((RT_ALIGN(uxItemSize, RT_ALIGN_SIZE) + sizeof(void *)) * uxQueueLength) + +BaseType_t rt_err_to_freertos(rt_err_t rt_err); + +#if CONFIG_APPTRACE_SV_ENABLE +extern int xPortSwitchFlag; +#define os_task_switch_is_pended(_cpu_) (xPortSwitchFlag) +#else +#define os_task_switch_is_pended(_cpu_) (false) +#endif + +#ifdef __cplusplus +} +#endif + +#endif //__ASSEMBLER__ + +#endif /* PORTMACRO_H */ diff --git a/bsp/ESP/ESP32_S3/idf_port/include/freertos/task_snapshot.h b/bsp/ESP/ESP32_S3/idf_port/include/freertos/task_snapshot.h new file mode 100644 index 000000000000..7489351beb33 --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_port/include/freertos/task_snapshot.h @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT || defined __DOXYGEN__ +/** + * @brief Task Snapshot structure + * + * - Used with the uxTaskGetSnapshotAll() function to save memory snapshot of each task in the system. + * - We need this structure because TCB_t is defined (hidden) in tasks.c. + */ +typedef struct xTASK_SNAPSHOT +{ + void *pxTCB; /*!< Address of the task control block. */ + StackType_t *pxTopOfStack; /*!< Points to the location of the last item placed on the tasks stack. */ + StackType_t *pxEndOfStack; /*!< Points to the end of the stack. pxTopOfStack < pxEndOfStack, stack grows hi2lo + pxTopOfStack > pxEndOfStack, stack grows lo2hi*/ +} TaskSnapshot_t; + +/** + * @brief Iterate over all tasks in the system + * + * - This function can be used to iterate over every task in the system + * - The first call to this function must set pxTask to NULL + * - When all functions have been iterated, this function will return NULL. + * - This function is only available when CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT is set to 1. + * + * @note This function should only be called when FreeRTOS is no longer running (e.g., during a panic) as this function + * does not acquire any locks. + * @param pxTask Handle of the previous task (or NULL on the first call of this function) + * @return TaskHandle_t Handle of the next task (or NULL when all tasks have been iterated over) + */ +TaskHandle_t pxTaskGetNext(TaskHandle_t pxTask); + +/** + * @brief Fill a TaskSnapshot_t structure for specified task. + * + * - This function is used by the panic handler to get the snapshot of a particular task. + * - This function is only available when CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT is set to 1. + * + * @note This function should only be called when FreeRTOS is no longer running (e.g., during a panic) as this function + * does not acquire any locks. + * @param[in] pxTask Task's handle + * @param[out] pxTaskSnapshot Snapshot of the task + * @return pdTRUE if operation was successful else pdFALSE + */ +BaseType_t vTaskGetSnapshot(TaskHandle_t pxTask, TaskSnapshot_t *pxTaskSnapshot); + +/** + * @brief Fill an array of TaskSnapshot_t structures for every task in the system + * + * - This function is used by the panic handler to get a snapshot of all tasks in the system + * - This function is only available when CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT is set to 1. + * + * @note This function should only be called when FreeRTOS is no longer running (e.g., during a panic) as this function + * does not acquire any locks. + * @param[out] pxTaskSnapshotArray Array of TaskSnapshot_t structures filled by this function + * @param[in] uxArrayLength Length of the provided array + * @param[out] pxTCBSize Size of the a task's TCB structure + * @return UBaseType_t + */ +UBaseType_t uxTaskGetSnapshotAll(TaskSnapshot_t * const pxTaskSnapshotArray, const UBaseType_t uxArrayLength, UBaseType_t * const pxTCBSize); + +#endif // CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT || defined __DOXYGEN__ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/ESP/ESP32_S3/idf_port/ld/memory.ld b/bsp/ESP/ESP32_S3/idf_port/ld/memory.ld new file mode 100644 index 000000000000..1040a8ede992 --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_port/ld/memory.ld @@ -0,0 +1,26 @@ + + +_esp_flash_mmap_prefetch_pad_size = 16; +_esp_memprot_prefetch_pad_size = 16; +_esp_memprot_align_size = 256; +_esp_mmu_block_size = (0x10000); +MEMORY +{ + iram0_0_seg (RX) : org = (0x40370000 + 0x4000), len = (((0x403CC700 - (0x40378000 - 0x3FC88000)) - 0x3FC88000) + 0x8000 - 0x4000) + iram0_2_seg (RX) : org = 0x42000020, len = 0x800000-0x20 + dram0_0_seg (RW) : org = (0x3FC88000), len = ((0x403CC700 - (0x40378000 - 0x3FC88000)) - 0x3FC88000) + drom0_0_seg (R) : org = 0x3C000020, len = 0x2000000-0x20 + rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000 - (0 + (24)) + rtc_reserved_seg(RW) : org = 0x600fe000 + 0x2000 - (0 + (24)), len = (0 + (24)) + rtc_slow_seg(RW) : org = 0x50000000 , len = 0x2000 + extern_ram_seg(RWX) : org = 0x3c000020 , len = 0x2000000-0x20 +} +_heap_start = _heap_low_start; +_heap_end = 0x40000000; +_data_seg_org = ORIGIN(rtc_data_seg); +REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); +REGION_ALIAS("rtc_data_location", rtc_slow_seg ); +REGION_ALIAS("default_code_seg", iram0_2_seg); +REGION_ALIAS("default_rodata_seg", drom0_0_seg); + ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg), + ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.") diff --git a/bsp/ESP/ESP32_S3/idf_port/ld/sections.ld b/bsp/ESP/ESP32_S3/idf_port/ld/sections.ld new file mode 100644 index 000000000000..44d60fb4bbca --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_port/ld/sections.ld @@ -0,0 +1,532 @@ +/* + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Default entry point */ +ENTRY(call_start_cpu0); + +_diram_i_start = 0x40378000; + +SECTIONS +{ + /** + * RTC fast memory holds RTC wake stub code, + * including from any source file named rtc_wake_stub*.c + */ + .rtc.text : + { + . = ALIGN(4); + _rtc_fast_start = ABSOLUTE(.); + _rtc_text_start = ABSOLUTE(.); + *(.rtc.entry.text) + + *(.rtc.literal .rtc.text .rtc.text.*) + + *rtc_wake_stub*.*(.literal .text .literal.* .text.*) + *(.rtc_text_end_test) + + /* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */ + . += _esp_memprot_prefetch_pad_size; + . = ALIGN(4); + + _rtc_text_end = ABSOLUTE(.); + } > rtc_iram_seg + + /** + * This section located in RTC FAST Memory area. + * It holds data marked with RTC_FAST_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_fast : + { + . = ALIGN(4); + _rtc_force_fast_start = ABSOLUTE(.); + + *(.rtc.force_fast .rtc.force_fast.*) + + *(.rtc.force_fast .rtc.force_fast.*) + . = ALIGN(4) ; + _rtc_force_fast_end = ABSOLUTE(.); + } > rtc_data_seg + + /** + * RTC data section holds RTC wake stub + * data/rodata, including from any source file + * named rtc_wake_stub*.c and the data marked with + * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + * The memory location of the data is dependent on + * CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM option. + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + + *(.rtc.data .rtc.data.*) + + *rtc_wake_stub*.*(.data .rodata .data.* .rodata.*) + _rtc_data_end = ABSOLUTE(.); + } > rtc_data_location + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.*(.bss .bss.*) + *rtc_wake_stub*.*(COMMON) + + *(.rtc.bss .rtc.bss.*) + + _rtc_bss_end = ABSOLUTE(.); + } > rtc_data_location + + /** + * This section holds data that should not be initialized at power up + * and will be retained during deep sleep. + * User data marked with RTC_NOINIT_ATTR will be placed + * into this section. See the file "esp_attr.h" for more information. + * The memory location of the data is dependent on CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM option. + */ + .rtc_noinit (NOLOAD): + { + . = ALIGN(4); + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } > rtc_data_location + + /** + * This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } > rtc_slow_seg + + /** + * This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ + .rtc_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. + Because data have adhered to the end of the segment and code is relied on it. + >> put new data here << */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + + _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start; + ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)), + "RTC reserved segment data does not fit.") + + /* Get size of rtc slow data based on rtc_data_location alias */ + _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) + ? (_rtc_force_slow_end - _rtc_data_start) + : (_rtc_force_slow_end - _rtc_force_slow_start); + + _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) + ? (_rtc_force_fast_end - _rtc_fast_start) + : (_rtc_noinit_end - _rtc_fast_start); + + ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), + "RTC_SLOW segment data does not fit.") + + ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), + "RTC_FAST segment data does not fit.") + + /* Send .iram0 code to iram */ + .iram0.vectors : + { + _iram_start = ABSOLUTE(.); + /* Vectors go to IRAM */ + _vector_table = ABSOLUTE(.); + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + _invalid_pc_placeholder = ABSOLUTE(.); + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.text : + { + /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); + + *(.iram1 .iram1.*) *(.iram .iram.*) + + } > iram0_0_seg + + /** + * This section is required to skip .iram0.text area because iram0_0_seg and + * dram0_0_seg reflect the same address space on different buses. + */ + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + MAX(_iram_end - _diram_i_start, 0); + } > dram0_0_seg + + .dram0.data : + { + _data_start = ABSOLUTE(.); + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + + *(.data .data.*) + + /* .dram1. holds DRAM_ATTR writable data that must live in internal RAM. + Collecting it here also prevents orphan output sections that broke DROM + contiguity required by esptool's 64KB flash mapping. */ + *(.dram1 .dram1.*) + + _data_end = ABSOLUTE(.); + . = ALIGN(4); + } > dram0_0_seg + + /** + * This section holds data that should not be initialized at power up. + * The section located in Internal SRAM memory region. The macro _NOINIT + * can be used as attribute to place data into this section. + * See the "esp_attr.h" file for more information. + */ + .noinit (NOLOAD): + { + . = ALIGN(4); + _noinit_start = ABSOLUTE(.); + *(.noinit .noinit.*) + . = ALIGN(4) ; + _noinit_end = ABSOLUTE(.); + } > dram0_0_seg + + /* RT-Thread system heap, carved out of DRAM before .bss. + * The fork's esp_system/startup.c calls + * rt_system_heap_init(&__heap_start__, &__heap_end__); ESP-IDF's own + * generated script has no such symbols (it exposes _heap_low_start for + * heap_caps), so this mirrors the patch the ESP32-C3 BSP applies to its + * sections.ld. Size kept at the C3 value; S3 has more DRAM, it can grow. */ + .heap (NOLOAD) : + { + . = ALIGN(8); + __HEAPSIZE__ = 76800; + __heap_start__ = .; + . += __HEAPSIZE__; + __heap_end__ = .; + } > dram0_0_seg + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + + *(.bss .bss.*) + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.share.mem) + *(.gnu.linkonce.b.*) + + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } > dram0_0_seg + + ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + + .flash.text : + { + _stext = .; + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ + _text_start = ABSOLUTE(.); + + *(.literal .text .literal.* .text.*) + + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /** CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += _esp_flash_mmap_prefetch_pad_size; + + _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ + _etext = .; + + /** + * Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } > default_code_seg + + /** + * This dummy section represents the .flash.text section but in default_rodata_seg. + * Thus, it must have its alignment and (at least) its size. + */ + .flash_rodata_dummy (NOLOAD): + { + _flash_rodata_dummy_start = ABSOLUTE(.); + /* Start at the same alignment constraint than .flash.text */ + . = ALIGN(ALIGNOF(.flash.text)); + /* Create an empty gap as big as .flash.text section */ + . = . + SIZEOF(.flash.text); + /* Prepare the alignment of the section above. Few bytes (0x20) must be + * added for the mapping header. */ + . = ALIGN(_esp_mmu_block_size) + 0x20; + } > default_rodata_seg + + .flash.appdesc : ALIGN(0x10) + { + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ + _rodata_start = ABSOLUTE(.); + + *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ + *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ + + /* Create an empty gap within this section. Thanks to this, the end of this + * section will match .flah.rodata's begin address. Thus, both sections + * will be merged when creating the final bin image. */ + . = ALIGN(ALIGNOF(.flash.rodata)); + } >default_rodata_seg + + .flash.rodata : ALIGN(0x10) + { + _flash_rodata_start = ABSOLUTE(.); + + *(.rodata .rodata.*) + + /* RT-Thread finsh tables: MSH_CMD_EXPORT / MSH_CMD_EXPORT_ALIAS put one + entry per command in FSymTab, and MS_VARI_ADAPT / MSH_CMD_EXPORT_VAR put + variables in VSymTab. The shell walks the range between these symbols, so + without these two lines msh would start with no commands at all. */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)); + __fsymtab_end = .; + . = ALIGN(8); + __vsymtab_start = .; + KEEP(*(VSymTab)); + __vsymtab_end = .; + . = ALIGN(8); + /* RT-Thread component init table. INIT_*_EXPORT puts a function pointer in + a .rti_fn. section and the level markers ("0", "0.end", "1.end", + "6.end") are emitted by src/components.c itself, so all that is needed + here is to collect the entries in name order between those markers. + Without this line every EXPORT is placed by an implicit rule out of order + and the ranges the kernel walks come out empty: nothing registers (the + "uart" serial device included), even though its code is linked in. */ + KEEP(*(SORT(.rti_fn*))); + . = ALIGN(8); + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + /* C++ constructor and destructor tables */ + /* Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt */ + __init_array_start = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*))) + __init_array_end = ABSOLUTE(.); + KEEP (*crtbegin.*(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ + soc_reserved_memory_region_start = ABSOLUTE(.); + KEEP (*(.reserved_memory_address)) + soc_reserved_memory_region_end = ABSOLUTE(.); + /* System init functions registered via ESP_SYSTEM_INIT_FN */ + _esp_system_init_fn_array_start = ABSOLUTE(.); + KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*))) + _esp_system_init_fn_array_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _thread_local_start = ABSOLUTE(.); + *(.tdata) + *(.tdata.*) + *(.tbss) + *(.tbss.*) + _thread_local_end = ABSOLUTE(.); + . = ALIGN(4); + } > default_rodata_seg + + _flash_rodata_align = ALIGNOF(.flash.rodata); + + /* + This section is a place where we dump all the rodata which aren't used at runtime, + so as to avoid binary size increase + */ + .flash.rodata_noload (NOLOAD) : + { + /* + This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address + We don't need to include the noload rodata in this section + */ + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN (4); + *(.rodata_noload .rodata_noload.*) + } > default_rodata_seg + + /** + * This section is required to skip flash rodata sections, because `extern_ram_seg` + * and `drom0_0_seg` are on the same bus + */ + .ext_ram.dummy (NOLOAD): + { + . = ORIGIN(extern_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start); + . = ALIGN (0x10000); + } > extern_ram_seg + + /* This section holds .ext_ram.bss data, and will be put in PSRAM */ + .ext_ram.bss (NOLOAD) : + { + _ext_ram_bss_start = ABSOLUTE(.); + + . = ALIGN(4); + _ext_ram_bss_end = ABSOLUTE(.); + } > extern_ram_seg + + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : + { + /* iram_end_test section exists for use by memprot unit tests only */ + *(.iram_end_test) + /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */ + . += _esp_memprot_prefetch_pad_size; + . = ALIGN(_esp_memprot_align_size); + _iram_text_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.data : + { + . = ALIGN(4); + _iram_data_start = ABSOLUTE(.); + + *(.iram.data .iram.data.*) + + _iram_data_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(4); + _iram_bss_start = ABSOLUTE(.); + + *(.iram.bss .iram.bss.*) + + _iram_bss_end = ABSOLUTE(.); + . = ALIGN(4); + _iram_end = ABSOLUTE(.); + } > iram0_0_seg + + /* Marks the end of data, bss and possibly rodata */ + .dram0.heap_start (NOLOAD) : + { + . = ALIGN (8); + /* Lowest possible start address for the heap */ + _heap_low_start = ABSOLUTE(.); + } > dram0_0_seg + + /** This section will be used by the debugger and disassembler to get more information + * about raw data present in the code. + * Indeed, it may be required to add some padding at some points in the code + * in order to align a branch/jump destination on a particular bound. + * Padding these instructions will generate null bytes that shall be + * interpreted as data, and not code by the debugger or disassembler. + * This section will only be present in the ELF file, not in the final binary + * For more details, check GCC-212 + */ + .xt.prop 0 : + { + KEEP (*(.xt.prop .gnu.linkonce.prop.*)) + } + + .xt.lit 0 : + { + KEEP (*(.xt.lit .gnu.linkonce.p.*)) + } +} + +ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), + "IRAM0 segment data does not fit.") + +ASSERT(((_heap_low_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), + "DRAM segment data does not fit.") diff --git a/bsp/ESP/ESP32_S3/idf_port/src/port.c b/bsp/ESP/ESP32_S3/idf_port/src/port.c new file mode 100644 index 000000000000..8b0ef1e39641 --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_port/src/port.c @@ -0,0 +1,58 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * ESP32-S3 (Xtensa) app-startup glue for the RT-Thread ESP BSP family. + * + * Derived from ESP-IDF's FreeRTOS-Kernel portable/xtensa/port.c (Apache-2.0) + * the same way the ESP32-C3 BSP derives its RISC-V counterpart: only the + * functions IDF code actually calls through the FreeRTOS-Wrapper shim are + * kept; the RISC-V include set is dropped and nothing Xtensa-specific beyond + * the core id is needed (coprocessor and vector handling live in + * libcpu/xtensa/esp32s3, not here). + * + * Change Logs: + * Date Author Notes + * 2026-09-27 RT-Thread first version (ESP32-S3) + */ + +#include "sdkconfig.h" +#include +#include "esp_attr.h" +#include "esp_system.h" +#include "esp_log.h" +#include +#include "FreeRTOS.h" /* This pulls in portmacro.h */ +#include "task.h" +#include "portmacro.h" + +static const char *TAG = "cpu_start"; + +/* ---------------------------------------------- Port Implementations --- */ + +BaseType_t xPortInIsrContext(void) +{ + return (BaseType_t)rt_interrupt_get_nest(); +} + +BaseType_t IRAM_ATTR xPortInterruptedFromISRContext(void) +{ + /* single core: reading the nesting counter is atomic wrt this task */ + return (BaseType_t)rt_interrupt_get_nest(); +} + +uint32_t xPortGetTickRateHz(void) +{ + return (uint32_t)configTICK_RATE_HZ; +} + +/* ---------------------------------------------- Misc Implementations --- */ + +extern void esp_startup_start_app_common(void); + +void esp_startup_start_app(void) +{ + esp_startup_start_app_common(); + + ESP_LOGI(TAG, "Starting scheduler."); + vTaskStartScheduler(); +} diff --git a/bsp/ESP/ESP32_S3/idf_port/src/port_common.c b/bsp/ESP/ESP32_S3/idf_port/src/port_common.c new file mode 100644 index 000000000000..4d90adf0a9c6 --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_port/src/port_common.c @@ -0,0 +1,142 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" +#include "esp_private/esp_int_wdt.h" +#include "esp_system.h" +#include "esp_heap_caps_init.h" +#include "esp_task_wdt.h" +#include "esp_task.h" +#include "esp_private/crosscore_int.h" +#include "esp_log.h" +#include "esp_memory_utils.h" +#include "esp_freertos_hooks.h" +#include "sdkconfig.h" +#include "esp_freertos_hooks.h" + +#if CONFIG_SPIRAM +#include "esp_psram.h" +#include "esp_private/esp_psram_extram.h" +#endif + +#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL +static const char *TAG = "cpu_start"; +#endif + +/* Architecture-agnostic parts of the FreeRTOS ESP-IDF port layer can go here. + * + * The actual call flow will be to call esp_startup_start_app() in /port.c, + * which will then call esp_startup_start_app_common() + */ + +// Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting +volatile unsigned port_xSchedulerRunning[portNUM_PROCESSORS] = { 0 }; + +// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) +// is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE +// should mirror each other's values. +// +// And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. +#if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE +#error "FreeRTOS and system configuration mismatch regarding the use of multiple cores." +#endif + +#if !defined CONFIG_IDF_RTOS_RTTHREAD +static void main_task(void *args); +#endif + +#ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME +void esp_gdbstub_init(void); +#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME + +extern void app_main(void); + +void esp_startup_start_app_common(void) +{ +#if CONFIG_ESP_INT_WDT + esp_int_wdt_init(); + //Initialize the interrupt watch dog for CPU0. + esp_int_wdt_cpu_init(); +#endif + + esp_crosscore_int_init(); + +#if CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME && !CONFIG_IDF_TARGET_ESP32C2 + esp_gdbstub_init(); +#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME + +#if !defined CONFIG_IDF_RTOS_RTTHREAD + portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main", + ESP_TASK_MAIN_STACK, NULL, + ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE); + assert(res == pdTRUE); + (void)res; +#endif +} + +#if !CONFIG_FREERTOS_UNICORE +static volatile bool s_other_cpu_startup_done = false; +static bool other_cpu_startup_idle_hook_cb(void) +{ + s_other_cpu_startup_done = true; + return true; +} +#endif + +#if !defined CONFIG_IDF_RTOS_RTTHREAD +static void main_task(void *args) +{ +#if !CONFIG_FREERTOS_UNICORE + // Wait for FreeRTOS initialization to finish on other core, before replacing its startup stack + esp_register_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID()); + while (!s_other_cpu_startup_done) + { + ; + } + esp_deregister_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID()); +#endif + + // [refactor-todo] check if there is a way to move the following block to esp_system startup + heap_caps_enable_nonos_stack_heaps(); + + // Now we have startup stack RAM available for heap, enable any DMA pool memory +#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL + if (esp_psram_is_initialized()) + { + esp_err_t r = esp_psram_extram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL); + if (r != ESP_OK) + { + ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool (error 0x%x)", r); + abort(); + } + } +#endif + + //Initialize TWDT if configured to do so +#if CONFIG_ESP_TASK_WDT + esp_task_wdt_config_t twdt_config = { + .timeout_ms = CONFIG_ESP_TASK_WDT_TIMEOUT_S * 1000, + .idle_core_mask = 0, +#if CONFIG_ESP_TASK_WDT_PANIC + .trigger_panic = true, +#endif + }; +#if CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 + twdt_config.idle_core_mask |= (1 << 0); +#endif +#if CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 + twdt_config.idle_core_mask |= (1 << 1); +#endif + ESP_ERROR_CHECK(esp_task_wdt_init(&twdt_config)); +#endif // CONFIG_ESP_TASK_WDT + + app_main(); + vTaskDelete(NULL); +} +#endif diff --git a/bsp/ESP/ESP32_S3/idf_port/src/rt-thread_balance_stub.c b/bsp/ESP/ESP32_S3/idf_port/src/rt-thread_balance_stub.c new file mode 100644 index 000000000000..bdea08ba5b96 --- /dev/null +++ b/bsp/ESP/ESP32_S3/idf_port/src/rt-thread_balance_stub.c @@ -0,0 +1,142 @@ +/* + * Link-compat shims for the ESP32-S3 BSP. + * + * The ESP32-C3 original also stubs out ceil()/floor() because the RISC-V + * multilib setup pulls no libm; the Xtensa toolchain links real libm through + * g++, so stubbing them here would silently mis-round IDF's math - they are + * deliberately NOT stubbed in this BSP. + * + * _end/_edata: referenced by IDF heap/newlib sbrk glue but not emitted by the + * esp32s3 sections.ld fragment (same situation as the C3 BSP handled here). + * + * opendir/readdir/closedir/select: newlib syscall entry points that would + * otherwise resolve against the VFS component, which this BSP does not + * compile (same rationale as ESP32-C3; kept because the xtensa newlib here is + * the same fork-provided library). + */ +#include "rtconfig.h" + +void _end(void) +{ + return; +} + +void _edata(void) +{ + return; +} + +#ifndef BSP_USING_BLE /* the BLE component brings VFS, which provides these */ +void opendir(void) +{ + return; +} + +void readdir(void) +{ + return; +} + +void closedir(void) +{ + return; +} + +void select(void) +{ + return; +} +#endif /* BSP_USING_BLE */ + +/* + * Link-compat stubs for ESP-IDF files that v1 of this BSP keeps in the build + * for boot-path reasons but whose optional features are switched off: + * + * - bootloader_sha256_* : image-signature checking. The real implementation + * lives on mbedtls, which is not compiled (no Wi-Fi/TLS). The app never + * verifies its own image at runtime; the second-stage bootloader we ship + * carries its own copy. Prototypes per + * components/bootloader_support/private_include/bootloader_sha.h. + * - esp_flash_encryption_enabled : defined by flash_encrypt.c (excluded, + * flash encryption off). Referenced unconditionally from bootloader_flash.c + * / esp_ota_ops / bootloader_utility. + * - task_wdt_timeout_abort_xtensa : esp_system/task_wdt.c compiles to nothing + * with CONFIG_ESP_TASK_WDT_INIT=0 (its xtensa abort path needs the real + * FreeRTOS snapshot API, absent in the RT-Thread wrapper), but + * esp_system/crosscore_int.c still references the symbol. + */ +#include +#include +#include + +void *bootloader_sha256_start(void); +void bootloader_sha256_data(void *handle, const void *data, size_t len); +void bootloader_sha256_finish(void *handle, uint8_t *digest); + +void *bootloader_sha256_start(void) +{ + return NULL; +} + +void bootloader_sha256_data(void *handle, const void *data, size_t len) +{ + (void)handle; + (void)data; + (void)len; +} + +void bootloader_sha256_finish(void *handle, uint8_t *digest) +{ + (void)handle; + if (digest) + { + for (int i = 0; i < 32; i++) + { + digest[i] = 0; + } + } +} + +bool esp_flash_encryption_enabled(void) +{ + return false; +} + +void task_wdt_timeout_abort_xtensa(bool current_core) +{ + (void)current_core; +} + +/* + * Debug aid while bringing the port up: esp_system_abort() is the common + * funnel of abort()/ESP_ERROR_CHECK/assert and its panic path is silent + * before the console exists. Linked via -Wl,--wrap=esp_system_abort (see + * rtconfig.py): print the reason with the ROM printf, then halt. + */ +void __attribute__((noreturn)) __wrap_esp_system_abort(const char *details) +{ + extern int esp_rom_printf(const char *fmt, ...); + esp_rom_printf("\nrt-s3: esp_system_abort: %s\n", details ? details : "(null)"); + for (;;) + { + } +} + +/* + * ESP32-S3 bring-up note (flash): + * The fork's esp_flash_api.c esp_flash_init_main() fast path reads the chip id + * out of the ROM legacy struct (rom_spiflash_legacy_data at 0x3fceffe4, struct + * at 0x3fcef6a4). On this board the other fields (chip_size 8MB, sector 4KB, + * status mask) survive, but device_id arrives 0, and the fork's live-RDID + * fallback path (written around a C6 cache-suspend bug) ends in + * ESP_ERR_NOT_FOUND at startup.c's assert. Until that fork bug is fixed + * properly, this BSP bypasses default-chip init: the bootloader already mapped + * the flash (partition table + app run through the cache), read-only access + * needs no driver re-init, and v1 offers no flash write/OTA API. + * -Wl,--wrap=esp_flash_init_default_chip routes startup.c's call here. + */ +typedef int esp_err_t; +esp_err_t __wrap_esp_flash_init_default_chip(void) +{ + return 0 /* ESP_OK */; +} diff --git a/bsp/ESP/ESP32_S3/main/SConscript b/bsp/ESP/ESP32_S3/main/SConscript new file mode 100644 index 000000000000..284e033584b7 --- /dev/null +++ b/bsp/ESP/ESP32_S3/main/SConscript @@ -0,0 +1,11 @@ +import os +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + +CPPPATH = [] + +group = DefineGroup('Main', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/ESP/ESP32_S3/main/main.c b/bsp/ESP/ESP32_S3/main/main.c new file mode 100644 index 000000000000..307ed14a2d09 --- /dev/null +++ b/bsp/ESP/ESP32_S3/main/main.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-09-27 RT-Thread first version (ESP32-S3-DevKitM-1) + */ + +#include + +/* + * v1 of this BSP brings up msh over UART0. + * GPIO, Wi-Fi, BLE and the on-board LED are left for later. + */ +int main(void) +{ + rt_kprintf("Hello! RT-Thread on ESP32-S3-DevKitM-1\r\n"); + while (1) + { + rt_thread_mdelay(10000); + } +} diff --git a/bsp/ESP/ESP32_S3/rtconfig.h b/bsp/ESP/ESP32_S3/rtconfig.h new file mode 100644 index 000000000000..d9aa83a460f0 --- /dev/null +++ b/bsp/ESP/ESP32_S3/rtconfig.h @@ -0,0 +1,417 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define IDLE_THREAD_STACK_SIZE 2048 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 2048 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x50301 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 4096 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +#define PKG_USING_FREERTOS_WRAPPER +#define PKG_FREERTOS_USING_CONFIG_H +#define PKG_USING_FREERTOS_WRAPPER_LATEST_VERSION +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ +#define PKG_USING_ESP_IDF +#define PKG_USING_ESP_IDF_LATEST_VERSION + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_ESPRESSIF +#define SOC_ESP32_S3 + +/* Hardware Drivers Config */ + +#define BSP_BOARD_ESP32S3_DEVKITM1 + +/* Onboard Peripheral Drivers */ + +#define RT_BSP_UART_PORT 0 +#define RT_BSP_UART_TX_PIN 43 +#define RT_BSP_UART_RX_PIN 44 +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/ESP/ESP32_S3/rtconfig.py b/bsp/ESP/ESP32_S3/rtconfig.py new file mode 100644 index 000000000000..dfb82e535fd6 --- /dev/null +++ b/bsp/ESP/ESP32_S3/rtconfig.py @@ -0,0 +1,64 @@ +import os +import sys + +BSP_ROOT = os.path.dirname(os.path.abspath(__file__)) +RTT_ROOT = os.getenv('RTT_ROOT') or os.path.normpath(os.path.join(BSP_ROOT, '..', '..', '..')) +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from env_package import find_package_path + +# toolchains options +ARCH ='xtensa' +CPU ='esp32s3' +CROSS_TOOL ='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'~/.espressif/tools/xtensa-esp32s3-elf/esp-12.2.0_20230208/xtensa-esp32s3-elf/bin' +else: + print('Please make sure your toolchains is GNU GCC!') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') +EXEC_PATH = os.path.expanduser(EXEC_PATH) + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'xtensa-esp32s3-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'g++' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + # -mlongcalls is what ESP-IDF uses everywhere: plain jumps cannot reach + # across the 0x3C000000/0x40370000/0x600xxxxx ranges this SoC maps code + # and ROM into. --specs=nosys.specs drops libgloss syscalls; the IDF + # newlib port in the ESP-IDF package provides the real ones. + DEVICE = ' -nostartfiles -mlongcalls --specs=nosys.specs -fasynchronous-unwind-tables ' + CFLAGS = DEVICE + '-include ../../components/libc/compilers/common/include/sys/ioctl.h -gdwarf-4 -ggdb -Og ' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + idf_path = find_package_path(BSP_ROOT, 'ESP-IDF-latest', relative_to=BSP_ROOT, pathsep='/') + # memory.ld + sections.ld under idf_port/ld are generated from ESP-IDF + # 5.1.4's esp32s3 templates (see idf_port/ld/ header comments); the ROM + # alias scripts and peripheral map come straight from the package. + LFLAGS = DEVICE + ' -Wl,--cref -Wl,--defsym=IDF_TARGET_ESP32S3=0 -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,call_start_cpu0 -T idf_port/ld/memory.ld -T idf_port/ld/sections.ld -T ' + idf_path + '/components/esp_rom/esp32s3/ld/esp32s3.rom.ld -T ' + idf_path + '/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld -T ' + idf_path + '/components/esp_rom/esp32s3/ld/esp32s3.rom.libgcc.ld -T ' + idf_path + '/components/esp_rom/esp32s3/ld/esp32s3.rom.newlib.ld -T ' + idf_path + '/components/esp_rom/esp32s3/ld/esp32s3.rom.version.ld -T ' + idf_path + '/components/soc/esp32s3/ld/esp32s3.peripherals.ld -Wl,--wrap=esp_system_abort -Wl,--wrap=esp_flash_init_default_chip ' + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -Oihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/ESP/libraries/drivers/Kconfig b/bsp/ESP/libraries/drivers/Kconfig index aa8c664423fe..a4d2f137bc8b 100644 --- a/bsp/ESP/libraries/drivers/Kconfig +++ b/bsp/ESP/libraries/drivers/Kconfig @@ -15,6 +15,15 @@ config SOC_ESP32_C3 select PKG_USING_FREERTOS_WRAPPER select PKG_FREERTOS_USING_CONFIG_H +config SOC_ESP32_S3 + bool "ESP32-S3" + select SOC_ESPRESSIF + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select PKG_USING_ESP_IDF + select PKG_USING_FREERTOS_WRAPPER + select PKG_FREERTOS_USING_CONFIG_H + config SOC_ESP32_C6 bool "ESP32-C6" select SOC_ESPRESSIF @@ -29,6 +38,7 @@ menu "Hardware Drivers Config" choice BSP_BOARD_SEL prompt "Select BSP board " + default BSP_BOARD_ESP32S3_DEVKITM1 if SOC_ESP32_S3 default BSP_BOARD_ESP32C6_DEVKITC1 if SOC_ESP32_C6 default BSP_BOARD_LUATOS_ESP32C3 @@ -40,6 +50,9 @@ choice BSP_BOARD_SEL bool "HONGXU ESP32C3 board" depends on SOC_ESP32_C3 + config BSP_BOARD_ESP32S3_DEVKITM1 + bool "ESP32-S3-DevKitM-1 board" + depends on SOC_ESP32_S3 config BSP_BOARD_ESP32C6_DEVKITC1 bool "ESP32-C6-DevKitC-1" depends on SOC_ESP32_C6 @@ -50,7 +63,7 @@ menu "Onboard Peripheral Drivers" int "LED GPIO PIN SET" default 12 if BSP_BOARD_LUATOS_ESP32C3 default 8 if BSP_BOARD_HX_EXP32C3 - depends on BSP_USING_GPIO && !BSP_BOARD_ESP32C6_DEVKITC1 + depends on BSP_USING_GPIO && !BSP_BOARD_ESP32C6_DEVKITC1 && !BSP_BOARD_ESP32S3_DEVKITM1 config RT_BSP_UART_PORT int "UART PORT SET" @@ -60,12 +73,14 @@ menu "Onboard Peripheral Drivers" config RT_BSP_UART_TX_PIN int "UART TX PIN SET" default 21 if BSP_BOARD_LUATOS_ESP32C3 + default 43 if BSP_BOARD_ESP32S3_DEVKITM1 default 16 if BSP_BOARD_ESP32C6_DEVKITC1 depends on BSP_USING_UART config RT_BSP_UART_RX_PIN int "UART RX PIN SET" default 20 if BSP_BOARD_LUATOS_ESP32C3 + default 44 if BSP_BOARD_ESP32S3_DEVKITM1 default 17 if BSP_BOARD_ESP32C6_DEVKITC1 depends on BSP_USING_UART diff --git a/bsp/ESP/libraries/drivers/board.c b/bsp/ESP/libraries/drivers/board.c index a97400216bce..6eb74bc00f37 100644 --- a/bsp/ESP/libraries/drivers/board.c +++ b/bsp/ESP/libraries/drivers/board.c @@ -20,14 +20,25 @@ #include "esp_attr.h" #include "esp_timer.h" #include "driver/gptimer.h" +#ifdef SOC_ESP32_S3 +#include /* XCHAL_INTLEVEL1_MASK */ +#endif static systimer_hal_context_t systimer_hal; IRAM_ATTR void rt_SysTickIsrHandler(void *arg) { systimer_ll_clear_alarm_int(systimer_hal.dev, SYSTIMER_LL_ALARM_OS_TICK_CORE0); +#ifdef SOC_ESP32_S3 + /* rt_interrupt_enter()/rt_interrupt_leave() are already around the whole + * level-1 dispatch, in rt_xt_irq_process() (libcpu/xtensa/esp32s3/cpuport.c). + * Counting them here too would make rt_interrupt_get_nest() report two + * interrupts for one. */ + rt_tick_increase(); +#else rt_interrupt_enter(); rt_tick_increase(); rt_interrupt_leave(); +#endif } void rt_hw_systick_init(void) @@ -45,9 +56,35 @@ void rt_hw_systick_init(void) systimer_hal_connect_alarm_counter(&systimer_hal, SYSTIMER_LL_ALARM_OS_TICK_CORE0, SYSTIMER_LL_COUNTER_OS_TICK); systimer_hal_set_alarm_period(&systimer_hal, SYSTIMER_LL_ALARM_OS_TICK_CORE0, 1000000UL / RT_TICK_PER_SECOND); systimer_hal_select_alarm_mode(&systimer_hal, SYSTIMER_LL_ALARM_OS_TICK_CORE0, SYSTIMER_ALARM_MODE_PERIOD); +#ifdef SOC_ESP32_S3 + /* SYSTIMER unit1 (the OS tick counter) has per-CPU "stall" enables that come + * out of reset set for both CPUs. This image runs core 0 only, so core 1 is + * never running and its stall line keeps unit1 frozen: the alarm compares + * against a counter stuck at 0 and no tick interrupt is ever raised. + * Free-running the counter is what light sleep would otherwise stop, and + * this BSP does not use light sleep. */ + systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 0, false); + systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 1, false); +#else systimer_hal_counter_can_stall_by_cpu(&systimer_hal, 1, 0, true); +#endif systimer_hal_enable_alarm_int(&systimer_hal, SYSTIMER_LL_ALARM_OS_TICK_CORE0); systimer_hal_enable_counter(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK); +#ifdef SOC_ESP32_S3 + /* This BSP services level-1 interrupts only: the tick and UART0 both + * allocate one, and its level 2-5 vectors are fatal by design. ESP-IDF's + * startup leaves sources enabled that nothing here asked for -- on this + * board two of them sit at level 4, one being ETS_LCD_CAM_INTR_SOURCE -- + * and an enabled source that is never serviced would reach a fatal vector. + * Mask everything above level 1 so that cannot happen. */ + { + uint32_t ie; + + __asm__ __volatile__("rsr %0, intenable" : "=r"(ie)); + ie &= XCHAL_INTLEVEL1_MASK; + __asm__ __volatile__("wsr %0, intenable; rsync" ::"r"(ie) : "memory"); + } +#endif } #ifdef SOC_ESP32_C6 diff --git a/bsp/ESP/libraries/drivers/drv_uart.c b/bsp/ESP/libraries/drivers/drv_uart.c index c226e2ca7a49..f9b09ee89cd0 100644 --- a/bsp/ESP/libraries/drivers/drv_uart.c +++ b/bsp/ESP/libraries/drivers/drv_uart.c @@ -124,6 +124,10 @@ int rt_hw_uart_init(void) #if CONFIG_UART_ISR_IN_IRAM intr_alloc_flags = ESP_INTR_FLAG_IRAM; #endif +#ifdef SOC_ESP32_S3 + /* This BSP services level-1 interrupts only: its level 2-5 vectors are fatal. */ + intr_alloc_flags |= ESP_INTR_FLAG_LEVEL1; +#endif ESP_ERROR_CHECK(uart_param_config(RT_BSP_UART_PORT, &uart_config)); ESP_ERROR_CHECK(uart_set_pin(RT_BSP_UART_PORT, RT_BSP_UART_TX_PIN, RT_BSP_UART_RX_PIN, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE)); diff --git a/bsp/ESP/libraries/drivers/sdkconfig.h b/bsp/ESP/libraries/drivers/sdkconfig.h index 0f6a4eba6225..237ebb2ceddf 100644 --- a/bsp/ESP/libraries/drivers/sdkconfig.h +++ b/bsp/ESP/libraries/drivers/sdkconfig.h @@ -4,7 +4,9 @@ */ #include "rtconfig.h" #pragma once -#ifdef SOC_ESP32_C6 +#ifdef SOC_ESP32_S3 +#include "sdkconfig_s3.h" +#elif defined(SOC_ESP32_C6) #include "sdkconfig_c6.h" #else #define CONFIG_SOC_ADC_SUPPORTED 1 diff --git a/bsp/ESP/libraries/drivers/sdkconfig_s3.h b/bsp/ESP/libraries/drivers/sdkconfig_s3.h new file mode 100644 index 000000000000..538c987391cd --- /dev/null +++ b/bsp/ESP/libraries/drivers/sdkconfig_s3.h @@ -0,0 +1,931 @@ +/* ESP32-S3 configuration. + * + * Body is ESP-IDF v5.1.4's generated sdkconfig.h for target esp32s3, + * single core, 8MB DIO flash, no Wi-Fi, no BLE, no PSRAM, + * UART0 console at 115200. + * + * CONFIG_IDF_RTOS_RTTHREAD is the switch the forked ESP-IDF-latest uses + * to hand control to RT-Thread instead of FreeRTOS; it is not an IDF + * option, so it is added here. + */ +#pragma once + +#define CONFIG_IDF_RTOS_RTTHREAD 1 +#define CONFIG_SOC_MPU_MIN_REGION_SIZE 0x20000000 +#define CONFIG_SOC_MPU_REGIONS_MAX_NUM 8 +#define CONFIG_SOC_ADC_SUPPORTED 1 +#define CONFIG_SOC_UART_SUPPORTED 1 +#define CONFIG_SOC_PCNT_SUPPORTED 1 +#define CONFIG_SOC_WIFI_SUPPORTED 1 +#define CONFIG_SOC_TWAI_SUPPORTED 1 +#define CONFIG_SOC_GDMA_SUPPORTED 1 +#define CONFIG_SOC_GPTIMER_SUPPORTED 1 +#define CONFIG_SOC_LCDCAM_SUPPORTED 1 +#define CONFIG_SOC_MCPWM_SUPPORTED 1 +#define CONFIG_SOC_DEDICATED_GPIO_SUPPORTED 1 +#define CONFIG_SOC_CACHE_SUPPORT_WRAP 1 +#define CONFIG_SOC_ULP_SUPPORTED 1 +#define CONFIG_SOC_ULP_FSM_SUPPORTED 1 +#define CONFIG_SOC_RISCV_COPROC_SUPPORTED 1 +#define CONFIG_SOC_BT_SUPPORTED 1 +#define CONFIG_SOC_USB_OTG_SUPPORTED 1 +#define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1 +#define CONFIG_SOC_CCOMP_TIMER_SUPPORTED 1 +#define CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED 1 +#define CONFIG_SOC_SUPPORTS_SECURE_DL_MODE 1 +#define CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define CONFIG_SOC_SDMMC_HOST_SUPPORTED 1 +#define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1 +#define CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED 1 +#define CONFIG_SOC_RTC_MEM_SUPPORTED 1 +#define CONFIG_SOC_PSRAM_DMA_CAPABLE 1 +#define CONFIG_SOC_XT_WDT_SUPPORTED 1 +#define CONFIG_SOC_I2S_SUPPORTED 1 +#define CONFIG_SOC_RMT_SUPPORTED 1 +#define CONFIG_SOC_SDM_SUPPORTED 1 +#define CONFIG_SOC_GPSPI_SUPPORTED 1 +#define CONFIG_SOC_LEDC_SUPPORTED 1 +#define CONFIG_SOC_I2C_SUPPORTED 1 +#define CONFIG_SOC_SYSTIMER_SUPPORTED 1 +#define CONFIG_SOC_SUPPORT_COEXISTENCE 1 +#define CONFIG_SOC_TEMP_SENSOR_SUPPORTED 1 +#define CONFIG_SOC_AES_SUPPORTED 1 +#define CONFIG_SOC_MPI_SUPPORTED 1 +#define CONFIG_SOC_SHA_SUPPORTED 1 +#define CONFIG_SOC_HMAC_SUPPORTED 1 +#define CONFIG_SOC_DIG_SIGN_SUPPORTED 1 +#define CONFIG_SOC_FLASH_ENC_SUPPORTED 1 +#define CONFIG_SOC_SECURE_BOOT_SUPPORTED 1 +#define CONFIG_SOC_MEMPROT_SUPPORTED 1 +#define CONFIG_SOC_TOUCH_SENSOR_SUPPORTED 1 +#define CONFIG_SOC_BOD_SUPPORTED 1 +#define CONFIG_SOC_XTAL_SUPPORT_40M 1 +#define CONFIG_SOC_APPCPU_HAS_CLOCK_GATING_BUG 1 +#define CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED 1 +#define CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED 1 +#define CONFIG_SOC_ADC_ARBITER_SUPPORTED 1 +#define CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +#define CONFIG_SOC_ADC_MONITOR_SUPPORTED 1 +#define CONFIG_SOC_ADC_DMA_SUPPORTED 1 +#define CONFIG_SOC_ADC_PERIPH_NUM 2 +#define CONFIG_SOC_ADC_MAX_CHANNEL_NUM 10 +#define CONFIG_SOC_ADC_ATTEN_NUM 4 +#define CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM 2 +#define CONFIG_SOC_ADC_PATT_LEN_MAX 24 +#define CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH 12 +#define CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH 12 +#define CONFIG_SOC_ADC_DIGI_RESULT_BYTES 4 +#define CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV 4 +#define CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM 2 +#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 +#define CONFIG_SOC_ADC_RTC_MIN_BITWIDTH 12 +#define CONFIG_SOC_ADC_RTC_MAX_BITWIDTH 12 +#define CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED 1 +#define CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED 1 +#define CONFIG_SOC_APB_BACKUP_DMA 1 +#define CONFIG_SOC_BROWNOUT_RESET_SUPPORTED 1 +#define CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED 1 +#define CONFIG_SOC_CACHE_FREEZE_SUPPORTED 1 +#define CONFIG_SOC_CPU_CORES_NUM 2 +#define CONFIG_SOC_CPU_INTR_NUM 32 +#define CONFIG_SOC_CPU_HAS_FPU 1 +#define CONFIG_SOC_CPU_BREAKPOINTS_NUM 2 +#define CONFIG_SOC_CPU_WATCHPOINTS_NUM 2 +#define CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 +#define CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN 4096 +#define CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH 16 +#define CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US 1100 +#define CONFIG_SOC_GDMA_GROUPS 1 +#define CONFIG_SOC_GDMA_PAIRS_PER_GROUP 5 +#define CONFIG_SOC_GDMA_SUPPORT_PSRAM 1 +#define CONFIG_SOC_GPIO_PORT 1 +#define CONFIG_SOC_GPIO_PIN_COUNT 49 +#define CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 +#define CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB 1 +#define CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT 1 +#define CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD 1 +#define CONFIG_SOC_GPIO_VALID_GPIO_MASK 0x1FFFFFFFFFFFF +#define CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0001FFFFFC000000 +#define CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM 8 +#define CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM 8 +#define CONFIG_SOC_DEDIC_GPIO_OUT_AUTO_ENABLE 1 +#define CONFIG_SOC_I2C_NUM 2 +#define CONFIG_SOC_I2C_FIFO_LEN 32 +#define CONFIG_SOC_I2C_CMD_REG_NUM 8 +#define CONFIG_SOC_I2C_SUPPORT_SLAVE 1 +#define CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS 1 +#define CONFIG_SOC_I2C_SUPPORT_XTAL 1 +#define CONFIG_SOC_I2C_SUPPORT_RTC 1 +#define CONFIG_SOC_I2S_NUM 2 +#define CONFIG_SOC_I2S_HW_VERSION_2 1 +#define CONFIG_SOC_I2S_SUPPORTS_XTAL 1 +#define CONFIG_SOC_I2S_SUPPORTS_PLL_F160M 1 +#define CONFIG_SOC_I2S_SUPPORTS_PCM 1 +#define CONFIG_SOC_I2S_SUPPORTS_PDM 1 +#define CONFIG_SOC_I2S_SUPPORTS_PDM_TX 1 +#define CONFIG_SOC_I2S_PDM_MAX_TX_LINES 2 +#define CONFIG_SOC_I2S_SUPPORTS_PDM_RX 1 +#define CONFIG_SOC_I2S_PDM_MAX_RX_LINES 4 +#define CONFIG_SOC_I2S_SUPPORTS_TDM 1 +#define CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK 1 +#define CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK 1 +#define CONFIG_SOC_LEDC_CHANNEL_NUM 8 +#define CONFIG_SOC_LEDC_TIMER_BIT_WIDTH 14 +#define CONFIG_SOC_LEDC_SUPPORT_FADE_STOP 1 +#define CONFIG_SOC_MCPWM_GROUPS 2 +#define CONFIG_SOC_MCPWM_TIMERS_PER_GROUP 3 +#define CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP 3 +#define CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR 2 +#define CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR 2 +#define CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR 2 +#define CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP 3 +#define CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP 1 +#define CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER 3 +#define CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP 3 +#define CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE 1 +#define CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM 1 +#define CONFIG_SOC_MMU_PERIPH_NUM 1 +#define CONFIG_SOC_PCNT_GROUPS 1 +#define CONFIG_SOC_PCNT_UNITS_PER_GROUP 4 +#define CONFIG_SOC_PCNT_CHANNELS_PER_UNIT 2 +#define CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT 2 +#define CONFIG_SOC_RMT_GROUPS 1 +#define CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP 4 +#define CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP 4 +#define CONFIG_SOC_RMT_CHANNELS_PER_GROUP 8 +#define CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL 48 +#define CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG 1 +#define CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION 1 +#define CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 +#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 +#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 +#define CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO 1 +#define CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 +#define CONFIG_SOC_RMT_SUPPORT_XTAL 1 +#define CONFIG_SOC_RMT_SUPPORT_RC_FAST 1 +#define CONFIG_SOC_RMT_SUPPORT_APB 1 +#define CONFIG_SOC_RMT_SUPPORT_DMA 1 +#define CONFIG_SOC_LCD_I80_SUPPORTED 1 +#define CONFIG_SOC_LCD_RGB_SUPPORTED 1 +#define CONFIG_SOC_LCD_I80_BUSES 1 +#define CONFIG_SOC_LCD_RGB_PANELS 1 +#define CONFIG_SOC_LCD_I80_BUS_WIDTH 16 +#define CONFIG_SOC_LCD_RGB_DATA_WIDTH 16 +#define CONFIG_SOC_LCD_SUPPORT_RGB_YUV_CONV 1 +#define CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH 128 +#define CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM 549 +#define CONFIG_SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH 128 +#define CONFIG_SOC_RTCIO_PIN_COUNT 22 +#define CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 +#define CONFIG_SOC_RTCIO_HOLD_SUPPORTED 1 +#define CONFIG_SOC_RTCIO_WAKE_SUPPORTED 1 +#define CONFIG_SOC_SDM_GROUPS 1 +#define CONFIG_SOC_SDM_CHANNELS_PER_GROUP 8 +#define CONFIG_SOC_SDM_CLK_SUPPORT_APB 1 +#define CONFIG_SOC_SPI_PERIPH_NUM 3 +#define CONFIG_SOC_SPI_MAX_CS_NUM 6 +#define CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE 64 +#define CONFIG_SOC_SPI_SUPPORT_DDRCLK 1 +#define CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define CONFIG_SOC_SPI_SUPPORT_CD_SIG 1 +#define CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 +#define CONFIG_SOC_SPI_SUPPORT_CLK_APB 1 +#define CONFIG_SOC_SPI_SUPPORT_CLK_XTAL 1 +#define CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1 +#define CONFIG_SOC_MEMSPI_IS_INDEPENDENT 1 +#define CONFIG_SOC_SPI_MAX_PRE_DIVIDER 16 +#define CONFIG_SOC_SPI_SUPPORT_OCT 1 +#define CONFIG_SOC_MEMSPI_SRC_FREQ_120M 1 +#define CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 +#define CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 +#define CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 +#define CONFIG_SOC_SPIRAM_SUPPORTED 1 +#define CONFIG_SOC_SPIRAM_XIP_SUPPORTED 1 +#define CONFIG_SOC_SYSTIMER_COUNTER_NUM 2 +#define CONFIG_SOC_SYSTIMER_ALARM_NUM 3 +#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO 32 +#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI 20 +#define CONFIG_SOC_SYSTIMER_FIXED_DIVIDER 1 +#define CONFIG_SOC_SYSTIMER_INT_LEVEL 1 +#define CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 +#define CONFIG_SOC_TIMER_GROUPS 2 +#define CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP 2 +#define CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH 54 +#define CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL 1 +#define CONFIG_SOC_TIMER_GROUP_SUPPORT_APB 1 +#define CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS 4 +#define CONFIG_SOC_TOUCH_VERSION_2 1 +#define CONFIG_SOC_TOUCH_SENSOR_NUM 15 +#define CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM 3 +#define CONFIG_SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED 1 +#define CONFIG_SOC_TOUCH_PAD_THRESHOLD_MAX 0x1FFFFF +#define CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX 0xFF +#define CONFIG_SOC_TWAI_CONTROLLER_NUM 1 +#define CONFIG_SOC_TWAI_CLK_SUPPORT_APB 1 +#define CONFIG_SOC_TWAI_BRP_MIN 2 +#define CONFIG_SOC_TWAI_BRP_MAX 16384 +#define CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS 1 +#define CONFIG_SOC_UART_NUM 3 +#define CONFIG_SOC_UART_FIFO_LEN 128 +#define CONFIG_SOC_UART_BITRATE_MAX 5000000 +#define CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND 1 +#define CONFIG_SOC_UART_SUPPORT_WAKEUP_INT 1 +#define CONFIG_SOC_UART_SUPPORT_APB_CLK 1 +#define CONFIG_SOC_UART_SUPPORT_RTC_CLK 1 +#define CONFIG_SOC_UART_SUPPORT_XTAL_CLK 1 +#define CONFIG_SOC_UART_REQUIRE_CORE_RESET 1 +#define CONFIG_SOC_USB_OTG_PERIPH_NUM 1 +#define CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE 3968 +#define CONFIG_SOC_SHA_SUPPORT_DMA 1 +#define CONFIG_SOC_SHA_SUPPORT_RESUME 1 +#define CONFIG_SOC_SHA_GDMA 1 +#define CONFIG_SOC_SHA_SUPPORT_SHA1 1 +#define CONFIG_SOC_SHA_SUPPORT_SHA224 1 +#define CONFIG_SOC_SHA_SUPPORT_SHA256 1 +#define CONFIG_SOC_SHA_SUPPORT_SHA384 1 +#define CONFIG_SOC_SHA_SUPPORT_SHA512 1 +#define CONFIG_SOC_SHA_SUPPORT_SHA512_224 1 +#define CONFIG_SOC_SHA_SUPPORT_SHA512_256 1 +#define CONFIG_SOC_SHA_SUPPORT_SHA512_T 1 +#define CONFIG_SOC_RSA_MAX_BIT_LEN 4096 +#define CONFIG_SOC_AES_SUPPORT_DMA 1 +#define CONFIG_SOC_AES_GDMA 1 +#define CONFIG_SOC_AES_SUPPORT_AES_128 1 +#define CONFIG_SOC_AES_SUPPORT_AES_256 1 +#define CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP 1 +#define CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP 1 +#define CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP 1 +#define CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP 1 +#define CONFIG_SOC_PM_SUPPORT_BT_WAKEUP 1 +#define CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP 1 +#define CONFIG_SOC_PM_SUPPORT_CPU_PD 1 +#define CONFIG_SOC_PM_SUPPORT_TAGMEM_PD 1 +#define CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD 1 +#define CONFIG_SOC_PM_SUPPORT_RC_FAST_PD 1 +#define CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD 1 +#define CONFIG_SOC_PM_SUPPORT_MAC_BB_PD 1 +#define CONFIG_SOC_PM_SUPPORT_MODEM_PD 1 +#define CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED 1 +#define CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY 1 +#define CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL 1 +#define CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA 1 +#define CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED 1 +#define CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 1 +#define CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION 1 +#define CONFIG_SOC_CLK_XTAL32K_SUPPORTED 1 +#define CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 +#define CONFIG_SOC_EFUSE_DIS_DOWNLOAD_DCACHE 1 +#define CONFIG_SOC_EFUSE_HARD_DIS_JTAG 1 +#define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 +#define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 +#define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 +#define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 +#define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +#define CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 +#define CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX 64 +#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1 +#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128 1 +#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256 1 +#define CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16 +#define CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE 256 +#define CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE 21 +#define CONFIG_SOC_MAC_BB_PD_MEM_SIZE 192 +#define CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH 12 +#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_OPI_MODE 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_TIME_TUNING 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_WRAP 1 +#define CONFIG_SOC_COEX_HW_PTI 1 +#define CONFIG_SOC_EXTERNAL_COEX_LEADER_TX_LINE 1 +#define CONFIG_SOC_SDMMC_USE_GPIO_MATRIX 1 +#define CONFIG_SOC_SDMMC_NUM_SLOTS 2 +#define CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK 1 +#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC 1 +#define CONFIG_SOC_WIFI_HW_TSF 1 +#define CONFIG_SOC_WIFI_FTM_SUPPORT 1 +#define CONFIG_SOC_WIFI_GCMP_SUPPORT 1 +#define CONFIG_SOC_WIFI_WAPI_SUPPORT 1 +#define CONFIG_SOC_WIFI_CSI_SUPPORT 1 +#define CONFIG_SOC_WIFI_MESH_SUPPORT 1 +#define CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW 1 +#define CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND 1 +#define CONFIG_SOC_BLE_SUPPORTED 1 +#define CONFIG_SOC_BLE_MESH_SUPPORTED 1 +#define CONFIG_SOC_BLE_50_SUPPORTED 1 +#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1 +#define CONFIG_SOC_BLUFI_SUPPORTED 1 +#define CONFIG_SOC_ULP_HAS_ADC 1 +#define CONFIG_SOC_PHY_COMBO_MODULE 1 +#define CONFIG_IDF_CMAKE 1 +#define CONFIG_IDF_TARGET_ARCH_XTENSA 1 +#define CONFIG_IDF_TARGET_ARCH "xtensa" +#define CONFIG_IDF_TARGET "esp32s3" +#define CONFIG_IDF_TARGET_ESP32S3 1 +#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0009 +#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1 +#define CONFIG_APP_BUILD_GENERATE_BINARIES 1 +#define CONFIG_APP_BUILD_BOOTLOADER 1 +#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1 +#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0 +#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1 +#define CONFIG_BOOTLOADER_LOG_LEVEL_INFO 1 +#define CONFIG_BOOTLOADER_LOG_LEVEL 3 +#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 +#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1 +#define CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE 1 +#define CONFIG_BOOTLOADER_WDT_ENABLE 1 +#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000 +#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0 +#define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 +#define CONFIG_SECURE_BOOT_V2_PREFERRED 1 +#define CONFIG_SECURE_ROM_DL_MODE_ENABLED 1 +#define CONFIG_APP_COMPILE_TIME_DATE 1 +#define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 16 +#define CONFIG_ESP_ROM_HAS_CRC_LE 1 +#define CONFIG_ESP_ROM_HAS_CRC_BE 1 +#define CONFIG_ESP_ROM_HAS_MZ_CRC32 1 +#define CONFIG_ESP_ROM_HAS_JPEG_DECODE 1 +#define CONFIG_ESP_ROM_UART_CLK_IS_XTAL 1 +#define CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING 1 +#define CONFIG_ESP_ROM_USB_OTG_NUM 3 +#define CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM 4 +#define CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG 1 +#define CONFIG_ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV 1 +#define CONFIG_ESP_ROM_GET_CLK_FREQ 1 +#define CONFIG_ESP_ROM_HAS_HAL_WDT 1 +#define CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND 1 +#define CONFIG_ESP_ROM_HAS_LAYOUT_TABLE 1 +#define CONFIG_ESP_ROM_HAS_SPI_FLASH 1 +#define CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG 1 +#define CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT 1 +#define CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE 1 +#define CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT 1 +#define CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG 1 +#define CONFIG_ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG 1 +#define CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG 1 +#define CONFIG_BOOT_ROM_LOG_ALWAYS_ON 1 +#define CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT 1 +#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1 +#define CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 1 +#define CONFIG_ESPTOOLPY_FLASHMODE "dio" +#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1 +#define CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT 1 +#define CONFIG_ESPTOOLPY_FLASHFREQ "80m" +#define CONFIG_ESPTOOLPY_FLASHSIZE_8MB 1 +#define CONFIG_ESPTOOLPY_FLASHSIZE "8MB" +#define CONFIG_ESPTOOLPY_BEFORE_RESET 1 +#define CONFIG_ESPTOOLPY_BEFORE "default_reset" +#define CONFIG_ESPTOOLPY_AFTER_RESET 1 +#define CONFIG_ESPTOOLPY_AFTER "hard_reset" +#define CONFIG_ESPTOOLPY_MONITOR_BAUD 115200 +#define CONFIG_PARTITION_TABLE_CUSTOM 1 +#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv" +#define CONFIG_PARTITION_TABLE_FILENAME "partitions.csv" +#define CONFIG_PARTITION_TABLE_OFFSET 0x8000 +#define CONFIG_PARTITION_TABLE_MD5 1 +#define CONFIG_COMPILER_OPTIMIZATION_DEFAULT 1 +#define CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE 1 +#define CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB 1 +#define CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL 2 +#define CONFIG_COMPILER_HIDE_PATHS_MACROS 1 +#define CONFIG_COMPILER_STACK_CHECK_MODE_NONE 1 +#define CONFIG_APPTRACE_DEST_NONE 1 +#define CONFIG_APPTRACE_DEST_UART_NONE 1 +#define CONFIG_APPTRACE_UART_TASK_PRIO 1 +#define CONFIG_APPTRACE_LOCK_ENABLE 1 +#define CONFIG_SPI_MASTER_ISR_IN_IRAM 1 +#define CONFIG_SPI_SLAVE_ISR_IN_IRAM 1 +#define CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM 1 +#define CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM 1 +#define CONFIG_EFUSE_MAX_BLK_LEN 256 +#define CONFIG_ESP_TLS_USING_MBEDTLS 1 +#define CONFIG_ESP_TLS_USE_DS_PERIPHERAL 1 +#define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1 +#define CONFIG_ETH_ENABLED 1 +#define CONFIG_ETH_USE_SPI_ETHERNET 1 +#define CONFIG_ESP_EVENT_POST_FROM_ISR 1 +#define CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR 1 +#define CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS 1 +#define CONFIG_HTTPD_MAX_REQ_HDR_LEN 512 +#define CONFIG_HTTPD_MAX_URI_LEN 512 +#define CONFIG_HTTPD_ERR_RESP_NO_DELAY 1 +#define CONFIG_HTTPD_PURGE_BUF_LEN 32 +#define CONFIG_ESP32S3_REV_MIN_0 1 +#define CONFIG_ESP32S3_REV_MIN_FULL 0 +#define CONFIG_ESP_REV_MIN_FULL 0 +#define CONFIG_ESP32S3_REV_MAX_FULL 99 +#define CONFIG_ESP_REV_MAX_FULL 99 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1 +#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR 1 +#define CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR 1 +#define CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES 4 +#define CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 1 +#define CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU 1 +#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1 +#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1 +#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 2000 +#define CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS 1 +#define CONFIG_RTC_CLK_SRC_INT_RC 1 +#define CONFIG_RTC_CLK_CAL_CYCLES 1024 +#define CONFIG_PERIPH_CTRL_FUNC_IN_IRAM 1 +#define CONFIG_XTAL_FREQ_40 1 +#define CONFIG_XTAL_FREQ 40 +#define CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE 32 +#define CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL 120 +#define CONFIG_ESP_NETIF_TCPIP_LWIP 1 +#define CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API 1 +#define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1 +#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20 +#define CONFIG_ESP_PHY_MAX_TX_POWER 20 +#define CONFIG_ESP_PHY_ENABLE_USB 1 +#define CONFIG_ESP_PHY_RF_CAL_PARTIAL 1 +#define CONFIG_ESP_PHY_CALIBRATION_MODE 0 +#define CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP 1 +#define CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP 1 +#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 1 +#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160 +#define CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB 1 +#define CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE 0x4000 +#define CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS 1 +#define CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS 8 +#define CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B 1 +#define CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE 32 +#define CONFIG_ESP32S3_DATA_CACHE_32KB 1 +#define CONFIG_ESP32S3_DATA_CACHE_SIZE 0x8000 +#define CONFIG_ESP32S3_DATA_CACHE_8WAYS 1 +#define CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS 8 +#define CONFIG_ESP32S3_DATA_CACHE_LINE_32B 1 +#define CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE 32 +#define CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM 0x0 +#define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1 +#define CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS 0 +#define CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE 1 +#define CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 1 +#define CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 1 +#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE 1 +#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK 1 +#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32 +#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2304 +#define CONFIG_ESP_MAIN_TASK_STACK_SIZE 3584 +#define CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0 1 +#define CONFIG_ESP_MAIN_TASK_AFFINITY 0x0 +#define CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE 2048 +#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1 +#define CONFIG_ESP_CONSOLE_SECONDARY_NONE 1 +#define CONFIG_ESP_CONSOLE_UART 1 +#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1 +#define CONFIG_ESP_CONSOLE_UART_NUM 0 +#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200 +#define CONFIG_ESP_INT_WDT 1 +#define CONFIG_ESP_INT_WDT_TIMEOUT_MS 300 +#define CONFIG_ESP_TASK_WDT_EN 1 +#define CONFIG_ESP_TASK_WDT_INIT 1 +#define CONFIG_ESP_TASK_WDT_TIMEOUT_S 5 +#define CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 1 +#define CONFIG_ESP_DEBUG_OCDAWARE 1 +#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1 +#define CONFIG_ESP_BROWNOUT_DET 1 +#define CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 1 +#define CONFIG_ESP_BROWNOUT_DET_LVL 7 +#define CONFIG_ESP_SYSTEM_BROWNOUT_INTR 1 +#define CONFIG_ESP_SYSTEM_BBPLL_RECALIB 1 +#define CONFIG_ESP_IPC_TASK_STACK_SIZE 1280 +#define CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER 1 +#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1 +#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584 +#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1 +#define CONFIG_ESP_TIMER_TASK_AFFINITY 0x0 +#define CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0 1 +#define CONFIG_ESP_TIMER_ISR_AFFINITY 0x1 +#define CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0 1 +#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1 +#define CONFIG_ESP_WIFI_ENABLED 1 +#define CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM 10 +#define CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM 32 +#define CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER 1 +#define CONFIG_ESP_WIFI_TX_BUFFER_TYPE 1 +#define CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM 32 +#define CONFIG_ESP_WIFI_STATIC_RX_MGMT_BUFFER 1 +#define CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUF 0 +#define CONFIG_ESP_WIFI_RX_MGMT_BUF_NUM_DEF 5 +#define CONFIG_ESP_WIFI_AMPDU_TX_ENABLED 1 +#define CONFIG_ESP_WIFI_TX_BA_WIN 6 +#define CONFIG_ESP_WIFI_AMPDU_RX_ENABLED 1 +#define CONFIG_ESP_WIFI_RX_BA_WIN 6 +#define CONFIG_ESP_WIFI_NVS_ENABLED 1 +#define CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN 752 +#define CONFIG_ESP_WIFI_MGMT_SBUF_NUM 32 +#define CONFIG_ESP_WIFI_IRAM_OPT 1 +#define CONFIG_ESP_WIFI_RX_IRAM_OPT 1 +#define CONFIG_ESP_WIFI_ENABLE_WPA3_SAE 1 +#define CONFIG_ESP_WIFI_ENABLE_SAE_PK 1 +#define CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT 1 +#define CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA 1 +#define CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE 1 +#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1 +#define CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM 7 +#define CONFIG_ESP_WIFI_MBEDTLS_CRYPTO 1 +#define CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT 1 +#define CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT 1 +#define CONFIG_ESP_COREDUMP_ENABLE_TO_NONE 1 +#define CONFIG_FATFS_VOLUME_COUNT 2 +#define CONFIG_FATFS_LFN_NONE 1 +#define CONFIG_FATFS_SECTOR_4096 1 +#define CONFIG_FATFS_CODEPAGE_437 1 +#define CONFIG_FATFS_CODEPAGE 437 +#define CONFIG_FATFS_FS_LOCK 0 +#define CONFIG_FATFS_TIMEOUT_MS 10000 +#define CONFIG_FATFS_PER_FILE_CACHE 1 +#define CONFIG_FATFS_VFS_FSTAT_BLKSIZE 0 +#define CONFIG_FREERTOS_UNICORE 1 +#define CONFIG_FREERTOS_HZ 100 +#define CONFIG_FREERTOS_OPTIMIZED_SCHEDULER 1 +#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1 +#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1 +#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1536 +#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16 +#define CONFIG_FREERTOS_TIMER_TASK_PRIORITY 1 +#define CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH 2048 +#define CONFIG_FREERTOS_TIMER_QUEUE_LENGTH 10 +#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0 +#define CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES 1 +#define CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER 1 +#define CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS 1 +#define CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER 1 +#define CONFIG_FREERTOS_ISR_STACKSIZE 1536 +#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1 +#define CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER 1 +#define CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1 1 +#define CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER 1 +#define CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT 1 +#define CONFIG_FREERTOS_NO_AFFINITY 0x7FFFFFFF +#define CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION 1 +#define CONFIG_FREERTOS_DEBUG_OCDAWARE 1 +#define CONFIG_HAL_ASSERTION_EQUALS_SYSTEM 1 +#define CONFIG_HAL_DEFAULT_ASSERTION_LEVEL 2 +#define CONFIG_HAL_WDT_USE_ROM_IMPL 1 +#define CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM 1 +#define CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM 1 +#define CONFIG_HEAP_POISONING_DISABLED 1 +#define CONFIG_HEAP_TRACING_OFF 1 +#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1 +#define CONFIG_LOG_DEFAULT_LEVEL 3 +#define CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT 1 +#define CONFIG_LOG_MAXIMUM_LEVEL 3 +#define CONFIG_LOG_COLORS 1 +#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1 +#define CONFIG_LWIP_LOCAL_HOSTNAME "espressif" +#define CONFIG_LWIP_TCPIP_TASK_PRIO 18 +#define CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES 1 +#define CONFIG_LWIP_TIMERS_ONDEMAND 1 +#define CONFIG_LWIP_ND6 1 +#define CONFIG_LWIP_MAX_SOCKETS 10 +#define CONFIG_LWIP_SO_REUSE 1 +#define CONFIG_LWIP_SO_REUSE_RXTOALL 1 +#define CONFIG_LWIP_IP_DEFAULT_TTL 64 +#define CONFIG_LWIP_IP4_FRAG 1 +#define CONFIG_LWIP_IP6_FRAG 1 +#define CONFIG_LWIP_IP_REASS_MAX_PBUFS 10 +#define CONFIG_LWIP_ESP_GRATUITOUS_ARP 1 +#define CONFIG_LWIP_GARP_TMR_INTERVAL 60 +#define CONFIG_LWIP_ESP_MLDV6_REPORT 1 +#define CONFIG_LWIP_MLDV6_TMR_INTERVAL 40 +#define CONFIG_LWIP_TCPIP_RECVMBOX_SIZE 32 +#define CONFIG_LWIP_DHCP_DOES_ARP_CHECK 1 +#define CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID 1 +#define CONFIG_LWIP_DHCP_OPTIONS_LEN 68 +#define CONFIG_LWIP_NUM_NETIF_CLIENT_DATA 0 +#define CONFIG_LWIP_DHCP_COARSE_TIMER_SECS 1 +#define CONFIG_LWIP_DHCPS 1 +#define CONFIG_LWIP_DHCPS_LEASE_UNIT 60 +#define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8 +#define CONFIG_LWIP_IPV4 1 +#define CONFIG_LWIP_IPV6 1 +#define CONFIG_LWIP_IPV6_NUM_ADDRESSES 3 +#define CONFIG_LWIP_NETIF_LOOPBACK 1 +#define CONFIG_LWIP_LOOPBACK_MAX_PBUFS 8 +#define CONFIG_LWIP_MAX_ACTIVE_TCP 16 +#define CONFIG_LWIP_MAX_LISTENING_TCP 16 +#define CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION 1 +#define CONFIG_LWIP_TCP_MAXRTX 12 +#define CONFIG_LWIP_TCP_SYNMAXRTX 12 +#define CONFIG_LWIP_TCP_MSS 1440 +#define CONFIG_LWIP_TCP_TMR_INTERVAL 250 +#define CONFIG_LWIP_TCP_MSL 60000 +#define CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT 20000 +#define CONFIG_LWIP_TCP_SND_BUF_DEFAULT 5760 +#define CONFIG_LWIP_TCP_WND_DEFAULT 5760 +#define CONFIG_LWIP_TCP_RECVMBOX_SIZE 6 +#define CONFIG_LWIP_TCP_QUEUE_OOSEQ 1 +#define CONFIG_LWIP_TCP_OOSEQ_TIMEOUT 6 +#define CONFIG_LWIP_TCP_OOSEQ_MAX_PBUFS 4 +#define CONFIG_LWIP_TCP_OVERSIZE_MSS 1 +#define CONFIG_LWIP_TCP_RTO_TIME 1500 +#define CONFIG_LWIP_MAX_UDP_PCBS 16 +#define CONFIG_LWIP_UDP_RECVMBOX_SIZE 6 +#define CONFIG_LWIP_CHECKSUM_CHECK_ICMP 1 +#define CONFIG_LWIP_TCPIP_TASK_STACK_SIZE 3072 +#define CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY 1 +#define CONFIG_LWIP_TCPIP_TASK_AFFINITY 0x7FFFFFFF +#define CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE 3 +#define CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS 5 +#define CONFIG_LWIP_ICMP 1 +#define CONFIG_LWIP_MAX_RAW_PCBS 16 +#define CONFIG_LWIP_SNTP_MAX_SERVERS 1 +#define CONFIG_LWIP_SNTP_UPDATE_DELAY 3600000 +#define CONFIG_LWIP_DNS_MAX_SERVERS 3 +#define CONFIG_LWIP_BRIDGEIF_MAX_PORTS 7 +#define CONFIG_LWIP_ESP_LWIP_ASSERT 1 +#define CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT 1 +#define CONFIG_LWIP_HOOK_IP6_ROUTE_NONE 1 +#define CONFIG_LWIP_HOOK_ND6_GET_GW_NONE 1 +#define CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE 1 +#define CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE 1 +#define CONFIG_LWIP_HOOK_IP6_INPUT_NONE 1 +#define CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC 1 +#define CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN 1 +#define CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN 16384 +#define CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN 4096 +#define CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE 1 +#define CONFIG_MBEDTLS_PKCS7_C 1 +#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE 1 +#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL 1 +#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS 200 +#define CONFIG_MBEDTLS_CMAC_C 1 +#define CONFIG_MBEDTLS_HARDWARE_AES 1 +#define CONFIG_MBEDTLS_AES_USE_INTERRUPT 1 +#define CONFIG_MBEDTLS_HARDWARE_MPI 1 +#define CONFIG_MBEDTLS_MPI_USE_INTERRUPT 1 +#define CONFIG_MBEDTLS_HARDWARE_SHA 1 +#define CONFIG_MBEDTLS_ROM_MD5 1 +#define CONFIG_MBEDTLS_HAVE_TIME 1 +#define CONFIG_MBEDTLS_ECDSA_DETERMINISTIC 1 +#define CONFIG_MBEDTLS_SHA512_C 1 +#define CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT 1 +#define CONFIG_MBEDTLS_TLS_SERVER 1 +#define CONFIG_MBEDTLS_TLS_CLIENT 1 +#define CONFIG_MBEDTLS_TLS_ENABLED 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA 1 +#define CONFIG_MBEDTLS_SSL_RENEGOTIATION 1 +#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_2 1 +#define CONFIG_MBEDTLS_SSL_ALPN 1 +#define CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS 1 +#define CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS 1 +#define CONFIG_MBEDTLS_AES_C 1 +#define CONFIG_MBEDTLS_CCM_C 1 +#define CONFIG_MBEDTLS_GCM_C 1 +#define CONFIG_MBEDTLS_PEM_PARSE_C 1 +#define CONFIG_MBEDTLS_PEM_WRITE_C 1 +#define CONFIG_MBEDTLS_X509_CRL_PARSE_C 1 +#define CONFIG_MBEDTLS_X509_CSR_PARSE_C 1 +#define CONFIG_MBEDTLS_ECP_C 1 +#define CONFIG_MBEDTLS_ECDH_C 1 +#define CONFIG_MBEDTLS_ECDSA_C 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_NIST_OPTIM 1 +#define CONFIG_MBEDTLS_ECP_FIXED_POINT_OPTIM 1 +#define CONFIG_MQTT_PROTOCOL_311 1 +#define CONFIG_MQTT_TRANSPORT_SSL 1 +#define CONFIG_MQTT_TRANSPORT_WEBSOCKET 1 +#define CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE 1 +#define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF 1 +#define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR 1 +#define CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT 1 +#define CONFIG_OPENTHREAD_NETWORK_NAME "OpenThread-ESP" +#define CONFIG_OPENTHREAD_MESH_LOCAL_PREFIX "fd00:db8:a0:0::/64" +#define CONFIG_OPENTHREAD_NETWORK_CHANNEL 15 +#define CONFIG_OPENTHREAD_NETWORK_PANID 0x1234 +#define CONFIG_OPENTHREAD_NETWORK_EXTPANID "dead00beef00cafe" +#define CONFIG_OPENTHREAD_NETWORK_MASTERKEY "00112233445566778899aabbccddeeff" +#define CONFIG_OPENTHREAD_NETWORK_PSKC "104810e2315100afd6bc9215a6bfac53" +#define CONFIG_OPENTHREAD_XTAL_ACCURACY 130 +#define CONFIG_OPENTHREAD_RX_ON_WHEN_IDLE 1 +#define CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0 1 +#define CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1 1 +#define CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2 1 +#define CONFIG_PTHREAD_TASK_PRIO_DEFAULT 5 +#define CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT 3072 +#define CONFIG_PTHREAD_STACK_MIN 768 +#define CONFIG_PTHREAD_TASK_CORE_DEFAULT -1 +#define CONFIG_PTHREAD_TASK_NAME_DEFAULT "pthread" +#define CONFIG_MMU_PAGE_SIZE_64KB 1 +#define CONFIG_MMU_PAGE_MODE "64KB" +#define CONFIG_MMU_PAGE_SIZE 0x10000 +#define CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC 1 +#define CONFIG_SPI_FLASH_BROWNOUT_RESET 1 +#define CONFIG_SPI_FLASH_HPM_AUTO 1 +#define CONFIG_SPI_FLASH_HPM_ON 1 +#define CONFIG_SPI_FLASH_HPM_DC_AUTO 1 +#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 +#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1 +#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1 +#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20 +#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1 +#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192 +#define CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED 1 +#define CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED 1 +#define CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED 1 +#define CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED 1 +#define CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED 1 +#define CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED 1 +#define CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED 1 +#define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_TH_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP 1 +#define CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE 1 +#define CONFIG_SPIFFS_MAX_PARTITIONS 3 +#define CONFIG_SPIFFS_CACHE 1 +#define CONFIG_SPIFFS_CACHE_WR 1 +#define CONFIG_SPIFFS_PAGE_CHECK 1 +#define CONFIG_SPIFFS_GC_MAX_RUNS 10 +#define CONFIG_SPIFFS_PAGE_SIZE 256 +#define CONFIG_SPIFFS_OBJ_NAME_LEN 32 +#define CONFIG_SPIFFS_USE_MAGIC 1 +#define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1 +#define CONFIG_SPIFFS_META_LENGTH 4 +#define CONFIG_SPIFFS_USE_MTIME 1 +#define CONFIG_WS_TRANSPORT 1 +#define CONFIG_WS_BUFFER_SIZE 1024 +#define CONFIG_UNITY_ENABLE_FLOAT 1 +#define CONFIG_UNITY_ENABLE_DOUBLE 1 +#define CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER 1 +#define CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE 256 +#define CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED 1 +#define CONFIG_USB_HOST_DEBOUNCE_DELAY_MS 250 +#define CONFIG_USB_HOST_RESET_HOLD_MS 30 +#define CONFIG_USB_HOST_RESET_RECOVERY_MS 30 +#define CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS 10 +#define CONFIG_USB_OTG_SUPPORTED 1 +#define CONFIG_VFS_SUPPORT_IO 1 +#define CONFIG_VFS_SUPPORT_DIR 1 +#define CONFIG_VFS_SUPPORT_SELECT 1 +#define CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT 1 +#define CONFIG_VFS_SUPPORT_TERMIOS 1 +#define CONFIG_VFS_MAX_COUNT 8 +#define CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS 1 +#define CONFIG_WL_SECTOR_SIZE_4096 1 +#define CONFIG_WL_SECTOR_SIZE 4096 +#define CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES 16 +#define CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT 30 +#define CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN 1 + +/* List of deprecated options */ +#define CONFIG_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET +#define CONFIG_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL +#define CONFIG_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 +#define CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEFAULT +#define CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART +#define CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE +#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT +#define CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM +#define CONFIG_ESP32S3_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET +#define CONFIG_ESP32S3_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL +#define CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 +#define CONFIG_ESP32S3_DEBUG_OCDAWARE CONFIG_ESP_DEBUG_OCDAWARE +#define CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY +#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 +#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ +#define CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES +#define CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC CONFIG_RTC_CLK_SRC_INT_RC +#define CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1 CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT +#define CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_SYSTIMER CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT +#define CONFIG_ESP32_APPTRACE_DEST_NONE CONFIG_APPTRACE_DEST_NONE +#define CONFIG_ESP32_APPTRACE_LOCK_ENABLE CONFIG_APPTRACE_LOCK_ENABLE +#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE CONFIG_ESP_COREDUMP_ENABLE_TO_NONE +#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE +#define CONFIG_ESP32_PHY_MAX_TX_POWER CONFIG_ESP_PHY_MAX_TX_POWER +#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER +#define CONFIG_ESP32_PTHREAD_STACK_MIN CONFIG_PTHREAD_STACK_MIN +#define CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT CONFIG_PTHREAD_TASK_CORE_DEFAULT +#define CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT CONFIG_PTHREAD_TASK_NAME_DEFAULT +#define CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT CONFIG_PTHREAD_TASK_PRIO_DEFAULT +#define CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT +#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED CONFIG_ESP_WIFI_AMPDU_RX_ENABLED +#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED CONFIG_ESP_WIFI_AMPDU_TX_ENABLED +#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM +#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER +#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM +#define CONFIG_ESP32_WIFI_ENABLED CONFIG_ESP_WIFI_ENABLED +#define CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA +#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE CONFIG_ESP_WIFI_ENABLE_WPA3_SAE +#define CONFIG_ESP32_WIFI_IRAM_OPT CONFIG_ESP_WIFI_IRAM_OPT +#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM CONFIG_ESP_WIFI_MGMT_SBUF_NUM +#define CONFIG_ESP32_WIFI_NVS_ENABLED CONFIG_ESP_WIFI_NVS_ENABLED +#define CONFIG_ESP32_WIFI_RX_BA_WIN CONFIG_ESP_WIFI_RX_BA_WIN +#define CONFIG_ESP32_WIFI_RX_IRAM_OPT CONFIG_ESP_WIFI_RX_IRAM_OPT +#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN +#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM +#define CONFIG_ESP32_WIFI_TX_BA_WIN CONFIG_ESP_WIFI_TX_BA_WIN +#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE CONFIG_ESP_WIFI_TX_BUFFER_TYPE +#define CONFIG_ESP_GRATUITOUS_ARP CONFIG_LWIP_ESP_GRATUITOUS_ARP +#define CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY +#define CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP +#define CONFIG_ESP_TASK_WDT CONFIG_ESP_TASK_WDT_INIT +#define CONFIG_FLASHMODE_DIO CONFIG_ESPTOOLPY_FLASHMODE_DIO +#define CONFIG_GARP_TMR_INTERVAL CONFIG_LWIP_GARP_TMR_INTERVAL +#define CONFIG_INT_WDT CONFIG_ESP_INT_WDT +#define CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS +#define CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE +#define CONFIG_LOG_BOOTLOADER_LEVEL CONFIG_BOOTLOADER_LOG_LEVEL +#define CONFIG_LOG_BOOTLOADER_LEVEL_INFO CONFIG_BOOTLOADER_LOG_LEVEL_INFO +#define CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE +#define CONFIG_MONITOR_BAUD CONFIG_ESPTOOLPY_MONITOR_BAUD +#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE +#define CONFIG_OPTIMIZATION_ASSERTION_LEVEL CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL +#define CONFIG_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEFAULT +#define CONFIG_POST_EVENTS_FROM_IRAM_ISR CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR +#define CONFIG_POST_EVENTS_FROM_ISR CONFIG_ESP_EVENT_POST_FROM_ISR +#define CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS +#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS +#define CONFIG_STACK_CHECK_NONE CONFIG_COMPILER_STACK_CHECK_MODE_NONE +#define CONFIG_SUPPORT_TERMIOS CONFIG_VFS_SUPPORT_TERMIOS +#define CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT +#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE +#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE +#define CONFIG_TASK_WDT CONFIG_ESP_TASK_WDT_INIT +#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 +#define CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIMEOUT_S +#define CONFIG_TCPIP_RECVMBOX_SIZE CONFIG_LWIP_TCPIP_RECVMBOX_SIZE +#define CONFIG_TCPIP_TASK_AFFINITY CONFIG_LWIP_TCPIP_TASK_AFFINITY +#define CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY +#define CONFIG_TCPIP_TASK_STACK_SIZE CONFIG_LWIP_TCPIP_TASK_STACK_SIZE +#define CONFIG_TCP_MAXRTX CONFIG_LWIP_TCP_MAXRTX +#define CONFIG_TCP_MSL CONFIG_LWIP_TCP_MSL +#define CONFIG_TCP_MSS CONFIG_LWIP_TCP_MSS +#define CONFIG_TCP_OVERSIZE_MSS CONFIG_LWIP_TCP_OVERSIZE_MSS +#define CONFIG_TCP_QUEUE_OOSEQ CONFIG_LWIP_TCP_QUEUE_OOSEQ +#define CONFIG_TCP_RECVMBOX_SIZE CONFIG_LWIP_TCP_RECVMBOX_SIZE +#define CONFIG_TCP_SND_BUF_DEFAULT CONFIG_LWIP_TCP_SND_BUF_DEFAULT +#define CONFIG_TCP_SYNMAXRTX CONFIG_LWIP_TCP_SYNMAXRTX +#define CONFIG_TCP_WND_DEFAULT CONFIG_LWIP_TCP_WND_DEFAULT +#define CONFIG_TIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH +#define CONFIG_TIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY +#define CONFIG_TIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH +#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE +#define CONFIG_UDP_RECVMBOX_SIZE CONFIG_LWIP_UDP_RECVMBOX_SIZE +#define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO +#define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT + +/* + * Deltas from the harvested official configuration, required because this + * BSP runs RT-Thread instead of FreeRTOS and compiles no VFS/mbedtls: + * + * CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT: the snapshot API walks the real + * kernel's List_t/TCB internals (freertos_tasks_c_additions.h), which the + * RT-Thread FreeRTOS-Wrapper does not have. + * CONFIG_VFS_SUPPORT_IO: esp_system/startup.c would then include + * esp_vfs_dev.h while no vfs component is compiled for this BSP. + * CONFIG_ESP_TASK_WDT_INIT=0: the xtensa branch of task_wdt.c aborts by + * reading a real FreeRTOS TCB through vTaskGetSnapshot(); the RT-Thread + * task wrapper has no snapshot API, and RT-Thread owns thread timeouts. + */ +#undef CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT +#undef CONFIG_VFS_SUPPORT_IO +#undef CONFIG_ESP_TASK_WDT_INIT +#define CONFIG_ESP_TASK_WDT_INIT 0 +/* CONFIG_ESP_INT_WDT: IDF arms this watchdog on timer group 1 and feeds it + * from its own vector wrappers (xt_int_enter/xt_int_exit). This BSP replaces + * those vectors with libcpu/xtensa/esp32s3/context_gcc.S, so nothing ever + * feeds it and it resets the CPU ~300 ms after boot -- observed as + * rst:0x8 (TG1WDT_SYS_RST) / "PRO CPU has been reset by WDT". RT-Thread has no + * equivalent (its interrupt nesting counter is checked by the scheduler). */ +#undef CONFIG_ESP_INT_WDT +#define CONFIG_ESP_INT_WDT 0 +/* CONFIG_SPI_FLASH_AUTO_SUSPEND / CONFIG_SPI_FLASH_HPM_ENABLE: both run live + * flash commands right after default-chip init; kept off for v1 (the normal + * read/write/mmap path through the ROM bootloader settings is unaffected). */ +#undef CONFIG_SPI_FLASH_AUTO_SUSPEND +#undef CONFIG_SPI_FLASH_HPM_ENABLE diff --git a/libcpu/xtensa/SConscript b/libcpu/xtensa/SConscript new file mode 100644 index 000000000000..0f1f2864c0a3 --- /dev/null +++ b/libcpu/xtensa/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] + +# rtconfig.CPU selects the SoC port below this directory (esp32s3 for now). +if rtconfig.CPU in os.listdir(cwd): + group += SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/xtensa/esp32s3/SConscript b/libcpu/xtensa/esp32s3/SConscript new file mode 100644 index 000000000000..f5e208243b69 --- /dev/null +++ b/libcpu/xtensa/esp32s3/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for ESP32-S3 (Xtensa LX7) CPU port + +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*_gcc.S') + +CPPPATH = [cwd] +ASFLAGS = ' -I ' + cwd + +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/xtensa/esp32s3/context_gcc.S b/libcpu/xtensa/esp32s3/context_gcc.S new file mode 100644 index 000000000000..f4cc13d38c42 --- /dev/null +++ b/libcpu/xtensa/esp32s3/context_gcc.S @@ -0,0 +1,820 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-09-27 RT-Thread ESP32-S3 (Xtensa LX7) vectors + context switch + * + * Xtensa windowed-ABI vector table and RT-Thread context switch for ESP32-S3. + * + * The window overflow/underflow vectors, the interrupt frame layout + * (XtExcFrame/XtSolFrame from Espressif's ) and the + * entry/exit sequences follow the canonical ESP-IDF Xtensa port + * (components/freertos/.../portable/xtensa, Apache-2.0), pared down to what + * this single-core BSP needs and re-targeted at RT-Thread: + * - the interrupt frame is on the interrupted thread's stack, but the C + * dispatcher runs on rt_xt_isr_stack, because a windowed spill needs 64 + * bytes below sp and the frame cannot hold both its saved registers and + * those spills (ESP-IDF: _frxt_int_enter / port_IntStack); + * - no FreeRTOS hooks: instead of XT_RTOS_INT_ENTER/EXIT bookkeeping, the + * vector calls the C dispatcher rt_xt_irq_process() (cpuport.c), which + * wraps the ESP-IDF _xt_interrupt_table dispatch in + * rt_interrupt_enter()/rt_interrupt_leave(); + * - the FPU (CP0) is enabled (CPENABLE bit 0; see cp_enable_fpu() in + * cpuport.c). Every level-1 interrupt saves the full FP state + * (FCR/FSR/f0-f15, RT_S3_FP_BLOCK_SIZE bytes) eagerly below the + * XtExcFrame, and cooperative switches save FCR/FSR into the + * solicited frame. AI/SIMD (CP3) stays disabled; + * - fatal vectors end in ESP-IDF's _xt_panic (register dump + backtrace). + */ + +#include +#include +#include +#include +#include +#include +#include +#include "cpuport.h" + +/* + * External symbols (see the .S notes at the top of cpuport.c): + * _xt_context_save/_xt_context_restore: ESP-IDF xtensa_context.S, spills + * register windows and saves the rest of the interrupt context; the + * caller must pre-store XT_STK_A12/A13 (windowed) and PS/PC/A0/A1. + * xthal_window_spill_nw: libxt_hal, non-windowed-clobber window spill. + * rt_xt_*: C glue in cpuport.c. + */ + .extern _xt_context_save + .extern _xt_context_restore + .extern rt_xt_irq_process + .extern rt_xt_exception_handler + .extern _xt_panic + + .extern rt_thread_switch_interrupt_flag + .extern rt_interrupt_from_thread + .extern rt_interrupt_to_thread + +/* + * rt_hw_context_switch() has to carry the `to` argument across its window + * spill, and no register survives that (xthal_window_spill_nw opens with + * `rsr a2, WINDOWBASE` and rotates windows as it walks). One .bss word is + * enough because the switch raises PS.INTLEVEL to XCHAL_EXCM_LEVEL before the + * spill, and every interrupt this BSP services is below that. + */ + .section .bss.rt_sol_to, "aw", @nobits + .align 4 +rt_xt_s3_sol_to: + .space 4 + +#if !XCHAL_HAVE_WINDOWED +#error this port requires the Xtensa windowed register ABI (ESP32-S3 LX7) +#endif +#if !XCHAL_HAVE_XEA2 +#error this port requires XEA2 vector layout (ESP32-S3 LX7) +#endif + + .text + +/* +------------------------------------------------------------------------------- + WINDOW VECTORS. Fixed .org offsets mirror XCHAL_WINDOW_OF*_VADDR; they are + the unmodified canonical Tensilica sequences (identical in every Xtensa RTOS + port): on overflow the victim window's a0-a3 are stored into the top of the + next-lower frame and rfwo rotates back; underflow reloads them. +------------------------------------------------------------------------------- +*/ + + .begin literal_prefix .WindowVectors + .section .WindowVectors.text, "ax" + .align 4 + + .org 0x0 + .global _WindowOverflow4 +_WindowOverflow4: + s32e a0, a5, -16 + s32e a1, a5, -12 + s32e a2, a5, -8 + s32e a3, a5, -4 + rfwo + + .org 0x40 + .global _WindowUnderflow4 +_WindowUnderflow4: + l32e a0, a5, -16 + l32e a1, a5, -12 + l32e a2, a5, -8 + l32e a3, a5, -4 + rfwu + +/* MOVSP-induced alloca: handled in the gap between call4 slots. */ + .align 4 + .global _rt_alloca_exc +_rt_alloca_exc: + rsr a0, WINDOWBASE + rotw -1 + rsr a2, PS + extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS + xor a3, a3, a4 + rsr a4, EXCSAVE_1 + slli a3, a3, XCHAL_PS_OWB_SHIFT + xor a2, a2, a3 + wsr a2, PS + rsync + _bbci.l a4, 31, _WindowUnderflow4 + rotw -1 + _bbci.l a8, 30, _WindowUnderflow8 + rotw -1 + j _WindowUnderflow12 + + .org 0x80 + .global _WindowOverflow8 +_WindowOverflow8: + s32e a0, a9, -16 + l32e a0, a1, -12 + s32e a1, a9, -12 + s32e a2, a9, -8 + s32e a3, a9, -4 + s32e a4, a0, -32 + s32e a5, a0, -28 + s32e a6, a0, -24 + s32e a7, a0, -20 + rfwo + + .org 0xC0 + .global _WindowUnderflow8 +_WindowUnderflow8: + l32e a0, a9, -16 + l32e a1, a9, -12 + l32e a2, a9, -8 + l32e a7, a1, -12 + l32e a3, a9, -4 + l32e a4, a7, -32 + l32e a5, a7, -28 + l32e a6, a7, -24 + l32e a7, a7, -20 + rfwu + + .org 0x100 + .global _WindowOverflow12 +_WindowOverflow12: + s32e a0, a13, -16 + l32e a0, a1, -12 + s32e a1, a13, -12 + s32e a2, a13, -8 + s32e a3, a13, -4 + s32e a4, a0, -48 + s32e a5, a0, -44 + s32e a6, a0, -40 + s32e a7, a0, -36 + s32e a8, a0, -32 + s32e a9, a0, -28 + s32e a10, a0, -24 + s32e a11, a0, -20 + rfwo + + .org 0x140 + .global _WindowUnderflow12 +_WindowUnderflow12: + l32e a0, a13, -16 + l32e a1, a13, -12 + l32e a2, a13, -8 + l32e a11, a1, -12 + l32e a3, a13, -4 + l32e a4, a11, -48 + l32e a5, a11, -44 + l32e a6, a11, -40 + l32e a7, a11, -36 + l32e a8, a11, -32 + l32e a9, a11, -28 + l32e a10, a11, -24 + l32e a11, a11, -20 + rfwu + + .end literal_prefix + +/* +------------------------------------------------------------------------------- + UNUSED VECTORS. v1 runs every interrupt at level 1; debug/NMI/kernel/double + and levels 2-5 are fatal firmware errors: stage the vector's own EPC into + EPC_1, publish the ESP-IDF panic reason in EXCCAUSE and fall into IDF's + _xt_panic, which builds the frame, saves the context and runs panicHandler + (register dump + backtrace over the ROM printf). Those vectors already + compile into this image, and their output is what an ESP32 developer reads. +------------------------------------------------------------------------------- +*/ + +/* _xt_panic allocates an XtExcFrame plus a C environment on whatever sp it is + * given, and the fatal vectors are exactly the case where that sp is no longer + * trustworthy -- hence a stack of our own, sized for the frame plus the + * window spills of the walk it does. */ +#define RT_S3_PANIC_STACK_SIZE 1024 + + .section .bss.rt_panic_stack, "aw", @nobits + .align 16 +rt_xt_panic_stack: + .space RT_S3_PANIC_STACK_SIZE +rt_xt_panic_stack_end: + +/* _rt_panic_halt: a2 = PANIC_RSN_*; does not return. */ + .section .iram1, "ax" + .align 4 + .type _rt_panic_halt, @function +_rt_panic_halt: + rsil a3, XCHAL_DEBUGLEVEL /* mask everything maskable */ + wsr a2, EXCCAUSE /* reason, as panicHandler expects */ + movi sp, rt_xt_panic_stack_end + call0 _xt_panic +.Lrt_halt_loop: + nop + nop + j .Lrt_halt_loop + +/* +------------------------------------------------------------------------------- + void rt_xt_panic_report(code, cause, epc, excvaddr, ra, sp) -- called from + _rt_panic_halt with a C environment set up. Lives in cpuport.c. +------------------------------------------------------------------------------- +*/ + + .begin literal_prefix .Level2InterruptVector + .section .Level2InterruptVector.text, "ax" + .global _Level2Vector + .align 4 +_Level2Vector: + wsr a0, EXCSAVE_2 + rsr a2, EPC_2 + wsr a2, EPC_1 + movi a2, 20 /* vector id, see _rt_panic_halt */ + j _rt_panic_halt + .end literal_prefix + + .begin literal_prefix .Level3InterruptVector + .section .Level3InterruptVector.text, "ax" + .global _Level3Vector + .align 4 +_Level3Vector: + wsr a0, EXCSAVE_3 + rsr a2, EPC_3 + wsr a2, EPC_1 + movi a2, 30 /* vector id, see _rt_panic_halt */ + j _rt_panic_halt + .end literal_prefix + + .begin literal_prefix .Level4InterruptVector + .section .Level4InterruptVector.text, "ax" + .global _Level4Vector + .align 4 +_Level4Vector: + wsr a0, EXCSAVE_4 + rsr a2, EPC_4 + wsr a2, EPC_1 + movi a2, 40 /* vector id, see _rt_panic_halt */ + j _rt_panic_halt + .end literal_prefix + + .begin literal_prefix .Level5InterruptVector + .section .Level5InterruptVector.text, "ax" + .global _Level5Vector + .align 4 +_Level5Vector: + wsr a0, EXCSAVE_5 + rsr a2, EPC_5 + wsr a2, EPC_1 + movi a2, 50 /* vector id, see _rt_panic_halt */ + j _rt_panic_halt + .end literal_prefix + + .begin literal_prefix .DebugExceptionVector + .section .DebugExceptionVector.text, "ax" + .global _DebugExceptionVector + .align 4 +_DebugExceptionVector: + wsr a0, EXCSAVE + XCHAL_DEBUGLEVEL + rsr a2, EPC + XCHAL_DEBUGLEVEL + wsr a2, EPC_1 + movi a2, PANIC_RSN_DEBUGEXCEPTION + j _rt_panic_halt + .end literal_prefix + + .begin literal_prefix .NMIExceptionVector + .section .NMIExceptionVector.text, "ax" + .global _NMIExceptionVector + .align 4 +_NMIExceptionVector: + wsr a0, EXCSAVE + XCHAL_NMILEVEL + movi a2, 60 /* vector id, see _rt_panic_halt */ + j _rt_panic_halt + .end literal_prefix + + .begin literal_prefix .KernelExceptionVector + .section .KernelExceptionVector.text, "ax" + .global _KernelExceptionVector + .align 4 +_KernelExceptionVector: + wsr a0, EXCSAVE_1 + movi a2, PANIC_RSN_KERNELEXCEPTION + j _rt_panic_halt + .end literal_prefix + + .begin literal_prefix .DoubleExceptionVector + .section .DoubleExceptionVector.text, "ax" + .global _DoubleExceptionVector + .align 4 +_DoubleExceptionVector: + /* No "break 1,4" here (IDF uses it to hand control to a debug agent): a + * debug exception would overwrite EPC_1 with the double vector's own PC + * and throw away the original cause we are trying to read. On a double + * exception EPC_1/EPS_1/EXCCAUSE still describe the first exception, and + * the double vector's own PC is in DEPC -- so just report. + * IDF also does `wsr a0, EXCSAVE_1` first (to clear a debugger single + * step); we skip that because EXCSAVE_1 holds the first fault's a0, i.e. + * the return address of the frame that faulted, which is the one piece of + * the picture EPC_1 cannot give. */ + movi a2, PANIC_RSN_DOUBLEEXCEPTION + j _rt_panic_halt + .end literal_prefix + +/* +------------------------------------------------------------------------------- + USER EXCEPTION VECTOR (VECBASE+0x340): level-1 interrupts AND exceptions + taken while PS.EXCM=0. Mirrors _xt_user_exc. Coprocessor-disabled causes + (>= EXCCAUSE_CP0_DISABLED) go to rt_xt_exception_handler (no lazy switch). +------------------------------------------------------------------------------- +*/ + + .begin literal_prefix .UserExceptionVector + .section .UserExceptionVector.text, "ax" + .global _UserExceptionVector + .type _UserExceptionVector, @function + .align 4 +_UserExceptionVector: + wsr a0, EXCSAVE_1 + call0 _rt_user_exc + /* never returns here - call0 is used as a jump */ + .end literal_prefix + + .section .iram1, "ax" + .literal_position + .align 4 + .type _rt_user_exc, @function +_rt_user_exc: + rsr a0, EXCCAUSE + beqi a0, EXCCAUSE_LEVEL1INTERRUPT, _rt_lowint1 + bnei a0, EXCCAUSE_ALLOCA, .Lrt_not_alloca + J _rt_alloca_exc /* long branch into window vectors */ +.Lrt_not_alloca: + + /* Any other exception: full frame so the C handler can print state. */ + mov a0, sp + addi sp, sp, -XT_STK_FRMSZ + s32i a0, sp, XT_STK_A1 + s32e a0, sp, -12 /* debug backtrace base-save slot */ + rsr a0, PS /* interruptee's PS, as IDF stores it */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_1 + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_1 + s32i a0, sp, XT_STK_A0 + s32e a0, sp, -16 + s32i a12, sp, XT_STK_A12 + s32i a13, sp, XT_STK_A13 + call0 _xt_context_save + rsr a0, EXCCAUSE + s32i a0, sp, XT_STK_EXCCAUSE + rsr a0, EXCVADDR + s32i a0, sp, XT_STK_EXCVADDR + + mov a10, sp /* the frame is the handler's argument */ + movi a0, rt_xt_isr_frame + s32i a10, a0, 0 /* same ISR-stack move as _rt_lowint1 */ + movi sp, rt_xt_isr_stack_end + + movi a0, PS_INTLEVEL(1) | PS_UM | PS_WOE + wsr a0, PS /* C environment */ + rsync + + call8 rt_xt_exception_handler /* prints, never returns */ + +/* +------------------------------------------------------------------------------- + LEVEL 1 INTERRUPT. Frame on the interrupted thread's stack (exactly + _xt_lowint1's prologue), then the C dispatch on rt_xt_isr_stack, then the + RT-Thread switch-in via the globals that + rt_hw_context_switch_interrupt() filled in. +------------------------------------------------------------------------------- +*/ + +/* + * Interrupt stack for C-level ISR code, and the word that remembers the + * exception frame while C runs elsewhere. + * + * A windowed-ABI function spill needs 64 bytes below its own sp, and an + * exception frame is only XT_STK_FRMSZ (192) bytes with most of that holding + * saved registers. Running the ISR C code directly on the frame therefore + * turns frame slots into spill links: a window overflow inside a handler would + * take its link out of a register slot and store through it. ESP-IDF makes the + * same move in _frxt_int_enter (pxCurrentTCB->pxTopOfStack, then port_IntStack). + * + * v1 is single-core and runs the C dispatch at PS.INTLEVEL = 1, which masks + * every level-1 source, so one stack and one frame slot are enough. + */ +#define RT_S3_ISR_STACK_SIZE 2048 + + .section .bss.rt_isr_stack, "aw", @nobits + .align 16 +rt_xt_isr_stack: + .space RT_S3_ISR_STACK_SIZE +rt_xt_isr_stack_end: + + .section .bss.rt_isr_frame, "aw", @nobits + .align 4 +rt_xt_isr_frame: + .space 4 + + .section .iram1, "ax" + .align 4 + .type _rt_lowint1, @function + .global _rt_lowint1 +_rt_lowint1: + mov a0, sp + addi sp, sp, -XT_STK_FRMSZ + s32i a0, sp, XT_STK_A1 + rsr a0, PS + s32i a0, sp, XT_STK_PS + rsr a0, EPC_1 + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_1 + s32i a0, sp, XT_STK_A0 + movi a0, _rt_user_exit + s32i a0, sp, XT_STK_EXIT + + s32i a12, sp, XT_STK_A12 /* _xt_context_save expects these */ + s32i a13, sp, XT_STK_A13 /* already written into the frame */ + call0 _xt_context_save /* windows + a2-a15 + extra state */ + + /* Allocate FP save block below the XtExcFrame. a2-a15 are already in the + * frame (_xt_context_save stored them), so they are free scratch here. */ + addi sp, sp, -RT_S3_FP_BLOCK_SIZE + rur.fcr a2 + s32i a2, sp, RT_S3_FP_FCR + rur.fsr a2 + s32i a2, sp, RT_S3_FP_FSR + ssi f0, sp, RT_S3_FP_F0 + 0 + ssi f1, sp, RT_S3_FP_F0 + 4 + ssi f2, sp, RT_S3_FP_F0 + 8 + ssi f3, sp, RT_S3_FP_F0 + 12 + ssi f4, sp, RT_S3_FP_F0 + 16 + ssi f5, sp, RT_S3_FP_F0 + 20 + ssi f6, sp, RT_S3_FP_F0 + 24 + ssi f7, sp, RT_S3_FP_F0 + 28 + ssi f8, sp, RT_S3_FP_F0 + 32 + ssi f9, sp, RT_S3_FP_F0 + 36 + ssi f10, sp, RT_S3_FP_F0 + 40 + ssi f11, sp, RT_S3_FP_F0 + 44 + ssi f12, sp, RT_S3_FP_F0 + 48 + ssi f13, sp, RT_S3_FP_F0 + 52 + ssi f14, sp, RT_S3_FP_F0 + 56 + ssi f15, sp, RT_S3_FP_F0 + 60 + movi a2, RT_S3_FP_FRAME_MARK + s32i a2, sp, RT_S3_FP_MARKER_OFS + + movi a0, rt_xt_isr_frame + s32i sp, a0, 0 /* publish the FP-block base ... */ + movi sp, rt_xt_isr_stack_end /* ... and leave it for the C code */ + l32i a0, a0, 0 /* a0 = FP-block base */ + + /* Copy the pre-exception base save area below the new sp. This is not + only for the debugger: a windowed spill handler fetches the previous + frame's sp from [sp-12], and on a stack this fresh ([sp-12] is zeroed + .bss) that read would become a store through a null link. Same block in + IDF's xtensa_vectors.S, whose a0 synthesis is left out here because + nothing unwinds this stack. + The XtExcFrame sits RT_S3_FP_BLOCK_SIZE bytes above the FP-block base + in a0, so the A0/A1 loads offset by that amount. */ + l32i a3, a0, RT_S3_FP_BLOCK_SIZE + XT_STK_A0 + s32e a3, sp, -16 + l32i a3, a0, RT_S3_FP_BLOCK_SIZE + XT_STK_A1 + s32e a3, sp, -12 + + movi a0, PS_INTLEVEL(1) | PS_UM | PS_WOE + wsr a0, PS /* C environment (EPS_1 write, like IDF) */ + rsync + + call8 rt_xt_irq_process /* dispatch */ + + movi a0, rt_thread_switch_interrupt_flag + l32i a1, a0, 0 + beqz a1, .Lrt_irq_noswitch + movi a1, 0 + s32i a1, a0, 0 /* consume the request */ + movi a2, rt_xt_isr_frame + l32i a2, a2, 0 /* the frame C was away from */ + movi a0, rt_interrupt_from_thread + l32i a0, a0, 0 + s32i a2, a0, 0 /* from_thread->sp = frame base */ + movi a0, rt_interrupt_to_thread + l32i a0, a0, 0 /* a0 = &to_thread->sp */ + l32i sp, a0, 0 /* sp = to_thread->sp */ + j _rt_s3_dispatch +.Lrt_irq_noswitch: + movi sp, rt_xt_isr_frame + l32i sp, sp, 0 /* resume the interrupted frame */ + j _rt_s3_dispatch /* not fall through: the .align below + is filled with non-instructions */ + +/* +------------------------------------------------------------------------------- + _rt_s3_dispatch -- resume the thread whose frame base is in sp. + sp points at either an FP save block (interrupt-preempted / initial thread) + or an XtSolFrame (cooperative yield). The first word decides: + 0 -> solicited frame, go to _rt_s3_sol_return + RT_S3_FP_FRAME_MARK -> FP block; restore FCR/FSR/f0-f15, step past + the block to the XtExcFrame, call + _xt_context_restore, jump to _rt_user_exit. + Reached by `j`, with interrupts masked, from the level-1 vector's tail and + from both context switch functions below. Only a2/a3 are used as scratch: + _xt_context_restore reloads them from the frame. +------------------------------------------------------------------------------- +*/ + + .align 4 + .type _rt_s3_dispatch, @function +_rt_s3_dispatch: + l32i a2, sp, 0 + beqz a2, _rt_s3_sol_return /* 0 -> solicited frame */ + + /* Exception frame with FP block: restore FP state first + * (_xt_context_restore is pure asm and does not touch FP). */ + l32i a3, sp, RT_S3_FP_FCR + wur.fcr a3 + l32i a3, sp, RT_S3_FP_FSR + wur.fsr a3 + lsi f0, sp, RT_S3_FP_F0 + 0 + lsi f1, sp, RT_S3_FP_F0 + 4 + lsi f2, sp, RT_S3_FP_F0 + 8 + lsi f3, sp, RT_S3_FP_F0 + 12 + lsi f4, sp, RT_S3_FP_F0 + 16 + lsi f5, sp, RT_S3_FP_F0 + 20 + lsi f6, sp, RT_S3_FP_F0 + 24 + lsi f7, sp, RT_S3_FP_F0 + 28 + lsi f8, sp, RT_S3_FP_F0 + 32 + lsi f9, sp, RT_S3_FP_F0 + 36 + lsi f10, sp, RT_S3_FP_F0 + 40 + lsi f11, sp, RT_S3_FP_F0 + 44 + lsi f12, sp, RT_S3_FP_F0 + 48 + lsi f13, sp, RT_S3_FP_F0 + 52 + lsi f14, sp, RT_S3_FP_F0 + 56 + lsi f15, sp, RT_S3_FP_F0 + 60 + + addi sp, sp, RT_S3_FP_BLOCK_SIZE /* sp now at XtExcFrame base */ + /* _xt_context_restore returns to the word after this call, so reaching the + * exit dispatcher needs an explicit jump: the next label is .align 4 and + * the assembler fills the gap with bytes that are not a valid instruction, + * so falling through would execute that fill. */ + call0 _xt_context_restore + j _rt_user_exit + +/* +------------------------------------------------------------------------------- + Exit dispatcher (== IDF _xt_user_exit): restore PS/PC/a0, pop the frame, + rfe. Referenced from every interrupt/initial XtExcFrame at XT_STK_EXIT. +------------------------------------------------------------------------------- +*/ + + .global _rt_user_exit + .type _rt_user_exit, @function + .align 4 +_rt_user_exit: + l32i a0, sp, XT_STK_PS + wsr a0, PS + l32i a0, sp, XT_STK_PC + wsr a0, EPC_1 + l32i a0, sp, XT_STK_A0 + l32i sp, sp, XT_STK_A1 + rsync + rfe + +/* +------------------------------------------------------------------------------- + _rt_s3_sol_return -- resume the thread whose solicited frame sp points at, + the way ESP-IDF's _frxt_dispatch_sol does: restore what such a frame carries + (threadptr, PS, return address, FCR, FSR) and `retw` into it. Only + _rt_s3_dispatch reaches it, and only for a frame marked RT_S3_SOL_YIELDED -- + the thread that left it owns a window chain, spilled by rt_hw_context_switch() + below, and the refill that `retw` triggers reads that chain. It must be a + jump, not a call: `call0` would overwrite the a0 just loaded from the frame. +------------------------------------------------------------------------------- +*/ + + .align 4 + .type _rt_s3_sol_return, @function +_rt_s3_sol_return: + l32i a2, sp, XT_SOL_THREADPTR + wur.threadptr a2 + l32i a0, sp, XT_SOL_PC + /* Restore FCR/FSR (saved by rt_hw_context_switch at sp+RT_S3_SOL_FCR/FSR). + * a2/a3 are scratch: _rt_s3_dispatch is the only caller and they are not + * needed past this point. */ + l32i a2, sp, RT_S3_SOL_FCR + wur.fcr a2 + l32i a2, sp, RT_S3_SOL_FSR + wur.fsr a2 + /* Solicited frames always hold a C-context PS (EXCM=0), so WSR.PS can + * install it even though that lowers INTLEVEL back to what the incoming + * thread ran with. PS.OWB/CALLINC are write-masked: the window rotation + * therefore stays the switcher's own, which is precisely what makes this + * return land inside another thread's call chain. */ + l32i a3, sp, XT_SOL_PS + wsr a3, PS + retw + +/* +------------------------------------------------------------------------------- + void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to) + Cooperative switch, mirroring vPortYield + _frxt_dispatch: save the solicited + frame (pc/ps/threadptr, plus RT_S3_SOL_YIELDED in the exit slot that marks the + frame type), let xthal_window_spill_nw put the caller's a0-a3 in the frame's + base-save area, save FCR/FSR into the frame at RT_S3_SOL_FCR/FSR, *from = + frame base, then hand over through _rt_s3_dispatch. The frame is + RT_S3_SOL_FRMSZ (XT_SOL_FRMSZ + 16) bytes: with `entry sp,RT_S3_SOL_FRMSZ` + the spill's base-save area lands at sp+0x20..0x2F and sp+0x10..0x1F are free + for FCR/FSR. +------------------------------------------------------------------------------- +*/ + + .align 4 + .global rt_hw_context_switch + .type rt_hw_context_switch, @function +rt_hw_context_switch: + entry sp, RT_S3_SOL_FRMSZ + + rsr a4, PS + s32i a0, sp, XT_SOL_PC + s32i a4, sp, XT_SOL_PS + rur.threadptr a5 + s32i a5, sp, XT_SOL_THREADPTR + movi a5, RT_S3_SOL_YIELDED + s32i a5, sp, XT_SOL_EXIT /* marks it solicited for the resume */ + + /* Save FCR/FSR into the solicited frame. All FP regs (f0-f15) are + * caller-saved in the Xtensa windowed ABI, so GCC has already spilled + * them before this call; only the control/status registers are per-thread. */ + rur.fcr a5 + s32i a5, sp, RT_S3_SOL_FCR + rur.fsr a5 + s32i a5, sp, RT_S3_SOL_FSR + + /* Both argument registers are scratch for xthal_window_spill_nw, which + opens with `rsr a2, WINDOWBASE` and rotates windows to walk them, so + publish *from while a2 still holds it, and park `to` in memory. */ + s32i sp, a2, 0 /* *from = solicited frame base */ + movi a2, rt_xt_s3_sol_to + s32i a3, a2, 0 + + /* Window spill: EXCM already clear (C code); disable WOE and raise + INTLEVEL to EXCM_LEVEL so no interrupt preempts the spill. */ + movi a6, ~(PS_WOE_MASK | PS_INTLEVEL_MASK) + and a4, a4, a6 + addi a4, a4, XCHAL_EXCM_LEVEL + wsr a4, PS + rsync + call0 xthal_window_spill_nw + l32i a4, sp, XT_SOL_PS + wsr a4, PS + + rsil a4, XCHAL_EXCM_LEVEL /* keep interrupts off for the swap */ + + movi a3, rt_xt_s3_sol_to + l32i a3, a3, 0 /* a3 = &to_thread->sp */ + l32i sp, a3, 0 /* sp = to_thread->sp */ + j _rt_s3_dispatch + +/* +------------------------------------------------------------------------------- + void rt_hw_context_switch_to(rt_ubase_t to) + First switch out of rt_system_scheduler_start(). to_thread->sp points at the + FP block below the exception frame rt_hw_stack_init() built; dispatch restores + the FP block then the frame and leaves through the exit dispatcher, whose + `rfe` installs the thread's UM/OWB/CALLINC -- a `wsr` may not write those + while the switcher still has PS.INTLEVEL raised. +------------------------------------------------------------------------------- +*/ + + .align 4 + .global rt_hw_context_switch_to + .type rt_hw_context_switch_to, @function +rt_hw_context_switch_to: + entry sp, 32 /* the ABI's minimum windowed frame */ + rsil a3, XCHAL_EXCM_LEVEL /* no interrupt may see the half-swap */ + l32i sp, a2, 0 /* sp = to_thread->sp */ + j _rt_s3_dispatch + +/* +------------------------------------------------------------------------------- + void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, ...) + Records the pending pair for _rt_lowint1's exit path. Same semantics as the + RISC-V weak implementation (first caller wins; nested rt_schedule() inside + one interrupt must not overwrite the interrupted thread). +------------------------------------------------------------------------------- +*/ + + .align 4 + .global rt_hw_context_switch_interrupt + .type rt_hw_context_switch_interrupt, @function +rt_hw_context_switch_interrupt: + entry sp, 32 + movi a4, rt_thread_switch_interrupt_flag + l32i a5, a4, 0 + bnez a5, .Lrt_swirec_to + movi a5, rt_interrupt_from_thread + s32i a2, a5, 0 +.Lrt_swirec_to: + movi a5, rt_interrupt_to_thread + s32i a3, a5, 0 + movi a5, 1 + s32i a5, a4, 0 + retw + +/* +------------------------------------------------------------------------------- + rt_base_t rt_hw_interrupt_disable(void); void rt_hw_interrupt_enable(level) + + RT-Thread passes an opaque token from disable to enable, and this port's + token is the *full* PS: rt_hw_interrupt_enable writes it back with WSR.PS. + RSIL returns the old INTLEVEL only, so it cannot be the token -- handing a + bare level to WSR.PS would install PS = 0..6, clearing UM/OWB/WOE; with WOE + off, the next window overflow/underflow is reported as IllegalInstruction + and the kernel dies in the first call/ret after re-enabling interrupts. + So: snapshot PS first, then RSIL to XCHAL_EXCM_LEVEL (3 here, which masks + every interrupt level v1 uses) and return the snapshot. +------------------------------------------------------------------------------- +*/ + + .align 4 + .global rt_hw_interrupt_disable + .type rt_hw_interrupt_disable, @function +rt_hw_interrupt_disable: + /* 32, not 16: the windowed ABI's minimum frame, because these are call8 + targets from C and the caller's 16-byte incoming area must not overlap + this frame's own spill save area. */ + entry sp, 32 + rsr a3, PS /* full PS before masking */ + rsil a2, XCHAL_EXCM_LEVEL /* a2 = old INTLEVEL only, discarded */ + mov a2, a3 + retw + + .align 4 + .global rt_hw_interrupt_enable + .type rt_hw_interrupt_enable, @function +rt_hw_interrupt_enable: + entry sp, 32 + wsr a2, PS /* full PS from rt_hw_interrupt_disable */ + rsync + retw + +/* +------------------------------------------------------------------------------- + Coprocessor bookkeeping linked in by ESP-IDF's xtensa_context.S: + _xt_coproc_savecs / _xt_coproc_restorecs (and siblings) reference the two + tables below as link-time dependencies. This port never calls them -- CP0 + state is saved and restored eagerly in the exception frame -- but the symbols + must still resolve and carry the right layout. _xt_coproc_owner_sa[] is + written by IDF's owner-tracking stores, so it lives in .bss (read-only would + fault with EXCCAUSE 29 / StoreProhibited); _xt_coproc_sa_offset[] is a pure + lookup table and lives in .rodata. Sizes and layouts follow the ESP-IDF + definitions; the owner array is sized for this single-core part. +------------------------------------------------------------------------------- +*/ +#if XCHAL_CP_NUM > 0 + .section .rodata, "a" + .global _xt_coproc_sa_offset + .type _xt_coproc_sa_offset, @object + .align 16 +_xt_coproc_sa_offset: + .word XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA + .word XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA + + .section .bss.rt_coproc, "aw", @nobits + .global _xt_coproc_owner_sa + .type _xt_coproc_owner_sa, @object + .align 16,,XCHAL_CP_MAX<<2 +_xt_coproc_owner_sa: + .space (XCHAL_CP_MAX) << 2 + + .section .iram1, "ax" + .global _frxt_task_coproc_state + .type _frxt_task_coproc_state, @function + .align 4 +_frxt_task_coproc_state: + /* XT_RTOS_CP_STATE hook: ESP-IDF's lazy coprocessor code asks the RTOS for + * the save area of the thread that owns the coprocessors. This port saves + * FP state eagerly in _rt_lowint1 and rt_hw_context_switch (CP0 / FPU + * enabled, CP3 / AI left off), so no thread owns a lazy save area and the + * correct answer is "none". Entered with call0, so only a15 may be + * written. */ + movi a15, 0 + ret +#endif /* XCHAL_CP_NUM > 0 */ diff --git a/libcpu/xtensa/esp32s3/cpuport.c b/libcpu/xtensa/esp32s3/cpuport.c new file mode 100644 index 000000000000..2fc3d88516cf --- /dev/null +++ b/libcpu/xtensa/esp32s3/cpuport.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-09-27 RT-Thread ESP32-S3 (Xtensa LX7) C glue for context_gcc.S + * + * Coprocessor policy (see also context_gcc.S): the FPU (CP0) is enabled + * (CPENABLE bit 0) so that applications can use single-precision float + * arithmetic. Every level-1 interrupt saves the full FP state eagerly + * (FCR/FSR/f0-f15) below the XtExcFrame, and cooperative switches save + * FCR/FSR into the solicited frame. AI/SIMD (CP3) stays disabled; using + * CP3 instructions triggers a CoprocessorDisabled exception reported by + * rt_xt_exception_handler. + * + * Because CP state is handled eagerly, there is no per-thread coprocessor + * save area on the stack (XT_CP_SIZE = 456 bytes is not reserved). ESP-IDF's + * lazy coprocessor machinery (_xt_coproc_savecs() / _xt_coproc_restorecs() / + * _frxt_task_coproc_state) is never invoked by this port: _xt_context_save() + * and _xt_context_restore() do not call them, and no other code path does. + * + * Level >= 2 interrupts are not handled (the vectors panic), so ISRs must be + * allocated with ESP_INTR_FLAG_LEVEL1. + * + * Frame types (see context_gcc.S for the assembly): there are two, and the + * resume path (_rt_s3_dispatch) picks one by the word at offset 0 of the + * frame -- 0 means a solicited frame left by a thread that gave the CPU away, + * RT_S3_FP_FRAME_MARK means an FP save block below an exception frame + * (preempted thread or initial thread). That is a change from the original + * ESP-IDF convention where the exit dispatcher address sat at offset 0; here + * the FP block's marker takes that slot and the XtExcFrame sits above it. + * - a thread that yields in rt_hw_context_switch() owns a real register-window + * chain, so it is resumed with `retw` and its registers refill from that + * chain; + * - a thread that was interrupted, and a thread that has never run, are both + * resumed through the exit dispatcher with `rfe` -- for the second case that + * is the only way its UM/OWB/CALLINC can be installed, and it is what + * pxPortInitialiseStack()/uxInitialiseStackFrame() do in ESP-IDF. + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "esp_attr.h" + +#include "cpuport.h" + +/* ---- globals referenced by context_gcc.S (same names/semantics as the + * ---- RISC-V common port, which this replaces for Xtensa) ---- */ +#ifndef RT_USING_SMP +volatile rt_ubase_t rt_interrupt_from_thread = 0; +volatile rt_ubase_t rt_interrupt_to_thread = 0; +volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0; +#endif + +/* Handler/arg table maintained by ESP-IDF xtensa_intr.c (xt_set_interrupt_handler, + * called from intr_alloc.c) and read by the level-1 dispatcher below exactly + * like dispatch_c_isr in the ESP-IDF vectors. The entry struct is private to + * xtensa_intr.c; this is its ABI (two words: handler, arg — see + * xtensa_intr_asm.S table init), single-core so index == interrupt number. */ +struct xt_int_entry +{ + void (*handler)(void *); + void *arg; +}; +extern struct xt_int_entry _xt_interrupt_table[]; + +/* the exit dispatcher in context_gcc.S, referenced by every thread's frame */ +extern void _rt_user_exit(void); + +/* ---- coprocessors: FPU on, AI off ---------------------------------------- + * + * CPENABLE is set here (rather than left to the reset value) because IDF's + * startup and ROM code may have changed it. This port enables CP0 (FPU) so + * that float arithmetic works, and leaves CP3 (AI/SIMD) off. The eager + * save/restore in context_gcc.S means every interrupt and cooperative switch + * moves FP state, so no per-thread save area is needed. + */ +static void cp_enable_fpu(void) +{ + const rt_uint32_t cpenable = (1 << 0); /* CP0 only, CP3 off */ + + __asm__ volatile("wsr %0, cpenable; rsync" ::"r"(cpenable) : "memory"); +} + +/* ---- interrupt dispatch (called from _rt_lowint1 with a C environment) ---- */ +void rt_xt_irq_process(void) +{ + rt_ubase_t enabled, active, pending; + + rt_interrupt_enter(); + do + { + __asm__ __volatile__("rsr %0, intenable" : "=r"(enabled)); + __asm__ __volatile__("rsr %0, interrupt" : "=r"(active)); + pending = enabled & active & XCHAL_INTLEVEL1_MASK; + if (!pending) + { + break; + } + + int n = 31 - __builtin_clz(pending); /* MSB first, like IDF */ + __asm__ __volatile__("wsr %0, intclear; rsync" ::"r"(1u << n)); + + /* Same table ESP-IDF's own dispatcher walks, so every driver that did + * allocate a level-1 handler here (the tick, gptimer, esp_timer) runs. */ + if (_xt_interrupt_table[n].handler) + { + _xt_interrupt_table[n].handler(_xt_interrupt_table[n].arg); + } + } while (1); + rt_interrupt_leave(); +} + +/* ---- exception report for non-interrupt user exceptions ---- */ +void rt_xt_exception_handler(XtExcFrame *frame) +{ + /* esp_rom_printf, not rt_kprintf: this can fire before RT-Thread's + * console device exists (e.g. from ESP-IDF startup, before the first + * context switch). */ + extern int esp_rom_printf(const char *fmt, ...); + esp_rom_printf("\nXtensa exception %u at 0x%08x (EXCVADDR 0x%08x, PS 0x%08x, A1 0x%08x)\n", + (unsigned)frame->exccause, (unsigned)frame->pc, + (unsigned)frame->excvaddr, (unsigned)frame->ps, (unsigned)frame->a1); + esp_rom_printf("A0=0x%08x A2=0x%08x A3=0x%08x A4=0x%08x SAR=0x%x\n", + (unsigned)frame->a0, (unsigned)frame->a2, (unsigned)frame->a3, + (unsigned)frame->a4, (unsigned)frame->sar); + while (1) + { + /* let the reset watchdog/POWERON bring us back */ + } +} + +/* ---- thread startup frame ---- */ + +/* + * Conservative headroom a thread stack needs beyond the frame it starts with. + * The initial context is released the moment the thread first runs -- dispatch + * restores sp above it -- so it does not stack with anything. What must fit: + * one exception frame + FP block for a preemption that lands on top of the + * initial frame, the initial frame + FP block itself (the first switch reads + * them before sp moves), and spill space for the windowed ABI save area below + * sp. The kernel's own threads default to a few hundred bytes, in which case + * the initial frame lands below thread->stack_addr and whatever the heap + * allocator parked there gets overwritten. The checks below make that a build + * error instead. + */ +#define RT_S3_STACK_MIN (2 * (XT_STK_FRMSZ + RT_S3_FP_BLOCK_SIZE) + 64) + +#ifdef IDLE_THREAD_STACK_SIZE +_Static_assert(IDLE_THREAD_STACK_SIZE >= RT_S3_STACK_MIN, + "IDLE_THREAD_STACK_SIZE below the ESP32-S3 Xtensa minimum"); +#endif +#ifdef RT_USING_TIMER_SOFT +_Static_assert(RT_TIMER_THREAD_STACK_SIZE >= RT_S3_STACK_MIN, + "RT_TIMER_THREAD_STACK_SIZE below the ESP32-S3 Xtensa minimum"); +#endif +#ifdef RT_USING_USER_MAIN +_Static_assert(RT_MAIN_THREAD_STACK_SIZE >= RT_S3_STACK_MIN, + "RT_MAIN_THREAD_STACK_SIZE below the ESP32-S3 Xtensa minimum"); +#endif + +/* + * Trampoline that wraps every thread's entry point. The windowed ABI starts + * the thread in a clean register window (PS.CALLINC=1, as if reached by + * call4), so a `retw` from the entry function has no caller window to return + * to -- putting texit in a0 does not work. Instead, the frame's pc points + * here, with entry/parameter/texit in a6/a7/a8 (the call4 argument slots), + * and this function calls texit() explicitly when entry() returns. + */ +static void __attribute__((noinline)) +rt_xt_thread_start(void (*entry)(void *), void *parameter, void (*texit)(void)) +{ + entry(parameter); + texit(); + while (1) + { + /* texit (_thread_exit) never returns; guard loop just in case */ + } +} + +/* + * The frame a thread starts in, mirroring uxInitialiseStackFrame() in + * ESP-IDF's Xtensa FreeRTOS port: an *interrupt/exception* frame, resumed + * through the exit dispatcher (_rt_user_exit in context_gcc.S) exactly like a + * thread that was preempted by an interrupt. Below the XtExcFrame sits an + * FP save block (RT_S3_FP_BLOCK_SIZE bytes) with the frame marker, FCR/FSR + * and f0-f15 all zeroed; thread->sp points at the FP block base. + * + * It cannot be a solicited frame. A solicited frame is left behind by a thread + * that has a register-window chain of its own, and resuming one is a `retw` + * whose register refill walks that chain; a thread that has never run has no + * chain, so there is nothing correct to refill. The exception return instead + * hands the window state to the hardware: PS.EXCM in the frame makes `rfe` + * install PS -- including UM, OWB and CALLINC, which a `wsr` may not write + * while PS.INTLEVEL is non-zero, i.e. while the switcher has interrupts masked + * -- and start the thread in a clean window. + * + * PS_CALLINC(1) makes the trampoline (rt_xt_thread_start) behave as if it had + * been reached by `call4`, so the argument registers of that call are the + * frame's a6..a8: a6 becomes entry, a7 becomes parameter, a8 becomes texit. + * a0 = 0 terminates a backtrace; the trampoline never returns, so a0 is never + * used as a return address. + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + static int fpu_enabled; + /* The kernel passes stack_addr + stack_size - sizeof(rt_ubase_t) as the + * top (src/thread.c); put the 4 back so the frame is placed flush below the + * end of the array rather than up to 16 bytes lower on some alignments. */ + rt_ubase_t top = (rt_ubase_t)stack_addr + sizeof(rt_ubase_t); + rt_ubase_t frame = (top - XT_STK_FRMSZ) & ~15U; + XtExcFrame *f = (XtExcFrame *)frame; + rt_ubase_t fp_block = frame - RT_S3_FP_BLOCK_SIZE; + + if (!fpu_enabled) + { + fpu_enabled = 1; + cp_enable_fpu(); + } + + /* Every slot of the frame and FP block is read by _xt_context_restore / + * _rt_s3_dispatch / _rt_user_exit, so nothing may be left uninitialized. */ + rt_memset((void *)frame, 0, XT_STK_FRMSZ); + rt_memset((void *)fp_block, 0, RT_S3_FP_BLOCK_SIZE); + + /* Marker at FP block offset 0 so _rt_s3_dispatch recognises this as an + * exception frame (not a solicited frame whose first word is 0). */ + *(rt_uint32_t *)fp_block = RT_S3_FP_FRAME_MARK; + + f->pc = (rt_ubase_t)rt_xt_thread_start; + f->a0 = 0; /* terminate a backtrace */ + f->a1 = frame + XT_STK_FRMSZ; /* the thread's own sp, above the frame */ + f->exit = (rt_ubase_t)_rt_user_exit;/* the resume path's tail jumps here */ + f->a6 = (rt_ubase_t)tentry; /* trampoline arg 0: entry function */ + f->a7 = (rt_ubase_t)parameter; /* trampoline arg 1: entry parameter */ + f->a8 = (rt_ubase_t)texit; /* trampoline arg 2: thread exit handler */ + f->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); + + /* First word of the non-coprocessor extra save area (threadptr); this BSP + * sets up no TLS. */ + *(rt_uint32_t *)(frame + XT_STK_EXTRA) = 0; + + return (rt_uint8_t *)fp_block; /* thread->sp = FP block base */ +} + +/* ---- misc port API ---- */ +void rt_hw_cpu_reset(void) +{ + extern void esp_restart(void); + esp_restart(); +} + +void rt_hw_cpu_shutdown(void) +{ + while (1) + { + } +} diff --git a/libcpu/xtensa/esp32s3/cpuport.h b/libcpu/xtensa/esp32s3/cpuport.h new file mode 100644 index 000000000000..779556b79958 --- /dev/null +++ b/libcpu/xtensa/esp32s3/cpuport.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-09-27 RT-Thread ESP32-S3 (Xtensa LX7) port helpers + * 2026-10-10 RT-Thread Add eager FPU (CP0) save/restore constants + */ + +#ifndef __CPU_PORT_H__ +#define __CPU_PORT_H__ + +/* + * Frame layouts come straight from Espressif's Xtensa port: + * defines XtExcFrame (XT_STK_*) and XtSolFrame + * (XT_SOL_*) with offsets that are visible to C and to the assembler alike. + * + * This port uses both, and which one a thread is sitting in is recorded in the + * frame's first word -- the slot ESP-IDF's _frxt_dispatch tests the same way: + * + * XtExcFrame: the first word of the XtExcFrame itself is still the exit + * dispatcher (_rt_user_exit), set by rt_hw_stack_init() and _rt_lowint1. + * An FP save block of RT_S3_FP_BLOCK_SIZE bytes sits below the XtExcFrame + * on the thread's stack; thread->sp points at the FP block, not the + * XtExcFrame. The first word of the FP block (at thread->sp) is + * RT_S3_FP_FRAME_MARK, which lets _rt_s3_dispatch distinguish it from a + * solicited frame. The FP block carries FCR, FSR, and f0-f15 -- every + * level-1 interrupt saves them eagerly, and _rt_s3_dispatch restores them + * before calling _xt_context_restore and jumping to _rt_user_exit. + * + * XtSolFrame: first word = RT_S3_SOL_YIELDED. Created by + * rt_hw_context_switch() when a thread gives the CPU away. Resumed with + * `retw`, whose register refill walks the window chain that that thread + * spilled when it yielded. The frame is RT_S3_SOL_FRMSZ (XT_SOL_FRMSZ + 16) + * bytes: the standard 32 bytes plus 16 bytes that hold FCR/FSR at + * RT_S3_SOL_FCR / RT_S3_SOL_FSR (the window spill's base-save area moves to + * sp+0x20..0x2F with the larger frame, leaving sp+0x10..0x1F free). + * + * The FPU (CP0) is enabled: CPENABLE has bit 0 set (see cp_enable_fpu in + * cpuport.c). The AI/SIMD coprocessor (CP3) stays disabled. CP state is + * saved/restored eagerly on every interrupt and cooperative switch, so there + * is no per-thread save area and no lazy owner tracking. ESP-IDF's lazy + * coprocessor machinery (_xt_coproc_savecs() / _xt_coproc_restorecs() / + * _frxt_task_coproc_state) is never invoked by this port. + */ + +#ifndef __ASSEMBLER__ +#include +#endif + +/* What rt_hw_context_switch() writes into a yielding thread's frame at + * XT_SOL_EXIT, to mark it as the solicited kind. */ +#define RT_S3_SOL_YIELDED 0 + +/* Solicited frame size: XT_SOL_FRMSZ (32) + 16 bytes for FCR/FSR. + * With entry sp,RT_S3_SOL_FRMSZ the window spill's base-save area lands at + * sp+0x20..0x2F, leaving sp+0x10..0x1F free for FCR and FSR. */ +#define RT_S3_SOL_FRMSZ (XT_SOL_FRMSZ + 16) +#define RT_S3_SOL_FCR 0x10 +#define RT_S3_SOL_FSR 0x14 + +/* FP save block: sits below every XtExcFrame (interrupt-preempted thread and + * initial thread frame). thread->sp points at the block. The marker at + * offset 0 lets _rt_s3_dispatch tell this from a solicited frame (whose + * first word is 0). Total size is padded to 16-byte alignment so both + * thread->sp and the XtExcFrame above stay 16-byte aligned. */ +#define RT_S3_FP_BLOCK_SIZE 80 +#define RT_S3_FP_MARKER_OFS 0 +#define RT_S3_FP_FCR 4 +#define RT_S3_FP_FSR 8 +#define RT_S3_FP_F0 12 /* fN at RT_S3_FP_F0 + 4*N */ +#define RT_S3_FP_FRAME_MARK 0x46505530 /* "FPU0" */ + +#endif /* __CPU_PORT_H__ */ diff --git a/tools/ci/bsp_detail.py b/tools/ci/bsp_detail.py index 7e68e16adcaf..7c30734e4b7d 100644 --- a/tools/ci/bsp_detail.py +++ b/tools/ci/bsp_detail.py @@ -29,6 +29,7 @@ 'llvm-arm': 'https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-16.0.0/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64.tar.gz', 'riscv-none-embed-gcc': 'https://github.com/RT-Thread/toolchains-ci/releases/download/v1.5/xpack-riscv-none-embed-gcc-8.3.0-2.3-linux-x64.tar.gz', 'riscv32-esp-elf-gcc': 'https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz', + 'xtensa-esp32s3-elf-gcc': 'https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz', 'clang': 'https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-16.0.0/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64.tar.gz', # 添加其他工具链的下载地址 } diff --git a/tools/ci/bsp_detail.yml b/tools/ci/bsp_detail.yml index 856abbe86c7b..6fff081740bd 100644 --- a/tools/ci/bsp_detail.yml +++ b/tools/ci/bsp_detail.yml @@ -21,6 +21,12 @@ ESP32_C3: gcc: riscv32-esp-elf-gcc menuconfig: true rtconfig.h: true +ESP32_S3: + .config: true + README.md: true + gcc: xtensa-esp32s3-elf-gcc + menuconfig: true + rtconfig.h: true ESP32_C6: .config: true README.md: true diff --git a/tools/ci/toolchain.sh b/tools/ci/toolchain.sh index c9040177efc5..135804f26e5b 100755 --- a/tools/ci/toolchain.sh +++ b/tools/ci/toolchain.sh @@ -8,6 +8,7 @@ declare -A download_urls=( ["riscv32-unknown-elf-gcc"]="https://github.com/hpmicro/riscv-gnu-toolchain/releases/download/2022.05.15/riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz" ["riscv-none-embed-gcc"]="https://github.com/RT-Thread/toolchains-ci/releases/download/v1.5/xpack-riscv-none-embed-gcc-8.3.0-2.3-linux-x64.tar.gz" ["riscv32-esp-elf-gcc"]="https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz" +["xtensa-esp32s3-elf-gcc"]="https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" ["clang"]="https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-16.0.0/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64.tar.gz" ["i686-atxhua-newlib-elf-gcc"]="https://github.com/atxhua/i686-atxhua-newlib-elf/releases/download/15.2.0/i686-atxhua-newlib-elf-linux.tar.gz" ["i686-atxhua-picolib-elf-gcc"]="https://github.com/atxhua/i686-atxhua-picolib-elf/releases/download/15.2.0/i686-atxhua-picolib-elf-linux.tar.gz" diff --git a/tools/ci/toolchain_bsp.yml b/tools/ci/toolchain_bsp.yml index f2698ba191c6..a9f955f34935 100644 --- a/tools/ci/toolchain_bsp.yml +++ b/tools/ci/toolchain_bsp.yml @@ -432,3 +432,8 @@ unicore32-linux-gcc: bsp: - sep6200 count: 1 +xtensa-esp32s3-elf-gcc: + bsp: + - ESP32_S3 + count: 1 + download_url: https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz