GPU Metal: keep the memory pools resident for the kernels

The kernels reach the device and host pools through the addresses stored in
constant memory, so Metal does not know a dispatch uses them and does not keep
them mapped for the GPU. About a second after the last blit that touched a
pool, the kernels read it as empty: every loop bounded by a count in device
memory finishes in ~20 us, Finalize step 2 takes 13 ms instead of 0.4 ms, and
the next blit stalls 0.2-0.3 s before it starts, mapping the pool again.

At 20 kHz the merger TrackFit alone runs for a second, so everything queued
behind it did nothing until the next transfer: 0 looper candidates, 1,246 of
21,679 retry refits, 536 of 2,701 looper fits, 245,145 tracks for 233,521 on
the CPU at 27 sectors. It is not the length of the dispatch: at pbpb30 a 1.5 s
host sleep before a normal TrackFit gives the same picture (0 retry refits, 0
looper candidates, 22,250 tracks for 21,360), and a 1.7 s single TrackFit
dispatch completes once the pools are made resident with useResource (207
looper fits, 4,521 retry refits, 10,775 candidates, 21,361 tracks, as without
the sleep).

pbpb30: 985-1087 ms/event against 1002-1075 before (3 rounds of 10 events);
the debug dumps are byte-identical, sim5pp identical to the CPU.

Author: ktf

GPU/GPUTracking/Base/metal/GPUReconstructionMetalKernels.mm

@@ -42,6 +42,10 @@
   // Slots 0 to 2 are what GPUCA_KRNL_BUFFERS and GPUCA_KRNL_SECTOR_ARG declare
   // in the generated signature; the kernel's own arguments follow from slot 3.
   [computeEncoder setComputePipelineState:pso];
+  // The kernels reach the pools through the addresses kept in constant memory,
+  // which Metal cannot see, so they have to be made resident explicitly.
+  [computeEncoder useResource:mInternals->mem_gpu usage:MTLResourceUsageRead | MTLResourceUsageWrite];
+  [computeEncoder useResource:mInternals->mem_host usage:MTLResourceUsageRead | MTLResourceUsageWrite];
   [computeEncoder setBuffer:mInternals->mem_gpu offset:0 atIndex:0];
   [computeEncoder setBuffer:mInternals->mem_constant offset:0 atIndex:1];
   const int32_t iSector = runRange.index;